JP7432567B2 - Signal generation device and signal generation method - Google Patents

Description

The present invention relates to a signal generation device using a variable delay circuit that varies the amount of delay of an input signal, and a signal generation method using a variable delay method.

As a variable delay circuit that varies the amount of delay of an input signal, for example, one disclosed in Patent Document 1 listed below is known. As shown in FIG. 14, the variable delay circuit 31 of Patent Document 1 is connected in parallel between an input terminal and an output terminal, and when each is operated independently, the input signal of the input terminal is delayed by a delay time Ta, Tb ( Delay section A and delay section B output to the output terminal at Ta>Tb), and analog control signals X and Y are input, and the current flowing through delay section A and delay section B is controlled according to the difference (X-Y). and a current control section 32 that sets a delay time that changes continuously according to the difference (XY) between the delay times Ta and Tb.

Further, in the variable delay circuit 31 of Patent Document 1, the load capacitor 33 is connected to the delay section A, and the peaking capacitor 34 and the peaking coil are connected to the delay section B so that the delay times Ta and Tb satisfy Ta>Tb. are doing. As a result, in the variable delay circuit 31 of Patent Document 1, the delay time of the delay section A is delayed by the load capacitance 33, and the delay time of the delay section B is advanced by the peaking capacitance 34 and the peaking coil. A delay difference occurs between the two, and a variable delay is achieved by controlling the current ratio (synthesis ratio) of the circuits of delay section A and delay section B.

JP2009-253366A

However, in the conventional variable delay circuit 31 disclosed in Patent Document 1 mentioned above, the number of amplifier circuit stages in delay section A and delay section B is the same, and the delay difference between delay section A and delay section B is The delay difference between delay section A and delay section B is not created by the difference in the number of stages of the amplifier circuit, but is created by the load capacitance 33 connected to delay section A, the peaking capacitance 34 connected to delay section B, and the peaking coil. The addition of the load capacitance 33, peaking capacitance 34, and peaking coil changes the frequency characteristics, causing a difference in the frequency characteristics of the delay section A side and the delay section B side, and the current ratio of the circuit (synthesis ratio ), there was a problem in that the amplitude of the combined output changed.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a signal generation device and a signal generation method that can suppress changes in output amplitude due to bias voltage dependence at high frequencies. There is.

In order to achieve the above object, the signal generating device according to claim 1 of the present invention includes a branch combining section 4 having a first amplifier circuit 11 and a second amplifier circuit 12 having different numbers of amplifier stages in the current mode logic circuit. Equipped with
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay path r1, and the path with the larger number of amplifier stages of the current mode logic circuit Let the route be the maximum delay route r2,
A capacitor C is connected in parallel with the emitter-to-emitter resistance of at least one current mode logic circuit on the maximum delay side path,
A transmission line Z is connected between at least one output of an emitter follower circuit connected between the current mode logic circuits of the maximum delay side path and an input of a subsequent current mode logic circuit,
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. The delay difference is set to be smaller than 1/5 period,
The applied voltage is changed so that the sum of drive currents of bias terminals A and B provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay side path are A pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction by a variable delay circuit that synthesizes and outputs signals by changing the ratio of output amplitudes is input to the device under test. It is characterized in that it is used in a measuring device that receives signals returned from

The signal generating device according to claim 2 of the present invention includes a branching and combining section 4 having a first amplifier circuit 11 and a second amplifier circuit 12 having different numbers of amplifier stages in the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay path r1, and the path with the larger number of amplifier stages of the current mode logic circuit Let the route be the maximum delay route r2,
A coil L is connected in series with an output load resistance of at least one current mode logic circuit of the maximum delay side path,
A transmission line Z is connected between at least one output of an emitter follower circuit connected between the current mode logic circuits of the maximum delay side path and an input of a subsequent current mode logic circuit,
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. The delay difference is set to be smaller than 1/5 period,
The applied voltage is changed so that the sum of drive currents of bias terminals A and B provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay side path are A pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction by a variable delay circuit that synthesizes and outputs signals by changing the ratio of output amplitudes is input to the device under test. It is characterized in that it is used in a measuring device that receives signals returned from

The signal generating device according to claim 3 of the present invention includes a branching and combining section 4 having a first amplifier circuit 11 and a second amplifier circuit 12 having different numbers of amplifier stages in the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay path r1, and the path with the larger number of amplifier stages of the current mode logic circuit Let the route be the maximum delay route r2,
A capacitor C is connected in parallel with the emitter-to-emitter resistance of at least one current mode logic circuit on the minimum delay side path,
A transmission line Z is connected to the input of at least one current mode logic circuit of the minimum delay side path,
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. The delay difference is set to be smaller than 1/5 period,
The applied voltage is changed so that the sum of drive currents of bias terminals A and B provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay side path are A pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction by a variable delay circuit that synthesizes and outputs signals by changing the ratio of output amplitudes is input to the device under test. It is characterized in that it is used in a measuring device that receives signals returned from

The signal generating device according to claim 4 of the present invention includes a branching and combining section 4 having a first amplifier circuit 11 and a second amplifier circuit 12 having different numbers of amplifier stages in the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay path r1, and the path with the larger number of amplifier stages of the current mode logic circuit Let the route be the maximum delay route r2,
A coil L is connected in series with an output load resistance of at least one current mode logic circuit of the minimum delay side path,
A transmission line Z is connected to the input of at least one current mode logic circuit of the minimum delay side path,
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. The delay difference is set to be smaller than 1/5 period,
The applied voltage is changed so that the sum of drive currents of bias terminals A and B provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay side path are A pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction by a variable delay circuit that synthesizes and outputs signals by changing the ratio of output amplitudes is input to the device under test. It is characterized in that it is used in a measuring device that receives signals returned from

The signal generating device according to claim 5 of the present invention includes a branching and combining section 4 having a first amplifier circuit 11 and a second amplifier circuit 12 having different numbers of amplifier stages in the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay path r1, and the path with the larger number of amplifier stages of the current mode logic circuit Let the route be the maximum delay route r2,
A capacitor C is connected between the output of the current mode logic circuit of the input stage of the maximum delay side path and the positive power supply VCC,
A transmission line Z is connected to the input of at least one current mode logic circuit of the minimum delay side path,
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. The delay difference is set to be smaller than 1/5 period,
The applied voltage is changed so that the sum of drive currents of bias terminals A and B provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay side path are A pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction by a variable delay circuit that synthesizes and outputs signals by changing the ratio of output amplitudes is input to the device under test, and along with this input, the pattern signal is It is characterized in that it is used in a measuring device that receives signals returned from

The signal generating device according to claim 6 of the present invention includes a branching and combining section 4 having a first amplifier circuit 11 and a second amplifier circuit 12 including a plurality of stages of current mode logic circuits having different numbers of amplifier stages,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay path r1, and the path with the larger number of amplifier stages of the current mode logic circuit Let the route be the maximum delay route r2,
A capacitor C is connected between the output of the current mode logic circuit of the input stage of the minimum delay side path and the positive power supply VCC,
A transmission line Z is connected between at least one output of an emitter follower circuit connected between the current mode logic circuits of the maximum delay side path and an input of a subsequent current mode logic circuit,
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. The delay difference is set to be smaller than 1/5 period,
The applied voltage is changed so that the sum of drive currents of bias terminals A and B provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay side path are A pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction by a variable delay circuit that synthesizes and outputs signals by changing the ratio of output amplitudes is input to the device under test. It is characterized in that it is used in a measuring device that receives signals returned from

The signal generation method according to claim 7 of the present invention uses a branching and combining section 4 having a first amplifier circuit 11 and a second amplifier circuit 12 having different numbers of amplifier stages in the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay path r1, and the path with the larger number of amplifier stages of the current mode logic circuit Let the route be the maximum delay route r2,
connecting a capacitor C in parallel with the emitter-to-emitter resistor of at least one current mode logic circuit of the maximum delay side path;
connecting a transmission line Z between at least one output of an emitter follower circuit connected between the current mode logic circuits of the maximum delay side path and an input of a subsequent current mode logic circuit;
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. setting the delay difference to be smaller than 1/5 period;
The applied voltage is changed so that the sum of drive currents of bias terminals A and B provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay side path are inputting a pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction using a variable delay method to the device under test; The present invention is characterized in that it is used in a measuring device that receives a signal reflected from the object to be measured .

The signal generation method according to claim 8 of the present invention uses a branching and combining section 4 having a first amplifier circuit 11 and a second amplifier circuit 12 having different numbers of amplifier stages in the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay path r1, and the path with the larger number of amplifier stages of the current mode logic circuit Let the route be the maximum delay route r2,
connecting a coil L in series with a resistance of an output load of at least one current mode logic circuit of the maximum delay side path;
connecting a transmission line Z between at least one output of an emitter follower circuit connected between the current mode logic circuits of the maximum delay side path and an input of a subsequent current mode logic circuit;
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. setting the delay difference to be smaller than 1/5 period;
The applied voltage is changed so that the sum of drive currents of bias terminals A and B provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay side path are inputting a pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction using a variable delay method to the device under test; The present invention is characterized in that it is used in a measuring device that receives a signal reflected from the object to be measured .

The signal generation method according to claim 9 of the present invention uses a branching and combining section 4 having a first amplifier circuit 11 and a second amplifier circuit 12 having different numbers of amplifier stages in the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay path r1, and the path with the larger number of amplifier stages of the current mode logic circuit Let the route be the maximum delay route r2,
connecting a capacitor C in parallel with an emitter-to-emitter resistor of at least one current mode logic circuit of the minimum delay side path;
connecting a transmission line Z to an input of at least one current mode logic circuit of the minimum delay side path;
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. setting the delay difference to be smaller than 1/5 period;
The applied voltage is changed so that the sum of drive currents of bias terminals A and B provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay side path are inputting a pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction using a variable delay method to the device under test; The present invention is characterized in that it is used in a measuring device that receives a signal reflected from the object to be measured .

The signal generation method according to claim 10 of the present invention uses a branching and combining section 4 having a first amplifier circuit 11 and a second amplifier circuit 12 having different numbers of amplifier stages in the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay path r1, and the path with the larger number of amplifier stages of the current mode logic circuit Let the route be the maximum delay route r2,
connecting a coil L in series with a resistance of an output load of at least one current mode logic circuit of the minimum delay side path;
connecting a transmission line Z to an input of at least one current mode logic circuit of the minimum delay side path;
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. setting the delay difference to be smaller than 1/5 period;
The applied voltage is changed so that the sum of drive currents of bias terminals A and B provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay side path are inputting a pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction using a variable delay method to the device under test; The present invention is characterized in that it is used in a measuring device that receives a signal reflected from the object to be measured .

The signal generation method according to claim 11 of the present invention uses a branching and combining section 4 having a first amplifier circuit 11 and a second amplifier circuit 12 having different numbers of amplifier stages in the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay path r1, and the path with the larger number of amplifier stages of the current mode logic circuit Let the route be the maximum delay route r2,
connecting a capacitor C between the output of the current mode logic circuit of the input stage of the maximum delay side path and the positive power supply VCC;
connecting a transmission line Z to an input of at least one current mode logic circuit of the minimum delay side path;
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. setting the delay difference to be smaller than 1/5 period;
The applied voltage is changed so that the sum of drive currents of bias terminals A and B provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay side path are inputting a pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction using a variable delay method to the device under test; The present invention is characterized in that it is used in a measuring device that receives a signal reflected from the object to be measured .

The signal generation method according to claim 12 of the present invention uses a branching and combining section 4 having a first amplifier circuit 11 and a second amplifier circuit 12 including a plurality of stages of current mode logic circuits having different numbers of amplifier stages,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay path r1, and the path with the larger number of amplifier stages of the current mode logic circuit Let the route be the maximum delay route r2,
connecting a capacitor C between the output of the current mode logic circuit of the input stage of the minimum delay side path and the positive power supply VCC;
connecting a transmission line Z between at least one output of an emitter follower circuit connected between the current mode logic circuits of the maximum delay side path and an input of a subsequent current mode logic circuit;
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. setting the delay difference to be smaller than 1/5 period;
The applied voltage is changed so that the sum of drive currents of bias terminals A and B provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay side path are inputting a pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction using a variable delay method to the device under test; The present invention is characterized in that it is used in a measuring device that receives a signal reflected from the object to be measured .

According to the present invention, it is possible to suppress changes in output amplitude due to bias voltage dependence at high frequencies while maintaining a variable delay amount.

FIG. 2 is a diagram showing the basic configuration of one stage of branching and combining of the variable delay circuit according to the present invention. FIG. 2 is a diagram showing a basic configuration of two stages of branching and combining of a variable delay circuit according to the present invention. FIG. 2 is a circuit diagram showing a first embodiment of a branching and combining section in a variable delay circuit according to the present invention. FIG. 2 is a circuit diagram showing a second embodiment of a branching and combining section in a variable delay circuit according to the present invention. FIG. 7 is a circuit diagram showing a third embodiment of a branching and combining section in a variable delay circuit according to the present invention. FIG. 7 is a circuit diagram showing a fourth embodiment of a branching and combining section in a variable delay circuit according to the present invention. FIG. 7 is a circuit diagram showing a fifth embodiment of a branching and combining section in a variable delay circuit according to the present invention. FIG. 7 is a circuit diagram showing a sixth embodiment of a branching and combining section in a variable delay circuit according to the present invention. FIG. 3 is a diagram showing changes in amplitude of the final post-synthesis output (64 GHz) with respect to bias voltage in the variable delay circuit according to the present invention. FIG. 3 is a diagram showing bias voltage-output amplitude characteristics before and after improvement of the variable delay circuit according to the present invention. FIG. 3 is a diagram showing bias voltage-variable delay amount characteristics before and after improvement of the variable delay circuit according to the present invention. 1 is a diagram showing a schematic configuration of a bit error measuring device including a signal generating device employing a variable delay circuit according to the present invention. FIG. 3 is a diagram showing changes in amplitude of the final post-synthesis output (64 GHz) with respect to bias voltage in a variable delay circuit for simulation. FIG. 2 is a diagram showing an example of a conventional variable delay circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the attached drawings.

[Basic configuration of variable delay circuit]
As shown in FIGS. 1 and 2, the variable delay circuit 1 (1A, 1B) is a differential circuit using transistors, and includes an input terminal 2 consisting of a positive input 2a and a negative input 2b, an input stage amplifier section 3, It is roughly configured with a branching and combining section 4, an output stage amplifier section 5, and an output terminal 6 consisting of a positive output 6a and a negative output 6b, and outputs the signal from the output terminal 6 by varying the amount of delay of the signal input to the input terminal 2. do.

The input stage amplifier section 3 and the output stage amplifier section 5 are composed of a current mode logic circuit or a Cherry-Hooper amplifier circuit with an arbitrary number of amplifier stages, and have the role of a buffer and operate as a limiting amplifier that defines the potential of the output signal. do.

The branching and combining section 4 is configured with an arbitrary number of branches and combinations, and branches the signal from the input stage amplifier section 3, combines the branched signals, and inputs the signal to the output stage amplifier section 5. FIG. 1 shows the basic configuration of the variable delay circuit 1 in the case of one stage of branching and combining, and FIG. 2 shows the basic configuration of the variable delay circuit 1 in the case of two stages of branching and combining.

The branching and combining section 4 includes a first amplifier circuit 11 and a second amplifier circuit 12 having different numbers of amplifier stages. Note that in the present invention, the path with the smaller number of amplifier stages (the first amplifier circuit 11 in FIGS. 1 and 2) is defined as the minimum delay route r1, and the path with the larger number of amplifier stages (the first amplifier circuit 11 in FIGS. 1 and 2) is defined as the minimum delay route r1. The path of the second amplifier circuit 12) is defined as the maximum delay side path r2.

An external power supply 7 is connected to the amplifier 11A of the first amplifier circuit 11 (minimum delay side path r1) in the variable delay circuit 1A in FIG. 1 via a bias terminal A for delay control. The applied voltage of A is variably controlled. Further, an external power supply 8 is connected to the output side amplifier 12A of the second amplifier circuit 12 (maximum delay side path r2) via a bias terminal B for delay control, and the external power supply 8 applies the bias terminal B. Voltage is variably controlled.

An external power supply 7 is connected to each stage of the amplifier 11A of the first amplifier circuit 4A (minimum delay side path r1) in the variable delay circuit 1B in FIG. The applied voltage is variably controlled. Further, an external power supply 8 is connected to the output side amplifier 12A of each stage of the second amplifier circuit 4B (maximum delay side path r2) via a bias terminal B, and the external power supply 8 applies the voltage applied to the bias terminal B. is variably controlled.

In the variable delay circuit 1 (1A, 1B) with the above configuration, when a signal is input from the input terminal 2 to the input stage amplifier section 3, after branching by the branching and combining section 4, the amplifier circuits 11, 12 of each path r1, r2 By changing the voltage applied to the bias terminals A and B connected to the amplifiers 11A and 12A, and changing the drive current amount of the amplifiers 11A and 12A, the output amplitude of the first amplifier circuit 11 and the second amplifier circuit 12 can be changed. Change the ratio. Since there is a delay difference between the minimum delay side path r1 and the maximum delay side path r2, if the ratio of the output amplitudes of the first amplifier circuit 11 and the second amplifier circuit 12 changes, the delay time of the combined output will change. Looks like it's changed. The variable delay circuit 1 (1A, 1B) is a circuit that uses this mechanism to vary the delay time of an output with respect to an input.

[Simulation data of variable delay circuit]
In order to find problems with the variable delay circuit 1 having the above configuration, the inventors conducted a simulation by varying the bias voltage within the range of ±2 V in the variable delay circuit 1B of FIG.

In this simulation, when varying the bias voltage in the range of ±2V, bias terminals A and B are in a balanced relationship, and when the bias voltage is ±0V, the drive currents of bias terminal A and bias terminal B are designed to be equal. Then, by changing the voltage in a positive/negative relation with ±0V as the base point, the sum of the drive currents of bias terminal A and bias terminal B is kept almost constant, and the output amplitude after synthesis remains almost unchanged, only the delay amount changes. Can be changed.

Note that the bias terminal A and the bias terminal B can be operated at voltages having different absolute values. In that case, the balance between the drive currents of bias terminal A and bias terminal B will be lost, and the output amplitude after synthesis will change depending on the bias. Therefore, the best condition is for the bias voltages of the bias terminals A and B to be swung in a positive/negative relationship with ±0V as the base point. However, the definition of how to apply the bias voltage is not limited to applying a voltage with a positive/negative inversion relationship.

As a result, it was confirmed that in the above simulation results, a variable delay amount of Δ6.6 ps during 32 GHz operation and Δ6.0 ps during 64 GHz operation was obtained in the bias voltage range of ±2 V.

[Issues with variable delay circuits]
Ideally, the variable delay circuit 1 should have a constant output amplitude even if the bias voltage is changed, but according to the simulation results described above, the waveform shown in FIG. As shown in FIG. 2, a problem was found in that the amplitude (Voh, Vol) of the output after synthesis changes.

Note that FIG. 13 is a diagram showing the change in amplitude of the final post-synthesis output (64 GHz) with respect to the bias voltage, and shows the waveform on the positive side of the differential. In Figure 13, the dotted line is the waveform when +2V is applied to bias terminal A and -2V is applied to bias terminal B (at the minimum delay), the solid line is the waveform when ±0V is applied to bias terminals A and B (at the time of balance), and the dashed line is the waveform The waveform is shown when -2V is applied to bias terminal A and +2V is applied to bias terminal B (at maximum delay).

Furthermore, as a result of investigating the cause of the problem in which the amplitude of the output after synthesis changes due to the bias voltage, when comparing the minimum delay side path r1 and the maximum delay side path R2 in the branch combining section 4, the minimum delay side path r1 and the maximum delay side path r1 and the maximum delay side path R2 are found to be It was found that there is a difference in frequency characteristics in the delay side path r2.

In addition, the variable delay circuit 1 can be applied, for example, by inputting a pattern signal generated by a signal generator to an object to be measured, and receiving a signal reflected from the object to be measured in response to this input by an error detector. The reference clock signal input from the outside of the bit error measuring device that detects errors is distributed, divided, and multiplied by the input clock processing section, and the timing of the reference clock signal is finely adjusted by the variable delay circuit 1 . When this reference clock signal, which has been finely adjusted in the time axis direction, is generated by a digital signal processing unit, for example, a signal for multiple lanes, the skew that occurs between lanes is removed, and the signal waveform eye is adjusted to the timing when the eye of the signal waveform is most open. In such a case, if there is a difference in the frequency characteristics of the two paths r1 and r2 over the entire operating frequency range, it will not be possible to stably output a delayed clock signal, and the digital signal processing unit or D/A converter will There is a problem in that a data signal containing an error is transmitted from the device to the device under test, resulting in an error in the measurement result of the device under test.

Therefore, in the present invention, by reducing the difference in frequency characteristics between the minimum delay side path r1 and the maximum delay side path r2 in the branch/combiner 4, changes in the output amplitude with respect to the bias voltage are suppressed.

Further, the present invention is intended to be used for measuring instruments, and is required to be compatible with a wide operating frequency range, such as from 1 GHz to 64 GHz. Therefore, it is insufficient to adjust the output amplitude under only one arbitrary frequency condition, and changes in the output amplitude with respect to the bias voltage are suppressed over the entire operating frequency range.

Hereinafter, the configuration of each embodiment of the branching/synthesizing section 4 provided between the input stage amplifier section 3 and the output stage amplifier section 5 in FIG. 1 or FIG. will be explained with reference to the drawings.

[First embodiment]
The configuration of the branching and combining section 4 (4A) of the first embodiment will be described with reference to FIG. 3. Note that in the first amplifier circuit 11 and the second amplifier circuit 12 in FIG. 3, the same components are given the same numbers.

First, the basic configuration of the branching and combining section 4A will be explained. As shown in FIG. 3, the basic configuration of the branch/combiner 4A is such that the first amplifier circuit 11 of the minimum delay side path r1 is composed of a one-stage current mode logic circuit 11a, and the second amplifier circuit of the maximum delay side path r2 is configured as follows. The amplifier circuit 12 is composed of a first stage current mode logic circuit 12a, an emitter follower circuit 12b, and a second stage current mode logic circuit 12c. This configuration has a large number of stages of current mode logic circuits.

In the current mode logic circuit 11a of the first amplifier circuit 11, a signal from the input stage amplifier section 3 is input to the bases of the npn transistors Tr1 and Tr2 via Port1: In(+) and Port3: In(-). , a signal is output from the collectors of transistors Tr1 and Tr2 to the output stage amplifier section 5 via Port2:Out(+) and Port4:Out(-).

In the current mode logic circuit 11a, the collector of the transistor Tr1 is connected to VCC (plus power supply) via a resistor R1 as an output load. Similarly, the collector of transistor Tr2 is connected to VCC via resistor R2 as an output load. Further, resistors R3 and R4 are connected in series between the emitters of the transistors Tr1 and Tr2, and an npn transistor Tr3 is connected between the midpoint thereof and VEE (negative power supply). Further, the transistor Tr3 has an emitter connected to VEE via a resistor R5, and a base connected to a bias terminal A via a resistor R6 and a bias circuit 13.

The bias circuit 13 is composed of a current mirror circuit, in which the collector and base of the npn transistor Tr4 are short-circuited, the collector of the transistor Tr4 is connected to the bias terminal A via the resistor R7, and the emitter of the transistor Tr4 is connected to the resistor. It is connected to VEE via R8, and has a diode-like connection with the collector-base side as an anode and the emitter side as a cathode. In the bias circuit 13, when a potential difference greater than or equal to the threshold (ON) voltage of the transistor Tr4 occurs between the base of the transistor Tr4 and VEE, the transistor Tr4 is turned on and current flows. On the other hand, if the potential difference is less than the threshold (ON) voltage of the transistor Tr4, the transistor Tr4 is turned off and no current flows. Furthermore, the bases of the transistors Tr3 and Tr4 are short-circuited via a damping resistor R6. Therefore, when a current flows through the transistor Tr4, a current also flows through the transistor Tr3. On the other hand, when no current flows through the transistor Tr4, no current also flows through the transistor Tr3.

The first stage current mode logic circuit 12a of the second amplifier circuit 12 connects the bases of the npn transistors Tr1 and Tr2 to the input stage amplifier section 3 via Port1: In(+) and Port3: In(-). A signal is input, and the signal is output from the collector of the second stage current mode logic circuit 12c via the emitter follower circuit 12b to the output stage amplifier section 5 via Port 2: Out (+) and Port 4: Out (-). .

In the first-stage and second-stage current mode logic circuits 12a and 12c, the collectors of transistors Tr1 are connected to VCC via a resistor R1 as an output load. Similarly, the collector of transistor Tr2 is connected to VCC via resistor R2 as an output load. Furthermore, resistors R3 and R4 are connected in series between the emitters of transistors Tr1 and Tr2, and the midpoint thereof is connected to VEE via resistor R5.

In the second-stage current mode logic circuit 12c, an npn transistor Tr3 is connected between the midpoint between the resistors R3 and R4 and the resistor R5. The transistor Tr3 has an emitter connected to VEE via a resistor R5, and a base connected to a bias terminal B via a resistor R6 and a bias circuit 13.

The bias circuit 13 is composed of a current mirror circuit, in which the collector and base of the npn transistor Tr4 are short-circuited, the collector of the transistor Tr4 is connected to the bias terminal B via the resistor R7, and the emitter of the transistor Tr4 is connected to the resistor. It is connected to VEE via R8, and has a diode-like connection with the collector-base side as an anode and the emitter side as a cathode. In the bias circuit 13, when a potential difference greater than or equal to the threshold (ON) voltage of the transistor Tr4 occurs between the base of the transistor Tr4 and VEE, the transistor Tr4 is turned on and current flows. On the other hand, if the potential difference is less than the threshold (ON) voltage of the transistor Tr4, the transistor Tr4 is turned off and no current flows. Furthermore, the bases of the transistors Tr3 and Tr4 are short-circuited via a damping resistor R6. Therefore, when a current flows through the transistor Tr4, a current also flows through the transistor Tr3. On the other hand, when no current flows through the transistor Tr4, no current also flows through the transistor Tr3.

In the emitter follower circuit 12b of the second amplifier circuit 12, the base of an npn transistor Tr5 is connected to the collector of the transistor Tr1 of the first stage current mode logic circuit 12a, and the transistor Tr2 of the first stage current mode logic circuit 12a is connected to the base of the npn transistor Tr5. The base of an npn transistor Tr6 is connected to the collector of the transistor Tr6.

The transistor Tr5 in the emitter follower circuit 12b has a collector connected to VCC, an emitter connected to VEE via a resistor R9, and also connected to the base of the transistor Tr2 of the second stage current mode logic circuit 12c. Similarly, the transistor Tr6 has a collector connected to VCC, an emitter connected to VEE via a resistor R10, and also connected to the base of the transistor Tr1 of the second stage current mode logic circuit 12c.

In the branching and combining unit 4A of the first embodiment, in the basic configuration described above, the transistors Tr1, A capacitor C is connected in parallel with resistors R3 and R4 between the emitters of Tr2. Capacitor C and resistors R3 and R4 constitute a high-pass filter, and capacitor C passes high frequency components without passing low frequency components. Thereby, it is possible to compensate for the frequency characteristics of the maximum delay side path r2, reduce the difference in frequency characteristics between the minimum delay side path r1 and the maximum delay side path r2, and suppress changes in the output amplitude with respect to the bias voltage.

In the example of FIG. 3, a capacitor C is connected in parallel with the resistors R3 and R4 between the emitters of the transistors Tr1 and Tr2 of both the first and second stage current mode logic circuits 12a and 12c of the maximum delay side path r2. However, the capacitor C may be connected in parallel with the resistors R3 and R4 between the emitters of the transistors Tr1 and Tr2 of either the first-stage or second-stage current mode logic circuits 12a and 12c. .

By the way, when the capacitor C is additionally connected in parallel with the resistors R3 and R4, the delay amount of the maximum delay side path r2 becomes small, and a problem arises in that the delay difference with the minimum delay side path r1 = variable delay amount cannot be obtained.

In order to solve this problem, in the branching and combining section 4A of the first embodiment, in the basic configuration described above, the output of the emitter follower circuit 12b of the maximum delay side path r2 and the input of the second stage current mode logic circuit 12c are Transmission line Z is connected to. Thereby, the delay amount can be earned to compensate for the decrease in the variable delay amount.

Specifically, in the variable delay circuit 1 that employs the branching and combining section 4A of the first embodiment, improvements are made by adjusting the constants of the capacitor C and the resistor R so as to suppress changes in amplitude with respect to the bias voltage. As the final post-synthesis output (64 GHz), the waveform shown in FIG. 9 could be obtained through simulation. In addition, for the 64 GHz output in Figure 9, the dotted line shows the waveform when +2V is applied to bias terminal A and -2V is applied to bias terminal B (at the minimum delay), and the solid line shows the waveform when ±0V is applied to bias terminals A and B (at the time of balance). ), and the dashed-dotted line shows the waveform when -2V is applied to bias terminal A and +2V is applied to bias terminal B (at maximum delay).

As shown in Figure 10, after the improvement (64GHz output waveform in Figure 9), the amplitude change due to bias voltage dependence is reduced by about 62.5% compared to before improvement (64GHz output waveform in Figure 13). I was able to suppress it. Furthermore, as shown in FIG. 11, the variable delay amount after the improvement was able to be maintained at the same level as compared to before the improvement. Note that the bias voltage of the bias terminal A was set to a value obtained by inverting the bias voltage of the bias terminal B ± (positive and negative). For example, if the bias voltage at bias terminal B is +1.5V, the bias voltage at bias terminal A is -1.5V.

[Second embodiment]
The configuration of the branching and combining section 4 (4B) of the second embodiment will be described with reference to FIG. 4. In addition, in FIG. 4, the same basic configuration as the branching and combining section 4A of the first embodiment described above is given the same number, and the explanation thereof will be omitted.

In the branch/combiner 4B of the second embodiment, in the basic configuration described above, the transistors Tr1 and Tr2 of the first stage current mode logic circuit 12a and the second stage current mode logic circuit 12c of the maximum delay side path r2 are A coil L is connected in series with resistors R1 and R2 as output loads. Thereby, it is possible to compensate for the frequency characteristics of the maximum delay side path r2, reduce the difference in frequency characteristics between the minimum delay side path r1 and the maximum delay side path r2, and suppress changes in the output amplitude with respect to the bias voltage.

In the example of FIG. 4, the coil L is connected in series with the resistors R1 and R2 as output loads of both the first and second stage current mode logic circuits 12a and 12c of the maximum delay side path r2. However, a configuration may also be adopted in which the coil L is connected in series with the resistors R1 and R2 as output loads of either the first-stage or second-stage current mode logic circuits 12a and 12c.

In addition, in the branching and combining section 4B of the second embodiment, in order to solve the problem that the delay amount of the maximum delay side path r2 becomes smaller due to the additional connection of the coil L, in the basic configuration described above, the emitter of the maximum delay side path r2 is A transmission line Z is connected between the output of the follower circuit 12b and the input of the second stage current mode logic circuit 12c. Thereby, the delay amount can be earned to compensate for the decrease in the variable delay amount.

[Third embodiment]
The configuration of the branching and combining section 4 (4C) of the third embodiment will be described with reference to FIG. 5. Note that in FIG. 5, the same basic configuration as the branching and combining section 4A of the first embodiment described above is given the same reference numeral, and the explanation thereof will be omitted.

In the branch/combiner 4C of the third embodiment, in the basic configuration described above, a capacitor C is connected in parallel with the resistors R3, R4 between the emitters of the transistors Tr1, Tr2 of the current mode logic circuit 11a of the minimum delay side path r1. ing. Capacitor C and resistors R3 and R4 constitute a high-pass filter, and capacitor C passes high frequency components without passing low frequency components. Thereby, it is possible to compensate for the frequency characteristics of the minimum delay side path r1, reduce the difference in frequency characteristics between the minimum delay side path r1 and the maximum delay side path r2, and suppress changes in the output amplitude with respect to the bias voltage.

Furthermore, in the branching/synthesizing section 4C of the third embodiment, the additional connection of the capacitor C causes a problem in that the waveform delay difference becomes too large and the waveform amplitude becomes small when balanced (±0 V is applied). In order to solve the above problem, in the basic configuration described above, the transmission line Z is connected to the input of the current mode logic circuit 11a of the minimum delay side path r1. Thereby, the delay amount can be earned to compensate for the decrease in the variable delay amount.

[Fourth embodiment]
The configuration of the branching and combining section 4 (4D) of the fourth embodiment will be described with reference to FIG. 6. In addition, in FIG. 6, the same basic configuration as the branching and combining section 4A of the first embodiment described above is given the same reference numeral, and the explanation thereof will be omitted.

In the branching and combining unit 4D of the fourth embodiment, in the basic configuration described above, the coil L is connected in series with the resistors R1 and R2 as output loads of the transistors Tr1 and Tr2 of the current mode logic circuit 11a of the minimum delay side path r1. are doing. Thereby, it is possible to compensate for the frequency characteristics of the minimum delay side path r1, reduce the difference in frequency characteristics between the minimum delay side path r1 and the maximum delay side path r2, and suppress changes in the output amplitude with respect to the bias voltage.

Further, in the branching/synthesizing section 4C of the fourth embodiment, the additional connection of the coil L causes the waveform delay difference to become too large, resulting in a problem that the waveform amplitude becomes small when balanced (±0 V is applied). In order to solve the above problem, in the basic configuration described above, the transmission line Z is connected to the input of the current mode logic circuit 11a of the minimum delay side path r1. Thereby, the delay amount can be earned to compensate for the decrease in the variable delay amount.

[Fifth embodiment]
The configuration of the branching and combining section 4 (4E) of the fifth embodiment will be described with reference to FIG. 7. In addition, in FIG. 7, the same basic configuration as the branching and combining section 4A of the first embodiment described above is given the same reference numeral, and the explanation thereof will be omitted.

In the branching/synthesizing unit 4E of the fifth embodiment, in the basic configuration described above, a capacitor C with respect to VCC is connected to the outputs of the transistors Tr1 and Tr2 of the first stage current mode logic circuit 12a of the maximum delay side path r2. are doing. That is, a capacitor C is connected between the collectors of the transistors Tr1 and Tr2 of the first stage current mode logic circuit 12a and VCC. Thereby, it is possible to increase the amount of loss at high frequencies in the maximum delay side path r2, reduce the difference in frequency characteristics between the minimum delay side path r1 and the maximum delay side path r2, and suppress changes in output amplitude with respect to bias voltage.

Furthermore, in the branching and combining section 4E of the fifth embodiment, in the basic configuration described above, the transmission line Z is connected to the input of the current mode logic circuit 11a of the minimum delay side path r1. Thereby, the delay amount can be earned to compensate for the decrease in the variable delay amount.

[Sixth embodiment]
The configuration of the branching and combining section 4 (4F) of the sixth embodiment will be described with reference to FIG. 8. In addition, in FIG. 8, the same basic configuration as the branching and combining section 4A of the first embodiment described above is given the same reference numeral, and the explanation thereof will be omitted.

The basic configuration of the branching and combining section 4F is that the first amplifier circuit 11 of the minimum delay side path r1 is composed of a first stage current mode logic circuit 11a, an emitter follower circuit 11b, and a second stage current mode logic circuit 11c. , the second amplifier circuit 12 of the maximum delay side path r2 is the first stage current mode logic circuit 12a, the first stage emitter follower circuit 12b, the second stage current mode logic circuit 12c, and the second stage emitter follower circuit. 12d, and a third stage current mode logic circuit 12e.

In the branching and combining section 4F of the sixth embodiment, in the basic configuration described above, a capacitor C with respect to VCC is connected to the output of the first stage current mode logic circuit 11a of the minimum delay side path r1. That is, a capacitor C is connected between the collectors of the transistors Tr1 and Tr2 of the first stage current mode logic circuit 11a and VCC. Since this point is not directly connected to the branching/combining point of the minimum delay side path r1 and the maximum delay side path r2, it does not affect the amplifier circuit 12 of the maximum delay side path r2, and the high frequency of the maximum delay side path r2. The amount of loss can be increased. Thereby, it is possible to compensate for the frequency characteristics of the minimum delay side path r1, reduce the difference in frequency characteristics between the minimum delay side path r1 and the maximum delay side path r2, and suppress changes in the output amplitude with respect to the bias voltage.

In the basic configuration of FIG. 3, it is possible to increase the amount of loss at high frequencies by adding a capacitor C with respect to VCC to the input or output of the current mode logic circuit 11a of the minimum delay side path r1. However, the current mode logic circuit 11a of the minimum delay side path r1 is directly connected to the maximum delay side path r2 via a branch or combination point. Therefore, if a capacitor is added to the input or output of the current mode logic circuit 11a on the minimum delay side path r1, the loss on the maximum delay side path r2 will also increase. As a result, it is not possible to reduce the difference in frequency characteristics between the minimum delay side path r1 and the maximum delay side path r2, and the above-mentioned problem cannot be solved.

In addition, in the branching and combining section 4F of the sixth embodiment, in the basic configuration described above, between the output of the first stage emitter follower circuit 12b of the maximum delay side path r2 and the input of the second stage current mode logic circuit 12c, A transmission line Z is connected between the inputs of the second stage emitter follower circuit 12d and the third stage current mode logic circuit 12e. Thereby, the delay amount can be earned to compensate for the decrease in the variable delay amount.

In the example of FIG. 8, between the output of the first stage emitter follower circuit 12b and the input of the second stage current mode logic circuit 12c of the maximum delay side path r2, and between the output of the second stage emitter follower circuit 12d and 3. Although the transmission line Z is connected between the inputs of the current mode logic circuit 12e in the second stage, the output of the emitter follower circuit 12b in the first stage of the maximum delay side path r2 and the current mode logic circuit 12c in the second stage are connected to each other. The transmission line Z may be connected either between the inputs or between the output of the second stage emitter follower circuit 12d and the input of the third stage current mode logic circuit 12e.

Incidentally, in the branching and combining sections 4A to 4F of each of the embodiments described above, the difference in the number of amplifier stages between the first amplifier circuit 11 and the second amplifier circuit 12 is one stage, but the present invention is not limited to this. It can be set according to the operating frequency. Specifically, the difference in the number of amplifier stages between the first amplifier circuit 11 and the second amplifier circuit 12 and the line length of the transmission line Z are the minimum delay side path r1 and the maximum delay when the reciprocal of the operating frequency is one period. The delay difference of the side route r2 is set to be smaller than 1/5 cycle.

[Application example]
The variable delay circuit 1 equipped with the branching/synthesizing section 4 (any one of 4A to 4F) configured as described above inputs the pattern signal generated by the signal generator 21 to the object under test W, as shown in FIG. , it can be used in the internal circuit of the signal generator 21 in the bit error measuring device 23 which detects errors by receiving the signal returned from the object under test W in response to this input in the error detector 22. The signal generating device 21 shown in FIG. 12 to which the variable delay circuit 1 of the present invention is applied is compatible with the transmission of NRZ/PAM signals from low speeds such as 2 Gbaud to high speeds of 100 Gbaud or more, and uses externally input reference clock signals. The input clock processing section 21a performs distribution and frequency division/multiplying processing, the variable delay circuit 1 finely adjusts the timing of the reference clock signal, and the finely adjusted reference clock signal is used to send the signal to the digital signal processing section 21b. The D/A converter 21c generates a pattern signal, and the D/A converter 21c converts the generated pattern signal into an analog signal and inputs it to the object W to be measured. To explain further, when the reference clock signal is input from the input clock processing section 21a, the variable delay circuit 1 in the signal generating device 21 of FIG. 12 sends the reference clock signal finely adjusted in the time axis direction to the digital signal processing section 21b. Output. This reference clock signal that has been finely adjusted in the time axis direction is used to remove skews that occur between lanes when the digital signal processing unit 21b generates signals for multiple lanes, and adjusts the timing at which the eye of the signal waveform opens the most. .

Note that the branching and combining section 4 having the above-described configuration can be applied not only to fine adjustment of the reference clock signal of the signal generating device 21 of FIG. 12, but also as a variable delay circuit and variable delay method for data signals.

In this way, according to the present embodiment, the voltages applied to the bias terminal A of the first amplifier circuit 11 and the bias terminal B of the second amplifier circuit 12 are changed, and the voltages applied to the bias terminal A of the first amplifier circuit 11 and the bias terminal B of the second amplifier circuit 12 are changed. When varying the delay amount by changing the output amplitude ratio of the amplifier circuit 12, a physical delay difference in the branching and combining section 4 is created by the difference in the number of amplifier stages between the first amplifier circuit 11 and the second amplifier circuit 12, By adopting any of the branching and combining sections 4 (4A to 4F) shown in FIGS. 3 to 8, and adding a capacitor C and a coil L, the difference in frequency characteristics between the minimum delay side path r1 and the maximum delay side path r2 is reduced, Changes in output amplitude with respect to bias voltage can be suppressed.

In addition, by adding and adjusting the transmission line Z in any of the adopted branch/combiner sections 4 (4A to 4F) in Figures 3 to 8, the above-mentioned addition of the capacitor C and coil L has changed. Delay differences can be compensated for. As a result, it is possible to realize a variable delay circuit with stable output amplitude against changes in bias voltage over the entire wide range of operating frequencies, such as from 1 to 64 GHz.

Although the best embodiments of the variable delay circuit, variable delay method, signal generation device, and signal generation method according to the present invention have been described above, the present invention is not limited to the description and drawings based on this embodiment. That is, it goes without saying that all other forms, embodiments, operational techniques, etc. made by those skilled in the art based on this form are included in the scope of the present invention.

1 (1A, 1B) Variable delay circuit 2 Input terminal 2a Plus input 2b Minus input 3 Input stage amplifier section 4 (4A to 4F) Branch synthesis section 5 Output stage amplifier section 6 Output terminal 6a Plus output 6b Minus output 7, 8 External Power supply A, B Bias terminal r1 Minimum delay side path r2 Maximum delay side path 11 First amplifier circuit 11A Amplifier 11a, 11c Current mode logic circuit 11b Emitter follower circuit 12 Second amplifier circuit 12A Amplifier 12a, 12c, 12e Logic circuit 12b, 12d Emitter follower circuit 13 Bias circuit 21 Signal generator 21a Input clock processing unit 21b Digital signal processing unit 21c D/A converter 22 Error detector 23 Bit error measuring device Tr1 to Tr6 Transistor R1 to R10 Resistor C Capacitor L coil Z transmission line

Claims (12)

A branch synthesis unit (4) having a first amplifier circuit (11) and a second amplifier circuit (12) with different numbers of amplifier stages of the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay side path (r1), which is the path with the smaller number of amplifier stages of the current mode logic circuit. Let the route with the largest delay be the route with the largest delay (r2),
A capacitor (C) is connected in parallel with a resistor between emitters of at least one current mode logic circuit of the maximum delay side path,
A transmission line (Z) is connected between at least one output of an emitter follower circuit connected between the current mode logic circuits of the maximum delay side path and an input of a subsequent current mode logic circuit,
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. The delay difference is set to be smaller than 1/5 period,
The applied voltage is changed so that the sum of drive currents of bias terminals (A, B) provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay path are A pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction by a variable delay circuit that synthesizes and outputs signals by changing the ratio of output amplitudes of the side paths is input to the device under test. A signal generating device characterized in that it is used in a measuring device that receives a signal reflected from an object to be measured . A branch synthesis unit (4) having a first amplifier circuit (11) and a second amplifier circuit (12) with different numbers of amplifier stages of the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay side path (r1), which is the path with the smaller number of amplifier stages of the current mode logic circuit. Let the route with the largest delay be the route with the largest delay (r2),
A coil (L) is connected in series with a resistance of an output load of at least one current mode logic circuit of the maximum delay side path,
A transmission line (Z) is connected between at least one output of an emitter follower circuit connected between the current mode logic circuits of the maximum delay side path and an input of a subsequent current mode logic circuit,
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. The delay difference is set to be smaller than 1/5 period,
The applied voltage is changed so that the sum of drive currents of bias terminals (A, B) provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay path are A pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction by a variable delay circuit that synthesizes and outputs signals by changing the ratio of output amplitudes of the side paths is input to the device under test. A signal generating device characterized in that it is used in a measuring device that receives a signal reflected from an object to be measured . A branch synthesis unit (4) having a first amplifier circuit (11) and a second amplifier circuit (12) with different numbers of amplifier stages of the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay side path (r1), which is the path with the smaller number of amplifier stages of the current mode logic circuit. Let the route with the largest delay be the route with the largest delay (r2),
A capacitor (C) is connected in parallel with a resistor between emitters of at least one current mode logic circuit of the minimum delay side path,
A transmission line (Z) is connected to the input of at least one current mode logic circuit of the minimum delay side path,
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. The delay difference is set to be smaller than 1/5 period,
The applied voltage is changed so that the sum of drive currents of bias terminals (A, B) provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay path are A pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction by a variable delay circuit that synthesizes and outputs signals by changing the ratio of output amplitudes of the side paths is input to the device under test. A signal generating device characterized in that it is used in a measuring device that receives a signal reflected from an object to be measured . A branch synthesis unit (4) having a first amplifier circuit (11) and a second amplifier circuit (12) with different numbers of amplifier stages of the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay side path (r1), which is the path with the smaller number of amplifier stages of the current mode logic circuit. Let the route with the largest delay be the route with the largest delay (r2),
A coil (L) is connected in series with an output load resistance of at least one current mode logic circuit of the minimum delay side path,
A transmission line (Z) is connected to the input of at least one current mode logic circuit of the minimum delay side path,
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. The delay difference is set to be smaller than 1/5 period,
The applied voltage is changed so that the sum of drive currents of bias terminals (A, B) provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay path are A pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction by a variable delay circuit that synthesizes and outputs signals by changing the ratio of output amplitudes of the side paths is input to the device under test. A signal generating device characterized in that it is used in a measuring device that receives a signal reflected from an object to be measured . A branch synthesis unit (4) having a first amplifier circuit (11) and a second amplifier circuit (12) with different numbers of amplifier stages of the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay side path (r1), which is the path with the smaller number of amplifier stages of the current mode logic circuit. Let the route with the largest delay be the route with the largest delay (r2),
A capacitor (C) is connected between the output of the current mode logic circuit of the input stage of the maximum delay side path and a positive power supply (VCC),
A transmission line (Z) is connected to the input of at least one current mode logic circuit of the minimum delay side path,
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. The delay difference is set to be smaller than 1/5 period,
The applied voltage is changed so that the sum of drive currents of bias terminals (A, B) provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay path are A pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction by a variable delay circuit that synthesizes and outputs signals by changing the ratio of output amplitudes of the side paths is input to the device under test. A signal generating device characterized in that it is used in a measuring device that receives a signal reflected from an object to be measured . A branching/synthesizing section (4) having a first amplifier circuit (11) and a second amplifier circuit (12) including a plurality of stages of current mode logic circuits having different numbers of amplifier stages,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay side path (r1), which is the path with the smaller number of amplifier stages of the current mode logic circuit. Let the route with the largest delay be the route with the largest delay (r2),
A capacitor (C) is connected between the output of the current mode logic circuit of the input stage of the minimum delay side path and a positive power supply (VCC),
A transmission line (Z) is connected between at least one output of an emitter follower circuit connected between the current mode logic circuits of the maximum delay side path and an input of a subsequent current mode logic circuit,
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. The delay difference is set to be smaller than 1/5 period,
The applied voltage is changed so that the sum of drive currents of bias terminals (A, B) provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay path are A pattern signal generated based on a clock signal that has been finely adjusted in the time axis direction by a variable delay circuit that synthesizes and outputs signals by changing the ratio of output amplitudes of the side paths is input to the device under test. A signal generating device characterized in that it is used in a measuring device that receives a signal reflected from an object to be measured . Using a branch synthesis unit (4) having a first amplifier circuit (11) and a second amplifier circuit (12) with different numbers of amplifier stages in the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay side path (r1), which is the path with the smaller number of amplifier stages of the current mode logic circuit. Let the route with the largest delay be the route with the largest delay (r2),
connecting a capacitor (C) in parallel with the emitter-to-emitter resistor of at least one current mode logic circuit of the maximum delay side path;
connecting a transmission line (Z) between at least one output of an emitter follower circuit connected between the current mode logic circuits of the maximum delay side path and an input of a subsequent current mode logic circuit;
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. setting the delay difference to be smaller than 1/5 period;
The applied voltage is changed so that the sum of drive currents of bias terminals (A, B) provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay path are inputting a pattern signal generated based on a clock signal finely adjusted in the time axis direction by a variable delay method to the device under test; A signal generation method characterized in that it is used in a measuring device that receives a signal reflected from the object to be measured as a result of the above . Using a branch synthesis unit (4) having a first amplifier circuit (11) and a second amplifier circuit (12) with different numbers of amplifier stages in the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay side path (r1), which is the path with the smaller number of amplifier stages of the current mode logic circuit. Let the route with the largest delay be the route with the largest delay (r2),
connecting a coil (L) in series with a resistance of an output load of at least one current mode logic circuit of the maximum delay side path;
connecting a transmission line (Z) between at least one output of an emitter follower circuit connected between the current mode logic circuits of the maximum delay side path and an input of a subsequent current mode logic circuit;
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. setting the delay difference to be smaller than 1/5 period;
The applied voltage is changed so that the sum of drive currents of bias terminals (A, B) provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay path are inputting a pattern signal generated based on a clock signal finely adjusted in the time axis direction by a variable delay method to the device under test; A signal generation method characterized in that it is used in a measuring device that receives a signal reflected from the object to be measured as a result of the above . Using a branch synthesis unit (4) having a first amplifier circuit (11) and a second amplifier circuit (12) with different numbers of amplifier stages in the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay side path (r1), which is the path with the smaller number of amplifier stages of the current mode logic circuit. Let the route with the largest delay be the route with the largest delay (r2),
connecting a capacitor (C) in parallel with the emitter-to-emitter resistor of at least one current mode logic circuit of the minimum delay side path;
connecting a transmission line (Z) to the input of at least one current mode logic circuit of the minimum delay side path;
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. setting the delay difference to be smaller than 1/5 period;
The applied voltage is changed so that the sum of drive currents of bias terminals (A, B) provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay path are inputting a pattern signal generated based on a clock signal finely adjusted in the time axis direction by a variable delay method to the device under test; A signal generation method characterized in that it is used in a measuring device that receives a signal reflected from the object to be measured as a result of the above . Using a branch synthesis unit (4) having a first amplifier circuit (11) and a second amplifier circuit (12) with different numbers of amplifier stages in the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay side path (r1), which is the path with the smaller number of amplifier stages of the current mode logic circuit. Let the route with the largest delay be the route with the largest delay (r2),
connecting a coil (L) in series with a resistance of an output load of at least one current mode logic circuit of the minimum delay side path;
connecting a transmission line (Z) to the input of at least one current mode logic circuit of the minimum delay side path;
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. setting the delay difference to be smaller than 1/5 cycle;
The applied voltage is changed so that the sum of drive currents of bias terminals (A, B) provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay path and the maximum delay path are inputting a pattern signal generated based on a clock signal finely adjusted in the time axis direction using a variable delay method to the device under test; A signal generation method characterized in that it is used in a measuring device that receives a signal reflected from the object to be measured as a result of the above . Using a branch synthesis unit (4) having a first amplifier circuit (11) and a second amplifier circuit (12) with different numbers of amplifier stages in the current mode logic circuit,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay side path (r1), which is the path with the smaller number of amplifier stages of the current mode logic circuit. Let the route with the largest delay be the route with the largest delay (r2),
connecting a capacitor (C) between the output of the current mode logic circuit of the input stage of the maximum delay side path and a positive power supply (VCC);
connecting a transmission line (Z) to the input of at least one current mode logic circuit of the minimum delay side path;
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. setting the delay difference to be smaller than 1/5 period;
The applied voltage is changed so that the sum of drive currents of bias terminals (A, B) provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay path are inputting a pattern signal generated based on a clock signal finely adjusted in the time axis direction by a variable delay method to the device under test; A signal generation method characterized in that it is used in a measuring device that receives a signal reflected from the object to be measured as a result of the above . Using a branching and combining section (4) having a first amplifier circuit (11) and a second amplifier circuit (12) including multiple stages of current mode logic circuits having different numbers of amplifier stages,
Of the two paths of the branching and combining section to which the signal is branched and inputted, the path with the smaller number of amplifier stages of the current mode logic circuit is designated as the minimum delay side path (r1), which is the path with the smaller number of amplifier stages of the current mode logic circuit. Let the route with the largest delay be the route with the largest delay (r2),
connecting a capacitor (C) between the output of the current mode logic circuit of the input stage of the minimum delay side path and a positive power supply (VCC);
connecting a transmission line (Z) between at least one output of an emitter follower circuit connected between the current mode logic circuits of the maximum delay side path and an input of a subsequent current mode logic circuit;
When the reciprocal of the operating frequency is one period, the difference in the number of amplifier stages between the first amplifier circuit and the second amplifier circuit and the line length of the transmission line are defined as the minimum delay side path and the maximum delay side path. setting the delay difference to be smaller than 1/5 period;
The applied voltage is changed so that the sum of drive currents of bias terminals (A, B) provided in each of the first amplifier circuit and the second amplifier circuit is constant, and the minimum delay side path and the maximum delay path are inputting a pattern signal generated based on a clock signal finely adjusted in the time axis direction using a variable delay method to the device under test; A signal generation method characterized in that it is used in a measuring device that receives a signal reflected from the object to be measured as a result of the above .

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