JP2006114969A - Oscillator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillator capable of performing phase control of an oscillation signal with a fine timewise resolution, and having small circuit scale and low power consumption. <P>SOLUTION: The oscillator 10 comprises inverters arranged in matrix seven by seven in a row direction and a column direction. The inverters R11-R77 arranged in the column direction are coupled annularly to form ring oscillators OC1-OC7 of seven sets in seven stages, the nodes between inverters of each stage of each of the ring oscillators OC1-OC7 are connected by inverters arranged in the column direction, and the inverters F11-F77 arranged in the row direction are coupled annularly, thereby multiplexing each of the ring oscillators OC1-OC7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an oscillation device, and more particularly to an oscillation device using a ring oscillator.

Conventionally, an oscillation device using a ring oscillator has been widely used for generating a clock signal for generating an operation timing of a digital circuit because a circuit can be configured with a small occupied area on a monolithic IC chip. .
A general ring oscillator is configured by connecting an odd number of inverters composed of CMOS inverters in a ring shape, and the logic level value is inverted each time the signal goes around the ring of the inverter and returns to its original state. However, the oscillation operation is performed by alternately repeating the low level and the high level without becoming the stable state at the same logic level value.

In a ring oscillator in which an odd number of inverters are connected in a ring shape, the oscillation period is proportional to the product of the gate delay time of each inverter and the number of inverters (the number of circuit stages and the number of gates). The minimum unit of phase control of the oscillation signal is the gate delay time.
Incidentally, in recent years, it is required to reduce the period of the clock signal in order to increase the operation speed of the digital circuit. Therefore, an oscillation device using a ring oscillator is required to control the phase of the oscillation signal with a time resolution (time accuracy) finer than the gate delay time of each inverter and generate the oscillation signal as a clock signal. ing.

  Therefore, M × N buffer circuits composed of two-input inverters are arranged in a matrix, and one ring oscillator is configured from M buffer circuits connected in a ring shape, and N ring oscillators are formed. A technique for multiplexing each ring oscillator by arranging and interconnecting them side by side has been proposed (see Patent Document 1).

  In the technique of Patent Document 1, the number of times the oscillation signal circulates in each ring oscillator (the number of rotations) is the upper bit, the gate delay time of each buffer circuit is the middle bit, and the output signal in the buffer circuit corresponding to each ring oscillator An oscillation signal can be generated with a time resolution finer than the gate delay time using the phase difference as a lower bit, and the generated oscillation signal can be used as a clock signal.

  However, in the technique of Patent Document 1, since one buffer circuit composed of two-input inverters is composed of several tens of CMOS inverters, the entire circuit scale becomes very large and small on a monolithic IC chip. In addition to the fact that the circuit cannot be configured with the occupied area, there is a disadvantage that the power consumption is large.

  Therefore, a ring ring having a ring shape and a node connected to the ring line, and a plurality of oscillation circuits whose oscillation phases depend on charges propagated by the ring line, and a greater influence in a specific direction are transmitted. A plurality of wiring circuits provided in the ring wiring, each of which is coupled so that more current flows between nodes of each oscillation circuit in a specific direction. An oscillation device composed of a ring oscillator has been proposed (see claim 1 of Patent Document 2).

  In addition, a plurality of oscillation circuits having a ring-shaped first ring wiring and a node connected to the ring wiring, the oscillation phase depending on the charge propagated by the ring wiring, and a greater influence in one specific direction And a plurality of wiring circuits provided in the first ring wiring that are coupled to each other so that more current flows between nodes of each oscillation circuit in a specific direction. The oscillation stage, the ring-shaped second ring wiring, and the characteristic that a greater influence is transmitted in one specific direction, each of which has more current in a specific direction between the first ring wiring of each oscillation stage. There has been proposed an oscillation device having a plurality of wiring circuits provided in the second ring wiring interconnected so as to flow (see claim 11 of Patent Document 2).

  A phase locked loop (PLL) circuit is proposed that uses the oscillation device of Patent Document 2 to synchronize with an arbitrary steady phase difference by following the frequency of an external periodic signal. (See claim 13 of Patent Document 2).

  Also, a time quantizer has been proposed that uses the oscillation device of Patent Document 2 to detect the positions of all zero crossings of the input signal with an arbitrary time resolution (see claim 14 of Patent Document 2).

  By the way, the present applicant is a ring oscillator in which an even number of inverting circuits that invert and output an input signal are connected in a ring shape, and circulates two types of pulse edges on the same circuit. One is configured as a first start-up inversion circuit that starts an inversion operation of an input signal by a first control signal from the outside, and further, the first start-up inversion circuit and the first start-up inversion circuit One of the inverting circuits other than the inverting circuit connected to the next stage of the circuit is configured as a second starting inverting circuit that starts the inverting operation of the input signal by the second control signal, and the first inverting circuit is externally provided. The first control signal is input to one start-up inversion circuit, and the first start-up inversion circuit starts the inversion operation. Then, the first inversion circuit starts the inversion operation. Are sequentially inverted by the inversion circuit. A ring oscillator provided with control signal input means for inputting the second control signal to the second starting inversion circuit until the edge of the pulse to be transmitted is input to the second starting inversion circuit (Refer to claim 1 of Patent Document 3).

  According to the technique of Patent Document 3, even though an even number of inverting circuits are connected in a ring shape, the entire circuit can circulate around the pulse edge without being in a stable state. If the output signal of a specific inverting circuit is taken out, a clock signal having a cycle that is an even multiple of the operation delay time (gate delay time) of the inverting circuit can be obtained.

  Further, the present applicant uses the ring oscillator of Patent Document 3, and uses the second input signal input from the outside at an arbitrary timing with respect to the first control signal, and the first control signal. A pulse phase difference encoding circuit that encodes a phase difference into a binary digital signal has been proposed (see claim 4 of Patent Document 3).

Further, the present applicant has proposed a digitally controlled oscillator (DCO: Digitally Controlled Oscillator) using the ring oscillator of Patent Document 3 as a pulse circuit and capable of controlling the oscillation cycle by digital data input from the outside. (See Patent Document 4).
US Pat. No. 5,717,362 Japanese Patent Laid-Open No. 2001-36387 (pages 2-7, FIGS. 1-11) Japanese Patent Laid-Open No. 6-216721 (pages 2 to 12 and FIGS. 1 to 6) Japanese Patent Laid-Open No. 7-106923 (pages 2 to 11 and FIGS. 1 to 5)

In recent years, with an increase in operation speed in a digital circuit, it is increasingly important to reduce the period of a clock signal. Therefore, there is a demand for an oscillation device that can control the phase of the oscillation signal with finer time resolution (time accuracy) than the oscillation device of Patent Document 2 and generate the oscillation signal as a clock signal.
Further, it is required to reduce the power consumption of the oscillation device in addition to reducing the circuit scale of the oscillation device and making it possible to configure the circuit with a small occupation area on a monolithic IC chip.

  The present invention has been made to satisfy the above-described requirements, and an object of the present invention is to provide an oscillation device capable of controlling the phase of an oscillation signal with fine time resolution and having a small circuit scale and low power consumption. It is to provide.

  According to the first aspect of the present invention, the same number of inverting circuits that invert the input signal and output are arranged in a matrix in the row direction and the column direction, and the inverting circuits arranged in the column direction are connected in a ring shape. A multi-stage ring oscillator is configured for each column, and nodes between inverting circuits in each stage of each ring oscillator are connected by an inverting circuit arranged in the row direction, and one inverting circuit arranged in the row direction is provided. A technical feature is that each ring oscillator is multiplexed by being connected in a ring shape.

  According to a second aspect of the present invention, in the oscillating device according to the first aspect, the inversion circuits are arranged in a matrix in the form of three or more odd numbers in the row direction and the column direction, and the inversion circuits arranged in the column direction. Each circuit is connected in a ring shape to form an odd-numbered ring oscillator having three or more stages.

  According to a third aspect of the present invention, in the oscillation device according to the first aspect, the inversion circuits are arranged in a matrix of 8 or more even numbers in the row direction and the column direction, and the inversion circuits arranged in the column direction. The circuits are connected in a ring shape to form an even-numbered ring oscillator of 8 or more stages. These even-numbered ring oscillators circulate two kinds of pulse edges on the same circuit and control one of the inverting circuits. Start-up inverting circuit that starts the inverting operation of the input signal by the signal, and start up until the pulse edge generated by the inverting operation of the inverting circuit of the next stage of the starting inverting circuit is input to the starting inverting circuit A technical feature is that control signal input means for inputting a control signal to the inverter circuit is provided.

  According to a fourth aspect of the present invention, in the oscillating device according to the third aspect, the control signal input means is connected in front of the starting inversion circuit by an even number equal to or more than half of the total number of the inversion circuits. The output signal of the predetermined inverting circuit is input as the control signal to the starting inverting circuit, and the inverting circuit for starting includes the control signal and an input signal from the inverting circuit before the starting inverting circuit. When the two signal levels are the same, the signal level is inverted and output, and when the two signal levels are different, the predetermined inversion circuit when the inversion circuit in the next stage of the start-up inversion circuit is not performing the inversion operation. A technical feature is that the same signal level as that of the control signal input from the inverting circuit is preferentially inverted and output.

(Claim 1)
In the invention of claim 1, each ring oscillator performs an oscillation operation.
Therefore, the gate delay time (operation delay time) of the inverting circuits arranged in the column direction constituting each ring oscillator is set to the row direction or the gate delay time of each inverting circuit arranged in the row direction. If the time is set to a multiple of the number of times arranged in the column direction, the oscillation signal is propagated between the input / output terminals of the inverting circuit of each stage of the ring oscillator and the number of times arranged in the row direction. It is the same timing that the oscillation signal is propagated between the inverting circuits.

  That is, a phase difference corresponding to the gate delay time of each inverting circuit arranged in the row direction is generated in the logic level value of the node in the same stage of each ring oscillator. In other words, the phase difference between the oscillation signals at the same stage of any two adjacent ring oscillators becomes the gate delay time of each inverting circuit arranged in the row direction.

  Therefore, according to the first aspect of the present invention, the number of times the oscillation signal circulates in each ring oscillator (the number of times it circulates) is set to the upper bits, and the gate delay times of the individual inverting circuits constituting each ring oscillator are arranged in the middle bits The phase of the oscillation signal is controlled with fine time resolution (time accuracy) using the gate delay time of each inverted circuit (that is, the phase difference of the oscillation signal in the same stage of two adjacent ring oscillators) as the lower bits, The oscillation signal can be generated as a clock signal.

  According to the invention of claim 1, wherein each ring oscillator is multiplexed by mutual coupling with each inverting circuit arranged in the row direction, a patent in which a plurality of ring oscillators are connected by only one or two ring wirings. Compared with the oscillation device of Document 2, the phase control of the oscillation signal can be performed with finer time resolution.

  The inverting circuit constituting the invention of claim 1 may be embodied by a CMOS inverter having a simple configuration and low power consumption. Therefore, according to the first aspect of the present invention, the overall circuit scale is reduced as compared with the technique of Patent Document 1 in which buffer circuits composed of two-input inverters composed of several tens of CMOSs are arranged in a matrix. In addition, a circuit can be configured with a small occupation area on a monolithic IC chip, and power consumption is also reduced.

(Claim 2: corresponds to the first embodiment)
According to the second aspect of the present invention, since the inverting circuits arranged in the column direction are connected in a ring shape to form an odd-numbered stage ring oscillator having three or more stages, the signal passes through the ring of the inverting circuit once. The logic level value is inverted each time the signal returns to the original state, and the oscillation operation is performed by alternately repeating the low level and the high level without the signal becoming stable at the same logic level value.

(Claim 3: corresponds to the second embodiment)
Normally, when an even number of inverting circuits are connected in a ring shape, the input / output signals of the inverting circuits have different logic level values, and the entire circuit becomes stable and does not oscillate.

  On the other hand, in the even-stage ring oscillator according to the third aspect of the present invention, since the two types of pulse edges having different generation timings are circulated on the same lap, the start-up inverting circuit generates a pulse edge (reset edge) generated by itself. ) Is returned, the output signal is inverted by a pulse edge (main edge) that is not generated by itself, so it is possible to circulate two types of pulse edges without the entire circuit becoming stable. Thus, the oscillation operation is performed.

(Claim 4: corresponds to the second embodiment)
According to a fourth aspect of the present invention, the control signal input means outputs an output signal of a predetermined inversion circuit connected in front of the activation inversion circuit by an even number equal to or more than half of the total number of the inversion circuits. The signal is input to the starting inversion circuit as a signal.

When the two signal levels of the control signal and the input signal from the preceding inverting circuit of the starting inverting circuit are the same, the starting inverting circuit inverts and outputs the signal level, When the signal levels are different, the same signal level as the signal level of the control signal input from the predetermined inversion circuit when the inversion circuit of the next stage of the activation inversion circuit is not performing inversion operation is given priority. Inverted to output.
Therefore, according to the invention of claim 4, the even-numbered ring oscillator of the invention of claim 3 can be operated stably.

(Explanation of terms)
The correspondence between the constituent elements described in [Means for Solving the Problems] described above and the constituent members described in [Best Mode for Carrying Out the Invention] described below is as follows. .

The “inverting circuit” corresponds to the inverters R11 to R77 and F11 to F77 in the first embodiment, and corresponds to the inverters R11 to R78, F11 to F88 or the NAND gates D1 to D8 in the second embodiment.
The “starting inverting circuit” corresponds to the NAND gates D1 to D8 of the second embodiment.
“The inversion circuit at the next stage of the start inversion circuit” corresponds to the first-stage inverters R11, R21, R31, R41, R51, R61, R71, and R81 of the second embodiment.

The “control signal” corresponds to the output signal of the fourth-stage inverters R14, R24, R34, R44, R54, R64, R74, and R84 of the second embodiment.
The “control signal input means” corresponds to inverters connected from the first stage to the fourth stage in the ring oscillators OC11 to OC18. For example, the ring oscillator OC11 corresponds to the inverters R11 to R14.

The “predetermined inverting circuit” in claim 4 corresponds to the fourth-stage inverters R14, R24, R34, R44, R54, R64, R74, R84 of the second embodiment.
The “inverting circuit in front of the starting inverting circuit” corresponds to the seventh-stage inverters R17, R27, R37, R47, R57, R67, R77, and R87 of the second embodiment.

  Hereinafter, embodiments embodying the present invention will be described with reference to the drawings. In each embodiment, the same constituent members are denoted by the same reference numerals, and redundant description of the same content is omitted.

(First embodiment)
FIG. 1 is a circuit diagram illustrating a schematic configuration of an oscillation device 10 according to the first embodiment.
The oscillation device 10 includes inverters (inverter gates) R11 to R17, R21 to R27, R31 to R37, R41 to R47, R51 to R57, R61 to R67, R71 to R77, F11 to F17, F21 to F27, F31 to F37, F41-F47, F51-F57, F61-F67, F71-F77 are comprised.

  Each inverter is arranged in a matrix of seven in the row direction and the column direction. Each inverter F11 to F77 arranged in the row direction is composed of CMOS inverters having the same structure, and each inverter R11 to R77 arranged in the column direction is It consists of a CMOS inverter with the same structure.

Each of the inverters R11 to R77 arranged in the column direction is connected in a ring shape (seven in series) to form a seven-stage ring oscillator OC1 to OC7.
For example, seven inverters R11 to R17 are connected in a ring shape to form a seven-stage ring oscillator OC1.

  Nodes between the inverters of the respective stages of the ring oscillators OC1 to OC7 are connected by inverters F12 to F17, F22 to F27, F32 to F37, F42 to F47, F52 to F57, F62 to F67, and F72 to F77. .

For example, the input terminals of the first-stage inverters R11, R21, R31, R41, R51, R61, and R71 of the ring oscillators OC1 to OC7 are connected by the inverters F12 to F17.
The input terminals of the seventh-stage inverters R17, R27, R37, R47, R57, R67, and R77 of the ring oscillators OC1 to OC7 are connected by the inverters F72 to F77.

  The input terminals of the inverters R11 to R17 at each stage of the ring oscillator OC1 and the input terminals of the inverters R72 to R77 and R71 at the subsequent stages of the ring oscillator OC7 are the inverters F11, F21, F31, and F41. , F51, F61, and F71.

For example, the input terminal of the first stage inverter R11 of the ring oscillator OC1 and the input terminal of the second stage (next stage of the first stage) inverter R72 of the ring oscillator OC7 are connected by the inverter F11.
Further, the input terminal of the seventh-stage inverter R17 of the ring oscillator OC1 and the input terminal of the first-stage (the seventh-stage next stage) inverter R71 of the ring oscillator OC7 are connected by an inverter F71.

  The output terminal of the inverter F71 is connected to the input terminal of the inverter F17 via a node between the inverters R77 and R71 of the ring oscillator OC7. As a result, the inverters F11 to F77 are connected (in series connection) in one ring shape.

  In other words, the oscillation device 10 includes seven inverters arranged in a matrix in the row direction and the column direction, and the inverters R11 to R77 arranged in the column direction are connected in a ring shape so that seven stages are provided for each column. The ring oscillators OC1 to OC7 are configured, and the nodes between the inverters of each stage of the ring oscillators OC1 to OC7 are connected by inverters arranged in the row direction, and the inverters F11 to F77 arranged in the row direction are connected in a ring shape. As a result, the ring oscillators OC1 to OC7 are multiplexed.

[Operations and effects of the first embodiment]
According to the first embodiment, the following actions and effects can be obtained.

[1-1]
Since each ring oscillator OC1 to OC7 is configured by connecting an odd number of seven inverters in a ring shape, the logic level value is inverted each time the signal goes around the inverter ring and returns to its original state. The oscillation operation is performed by alternately repeating the low level and the high level without the signal becoming stable at the same logic level value.

  Here, the gate delay time (operation delay time) Tr of each of the inverters R11 to R77 constituting each of the ring oscillators OC1 to OC7 is seven times the gate delay time Tf of each of the inverters F11 to F77 arranged in the row direction. The time is set (Ta = 7 × Tb).

For this reason, the oscillation signal is propagated between the input / output terminals of the inverters R11 to R77 and the oscillation signal is propagated between the seven inverters arranged in the row direction at the same timing.
For example, an oscillation signal is propagated between the input / output terminals of the first-stage inverter R71 of the ring oscillator OC7, and an oscillation signal is propagated between the seven inverters F11 to F17 arranged in the row direction. Are at the same timing.

FIG. 2 is a timing chart showing temporal changes in the logic level values at the nodes Na to Nc of the oscillation device 10.
The node Na is a node between the inverters R71 and R72 of the ring oscillator OC7, and is connected to the output terminal of the inverter R71 and to the input terminal of the inverter R72.
The node Nb is a node between the inverters R72 and R73 of the ring oscillator OC7, and is connected to the output terminal of the inverter R72 and to the input terminal of the inverter R73.
The node Nc is a node between the inverters R61 and R62 of the ring oscillator OC6, and is connected to the output terminal of the inverter R61 and to the input terminal of the inverter R62.

Each of the inverters R11 to R77 constituting each of the ring oscillators OC1 to OC7 is composed of a CMOS inverter having the same structure and has the same gate delay time Tr.
For this reason, the logic level values of the nodes Na and Nb are completely inverted without deviation.

The node Nc is connected to the input terminal of the inverter R71 via the inverters R61 and F17.
For this reason, the logic level value of the node Nc is in a state of changing with a delay from the change of the logic level value of the node Na by the gate delay time Tf of the inverter F17.

That is, a phase difference corresponding to the gate delay time Tf is generated in the logic level values of the nodes Na and Nc in the same stage of the ring oscillators OC7 and OC6.
In other words, the phase difference between the oscillation signals at the same stage of any two adjacent ring oscillators is the gate delay time Tf.

  Therefore, in the oscillation device 10, the number of times the oscillation signal circulates in each ring oscillator OC1 to OC7 (the number of laps) is the upper bit, and the gate delay time Tr of each of the inverters R11 to R71 constituting each ring oscillator OC1 to OC7 is set to the middle. Fine time resolution (time accuracy) with the low-order bit as the low-order bit and the gate delay time Tr of each of the inverters F11 to F77 arranged in the row direction (that is, the phase difference of the oscillation signals at the same stage of two adjacent ring oscillators) ) To control the phase of the oscillation signal and generate the oscillation signal as a clock signal.

  Then, according to the oscillation device 10 in which the ring oscillators OC1 to OC7 are mutually coupled by the inverters F11 to F77 arranged in the row direction, a plurality of ring oscillators are formed by only one or two ring wirings. Compared with the connected oscillator of Patent Document 2, the phase of the oscillation signal can be controlled with finer time resolution.

[1-2]
Each of the inverters R11 to R77 and F11 to F77 constituting the oscillation device 10 is a CMOS inverter having a simple configuration and low power consumption.
Therefore, according to the oscillation device 10, the overall circuit scale is smaller and monolithic compared to the technique of Patent Document 1 in which buffer circuits composed of two-input inverters composed of several tens of CMOSs are arranged in a matrix. A circuit can be configured with a small occupation area on an IC chip, and power consumption is also reduced.

[1-3]
FIG. 3 is a circuit diagram showing a schematic configuration of an oscillation device 20 which is a modification of the first embodiment.
The oscillating device 20 omits only the inverters R11 to R13, R21 to R23, R31 to R33, F11 to F13, F21 to F23, and F31 to F33 from the oscillating device 10 by shorting the input terminals of the other inverters. Is.

  That is, the oscillation device 20 includes three inverters arranged in a matrix in the row direction and the column direction, and the inverters R11 to R33 arranged in the column direction are connected in a ring shape, and three stages are provided for each column. The ring oscillators OC1 to OC3 are configured, and the nodes between the inverters of each stage of the ring oscillators OC1 to OC3 are connected by inverters arranged in the row direction, and the inverters F11 to F33 arranged in the row direction are connected in a ring shape As a result, the ring oscillators OC1 to OC3 are multiplexed.

  That is, the first embodiment includes three or more odd-numbered inverters arranged in a matrix in the row direction and the column direction, and the inverters arranged in the column direction are connected in a ring shape to form an odd number of three or more stages. Three or more stage ring oscillators may be configured and each ring oscillator may be changed to be multiplexed, and the oscillation device 20 is an example in which the first embodiment is embodied with a minimum circuit scale.

[1-4]
The first embodiment may be applied to the phase synchronization circuit described in FIG.
In other words, the oscillation devices 10 and 20 of the first embodiment may be used to configure a phase synchronization circuit that synchronizes with an arbitrary steady phase difference by following the frequency with respect to a periodic signal from the outside.
In this case, the oscillation device 10C shown in FIG. 9 of Patent Document 2 is replaced with the oscillation devices 10 and 20 of the first embodiment, and the output voltage of the loop filter 23 shown in FIG. For example, an output signal of an appropriate inverter of the ring oscillator OC1 may be fed back to the phase frequency comparison circuit 21 shown in FIG.

[1-5]
The first embodiment may be applied to the time quantizer described in FIG.
In other words, a time quantizer that uses the oscillation devices 10 and 20 of the first embodiment and detects all zero-crossing positions of the input signal with an arbitrary time resolution may be configured.
In this case, the oscillating device 10D shown in FIG. 10 of Patent Document 2 is replaced with the oscillating devices 10 and 20 of the first embodiment, and the output signal of an appropriate inverter of each ring oscillator of the first embodiment is changed to FIG. As a clock signal for the flip-flop shown in FIG.

(Second Embodiment)
FIG. 4 is a circuit diagram illustrating a schematic configuration of the oscillation device 30 according to the second embodiment.
The oscillation device 30 includes inverters R11 to R17, R21 to R27, R31 to R37, R41 to R47, R51 to R57, R61 to R67, R71 to R77, R81 to R87, F11 to F18, F21 to F28, F31 to F38, F41 to F48, F51 to F58, F61 to F68, F71 to F78, F81 to F88, and two-input NAND gates (Nand gates) D1 to D7.

  Each inverter is arranged in a matrix of 8 pieces in the row direction and 7 pieces in the column direction, and the inverters F11 to F88 arranged in the row direction are composed of CMOS inverters having the same structure, and are arranged in the column direction. Inverters R11 to R87 are CMOS inverters having the same structure.

  The inverter circuit composed of inverters R11 to R87 and NAND gates D1 to D8 arranged in the column direction has seven inverters and one NAND gate connected in a ring shape (in series connection), An eight-stage ring oscillator OC11 to OC18 in which inverting circuits are connected in a ring shape is configured.

  For example, in the ring oscillator OC11, seven inverters R11 to R17 are connected, the output terminal of the inverter R17 is connected to the first input terminal of the NAND gate D1, and the output terminal of the inverter R14 is the second input terminal of the NAND gate D1. (Referred to as “control terminal” in the following description), and the output terminal of the NAND gate D1 is connected to the input terminal of the inverter R11.

  The nodes between the inverting circuits (inverters R11 to R87, NAND gates D1 to D8) of each stage of the ring oscillators OC11 to OC18 are inverters F12 to F18, F22 to F28, F32 to F38, F42 to F48, F52 to F58. , F62 to F68, F72 to F78, and F81 to F88.

For example, the input terminals of the first-stage inverters R11, R21, R31, R41, R51, R61, R71, and R81 of the ring oscillators OC11 to OC18 are connected by the inverters F12 to F18.
The input terminals of the seventh-stage inverters R17, R27, R37, R47, R57, R67, R77, and R87 of the ring oscillators OC11 to OC18 are connected by the inverters F72 to F78.
The first input terminals of the NAND gates D1 to D8, which are the eighth-stage inverting circuits of the ring oscillators OC11 to OC18, are connected by the inverters F82 to F88.

  Then, the input terminals or first input terminals of the inverting circuits (inverters R11 to R17, NAND gate D1) of each stage of the ring oscillator OC11, and the inverting circuits (inverters R82 to R87, The D gate D18 and the input terminal or first input terminal of the inverter R81) are connected to each other by inverters F11, F21, F31, F41, F51, F61, F71, and F81.

For example, the input terminal of the first stage inverter R11 of the ring oscillator OC11 and the input terminal of the second stage (next stage of the first stage) inverter R82 of the ring oscillator OC18 are connected by the inverter F11.
The input terminal of the seventh-stage inverter R17 of the ring oscillator OC11 and the first input terminal of the NAND gate D18 that is the inverting circuit of the eighth stage (next stage of the seventh stage) in the ring oscillator OC18 are the inverter F71. Connected by.
Further, the first input terminal of the NAND gate D18 that is the eighth-stage inversion circuit of the ring oscillator OC11 and the input terminal of the first-stage (the eighth-stage next stage) inverter D81 in the ring oscillator OC18 are the inverter F81. Connected by.

  The output terminal of the inverter F81 is connected to the input terminal of the inverter F18 via a node between the NAND gate D18 of the ring oscillator OC18 and the inverter R81. As a result, the inverters F11 to F88 are connected (in series connection) in one ring shape.

  That is, the oscillation device 30 includes inverting circuits (inverters R11 to R87, NAND gates D1 to D8) arranged in a matrix of eight in the row direction and the column direction, and inverters R11 to R87 arranged in the column direction. NAND gates D1 to D8 are connected in a ring shape to form 8-stage ring oscillators OC11 to OC18 for each column, and nodes between inverting circuits of each stage of each ring oscillator OC11 to OC18 are arranged in the row direction. The ring oscillators OC11 to OC18 are multiplexed by connecting the inverters F11 to F88 connected by the inverter and arranged in the row direction in a ring shape.

[Operation and Effect of Second Embodiment]
According to the second embodiment, the following actions and effects can be obtained.

[2-1]
FIG. 5 is a circuit diagram showing the ring oscillator OC11 taken out from the oscillation device 30. As shown in FIG.
Hereinafter, the oscillation operation of the ring oscillator OC11 will be described with reference to FIG.

  [A] When the output signal P1 of the inverter R11 is inverted from the high level to the low level, the output signals of the subsequent inverters R12 to R17 are sequentially inverted, and the output signals of the odd-numbered inverters R13, R15, and R17 are high. The level changes from the low level to the low level, and the output signals of the even-numbered inverters R12, R14, R16 change from the low level to the high level.

In the following description, the ring oscillator OC11 sequentially circulates as the falling output of the odd-numbered inverters R11, R13, R15, and R17, and rises of the even-numbered inverters R12, R14, R16, and the NAND gate D1. An edge of an oscillation signal (pulse signal) that sequentially circulates as an output is called a “main edge”.
Here, the falling output is an output signal that changes from a high level to a low level, and the rising output is an output signal that changes from a low level to a high level.

  [B] Since the output level of the inverter R17 is still high when the main edge reaches the inverter R14 and the output signal P4 of the inverter R14 is inverted from low level to high level, the two inputs of the NAND gate 32 Both signals become high level, the NAND gate D1 performs an inverting operation, and the output signal of the NAND gate D1 is inverted from the high level to the low level.

As described above, the main edge is input to the NAND gate D1 from the control terminal and inverted by the NAND gate D1, and then sequentially circulates as the rising output of the odd-numbered inverters R11, R13, R15, R17, and the even-numbered stage. The edge of the oscillation signal that circulates sequentially as the falling output of the inverters R14, R14, R16 of the eye and the NAND gate D1 is called the “reset edge” in the following description after being inverted by the NAND gate D1. To.
The reset edge circulates on the ring oscillator OC11 together with the main edge.

[C] After that, the main edge is sequentially inverted and propagated by the inverters R15 to R17 subsequent to the inverter R14, the output signal of the inverter R17 is inverted from the high level to the low level, and the low level output signal is output. Input to the NAND gate D1.
At this time, since the input signal to the control terminal of the NAND gate D1 (the output signal of the inverter R14) is at the high level, the main edge is sequentially inverted by the NAND gate D1 and the inverters R11 to R17 as it is, so that the ring oscillator Propagated on DC11.

  Thus, when the main edge reaches the NAND gate D1 via the inverters R15 to R17, the output signal of the inverter R14 is still at the high level because the number of gates from the inverter R15 to the inverter R17 is three. In contrast, since the number of gates from the NAND gate D1 to the inverter R14 is five, the main edge is input to the NAND gate D1 earlier than the reset edge is propagated from the NAND gate D1 to the inverter R14. This is because that.

  [D] On the other hand, the reset edge generated by the NAND gate D1 reaches the inverter R14 again via the inverters R11 to R13, and inverts the input signal of the control terminal of the NAND gate D1 from the high level to the low level. Let At this time, since the input signal from the inverter R17 of the NAND gate D1 is already at the low level due to the main edge, the logic level value of the output signal of the NAND gate D1 does not change, and the reset edge is changed from the inverter R14 to the inverters R15 to R15. The signal is propagated to the NAND gate D1 via R17.

  [E] When the reset edge reaches the inverter R17, the input signal from the inverter R17 of the NAND gate D1 is inverted from the low level to the high level. At substantially the same time, the main edge reaches the inverter R14, and the input signal to the control terminal of the NAND gate D1 is also inverted from the low level to the high level.

That is, the main edge goes around the ring oscillator OC11 via the inverters R11 to R17 and then reaches the inverter R14 again via the inverters R11 to R13.
On the other hand, the reset edge is generated by the inversion operation of the NAND gate D1 after the main edge reaches the inverter R14 via the inverters R11 to R13, and then the ring is transmitted via the inverters R11 to R17. It goes around the oscillator OC11.

Therefore, the total number of gates through which both edges reach the NAND gate D1 is exactly the same as twelve.
Therefore, the main edge reaches the inverter R14 almost simultaneously with the reset edge reaching the inverter R17.

Here, in each of the inverters R15 to R17, the inversion response time (gate delay time) of the even-numbered stage inverter R16 is faster for the falling output than for the rising output, and conversely, the odd-numbered inverters R15 and R17. The inversion response time is set so that the rising output is faster than the falling output.
Therefore, the reset edge reaches the NAND gate D1 slightly faster than the main edge.

  That is, even if the output signal of the inverter R17 is inverted from the low level to the high level by the reset edge, the input signal (output signal of the inverter R14) of the control terminal of the NAND gate D1 is still at the low level. The logic level value of the output signal of D1 is not inverted, and when the main edge reaches the inverter R14 slightly later than the reset edge, the input signal at the control terminal of the NAND gate D1 is inverted from the low level to the high level. The reset edge once disappears here and is regenerated by the main edge, such as the output signal of the gate D1 being inverted from the high level to the low level.

In this way, the output signal of the NAND gate D1 is inverted by the main edge input from the control terminal, which is the same operation as [b].
That is, in the ring oscillator OC11, the reset edge is regenerated by the main edge, propagated from the NAND gate D1 to the inverter R11, and the main edge is propagated to the NAND gate D1 via the inverters R14 to R17. Further, the main edge and the reset edge circulate on the ring oscillator OC11.

[F] Thereafter, the operations of [c] to [e] are repeated, and the reset edge is regenerated every time the main edge makes a round of the ring oscillator OC11. Both edges circulate on the ring oscillator OC11.
The operations of the other ring oscillators OC12 to OC18 are the same as those of the ring oscillator OC11.

[2-2]
Normally, when an even number of inverting circuits (inverters, NAND gates) are connected in a ring shape, the input / output signals of the respective inverting circuits have different logic level values, and the entire circuit becomes stable and does not oscillate.
On the other hand, in the 8-stage ring oscillator OC11 in which seven inverters R11 to R17 and one NAND gate D1 are connected in a ring shape, two types of pulse edges (main edge, reset) having different generation timings on the same circuit. Edge).

Therefore, in the first-stage inverter R11, the logic level value of the output signal is inverted by the reset edge before the main edge returns.
The NAND gate D1 also inverts the logic level value of the output signal by the main edge before the reset edge generated by the NAND gate D1 returns.
Therefore, in the ring oscillator OC11, the entire circuit is not in a stable state, and two types of pulse edges (main edge and reset edge) circulate forever.

  Moreover, in each of the inverters R15 to R17 of the ring oscillator OC11, the inversion response time of the even-numbered inverter R16 is faster for the falling output than for the rising output, and conversely, the inversion of the odd-numbered inverters R15 and R17. The response time is set so that the rising output is faster than the falling output.

  Therefore, when the main edge is input from the inverter R14 to the NAND gate D1 and the reset edge is input from the inverter R17 to the NAND gate D1, the reset edge is always input to the NAND gate D1 faster than the main edge. In this way, once the reset edge disappears completely, the reset edge is regenerated by the main edge.

  In (e), when the main edge reaches the NAND gate D1 slightly faster than the reset edge, the NAND gate D1 finally outputs the output signal at the input timing of the reset edge that becomes the high level. Since the logic level value is inverted, the main edge catches up with the reset edge while the main edge and the reset edge circulate on the ring oscillator OC11, and the entire circuit finally becomes stable. This is to prevent the oscillation from stopping.

  Thus, according to the 8-stage ring oscillator OC11, a total of eight even number of inverting circuits including seven inverters R11 to R17 and one NAND gate D1 are connected in a ring shape. Nevertheless, it becomes possible to circulate two types of pulse edges (main edge and reset edge) without the entire circuit being in a stable state, and an oscillation operation is performed.

  According to the ring oscillator OC11, it is possible to always circulate both edges stably without being affected by variations in the inversion response time of each of the inverters R11 to R17 and the NAND gate D1, and thus each inverter R11. If an arbitrary output signal of .about.R17 and NAND gate D1 is taken out, an accurate clock signal having a period eight times the gate delay time (operation delay time) of each of inverters R11-R17 and NAND gate D1 can be obtained.

  That is, the 8-stage ring oscillator OC11 is the same as the 32-stage ring oscillator 2 shown in FIG. 1 of Patent Document 3, except that the NAND gate NAND1 is replaced with the inverter R11, the inverters INV2 to INV18 are replaced with the inverters R12 to R14, and the inverters INV19 to INV31 is replaced with inverters R15 to R17, and NAND gate NAND1 is replaced with NAND gate D1.

The other ring oscillators OC12 to OC18 can provide the same operations and effects as the 8-stage ring oscillator OC11.
Further, the NAND gates D1 to D8 of the ring oscillators OC11 to OC18 may be replaced with NOR gates (nor gates), respectively.

[2-3]
The gate delay time (operation delay time) Tr of each inverting circuit (inverters R11 to R87, NAND gates D1 to D8) constituting each ring oscillator OC11 to OC18 is the gate of each inverter F11 to F88 arranged in the row direction. The time is set to 8 times the delay time Tf (Ta = 8 × Tb).

Therefore, an oscillation signal is propagated between the input / output terminals of the inverters R11 to R87 and between the first input terminals of the NAND gates D1 to D8, and an oscillation signal is propagated between the eight inverters arranged in the row direction. The same timing is used.
For example, an oscillation signal is propagated between the input / output terminals of the first-stage inverter R81 of the ring oscillator OC18, and an oscillation signal is propagated between the eight inverters F11 to F18 arranged in the row direction. Are at the same timing.

FIG. 6 is a timing chart showing temporal changes in the logic level values at the nodes Na to Nc of the oscillation device 30.
The node Na is a node between the inverters R81 and R82 of the ring oscillator OC18, and is connected to the output terminal of the inverter R81 and to the input terminal of the inverter R82.
Node Nb is a node between inverters R82 and R83 of ring oscillator OC18, and is connected to the output terminal of inverter R82 and to the input terminal of inverter R83.
The node Nc is a node between the inverters R71 and R72 of the ring oscillator OC17, and is connected to the output terminal of the inverter R71 and to the input terminal of the inverter R72.

The inverting circuits (inverters R11 to R87, NAND gates D1 to D8) constituting the ring oscillators OC11 to OC18 have the same gate delay time Tr.
For this reason, the logic level values of the nodes Na and Nb are completely inverted without deviation.

The node Nc is connected to the input terminal of the inverter R81 via the inverters R71 and F18.
Therefore, the logic level value of the node Nc is in a state of being changed with a delay from the change of the logic level value of the node Na by the gate delay time Tf of the inverter F18.

That is, a phase difference corresponding to the gate delay time Tf is generated in the logic level values of the nodes Na and Nc in the same stage of the ring oscillators OC18 and OC17.
In other words, the phase difference between the oscillation signals at the same stage of any two adjacent ring oscillators is the gate delay time Tf.

  Therefore, in the oscillation device 30, the number of times the oscillation signal circulates in each ring oscillator OC11 to OC18 (the number of laps) is the upper bit, and the individual inverting circuits (inverters R11 to R87, NAND gate D1) constituting each ring oscillator OC11 to OC18. ˜D8) is the middle bit, and the gate delay times Tr of the inverters F11 to F88 arranged in the row direction (that is, the phase difference of the oscillation signals in the same stage of two adjacent ring oscillators). As the lower bits, the phase control of the oscillation signal can be performed with fine time resolution (time accuracy), and the oscillation signal can be generated as a clock signal.

  Then, according to the oscillation device 10 in which the ring oscillators OC11 to OC18 are mutually coupled by the inverters F11 to F88 arranged in the row direction and multiplexed, a plurality of ring oscillators can be formed by only one or two ring wirings. Compared with the connected oscillator of Patent Document 2, the phase of the oscillation signal can be controlled with finer time resolution.

[2-4]
Each of the inverters R11 to R87 and F11 to F88 constituting the oscillation device 30 is composed of a CMOS inverter having a simple configuration and low power consumption, and the NAND gates D1 to D8 are composed of several transistors.
Therefore, according to the oscillation circuit 30, compared with the technique of Patent Document 1 in which buffer circuits composed of two-input inverters composed of several tens of CMOSs are arranged in a matrix, the entire circuit scale is reduced, and the monolithic structure is reduced. A circuit can be configured with a small occupation area on an IC chip, and power consumption is also reduced.

[2-5]
The second embodiment includes inverting circuits (inverters and NAND gates) arranged in a matrix of 8 or more even numbers in the row direction and the column direction, and connects the inverting circuits arranged in the column direction in a ring shape. The number of even-numbered ring oscillators of eight or more stages may be configured so that each ring oscillator is multiplexed, and the oscillation device 30 is an example in which the second embodiment is embodied with a minimum circuit scale. .

In the ring oscillator OC11 of the second embodiment, three inverters D15 to D17 are connected between the inverter R14 that outputs an output signal to the control terminal of the NAND gate D1 and the NAND gate D1.
In order to configure an even-numbered ring oscillator having eight or more stages, all of the inverting circuits (inverters and NAND gates) are arranged between a predetermined inverter that outputs an output signal to the control terminal of the NAND gate and the NAND gate. An odd number of inverters less than half the number (number of stages of the ring oscillator) may be connected.

In other words, in the ring oscillator OC11 of the second embodiment, four inverters R11 to R14 are connected in front of the NAND gate D1, and the output signal of the fourth inverter R14 is connected to the control terminal of the NAND gate D1. It is output.
In order to configure an even-numbered ring oscillator having eight or more stages, an even number of half or more of the total number of inverter circuits (inverters and NAND gates) (the number of stages of the ring oscillator) is connected in front of the NAND gate D1. The output signal of the inverter may be output to the control terminal of the NAND gate D1.
In this way, even in an even-numbered ring oscillator having eight or more stages, the same operations and effects as the above [2-1] [2-2] can be obtained.

[2-6]
Similarly to [1-4] of the first embodiment, the second embodiment may be applied to the phase synchronization circuit described in FIG.

[2-7]
Similar to [1-5] of the first embodiment, the second embodiment may be applied to the time quantizer described in FIG.

[2-8]
The second embodiment may be applied to the pulse phase difference encoding circuit described in FIG. 3 or FIG.
That is, the pulse phase difference encoding circuit that encodes the phase difference between two input signals into a binary digital signal may be configured by using the oscillation device 30 of the second embodiment.

  In this case, the even-stage ring oscillator 2 shown in FIG. 3 or 6 of Patent Document 3 is replaced with the oscillation device 30 of the second embodiment, and the first-stage inverter of each ring oscillator of the oscillation device 30 is a 2-input NAND. In addition to replacing the gate, a 24-stage ring oscillator is configured by adding 24 inverters. A first input signal (start pulse PA) is externally applied to an input terminal not connected to the inverter of the added 2-input NAND gate. Enter it.

  In this way, the oscillation operation of the 32-stage ring oscillator is started by the first input signal, and the second input signal (latch pulse PB) input from the outside at an arbitrary timing with respect to the first input signal. And a phase difference between the first input signal and the first input signal can be encoded into a binary digital signal.

By the way, it is also conceivable to apply the first embodiment to the pulse phase difference encoding circuit described in FIG.
However, since the oscillation devices 10 and 20 of the first embodiment are composed of odd-numbered ring oscillators, the odd-numbered stages from when the first input signal is input to when the second input signal is input are included. By simply binary encoding the number of oscillating signals on the ring oscillator and the position of the inverter on which the oscillation signal arrived on the odd-numbered ring oscillator, the phase difference of each input signal is encoded into a binary digital signal. Code loss occurs when it is converted.

Therefore, in order to obtain a binary digital signal, the number of oscillations of the oscillation signal that circulates in the odd-numbered ring oscillator must be calculated using a subtractor, and the entire pulse phase difference encoding circuit is equivalent to the subtractor. In addition to the increase in the circuit scale, there is a problem that the processing speed of the encoding is reduced by the operation time of the subtractor.
In addition, a configuration in which the output signal of one inverter among the inverters constituting the odd-numbered ring oscillator is not intentionally used and the phase difference of each input signal is detected from the output signals of other even number of inverters is also conceivable. In this case, there is a problem that the detection accuracy of the phase difference is lowered.

  However, when the second embodiment is applied to the pulse phase difference encoding circuit described in FIG. 3 or FIG. 6 of Patent Document 3, since the code missing does not occur, the problem caused by the subtracter is not caused. This can be avoided and a decrease in detection accuracy of the phase difference can be prevented.

[2-9]
The second embodiment may be applied to the digitally controlled oscillator described in FIG.
That is, a digitally controlled oscillation device that can control the oscillation cycle by using digital data input from the outside using the oscillation device 30 of the second embodiment may be configured.

  In this case, the ring oscillator 2 shown in FIG. 1 of Patent Document 4 is replaced with the oscillation device 30 of the second embodiment, the first-stage inverter of each ring oscillator of the oscillation device 30 is replaced with a 2-input NAND gate, A 24-stage ring oscillator is configured by adding 24 inverters, and an input signal (control signal PA) may be input from the outside to an input terminal not connected to the added 2-input NAND gate inverter.

1 is a circuit diagram showing a schematic configuration of an oscillation device 10 according to a first embodiment embodying the present invention. 3 is a timing chart showing temporal changes in logic level values at nodes Na to Nc of the oscillation device 10; The circuit diagram which shows schematic structure of the oscillation apparatus 20 which is a modification of 1st Embodiment. The circuit diagram which shows schematic structure of the oscillation apparatus 30 of 2nd Embodiment which actualized this invention. FIG. 6 is a circuit diagram showing an 8-stage ring oscillator OC11 taken out from the oscillation device 30. 4 is a timing chart showing temporal changes in logic level values at nodes Na to Nc of the oscillation device 30.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 20, 30 ... Oscillator R11-R77, F11-F77 ... Inverter OC1-OC7 ... Seven stage ring oscillator OC11-OC18 ... Eight stage ring oscillator D1-D8 ... NAND gate

Claims (4)

An inverting circuit that inverts and outputs an input signal is arranged in a matrix by the same number in the row direction and the column direction,
The inverting circuits arranged in the column direction are connected in a ring shape to form a multistage ring oscillator for each column,
Nodes between the inverting circuits of each stage of each ring oscillator are connected by an inverting circuit arranged in the row direction, and the inverting circuits arranged in the row direction are connected in one ring shape, thereby each ring oscillator. An oscillating device in which is multiplexed. The oscillation device according to claim 1,
The inversion circuits are arranged in a matrix in an odd number of 3 or more in the row direction and the column direction,
The inverting circuit arranged in the column direction is connected in a ring shape to form an odd-numbered ring oscillator having three or more stages. The oscillation device according to claim 1,
The inversion circuits are arranged in a matrix in an even number of 8 or more in the row direction and the column direction,
The inverting circuits arranged in the column direction are connected in a ring shape to form an even-numbered ring oscillator of 8 or more stages,
Those even ring oscillators are
Two types of pulse edges circulate on the same lap,
One of the inverting circuits is a starting inverting circuit that starts an inverting operation of an input signal by a control signal,
Control signal input means for inputting a control signal to the start-up inversion circuit is provided until the pulse edge generated by the inversion operation of the next-stage inversion circuit of the start-up inversion circuit is input to the start-up inversion circuit. An oscillation device characterized by that. The oscillation device according to claim 3.
The control signal input means includes
An output signal of a predetermined inversion circuit connected before the start inversion circuit by an even number equal to or more than half of the total number of the inversion circuits is input to the start inversion circuit as the control signal,
The inversion circuit for starting is
When the two signal levels of the control signal and the input signal from the preceding inverting circuit of the starting inverting circuit are the same, the signal level is inverted and output,
When the two signal levels are different, the signal level equal to the signal level of the control signal input from the predetermined inverting circuit when the inverting circuit of the next stage of the starting inverting circuit is not performing the inverting operation. An oscillation device characterized by preferentially inverting and outputting.

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