KR101747430B1 - High resolution low noise digital contolled oscillator - Google Patents

Abstract

The digital controlled oscillator includes a differential digital-to-analog converter for receiving an N-bit digital code signal as an input and generating a first differential current signal and a second differential current signal corresponding to the digital code signal; And a differential current controlled oscillator for generating an oscillation frequency that is adaptively adjusted according to the difference between the first differential current signal and the second differential current signal.

Description

[0001] HIGH RESOLUTION LOW NOISE DIGITAL CONTOLLED OSCILLATOR [0002]

The present invention relates to a frequency oscillator which can be controlled by a digital code.

The present invention was derived from the research conducted as part of the IT growth engine technology development project of the Ministry of Knowledge Economy and the Korea Information Society Agency. [Project Assignment Number: 2009-S-043-01, Project: Development of Scalable Microflow Processing Technology] .

A digitally controlled oscillator is a signal for controlling the oscillation frequency. It does not use an analog voltage or current but controls the oscillation frequency using a digital code. A digitally controlled oscillator using digital codes is widely used because of its strong noise immunity.

The structure of a low-gain digitally controlled oscillator that can finely control the frequency of an oscillator can be roughly classified into two types. One is a structure including a digital-analog converter in a digital controlled oscillator, and the other is a structure using an external digital-analog converter.

There are a variety of examples using structures that incorporate digital-to-analog converters.

The present invention provides a digitally controlled oscillator for controlling the oscillation frequency using at least a pair of differential current signals and a differential digital-to-analog converter for the digitally controlled oscillator.

A digital controlled oscillator according to an embodiment of the present invention includes a differential digital-to-analog converter (ADC) that receives an N-bit digital code signal as an input and generates a first differential current signal and a second differential current signal corresponding to the digital code signal ; And a differential current controlled oscillator for generating an oscillation frequency that is adaptively adjusted according to the difference between the first differential current signal and the second differential current signal.

The differential current controlled oscillator of the present invention can maintain the linearity well by generating the oscillation frequency that changes according to the difference of the magnitudes of the first differential current signal and the second differential current signal input to the input, Can receive.

In addition, the digital-to-analog converter of the present invention can output two differential current signals having different magnitudes according to a digital code after copying a current from a reference current source. Therefore, since the current of one current source is divided into two, the sum of the magnitudes of the two currents is always constant.

In addition, the present invention can easily adjust the resolution of a digital-analog converter simply by adjusting the size of a transistor constituting a current divider.

1 is a diagram showing an example of a digitally controlled oscillator using a voltage-controlled oscillator and a digital-analog converter.
FIG. 2 is a graph showing changes in oscillation frequency according to an analog voltage signal in the digital controlled oscillator shown in FIG.
3 is a diagram showing an example of a digitally controlled oscillator of the present invention.
FIG. 4A is a diagram showing the digital-analog converter shown in FIG. 3 in detail.
4B shows an equivalent circuit of the circuit shown in FIG. 4A.
5 is a diagram showing an example of a differential current controlled oscillator.
6A and 6B are diagrams illustrating the delay cells included in the differential current controlled oscillator.
7 is a diagram showing another example of the differential current controlled oscillator.
8 is a diagram showing another example of the differential current controlled oscillator.

Before describing the present invention, a structure in which a digital-analog converter is included in a digital controlled oscillator will be described.

First, there is a method of controlling the oscillation frequency by changing the resonance frequency of the LC tank by adjusting the amount of capacitance connected in parallel to the inductor by using a switched capacitor array.

Second, there is a method of controlling the oscillation frequency by changing the RC time constant by connecting a switched capacitor array in parallel with a general ring type oscillator.

In the case of using the above-described schemes, in order to increase the resolution, the minimum unit capacitor that can be turned on and off must be very small. As the process progresses, the size of the minimum unit capacitor gradually decreases. However, it is difficult to achieve a high resolution within a few ppm unless a complicated additional circuit for increasing the resolution is designed. On the contrary, in order to lower the resolution, the minimum unit capacitor must be increased in size. Therefore, it is difficult to design the frequency resolution of the digitally controlled oscillator when the above structures are used.

Third, a tri-state buffer is connected in parallel to a general ring type oscillator, the state of the buffer is turned on and off by a digital code, the output resistance of each stage is changed, and the RC time constant is changed, .

With the third approach, the design of lowering the frequency resolution is easy, but conversely, to increase the resolution, the size of the parallel connected three-state buffer must be very small. It is very difficult to achieve a high resolution within a few tens of ppm even if a fine process of 65 nm or less is used.

In order to solve the above-mentioned disadvantage, as shown in FIG. 1, a structure is used in which an external digital-analog converter is used to convert a digital signal into an analog voltage signal and then applied to an analog voltage controlled oscillator. This is because designs that lower the frequency gain (Hz / volt) of the voltage-controlled oscillator and designs that increase the resolution of the digital-to-analog converter are relatively straightforward and both methods can easily increase the resolution of the digitally controlled oscillator .

However, a commonly used analog voltage controlled oscillator controls the frequency with a single voltage signal. Due to the nonlinearity of the circuit elements, the oscillation frequency curve according to the control voltage is very nonlinear as shown in FIG. This non-linearity can be a significant problem when using a digitally controlled oscillator in a feed-back system such as a phase-locked loop.

Mask design by reducing the magnitude of the output voltage range of the analog converter get narrowing the area of the control voltage, for example, digital-to-end in front of a digital analog converter in order to solve the above problem of the output diagram of V 2 _{cont. min} and V _{cont . max} , it is possible to secure linearity within a narrow region.

However, when a voltage controlled oscillator is actually implemented in a chip, the frequency characteristics of the circuit vary greatly depending on the process, power supply voltage, and temperature, and the four parameters shown in FIG. 2 (V _{cont . Min} , V _{cont . Max} , f _min , f _max ) is very difficult to predict. In the design, the output voltage range of the digital-to-analog converter is V _{cont . min} and V _{cont .} to be included between the _max, i.e. the linear region, even if only the design to ensure the linearity, when actually implemented in a chip V _{cont. min} and V _{cont . the max} value is changed and the linear region is changed, and the control voltage region is out of the linear region, so that the linearity may be broken. If such a characteristic change is severe, if the output voltage range of the digital-to-analog converter deviates completely from the linear region, the possible oscillation frequency range (f _min ~ f _max ) may become too narrow to oscillate at the desired frequency.

When the control voltage is too low or high, some of the transistors in the circuit are out of the saturation region. Even if the control voltage is changed, the amount of current flowing in the delay cell circuit And the oscillation frequency does not change. To solve this problem, it is possible to use a digital-to-analog converter and a current-controlled oscillator which output a current signal instead of a voltage signal as an output. In the case of the current controlled oscillator, since the amount of current flowing in the delay cell is controlled regardless of the threshold voltage of the transistor forming the delay cell, the transistor does not go out of the saturation region and the above-described problem is solved to some extent The linearity can be improved. However, since only one control signal is used, it is vulnerable to power supply voltage noise, and there is still a problem that the phase noise performance of the oscillator is poor due to the noise introduced into the control signal.

These problems can be solved by the embodiments of the present invention described below. Hereinafter, embodiments of the present invention will be described in detail.

3 is a diagram showing an example of a digitally controlled oscillator of the present invention.

3, a digitally controlled oscillator 300 includes a differential digital-to-analog converter 310 that receives a digital code and generates two differential current signals, and a differential-to-analog converter 310 that generates a differential current And a control oscillator 320. Here, it is assumed that the N-bit digital code is a thermometer code.

When the differential digital-to-analog converter 310 is ideally operated, the two differential current signals (the first differential current signal and the second differential current signal) output from the differential digital-to-analog converter 310 are expressed by Equation 1 As shown in Fig.

[Equation 1]

는 디지털 코드가 1만큼 변할 때에 차동 전류 신호들의 크기가 변하는 양으로서, 변환기 이득이다.In Equation (1), 'code' represents the value of the digital code, and the digital code is the thermometer code of N bits of C ₀ through C _{N -1} . Therefore, the value of the digital code is equal to the number of bits having a value of 1 out of N bits of C ₀ to C _{N -1} . I ₀ is a common-mode current of the differential current signal,

Is the amount by which the magnitude of the differential current signals changes when the digital code is changed by one.

The oscillation frequency of the ideal differential current controlled oscillator 320 can be expressed by the following equation (2).

&Quot; (2) "

는 발진기의 기본 발진주파수이며,

는 전류 제어 발진기의 이득이고 단위는

이다. 두 전류 신호 크기의 차이에 따라서 주파수가 제어되기 때문에, 이상적으로는 차동 전류 신호들의 공통 모드 값이 발진기에 영향을 주지 않는다. 따라서, 두 개의 차동 전류 신호들에 공통으로 영향을 주는 외부 잡음(전원전압 잡음 등)이 발진기에 주는 영향이 줄어들고, 그에 따라 위상 잡음 성능이 좋아진다.From here

Is the fundamental oscillation frequency of the oscillator,

Is the gain of the current controlled oscillator and the unit is

to be. Ideally, the common mode value of the differential current signals does not affect the oscillator since the frequency is controlled by the difference between the two current signal magnitudes. Therefore, the influence of external noise (such as power supply voltage noise) affecting the two differential current signals on the oscillator is reduced, thereby improving phase noise performance.

Combining Equations (1) and (2), the oscillation frequency of the digitally controlled oscillator can be expressed as Equation (3).

&Quot; (3) "

의 값이 디지털 제어 발진기의 이득이 되고, 이 값이 작을수록 디지털 제어발진기의 해상도가 높아질 수 있다.therefore,

Is the gain of the digitally controlled oscillator. The smaller the value, the higher the resolution of the digitally controlled oscillator.

FIG. 4A is a diagram showing the digital-analog converter shown in FIG. 3 in detail, and FIG. 4B is a diagram showing an equivalent circuit of the circuit shown in FIG. 4A.

The differential digital-analog converter shown in Fig. 3 can be implemented with the circuit shown in Fig. 4A. As can be seen from Equation (1), the circuit shown in FIG. 4A is to output differential current signals proportional to the value of the digital code consisting of N bits of C ₀ to C _{N -1} .

4A, a current I _T flowing from a fixed current source for flowing a constant current flows in two paths, and N + 1 PMOS transistors for controlling the amount of current flowing in each path Are connected in parallel. Also, the gate width of the N transistors in the left path is W ₀ . Then, the N digital codes (C ₀ to C _{N -1} ) are input to the gates to turn on or turn off the transistors. The remaining one transistor has a width W _S, and the gate of the transistor is grounded and always operates in the turn-on state. The remaining one transistor is a current radiating circuit formed of an NMOS transistor, and converts the current signal flowing in the path into a voltage signal and outputs it. The opposite path is designed identically, and the digital code is inverted. Thus, the sum of the number of transistors in the turn-on state in each of the two paths is constant.

In this case, all the transistors connected in parallel except for the transistor in the turn-off state share the same source node, drain node, and gate node, and therefore, N + 1 transistors are modeled as one transistor as shown in FIG. . In Figure 4b, if the width of that of the left transistors W _1, the width of the right transistor W _2, may be an expression (4) it is satisfied.

&Quot; (4) "

At this time, if the amount of the basic current flowing on both sides is relatively larger than the amount of change of the current according to the digital code, that is, if the difference between I _{cont +} and I _{cont -} is not large, V ₁ , V ₂ ) can be said to be similar. Therefore, the following equation (5) can be established.

&Quot; (5) "

I _{cont +} and I _{cont -} Since the current is separated from one fixed current source, the sum of the magnitudes of the two currents is always I _T. Therefore, the following equation (6) can be established.

&Quot; (6) "

Combining Equations (4) to (6), the following Equation (7) can be established.

&Quot; (7) "

, 즉 해상도는 트랜지스터의 너비인 W0과 WS의 비율에 의해서 결정된다는 사실을 알 수 있다. 따라서 회로를 설계할 때에 트랜지스터의 너비를 바꾸어주는 것만으로 디지털-아날로그 변환기의 해상도를 간단히 설정할 수 있다. 또한, 상기 수학식 6에서 나타났듯이 출력되는 두 개의 차동 전류 신호들의 합은 일정하므로, 외부 잡음의 영향을 덜 받고, 디지털 제어 발진기의 위상 잡음 성능을 높일 수 있다.Referring to Equation (1) to Equation (7), the digital-to-analog converter gains

, That is, the resolution is determined by the ratio of W0 and WS, which is the width of the transistor. Therefore, when designing the circuit, the resolution of the digital-to-analog converter can be simply set by changing the width of the transistor. Also, as shown in Equation (6), since the sum of the two differential current signals outputted is constant, the phase noise performance of the digitally controlled oscillator can be improved by being less influenced by external noise.

The differential current controlled oscillator, which is the remaining block of FIG. 3, can be designed in two configurations, one using a differential interpolator circuit and the other using a latch circuit to connect a negative resistor to the output node of the differential amplifier They are connected in parallel.

5 is a diagram showing an example of a differential current controlled oscillator.

Referring to FIG. 5, a ring oscillator is designed by connecting a plurality of stages of delay cells in series. The interior of each stage of the delay cell is divided into a path having one buffer (fast path) and two paths having a slow path . When a pulse is input to one delay cell, a pulse is delivered with a small delay through a fast path and a pulse is delivered with a large delay through a slow path. If the weight of the fast path is larger, the delay time of the delay cell will be small, and in the opposite case, the delay time will be large. Since the oscillation frequency changes according to the delay time of the ring-shaped delay cell, the oscillation frequency of the ring-shaped oscillator changes according to the value of a, which is a weight parameter for adjusting the interpolator of each delay cell.

6A and 6B are diagrams illustrating the delay cells included in the differential current controlled oscillator.

6A and 6B, an interpolator circuit in which two pairs of differential NMOS pairs share a pair of resistors functions as two delay buffers, while at the same time changing the weight of the input according to the current flowing in each differential NMOS pair It acts as an adder. Since the weight of the interpolator is adjusted by the current signal and the sum of the two weights is always constant, it can be usefully used as a delay cell constituting a differential current controlled oscillator.

7 is a diagram showing another example of the differential current controlled oscillator.

FIG. 7 shows an embodiment in which a ring oscillator is designed in a different manner using an interpolator. The previous structure and principle are similar, but not all interpolators are used in all delay cells. An interpolator is placed in the middle of the ring oscillator, and the signal passed through the N-stage delay cell and the M-stage delay cell are further passed through the N + M stage. Add the signal. If the weight for the signal through the N stages is larger, the oscillation frequency increases accordingly.

8 is a diagram showing another example of the differential current controlled oscillator.

Figure 8 shows another embodiment of designing a differential current controlled oscillator without using an interpolator. When additional latches are connected in parallel to a typical differential amplifier, this latch acts as a parallel connection of a resistor with a negative resistance when analyzed with a small signal equivalent circuit. At this time, the total output resistance value changes according to the ratio of the current flowing in the amplifier main body (left side in Fig. 8) and the current flowing in the latch (right side in Fig. 8), and the RC time constant is changed to change the delay time. When the ring oscillator is designed by combining these delay cells, the oscillation frequency is controlled in accordance with the ratio of the current flowing in the latch to the current flowing in the amplifier main body, and thus operates as a differential current controlled oscillator.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the equivalents of the claims, as well as the claims.

310: Differential Digital-to-Analog Converter
320: Differential current controlled oscillator

Claims (10)

A differential digital-to-analog converter for receiving an N-bit digital code signal as an input and generating a first differential current signal and a second differential current signal corresponding to the digital code signal; And
A differential current control oscillator for generating an oscillation frequency that is adaptively adjusted according to a difference between the first differential current signal and the second differential current signal,
Lt; / RTI >
The differential digital-to-
Wherein the N-bit digital code signal is input to a gate of a plurality of first transistors connected in parallel on one side to generate the first differential current signal by operating each of the plurality of first transistors,
The inverted signal of the N-bit digital code signal is inputted to the gates of the plurality of second transistors connected in parallel on the other side of the side surface to operate each of the plurality of second transistors, / RTI > delete The method according to claim 1,
Wherein the gate width of the transistors whose gates are input to the gates of the plurality of first transistors and the second transistors and the gate widths of the gates of the transistors whose gates are grounded are different from each other. The method according to claim 1,
Wherein the gain of the differential digital-to-analog converter is determined by the ratio of the gate width of transistors to which the digital code is input to the gate and the gate width of the transistor to which the gate is grounded. The method according to claim 1,
Wherein the differential current controlled oscillator comprises:
A digitally controlled oscillator that generates an oscillating frequency using a differential interpolator circuit or a latch circuit. Receiving an N-bit digital code signal as an input, generating a first differential current signal and a second differential current signal corresponding to the digital code signal; And
Generating an oscillation frequency that is adaptively adjusted according to a difference between the first differential current signal and the second differential current signal,
Lt; / RTI >
Wherein the step of generating the first differential current signal and the second differential current signal comprises:
Wherein the N-bit digital code signal is input to a gate of a plurality of first transistors connected in parallel on one side to generate the first differential current signal by operating each of the plurality of first transistors,
The inverted signal of the N-bit digital code signal is inputted to the gates of the plurality of second transistors connected in parallel on the other side of the side surface to operate each of the plurality of second transistors, And generating a digital control oscillation signal. delete The method according to claim 6,
Wherein a gate width of a transistor in which a digital code is input as a gate and a gate width of a transistor in which a gate is grounded are different from each other among the plurality of first transistors and the second transistors. 9. The method of claim 8,
Wherein the gain of the differential digital-analog conversion is determined by the ratio of the gate width of the transistors to which the digital code is input to the gate and the gate width of the transistor to which the gate is grounded. The method according to claim 6,
The step of generating the oscillating frequency comprises:
A digital controlled oscillation method for generating an oscillation frequency using a differential interpolator circuit or a latch circuit.

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