JP2009176980A - Power mos transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power MOS transistor which is hard to be restricted by electromigration, lower in wiring resistance and power loss, and has a little restriction on arrangement of a pad. <P>SOLUTION: In the MOS transistor, a source region 2 and a drain region 3 formed in a semiconductor substrate 1 adjoin each other holding a gate 4 therebetween which is formed into a lattice type, and the transistor includes metal wires 5, 6, 7 of three layers which are formed in order on the semiconductor substrate 1. The metal wires are electrically connected to the source region and the drain region, and when the drain region is connected to the metal wire 7 of the third layer, the source region is connected to the metal wire 6 of the second layer and the metal wire 5 of the first layer. Drain wiring of the metal wire 7 of the third layer is arranged so that it may cover an entire region of the semiconductor substrate 1, and source wiring of the metal wires 5, 6 of the first layer and the second layer are arranged so that these may cover an entire region of the metal wires of the first layer and the second layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a power MOS transistor in which a source region and a drain region are formed so as to be adjacent to each other across a gate formed in a lattice shape.

  Conventionally, a MOS transistor having a finger-shaped gate is known as a power MOS transistor (see FIG. 9). This transistor has a structure in which source / drain regions are formed on the left and right sides of the finger part of the gate. In order to increase the efficiency of the transistor width per unit area of such a power MOS transistor, a MOS transistor having a lattice shape (also called a waffle) has been used. This transistor is a gate whose lattice is made of polysilicon or the like, and a diffusion region surrounded by the gate constitutes a source or a drain. When a certain diffusion region is a source, the upper, lower, left and right diffusion regions adjacent to the diffusion region are drains. When this portion is viewed as a whole, the source and drain are continuously formed in an oblique direction.

  With reference to FIG. 7, a conventional lattice-like MOS transistor disclosed in Patent Document 1 will be described. 7A is a cross-sectional view of the lattice-like MOS transistor (corresponding to a portion along the line AA ′ in FIG. 7B), and FIG. 7B shows the first-layer metal wiring 77 and the first metal wiring 77. FIG. 5 is a schematic plan view of a MOS transistor when a two-layer metal wiring 78 is removed. A back gate diffusion layer 72 is formed on the surface of the P-type silicon substrate 71. A source region 73 and a drain region 74 are repeatedly formed in the surface layer portion of the back gate diffusion layer 72. A polysilicon gate 76 is formed on the channel region between the source region 73 and the drain region 74 via a gate oxide film 75. A first layer metal wiring 77 formed on the silicon substrate 71 is connected to the source region 73 through a contact formed in the lower interlayer insulating film. A second layer metal wiring 78 formed on the upper interlayer insulating film is connected to the drain region 74 through a first layer metal wiring 77 and via contacts formed in the upper interlayer insulating film. Yes.

FIG. 7B shows the MOS transistor when the first layer metal wiring 77 and the second layer metal wiring 78 are removed. The source region 73 and the drain region 74 are formed so that the source and the drain are adjacent to each other in a checkered pattern with the polysilicon gate 76 formed in a lattice shape interposed therebetween (hereinafter, the source region and the drain region). A transistor whose region is arranged in such a pattern is called a lattice-like MOS transistor). Such a conventional lattice-shaped MOS transistor can increase current capability per unit area because current can flow in the horizontal and vertical directions on the chip.
Since the power MOS transistor is usually large in size, the power MOS transistor is constituted by an aggregate of a plurality of parts. When viewed from the chip surface, the plurality of source and drain diffusion regions alternately arranged in a lattice form are parallel to each other in an oblique direction. These diffusion regions are connected to the first layer metal wiring through contacts. The first layer metal wiring is connected to the second layer metal wiring. The second layer metal wiring is connected to a pad (PAD) when connected to the outside of the IC package as an input / output terminal.
JP 2006-245040 A

In the first layer metal wiring existing in the boundary region of the second layer metal wiring connected to the source and drain formed in the conventional semiconductor chip, it is connected to the drain below the second layer metal wiring connected to the source. The first-layer metal wiring (drain wiring) connected to the drain and the first-layer metal wiring (source wiring) connected to the source under the second-layer metal wiring connected to the drain are connected via this boundary region. In this boundary region, the current load on the metal is large and is subject to electromigration restrictions (see FIG. 8).
Considering the route through which the current flows, the elongated wiring of the first layer metal wiring and the wiring of the detour route increase the wiring resistance, resulting in the power loss of the transistor.
The second layer metal wiring connected to the source and drain of the transistor is laid out so as to divide the wiring region on the transistor into two. Therefore, when both are connected to the pad, the source pad and the drain pad are the outer peripheral portions excluding the boundary region between the respective second layer metal wirings (source wiring and drain wiring) connected to the source and drain. Must be arranged to face each other. Similarly, when there is an element connected in parallel or in series with the transistor, a placement restriction is generated.

  The present invention has been made to solve the above-described problems, and provides a power MOS transistor that is less susceptible to electromigration restrictions, has low wiring resistance, and has less transistor power loss and less pad arrangement restrictions.

  One aspect of the power MOS transistor of the present invention is a MOS transistor in which a semiconductor substrate and a source region and a drain region formed in the semiconductor substrate are arranged adjacent to each other with a gate formed in a lattice shape interposed therebetween ( A grid-like MOS transistor), comprising a plurality of metal wirings sequentially formed on the semiconductor substrate and connected to the source region or the drain region, the metal wiring connected to the one region and the other The metal wiring is connected to the source region or the drain region so that the wiring resistance of the metal wiring connected to the region is the same. In the case of an n-layer multilayer wiring in which the plurality of metal wirings are stacked, the number of metal wirings to be combined with the uppermost metal wiring of the multilayer wiring as a source wiring connected to the source region is k (n> k ≧ Assuming that the combined sheet resistance Ra of the source wiring is (Rx.times.Rtop) / (Rx + k.times.Rtop) (Rtop is the sheet resistance of the uppermost metal wiring, Rx is a metal wiring other than the uppermost metal wiring) The combined sheet resistance Rb of the drain wiring is expressed as Rx / (n-1-k), and the combined sheet resistance Ra and the combined sheet resistance Rb may be equal to each other. . The drain wiring may be arranged on the uppermost metal wiring of the multilayer wiring. When the source region is connected to the uppermost third layer metal wiring, the drain region is connected to the second layer metal wiring and the first layer metal wiring below the second layer metal wiring. When the drain region is connected to the third layer metal wiring, the source region may be connected to the second layer metal wiring and the first layer metal wiring. The first layer metal wiring and the second layer metal wiring may be flattened. The uppermost third-layer metal wiring may have a thickness greater than that of the first-layer metal wiring and the second-layer metal wiring.

  With the above configuration, the present invention can provide a power MOS transistor that is less susceptible to electromigration restrictions, has low wiring resistance, and has less transistor power loss and less pad arrangement restrictions.

  Hereinafter, embodiments of the invention will be described with reference to examples.

First, Embodiment 1 will be described with reference to FIGS.
FIG. 1 is a plan view for explaining the state of the surface of a semiconductor substrate on which a power MOS transistor (lattice MOS transistor) according to this embodiment is formed, and a sectional view taken along line AA ′. FIG. FIG. 3 is a plan view for explaining the state of the first layer metal wiring formed on the surface of the semiconductor substrate 1 and a sectional view of a portion along the line BB ′. FIG. FIG. 4 is a plan view for explaining the state of the layer metal wiring, and a sectional view of the portion along the line CC ′. FIG. 4 is a plan view for explaining the state of the third layer metal wiring formed on the surface of the semiconductor substrate of FIG. FIG. 5 is a plan view for explaining the state of the metal wiring formed on the surface of the semiconductor substrate of FIG. 1.
The power MOS transistor of this embodiment includes a lattice MOS transistor formed on a semiconductor substrate 1 such as silicon, and three layers of metal wirings sequentially formed on the semiconductor substrate 1. The source region 2 of the lattice MOS transistor is connected to the first and second layer metal wirings 5 and 6 through the contact 8 or the contact 8 and the via 10, and the drain region 3 is the uppermost third layer metal. Connected to wiring 7.

In a semiconductor substrate 1 such as silicon, a source region 2 and a drain region 3 are arranged adjacent to each other with a gate 4 formed in a lattice shape.
As shown in FIG. 4, a gate 4 made of polysilicon or the like is formed on a channel region between the source region 2 and the drain region 3 through a gate oxide film (not shown). The surface of the semiconductor substrate 1 on which the gate 4 is formed is covered with a lower interlayer insulating film (not shown). In the lower interlayer insulating film, the first layer metal wiring 5 is formed on the flattened surface. The first layer metal wiring 5 is covered with an intermediate interlayer insulating film (not shown). In the intermediate interlayer insulating film, the second layer metal wiring 6 is formed on the flattened surface. The second layer metal wiring 6 is covered with an upper interlayer insulating film (not shown). A third layer metal wiring 7 is formed on the surface of the upper interlayer insulating film. The first layer metal wiring 5 is electrically connected to the source region 2 and the drain region 3 via contacts 8 and 9 embedded in the lower interlayer insulating film, respectively. The second layer metal wiring 6 is electrically connected to the first layer metal wiring 5 through vias 10 and 11 embedded in an intermediate interlayer insulating film. The third layer metal wiring 7 is electrically connected to the second layer metal wiring 6 through a via 12 embedded in an upper interlayer insulating film.

As shown in FIG. 2, most of the first layer metal wiring 5 is used as a source wiring, and a part of the island region is used as a relay wiring electrically connected to the drain wiring. The source wiring region is connected to the source region 2 through the contact 8. The island region is connected to the drain region 3 through the contact 9.
As shown in FIG. 3, the second layer metal wiring 6 is mostly used as a source wiring, and a part of the island region is used as a relay wiring electrically connected to the drain wiring. The source wiring region is connected to the source wiring region of the first layer metal wiring 5 through the via 10. The island region is connected to the drain wiring region of the first layer metal wiring 5 through the via 11.
The third layer metal wiring 7 is used as a drain wiring as shown in FIG. The drain wiring is electrically connected to the island region of the second layer metal wiring 6 through the via 12. The drain wiring of the third layer metal wiring 7 is arranged so as to cover the entire region of the semiconductor substrate 1, and the third layer metal wiring 7 → via 12 → second layer metal wiring 6 → via 11 → first layer metal wiring 5. The contact 9 is connected to the drain region 3. The source wiring is arranged so as to cover a region avoiding the island region of the first layer metal wiring and the second layer metal wiring.

In general, when a multilayer metal wiring is used in the manufacturing process of a semiconductor device, the metal layer excluding the uppermost layer is deposited on a silicon wafer and then subjected to a planarization process to facilitate subsequent process steps. Since it is done, it is thin. On the other hand, the metal wiring of the uppermost layer (corresponding to the third layer in this embodiment) omits an extra step and is not subjected to planarization. Accordingly, the thickness of the metal wiring is such that the uppermost metal layer (top metal) is thicker than the metals of the other metal layers. The sheet resistance value of the metal is inversely proportional to the thickness of the metal layer, and the allowable current value related to electromigration increases in proportion to the thickness of the metal layer. Therefore, the uppermost metal wiring is superior in current characteristics to the other metal wiring.
In a product using three-layer metal wiring, when considering the metal distribution method to the source region and drain region, when the third-layer metal wiring (the uppermost metal wiring) is used as the source wiring for the above reason, When the first-layer metal wiring and the second-layer metal wiring are drain wirings, and the third-layer metal wiring is a drain wiring, a combination in which the first-layer metal wiring and the second-layer metal wiring are source wirings is optimal.

In the wiring configuration of this embodiment, each of the first layer metal wiring and the second layer metal wiring has a substantial wiring area smaller than that of the third layer metal wiring. The reason is that in order to avoid various contacts connecting from the third layer metal wiring to the source / drain region, the metal wiring of the first layer and the second layer has a shape in which a slit exists, and the substantial wiring region This is because becomes smaller.
In this embodiment, in order to balance the current characteristics of the source and drain, wiring resistance, and electromigration, the first layer and second layer metal wirings are used as source (drain) wirings, and the third layer metal wiring is used as a drain. (Source) wiring combination. This can be said to be effective even when the flattening process is not performed.

For example, when the above three-layer multilayer wiring is to be realized with the same wiring configuration in the two-layer structure, that is, when “first layer metal wiring + second layer metal wiring” is changed to “first layer metal wiring”. The first layer metal wiring is significantly inferior in wiring resistance and electromigration as compared with the second layer metal wiring corresponding to the third layer metal wiring of the present invention. That is, the allowable current value of the transistor is determined by the first layer metal wiring. In general, since the source and drain currents of MOS transistors are equal, it is desirable that the resistances and allowable current values of the source and drain wirings are equal. Therefore, as in this embodiment, the third layer metal wiring is used as the drain wiring, and the first layer + second layer metal wiring is used as the source wiring. Further, since the source wiring and the drain wiring are not divided and distributed in the wiring region of the transistor, the arrangement of the source and drain pads is not restricted.
In the first embodiment, the case where the metal wiring has three layers has been described. For example, in the case of the metal wiring having four layers, the source (drain) is 1 layer + 2 layers and the drain (source) is 3 layers + 4 layers. I can do it. Further, the source (drain) may be 1 layer + 2 layers + 3 layers, and the drain (source) may be 4 layers. Even in the case of five or more metal wiring layers, the source and drain can be optimally combined to balance the resistance value.
In this embodiment, a grid-like MOS transistor with less wiring arrangement and less pad arrangement restrictions can be obtained without being restricted by electromigration.

Next, Embodiment 2 will be described with reference to FIG.
FIG. 6 is a cross-sectional view for explaining the state of the first layer, the second layer, and the third layer metal wiring provided on the surface of the semiconductor substrate on which the lattice MOS transistor which is the power MOS transistor of this embodiment is formed. . In this embodiment, the source is a third layer metal wiring, and the drain is a first layer and second layer metal wiring.
The power MOS transistor includes a lattice MOS transistor formed on the semiconductor substrate 21 and three layers of metal wirings sequentially formed on the semiconductor substrate 21. The source region 22 of the lattice MOS transistor is connected to the uppermost third-layer metal wiring 27 through contacts and vias, and the drain region 23 is connected to the first-layer and second-layer metal wirings through contacts and vias. 25, 26. In a semiconductor substrate 21 such as silicon, a source region 22 and a drain region 23 are arranged adjacent to each other with a gate 24 formed in a lattice shape.

  As shown in FIG. 6, a gate 24 made of polysilicon or the like is formed on a channel region between the source region 22 and the drain region 23 through a gate oxide film (not shown). On the semiconductor substrate 21, a first layer metal wiring 25, a second layer metal wiring 26, and a third layer metal wiring 27 are sequentially formed. The first layer metal wiring 25 is electrically connected to the source region 22 and the drain region 23 through the contacts 14 and 13, respectively. The second layer metal wiring 26 is electrically connected to the first layer metal wiring 25 through the vias 15 and 16. The third layer metal wiring 27 is electrically connected to the second layer metal wiring 26 through the via 17.

  The first layer metal wiring 25 is mostly used as a drain wiring, and a part of the island region is used as a relay wiring electrically connected to the source wiring. The drain wiring region is connected to the drain region 23 through the contact 13. The island region is connected to the source region 22 via the contact 14. The second layer metal wiring 26 is mostly used as a drain wiring, and a part of the island region is used as a relay wiring that is electrically connected to the source wiring. The drain wiring region is connected to the drain wiring region of the first layer metal wiring 25 through the via 15. The island region is connected to the island region of the first layer metal wiring 25 through the first layer via 16. The third layer metal wiring 27 is used as a source wiring. The source wiring is electrically connected to the island region of the second layer metal wiring 26 through the second layer via 17. The source wiring of the third layer metal wiring 27 is arranged so as to cover the entire region of the semiconductor substrate 21, and the third layer metal wiring 27 → via 17 → second layer metal wiring 26 → via 16 → first layer metal wiring 25. → Contact 14 → Source region 22 is configured to be connected. The drain wiring is arranged so as to cover the entire area of the first layer metal wiring and the second layer metal wiring, avoiding the island region of the first layer metal wiring and the second layer metal wiring.

In a product using three-layer metal wiring, when a metal distribution method to the source region and drain region is considered, the third-layer metal wiring (uppermost-layer metal wiring) is replaced with the source wiring for the same reason as in the first embodiment. Then, the combination of first layer metal wiring + second layer metal wiring is optimal for the drain wiring.
Each wiring of the first layer and the second layer metal wiring has a wiring area smaller than that of the third layer metal wiring. In order to compensate for this, in this embodiment, the first layer and the second layer metal wiring are replaced with each other. A combination of source (drain) wiring and third layer metal wiring as drain (source) wiring was used to balance the wiring resistance and electromigration.
Since the MOS transistor preferably has the same source and drain currents, and the source and drain wirings have the same resistance and allowable current values, the third layer metal wiring is used as the source wiring, and the first layer + second layer Metal wiring was used as drain wiring. Further, since the source wiring and the drain wiring are not divided and distributed in the wiring region of the transistor, the arrangement of the source and drain pads is not restricted.

In this embodiment, the contacts and vias, which are connection wirings, are each composed of a plurality of connection bodies. For example, the source region 22 and the intermediate wiring of the first layer metal wiring 25 are connected by two contacts 14, and the first layer metal wiring 25 that is a drain wiring and the second layer metal wiring 26 that is also a drain wiring are connected. The via 15 to be connected is composed of three connected bodies. By dispersing the current path in this way, the current flows uniformly and the wiring resistance is reduced.
This embodiment is less susceptible to electromigration restrictions, and can provide a lattice MOS transistor with less wiring resistance and less transistor power loss and less pad arrangement restrictions.

As described above, as described in each embodiment, it is desirable that the power MOS transistors have the same source and drain currents, and the resistance and allowable current value of each source / drain wiring are the same. Based on such a premise, an ideal combination of metal wirings in a metal multi-layer process constituting a multi-layer wiring of a power MOS transistor is expressed as follows.
Assume that the source wiring and drain wiring electrically connected to the source and drain of the power MOS transistor are composed of n-layer metal wiring, and the sheet resistance value of the metal wiring of each layer at this time is obtained. Here, the sheet resistance value of the wiring (Top metal) in the uppermost layer of the multilayer wiring that is not subjected to the planarization process is Rtop. In addition, with respect to other metal wirings that are subjected to planarization processing, the substantial increase in resistance due to the reduction of the wiring area by the slit that avoids the island area provided to connect to the lower layer wiring or the upper layer wiring is considered. Sheet resistance Rx of a typical metal wiring (the thickness of the metal wiring is the same except for the uppermost layer).

Assuming that the number of metals combined with the Top metal as the source wiring or drain wiring is k (integer of n> k ≧ 0), the combined sheet resistance Ra of the source wiring (in this embodiment, for example, the wiring including the Top metal is defined as the source wiring. Is expressed as the following equation.
1 / Ra = 1 / Rtop + 1 / Rn-1 + 1 / Rn-2 + ... + 1 / Rn-k = 1 / Rtop + k / Rx (1)
Therefore, Ra = (Rx.times.Rtop) / (Rx + k.times.Rtop) (2)
The combined sheet resistance Rb of the drain wiring is expressed by the following equation.
1 / Rb = 1 / Rn-1-k + 1 / Rn-2-k + ... + 1 / R1 = (n-1-k) / Rx (3)
Therefore, Rb = Rx / (n-1-k) (4)
Of course, the wiring resistance (Ra + Rb) of the power MOS transistor is desirably as small as possible. Furthermore, in consideration of electromigration, in order to balance the source and drain currents, it is necessary to make the combined resistance values of Ra and Rb close to each other. Therefore, it is desirable that the formulas (2) and (4) are equal (Ra = Rb). That is, it is optimal to select a combination of metal wirings in order to realize Ra = Rb.

FIG. 3 is a plan view for explaining the state of the surface of the semiconductor substrate on which the lattice MOS transistor, which is a power MOS transistor according to the first embodiment, is formed, and a cross-sectional view of a portion along the line AA ′. The top view explaining the state of the 1st layer metal wiring formed in the semiconductor substrate surface of FIG. 1, and sectional drawing of the part along a BB 'line. The top view explaining the state of the 2nd layer metal wiring formed in the semiconductor substrate surface of FIG. 1, and sectional drawing of the part along a CC 'line. The top view explaining the state of the 3rd layer metal wiring formed in the semiconductor substrate surface of FIG. 1, and sectional drawing of the part along a DD 'line. The top view explaining the state of the metal wiring formed in the semiconductor substrate surface of FIG. Sectional drawing explaining the state of the 1st layer, 2nd layer, and 3rd layer metal wiring provided in the semiconductor substrate surface in which the grid | lattice-like MOS transistor which is a power MOS transistor of Example 2 was formed. (A) Cross-sectional view of a lattice MOS transistor which is a conventional power MOS transistor, and (b) a schematic plan view of the lattice MOS transistor when the first layer metal wiring and the second layer metal wiring in (a) are removed. A schematic plan view for explaining the state of the first layer and the second layer metal wiring provided on the surface of the semiconductor substrate on which the lattice-like MOS transistor, which is a conventional power MOS transistor, is formed, and a cross section along the line BB ′. Figure. FIG. 6 is a schematic plan view of a conventional power MOS transistor having a finger-shaped gate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 21 ... Semiconductor substrate 2, 22 ... Source region 3, 23 ... Drain region 4, 24 ... Gate 5, 25 ... First layer metal wiring 6, 26 ... Second Layer metal wiring 7, 27 ... Third layer metal wiring 8, 9, 13, 14 ... Contact 10, 11, 12, 15, 16, 17 ... Via

Claims (5)

A MOS transistor in which a semiconductor substrate and a source region and a drain region formed in the semiconductor substrate are arranged so as to be adjacent to each other with a gate formed in a lattice shape interposed therebetween, which are sequentially formed on the semiconductor substrate. A plurality of metal wirings connected to the source region or the drain region, and the metal wiring connected to the one region and the metal wiring connected to the other region have the same wiring resistance. A power MOS transistor comprising a metal wiring connected to the source region or drain region. In the case of an n-layer multilayer wiring in which the plurality of metal wirings are stacked, the number of metal wirings to be combined with the uppermost metal wiring of the multilayer wiring as a source wiring connected to the source region is k (n> k ≧ Assuming that the combined sheet resistance Ra of the source wiring is (Rx.times.Rtop) / (Rx + k.times.Rtop) (Rtop is the sheet resistance of the uppermost metal wiring, Rx is a metal wiring other than the uppermost metal wiring) The combined sheet resistance Rb of the drain wiring is expressed as Rx / (n-1-k), and the combined sheet resistance Ra and the combined sheet resistance Rb are equal to each other. The power MOS transistor according to claim 1. When the source region is connected to the uppermost third layer metal wiring, the drain region is connected to the second layer metal wiring and the first layer metal wiring below the second layer metal wiring. 3. When the drain region is connected to the third-layer metal wiring, the source region is connected to the second-layer metal wiring and the first-layer metal wiring. Power MOS transistor. 4. The power MOS transistor according to claim 3, wherein the first layer metal wiring and the second layer metal wiring are planarized. 5. 5. The power MOS transistor according to claim 3, wherein the third-layer metal wiring in the uppermost layer has a thickness greater than that of the first-layer metal wiring and the second-layer metal wiring.

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