JP5304195B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce resistance of gate wiring by suppressing an increase in wiring resistance of a source and a drain. <P>SOLUTION: In a semiconductor device, a first wiring layer 20 disposed at a position closest to a semiconductor substrate 10 includes first source wiring 21 electrically connected to a source region 15 of a semiconductor element, first drain wiring 22 electrically connected to a drain region 12 of the semiconductor element, and a relay portion 23 electrically connected to a gate electrode 17. Then the relay portion 23 is arranged in a gap 24 provided by a source-side recessed portion 21a and a drain-side recessed portion 22a provided in the first source wiring 21 and first drain wiring 22 respectively. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device including a horizontal semiconductor element.

  Conventionally, in order to increase the speed of a power element used as a switching element, it is required to reduce the resistance of the gate wiring. Therefore, as a technique for reducing the resistance of the gate wiring, a silicide process for metallizing a part of polysilicon as a gate material is employed.

  However, there is a problem in that the process cost increases due to the addition of the silicide process in manufacturing the semiconductor device. On the other hand, Patent Document 1 proposes a technique of backing a gate wiring with a wiring used for a source / drain as a technique for reducing the resistance of the gate wiring at a low cost.

Patent Document 1 proposes a semiconductor device including a trench lateral power semiconductor element having a mesh pattern trench provided with a gate wiring such as polysilicon extending in parallel with a source wiring and a drain wiring. A gate wiring is reduced by forming a backing wiring such as aluminum on the gate wiring.
Japanese Patent Laid-Open No. 2005-12019

  However, the conventional technique has a problem in that the width of the source wiring and the drain wiring must be narrowed because the gate wiring is provided in parallel with the source wiring and the drain wiring in the same wiring layer as the source wiring and the drain wiring. As a result, the source / drain wiring resistance increases, and the on-resistance of the power semiconductor element increases.

  Further, since the gate wiring such as polysilicon is provided along the source wiring and the drain wiring, it functions as a resistor. For this reason, distribution occurs in the on / off timing of switching in the cell, and the current flowing in the cell is biased. Accordingly, there is a problem that the efficiency of the power semiconductor element is lowered.

  The present invention has been made in view of the above points, and it is an object of the present invention to suppress an increase in source / drain wiring resistance and to reduce the resistance of a gate wiring.

  In order to achieve the above object, according to the first aspect of the present invention, a lateral semiconductor element including a source region (15), a drain region (12), and a gate electrode (17) is formed on a semiconductor substrate (10). A semiconductor device in which a plurality of wiring layers are formed on a semiconductor substrate (10), and the first wiring layer (20) located closest to the semiconductor substrate (10) among the plurality of wiring layers is a semiconductor A first source wiring (21) electrically connected to the source region (15) of the element, a first drain wiring (22) electrically connected to the drain region (12) of the semiconductor element, and a gate electrode ( 17) and the first source wiring (21) and the first drain wiring (22) in a direction parallel to the surface (11) of the semiconductor substrate (10). Arranged in stripes One or both of the first source wiring (21) and the first drain wiring (22) are recessed portions (21a, 22a) that widen the distance between the first source wiring (21) and the first drain wiring (22). The relay section (23) includes a first source wiring (21) widened by a recess (21a, 22a) between the first source wiring (21) and the first drain wiring (22). It is characterized by being arranged in the gaps (24, 26, 27) with respect to one drain wiring (22).

  This eliminates the need to reduce the entire widths of the first source wiring (21) and the first drain wiring (22), thereby increasing the wiring resistance of the first source wiring (21) and the first drain wiring (22). Can be suppressed.

  Further, a gate voltage is applied to the gate electrode (17) via a relay portion (23) that functions as a connection portion to the wiring layer on the first wiring layer (20). For this reason, it is possible to significantly reduce the influence of the resistance of the gate electrode (17) on the gate voltage according to the distance from the gate pad to the gate of the semiconductor element. Therefore, the gate resistance of the semiconductor element can be reduced.

In the first aspect of the present invention, the first source wiring (21) includes a source-side recess (21a) in which the width of a part of the first source wiring (21) is narrowed as a recess, and the first drain wiring ( 22) includes a drain-side recess (22a) in which a width of a part of the first drain wiring (22) is narrowed as a recess, and the source-side recess (21a) and the drain-side recess (22a) are opposed to each other. The relay portion (23) is widened by the source-side recess (21a) and the drain-side recess (22a) between the first source wiring (21) and the first drain wiring (22). It is arranged in the gap (24).

In the invention according to claim 7 , the first source wiring (21) includes a source-side recess (21a) in which a part of the width of the first source wiring (21) is narrowed as a recess, and the relay part (23). Is arranged in a gap (26) widened by the source-side recess (21a) between the first source wiring (21) and the first drain wiring (22).

In the invention according to claim 8 , the first drain wiring (22) includes a drain-side recess (22a) in which a part of the width of the first drain wiring (22) is narrowed as a recess, and the relay section (23). Are arranged in a gap (27) widened by the drain-side recess (22a) between the first source wiring (21) and the first drain wiring (22).

According to the second aspect of the present invention, the first source wiring (21) includes a source-side recess (21a) in which a part of the width of the first source wiring (21) is narrowed as a recess, and the first drain wiring ( 22) includes a drain-side recess (22a) in which a part of the width of the first drain wiring (22) is narrowed as a recess, and the relay section (23) is connected to the first source wiring (21) and the first drain wiring (22). Between the drain wiring (22) and the drain wiring (22), the drain wiring (22a) is disposed in the gap (26) between the first drain wiring (22) and the source side concave section (21a) widened by the source side concave section (21a). It is characterized by being arranged in a gap (27) between the first source wiring (21) widened by the side recess (22a) and the drain side recess (22a).

  As described above, the source side recess (21a) and the drain side recess (22a) are provided in at least one of the first source wiring (21) and the first drain wiring (22). Thereby, the relay part (23) connected to the gate electrode (17) can be arranged without making the entire first source wiring (21) and first drain wiring (22) thin.

According to the third and ninth aspects of the present invention, the plurality of wiring layers include the second wiring layer (30) on the first wiring layer (20), and the second wiring layer (30) includes the first wiring layer (30). The second source wiring (31) electrically connected to the source wiring (21), the second drain wiring (32) electrically connected to the first drain wiring (22), and the relay section (23) It is characterized by comprising an electrically connected backing wiring (33).

  Thereby, a gate voltage can be applied to the gate electrode (17) from the backing wiring (33) via the relay portion (23). That is, the gate resistance can be substantially the resistance of the backing wiring (33).

As in the fourth aspect of the invention, the source region (15) and the drain region (12) may be formed in a stripe shape on the semiconductor substrate (10).

As in the fifth and sixth aspects of the present invention, the source region (15) and the drain region (12) may be formed in a mesh shape on the semiconductor substrate (10).

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention.

  As illustrated in FIG. 1, the semiconductor device includes a semiconductor substrate 10 and a plurality of wiring layers formed on the semiconductor substrate 10. An N-type silicon substrate is used as the semiconductor substrate 10. A lateral diffusion MOS (LDMOS) transistor is formed as a semiconductor element on the surface 11 side of the semiconductor substrate 10.

  Specifically, N + type drain regions 12 and P type channel regions 13 are alternately formed in one direction parallel to the surface 11 of the semiconductor substrate 10 in the surface layer portion of the N type semiconductor substrate 10. In the present embodiment, the drain regions 12 and the channel regions 13 are alternately arranged in stripes in a direction parallel to the surface 11 of the semiconductor substrate 10. A LOCOS oxide film 14 is formed so as to sandwich the drain region 12.

  On the other hand, N + type source regions 15 are formed on the surface layer portion of the channel region 13 so as to be separated from each other. The source region 15 extends in one direction parallel to the surface 11 of the semiconductor substrate 10 together with the channel region 13. A P + type body region 16 is formed between the source regions 15. The drain region 12 corresponds to the drain of the LDMOS transistor, and the source region 15 corresponds to the source of the LDMOS transistor.

  Further, a gate electrode 17 is formed to cover a part of the source region 15, an outer edge of the channel region 13, a part of the surface 11 of the semiconductor substrate 10, and a part of the LOCOS oxide film 14. The gate electrode 17 is made of, for example, polysilicon.

  An interlayer insulating film 18 made of a PSG film or the like is formed on the semiconductor substrate 10 having such a structure. The interlayer insulating film is provided with contact holes exposing part of the source region 15, part of the body region 16, part of the drain region 12, and part of the gate electrode 17. A first wiring layer 20 located closest to the semiconductor substrate 10 among the plurality of wiring layers is formed in the contact hole and on the interlayer insulating film 18.

  The first wiring layer 20 includes a first source wiring 21 connected to the source region 15 and the body region 16, a first drain wiring 22 connected to the drain region 12, and a relay electrically connected to the gate electrode 17. Part 23.

  The first source wiring 21, the first drain wiring 22, and the relay portion 23 are formed on the W (tungsten) plug formed in the contact hole provided in the interlayer insulating film 18 and the interlayer insulating film 18. 1stAl (aluminum). This configuration is an example, and of course, the entire first source wiring 21, the entire first drain wiring 22, and the entire relay portion 23 may be formed of only Al.

  FIG. 2 is a plan view showing a layout of a plurality of wiring layers, and FIG. 2A is a plan view showing a part of the layout of the first wiring layer 20. 2A corresponds to the cross-sectional view of FIG.

  As shown in FIG. 2A, the first source lines 21 and the first drain lines 22 are alternately arranged in a stripe shape in a direction parallel to the surface 11 of the semiconductor substrate 10. This is because the first source wiring 21 and the first drain wiring 22 are provided corresponding to the source region 15 and the drain region 12 of the semiconductor element provided in a stripe shape. The width of the first source line 21 and the first drain line 22 is, for example, less than 10 μm.

  In the present embodiment, the first source line 21 includes a source-side recess 21 a in which a part of the first source line 21 is narrowed. Similarly, the first drain wiring 22 includes a drain-side recess 22a in which a part of the first drain wiring 22 is narrowed. In other words, the source-side recess 21a is a portion where the first source wiring 21 is recessed in a direction perpendicular to the direction in which the first source wiring 21 is extended. Similarly, the drain-side recess 22a is a portion where the first drain wiring 22 is recessed in a direction perpendicular to the direction in which the first drain wiring 22 extends. The depth of the recess in the source-side recess 21a and the depth of the recess in the drain-side recess 22a may be the same or different.

  The source-side recess 21a and the drain-side recess 22a have a shape in which the first source wiring 21 and the first drain wiring 22 are recessed in a U-shape. The source-side recess 21a and the drain-side recess 22a are arranged so as to face each other. As a result, the gap between the source-side recess 21a and the drain-side recess 22a is wider than the gap in the first source wiring 21 and the first drain wiring 22 where the source-side recess 21a and the drain-side recess 22a are not provided. A gap 24 is created. The relay portion 23 is disposed in the gap 24 between the source-side recess 21a and the drain-side recess 22a.

  The relay unit 23 has a square shape, for example. The size of the relay unit 23 may be equal to or larger than the minimum size necessary for relaying to the wiring layer above the first wiring layer 20. For example, the size is equal to or larger than the size of the via 40 that connects the first wiring layer 20 and the second wiring layer 30 described later.

  Specifically, the relay unit 23 has a size of, for example, 1 μm square. This is because it is not necessary to flow a large current flowing through the first source wiring 21 and the first drain wiring 22 to the gate electrode 17 of the semiconductor element, so that the relay portion 23 is similar to the first source wiring 21 and the first drain wiring 22. This is because it is not necessary to configure the wiring with a thickness of.

  A plurality of source-side recesses 21 a and drain-side recesses 22 a are provided in each of the first source wiring 21 and the first drain wiring 22, and accordingly, a plurality of gaps 24 are also provided. A relay portion 23 is disposed in each gap 24. As a result, as shown in FIG. 2A, the relay units 23 are arranged in a scattered manner. Each relay part 23 functions as a connection part to the second wiring layer 30 on the first wiring layer 20.

  As shown in FIG. 1, an interlayer insulating film 25 that covers the first source wiring 21, the first drain wiring 22, and the relay portion 23 is formed on the first wiring layer 20 having such a configuration. . A second wiring layer 30 is formed on the interlayer insulating film 25.

  FIG. 2B is a plan view showing a part of the layout of the second wiring layer 30. In FIG. 2B, the AA cross section corresponds to the cross sectional view of FIG.

  As shown in FIG. 2B, the second wiring layer 30 includes a second source wiring 31 electrically connected to the first source wiring 21 and a second source wiring 31 electrically connected to the first drain wiring 22. A two-drain wiring 32 and a backing wiring 33 electrically connected to the relay portion 23 are provided.

  In the present embodiment, the second source wiring 31, the second drain wiring 32, and the backing wiring 33 are repeatedly arranged in the order of the backing wiring 33, the second source wiring 31, the backing wiring 33, and the second drain wiring 32. Has been. In addition, the second source wiring 31, the second drain wiring 32, and the backing wiring 33 are each extended perpendicular to the direction in which the first source wiring 21 and the first drain wiring 22 are extended. As shown in FIG. 1, the backing wiring 33 in the second wiring layer 30 is provided in a direction parallel to the paper surface with respect to the first wiring layer 20 extending in the direction perpendicular to the paper surface of the drawing.

  The second source wiring 31, the second drain wiring 32, and the backing wiring 33 are so-called 2ndAl, and are formed of Al. The width of the second source wiring 31 and the second drain wiring 32 is, for example, 50 μm to 100 μm.

  The first source line 21 and the second source line 31 are electrically connected by a via 40 provided in the interlayer insulating film 25. Similarly, the first drain wiring 22 and the second drain wiring 32 are electrically connected by a via 40 provided in the interlayer insulating film 25. The relay portion 23 and the backing wiring 33 are also electrically connected by a via 40. In the present embodiment, the via 40 is provided as a set of four locations between the relay unit 23 and the relay unit 23 in the direction in which, for example, the first source wiring 21 and the first drain wiring 22 are extended.

  The backing wiring 33 corresponds to a gate wiring connected to the gate electrode 17 of the semiconductor element via the relay portion 23. The backing wiring 33 is directly connected to a gate pad (not shown) or is connected to the gate pad via a wiring above the second wiring layer 30.

  As shown in FIG. 2B, in the layer of the second wiring layer 30, since the backing wiring 33 is laid out as the gate wiring, the second source wiring 31 and the second drain wiring 32 are thin. However, since the degree of freedom of layout is large, the second source wiring 31 and the second drain wiring 32 can be laid out thickly, and the increase in resistance does not affect the characteristics of the semiconductor element.

  In this case, outside the effective transistor, the second source wiring 31 and the second drain wiring 32 may be connected to the first source wiring 21 and the first drain wiring 22 which are 1st Al again.

  A plurality of wiring layers are configured by further stacking a wiring layer (not shown) on the second wiring layer 30 having such a configuration. As described above, the plurality of wiring layers only need to be configured by at least the first wiring layer 20 and the second wiring layer 30, and of course, may be configured by three or more layers. The above is the overall configuration of the semiconductor device according to the present embodiment.

  In the semiconductor device, the first wiring layer 20 is formed as follows. First, an interlayer insulating film 18 is formed on the surface 11 of the semiconductor substrate 10 on which a semiconductor element is formed, and contact holes are provided in the interlayer insulating film 18 by an etching method. Then, a W plug or the like is formed in the contact hole, and a metal layer to be the first wiring layer 20 is formed on the interlayer insulating film 18 by a method such as vapor deposition, sputtering, or CVD.

  Subsequently, for example, a resist is formed on the metal layer, and the resist is opened by exposure. At this time, the resist is exposed so that the source-side recess 21a and the drain-side recess 22a that narrow the width of part of the first source wiring 21 and the first drain wiring 22 are formed. Further, exposure is performed so that the resist remains on the portion of the metal layer that becomes the relay portion 23 so that the relay portion 23 is formed in the gap 24 by providing the source-side recess portion 21a and the drain-side recess portion 22a.

  Thereafter, the metal layer is patterned by an etching method using a resist as a mask. Thus, the first source wiring 21, the first drain wiring 22, and the relay portion 23 having the layout configuration shown in FIG. 2A are formed from the metal layer. Then, the interlayer insulating film 25 and the via 40 are formed on the first wiring layer 20, and the second wiring layer 30 is formed by the same method as the method for forming the first wiring layer 20. In this way, the semiconductor device having the configuration shown in FIGS. 1 and 2 is obtained.

  Next, the operation of the relay unit 23 included in the first wiring layer 20 will be described. First, polysilicon is a material having a higher resistance than Al used as a wiring material. Therefore, if the gate electrode 17 connected to the gate pad extends in parallel with the first source wiring 21 and the first drain wiring 22 as in the prior art, the farther from the gate pad in the cell, The resistance of the gate electrode 17 is increased.

  For example, if the width of the LDMOS transistor is 100 μm and five LDMOS transistors are arranged, the resistance of the gate electrode 17 from the pad to the farthest place is a resistance of 500 μm.

  On the other hand, in the present embodiment, as described above, the relay unit 23 serves as a connection unit that connects the gate electrode 17 formed of polysilicon and the backing wiring 33 formed of Al constituting the second wiring layer 30. It has been adopted. That is, it means that the gate voltage is applied to the gate electrode 17 from the backing wiring 33 connected to the gate pad through the relay portion 23 arranged at a constant interval. The interval is determined by the gate wiring resistance specification.

  For example, if the relay portion 23 is arranged at an interval of 1/10 of the width of the LDMOS transistor, the gate resistance from the gate pad can be reduced to 1/10. Specifically, when five LDMOS transistors having a width of 100 μm are arranged, the conventional gate resistance is 500 μm from the pad to the farthest place. The gate resistance can be reduced by a factor of 50 μm.

  In this way, the relay portion 23 functions as a connection between the gate electrode 17 and the backing wiring 33 to the last. Therefore, the gate resistance is not determined by the resistance of the relay unit 23 but is determined by the backing wiring 33 connected to the relay unit 23. Since the backing wiring 33 is a low-resistance wiring made of Al instead of polysilicon, the gate resistance can be reduced.

  As described above, in the present embodiment, the relay portion 23 is connected to the gate electrode 17 of the semiconductor element in the first wiring layer 20. In this case, in order to arrange the relay portion 23 in the layer of the first wiring layer 20, the first source wiring 21 and the first drain wiring 22 are provided with the source-side recess 21a and the drain-side recess 22a, respectively, to create a gap 24, The relay portion 23 is arranged in the gap 24.

  Thereby, it is not necessary to reduce the entire widths of the first source line 21 and the first drain line 22 through which a large current flows. For this reason, an increase in wiring resistance of the first source wiring 21 and the first drain wiring 22 can be suppressed.

  Further, since the widths of the first source wiring 21 and the first drain wiring 22 can be secured, it is possible to prevent a resistance from flowing for a large current instantaneously, and it is possible to suppress a decrease in ESD tolerance.

  A gate voltage is applied to the gate electrode 17 from the backing wiring 33 through the relay portion 23. Therefore, the resistance of the gate electrode 17 according to the distance from the gate pad to the gate of the LDMOS transistor does not affect the gate voltage. Therefore, the gate resistance can be reduced. Thus, the LDMOS transistor can be operated uniformly during the high-speed operation of the LDMOS transistor, and the LDMOS transistor can be operated at a high speed.

  Such a reduction in gate resistance can be achieved by improving the process cost even with the conventional wiring structure, but it is not preferable because the cost and the number of manufacturing steps increase. However, by providing the relay unit 23 as described above, a semiconductor device can be configured without increasing the process cost and the number of steps.

  The semiconductor devices depicted in FIGS. 1 and 2 are schematic views and do not represent actual dimensions (aspect ratio) such as the first wiring layer 20. The same applies to the figures shown below.

(Second Embodiment)
In the present embodiment, only different parts from the first embodiment will be described. FIG. 3A is a plan view showing a part of the layout of the first wiring layer 20 according to the present embodiment, and FIG. 3B is a plan view showing a part of the layout of the second wiring layer 30. FIG.

  As shown in FIG. 3A, the via 40 is provided as a set of two places between the relay unit 23 and the relay unit 23 in the direction in which the first source wiring 21 is extended. Accordingly, as shown in FIG. 3B, the second source wiring 31 and the second drain wiring 32 in the second wiring layer 30 are arranged between the backing wiring 33 and the backing wiring 33, respectively. Has been. That is, the second source wiring 31, the second drain wiring 32, the backing wiring 33, the second source wiring 31.

  As described above, by changing the arrangement of the vias 40 that relay the first wiring layer 20 and the second wiring layer 30, the second source wiring 31, the second drain wiring 32, and the backing in the second wiring layer 30 are changed. It is possible to change the layout of the wiring 33 for use.

(Third embodiment)
In the present embodiment, only parts different from the first and second embodiments will be described. The present embodiment is characterized in that a gap is provided between the source-side recess 21 a and the first drain wiring 22, and a gap is provided between the drain-side recess 22 a and the first source wiring 21. .

  FIG. 4 is a plan view showing a part of the layout of the first wiring layer 20 according to the present embodiment. As shown in this figure, the first source line 21 is provided with a source-side recess 21 a in which a part of the first source line 21 is narrowed. In addition, a gap 26 is provided between the first source wiring 21 and the first drain wiring 22 between the first drain wiring 22 widened by the source side recess 21a and the source side recess 21a. A relay portion 23 is disposed in the gap 26.

On the other hand, the first drain wiring 22 is provided with a drain-side recess 22 a in which a part of the first drain wiring 22 is narrowed. Further, a gap 27 is provided between the first source line 21 and the first drain line 22 between the first source line 21 and the drain side recess 22a widened by the drain side recess 22a. Then, the relay portion 23 is disposed in the gap 27. The arrangement of the via 40 is the same as in the second embodiment. Therefore, the second wiring layer 30 is the same as that shown in FIG. Of course, the arrangement of the vias 40 may be a set of four locations as in the first embodiment.

  As described above, the gap 26 is provided between the first source wiring 21 and the first drain wiring 22 only by the source-side recess 21 a provided in the first source wiring 21, and the relay portion 23 is disposed in the gap 26. Can do. Similarly, a gap 27 may be provided between the first source line 21 and the first drain line 22 only by the drain side recess 22 a provided in the first drain line 22, and a relay part may be disposed in the gap 26.

(Fourth embodiment)
In the present embodiment, only parts different from the first to third embodiments will be described. In each of the above embodiments, the drain region 12 and the source region 15 constituting the semiconductor element are arranged in stripes with respect to the semiconductor substrate 10, and the first wiring layer 20 and the first wiring layer 20 for such a semiconductor element are shown. The layout of the two wiring layers 30 is shown. The present embodiment is characterized in that the first wiring layer 20 and the second wiring layer 30 are laid out with respect to the drain region 12 and the source region 15 constituting the semiconductor element formed on the semiconductor substrate 10 in a mesh shape. It has become.

  FIG. 5 is a plan view of a plurality of wiring layers of the semiconductor device according to the present embodiment. A first source wiring 21 is formed so as to connect the source region 15 in a straight line to a place where the drain region 12 and the source region 15 are formed in a mesh shape on the semiconductor substrate 10. A first drain wiring 22 is formed so as to be connected in a straight line. The first source lines 21 and the second source lines 31 are alternately arranged in a stripe shape, as in the above embodiments.

  In addition, vias 41 are provided on the first source wiring 21 at regular intervals. The via 41 is used as a relay between the first source line 21 and the second source line 31. Similarly, vias 42 are provided on the first drain wiring 22 at regular intervals. The via 42 is used as a relay between the first drain wiring 22 and the second drain wiring 32.

  The second source wirings 31 and the second drain wirings 32 are alternately provided in stripes so as to intersect the first source wirings 21 and the first drain wirings 22. The end portions of the second source lines 31 are electrically connected to each other.

  FIG. 6 shows a detailed plan view in which the first wiring layer 20 and the second wiring layer 30 among the plurality of wiring layers in the plan view shown in FIG. 5 are disassembled. FIG. 6A is a plan view of the first wiring layer 20, and FIG. 6B is a plan view of the second wiring layer 30.

  As shown in FIG. 6A, the source-side recess 21a is provided in the first source wiring 21, the drain-side recess 22a is provided in the first drain wiring 22, and the recesses 21a, 22a are arranged to face each other. Has been. And the relay part 23 is arrange | positioned in the gap | interval 24 formed by each recessed part 21a, 22a. The relay portions 23 are interspersed in the first wiring layer 20.

  Further, as shown in FIG. 6B, the second source wiring 31 and the second drain wiring 32 are provided in a direction perpendicular to the extending direction of the first source wiring 21 and the first drain wiring 22, respectively. ing. The second source wiring 31 and the second drain wiring 32 are electrically connected to the lower first source wiring 21 and first drain wiring 22 through vias 41 and 42.

  Further, in the second wiring layer 30, a backing wiring 33 that functions as a gate extends between the second source wiring 31 and the second drain wiring 32. The backing wiring 33 is electrically connected to each relay portion 23.

  As described above, even if the drain region 12 and the source region 15 are provided in a mesh shape, the first wiring layer 20 and the second wiring layer 30 can be provided as in the above embodiments.

  In the above description, the source-side recess 21a of the first source wiring 21 and the drain-side recess 22a of the first drain wiring 22 are arranged to face each other to form a gap 24. However, the relay portion 23 is disposed. The gap 24 may be provided by other means. For example, as shown in FIG. 4, at least one of the first source wiring 21 and the first drain wiring 22 may be provided with a source-side recess 21 a and a drain-side recess 22 a.

(Other embodiments)
In each of the above embodiments, the LDMOS transistor is described as an example of the semiconductor element. However, this is an example, and another semiconductor element may be used. For example, lateral type elements (surface devices) such as DMOS transistors and IGBTs can be employed.

  Although the relay part 23 shown by said each embodiment has comprised the square, the planar shape of the relay part 23 is not restricted to a square, Other shapes may be sufficient. For example, a rectangle, polygon, or circle may be used.

  In each of the above embodiments, the relay units 23 are regularly arranged as shown in FIG. 2A, for example. This is an example of the arrangement of the relay units 23, and is another arrangement. Also good. Of course, it may be scattered irregularly according to the position of the gate electrode 17.

  The source-side recess 21a and the drain-side recess 22a shown in the above embodiments have a shape in which the first source wiring 21 and the first drain wiring 22 are recessed in a U-shape, but this is an example. It may be other shapes. For example, an arc shape may be used.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. (A) is a plan view showing a part of the layout of the first wiring layer, (b) is a plan view showing a part of the layout of the second wiring layer. (A) is the top view which showed a part of layout of the 1st wiring layer based on 2nd Embodiment of this invention, (b) is the top view which showed a part of layout of the 2nd wiring layer. is there. It is the top view which showed a part of layout of the 1st wiring layer which concerns on 3rd Embodiment of this invention. It is a top view of a plurality of wiring layers of a semiconductor device concerning a 4th embodiment of the present invention. (A) is a top view of the 1st wiring layer shown by FIG. 5, (b) is a top view of the 2nd wiring layer shown by FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Surface of semiconductor substrate 12 Drain area | region 15 Source area | region 17 Gate electrode 20 1st wiring layer 21 1st source wiring 21a Source side recessed part 22 1st drain wiring 22a Drain side recessed part 23 Relay part 24, 26, 27 Gap 30 Second wiring layer 31 Second source wiring 32 Second drain wiring 33 Backing wiring

Claims (9)

A lateral semiconductor element including a source region (15), a drain region (12), and a gate electrode (17) is formed on a semiconductor substrate (10), and a plurality of wiring layers are formed on the semiconductor substrate (10). A semiconductor device comprising:
Of the plurality of wiring layers, the first wiring layer (20) located closest to the semiconductor substrate (10) is a first source wiring (21) electrically connected to the source region (15) of the semiconductor element. A first drain wiring (22) electrically connected to the drain region (12) of the semiconductor element, and a relay part (23) electrically connected to the gate electrode (17),
The first source wiring (21) and the first drain wiring (22) are arranged in a stripe shape in a direction parallel to the surface (11) of the semiconductor substrate (10),
The first source line (21) includes a source-side recess (21a) in which a part of the first source line (21) is narrowed.
The first drain wiring (22) includes a drain side recess (22a) in which a part of the width of the first drain wiring (22) is narrowed.
The source-side recess (21a) and the drain-side recess (22a) are arranged to face each other,
The relay portion (23) is widened by the source-side recess (21a) and the drain-side recess (22a) between the first source wiring (21) and the first drain wiring (22). A semiconductor device, which is disposed in the gap (24) . A lateral semiconductor element including a source region (15), a drain region (12), and a gate electrode (17) is formed on a semiconductor substrate (10), and a plurality of wiring layers are formed on the semiconductor substrate (10). A semiconductor device comprising:
Of the plurality of wiring layers, the first wiring layer (20) located closest to the semiconductor substrate (10) is a first source wiring (21) electrically connected to the source region (15) of the semiconductor element. A first drain wiring (22) electrically connected to the drain region (12) of the semiconductor element, and a relay part (23) electrically connected to the gate electrode (17),
The first source wiring (21) and the first drain wiring (22) are arranged in a stripe shape in a direction parallel to the surface (11) of the semiconductor substrate (10),
The first source line (21) includes a source-side recess (21a) in which a part of the first source line (21) is narrowed.
The first drain wiring (22) includes a drain side recess (22a) in which a part of the width of the first drain wiring (22) is narrowed.
The relay portion (23) includes the first drain wiring (22) widened by the source-side recess (21a) between the first source wiring (21) and the first drain wiring (22). The first source wiring (21) and the drain side recess (22a) disposed in the gap (26) between the source side recess (21a) and widened by the drain side recess (22a), A semiconductor device, which is disposed in a gap (27) between the two . The plurality of wiring layers include a second wiring layer (30) on the first wiring layer (20),
The second wiring layer (30)
A second source line (31) electrically connected to the first source line (21);
A second drain wiring (32) electrically connected to the first drain wiring (22);
The semiconductor device according to claim 1 or 2, characterized in that it comprises a and electrically connected to the backing wire (33) to the relay unit (23). It said source region (15) and said drain region (12) The semiconductor device according to any one of claims 1 to 3, characterized in that is formed in a stripe shape on the semiconductor substrate (10). It said source region (15) and said drain region (12) The semiconductor device according to any one of claims 1 to 3, characterized in that is formed in a mesh pattern on the semiconductor substrate (10). A lateral semiconductor element including a source region (15), a drain region (12), and a gate electrode (17) is formed on a semiconductor substrate (10), and a plurality of wiring layers are formed on the semiconductor substrate (10). A semiconductor device comprising:
Of the plurality of wiring layers, the first wiring layer (20) located closest to the semiconductor substrate (10) is a first source wiring (21) electrically connected to the source region (15) of the semiconductor element. A first drain wiring (22) electrically connected to the drain region (12) of the semiconductor element, and a relay part (23) electrically connected to the gate electrode (17),
The first source wiring (21) and the first drain wiring (22) are arranged in a stripe shape in a direction parallel to the surface (11) of the semiconductor substrate (10),
One or both of the first source wiring (21) and the first drain wiring (22) is a recess (in which a distance between the first source wiring (21) and the first drain wiring (22) is increased. 21a, 22a)
The relay part (23) includes the first source line (21) widened by the recesses (21a, 22a) between the first source line (21) and the first drain line (22). Disposed in the gap (24, 26, 27) with the first drain wiring (22) ,
The semiconductor device, wherein the source region (15) and the drain region (12) are formed in a mesh shape on the semiconductor substrate (10) . The first source wiring (21) includes a source-side recess (21a) in which a width of a part of the first source wiring (21) is narrowed as the recess.
The relay portion (23) is disposed in a gap (26) widened by the source-side recess (21a) between the first source wiring (21) and the first drain wiring (22). The semiconductor device according to claim 6 . The first drain wiring (22) includes a drain-side recess (22a) in which a part of the width of the first drain wiring (22) is narrowed as the recess,
The relay portion (23) is disposed in a gap (27) widened by the drain-side recess (22a) between the first source wiring (21) and the first drain wiring (22). The semiconductor device according to claim 6 . The plurality of wiring layers include a second wiring layer (30) on the first wiring layer (20),
The second wiring layer (30)
A second source line (31) electrically connected to the first source line (21);
A second drain wiring (32) electrically connected to the first drain wiring (22);
The semiconductor device according to any one of claims 6 to 8, characterized in that it comprises a and electrically connected to the backing wire (33) to the relay unit (23).

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