JP2009130312A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance a power supply function without increasing the number of wiring layers in a power supply line. <P>SOLUTION: A semiconductor device has: a semiconductor substrate 1 on which a plurality of semiconductor elements are formed; a first wiring pattern 4a formed on the semiconductor substrate 1 while interposing a first interlayer insulating film 2 therebetween and to which a power supply potential is applied; and a second wiring pattern 6a formed at least on the first wiring pattern 4a while interposing a third interlayer insulating film 5 therebetween. The second wiring pattern 6a is formed to grow isotropically in a region exposed from a contact hole 5a formed in the third interlayer insulating film 5 on the first wiring pattern 4a. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a pad electrode and a signal wiring.

  In order to cope with downsizing of a semiconductor device, there is a flip chip mounting method in which the surface of the semiconductor chip itself and a resin substrate for mounting are directly connected. At this time, a mounting method is known in which the pad electrode is plated as, for example, a nickel layer and a gold layer, solder balls are formed on the formed pad electrode, and the semiconductor chip is electrically connected to the resin substrate. (For example, see Patent Document 1). The plating layer here is formed as a wiring having a pattern different from that of the underlying wiring.

  Further, for example, Patent Document 2 discloses a technique of using electroless plating for the metal layer of the pad electrode. In this document, only the pad electrode which is a connection part is formed by electroless plating.

  17 (a) and 17 (b) show a conventional semiconductor device described in Patent Document 2. FIG. In FIG. 17B, although not shown, semiconductor elements such as transistors and wirings are formed on the top and top surfaces of the semiconductor substrate 101, and these semiconductor elements and wirings are formed in the first interlayer insulating film 102. Covered by.

  As shown in FIGS. 17A and 17B, on the first interlayer insulating film 102, the first wiring layer 104 in which each periphery is embedded with the second interlayer insulating film 103 is formed. The first wiring layer 104 is formed of a wiring portion 104a and a pad portion 104b disposed in the periphery thereof.

  A third interlayer insulating film 105 is formed on the second interlayer insulating film 103 including the first wiring layer 104, and each of the first wiring layers 104 in the third interlayer insulating film 105 is formed. A contact hole (opening) 105a exposing the upper surface of each pad portion 104b is formed in the upper portion of the pad portion 104b.

  From each contact hole 105a of the third interlayer insulating film 105, a pad electrode 106 made of an aluminum layer and a nickel layer is formed by electroless plating.

Further, as shown in FIG. 17A, a wiring pattern electrically connected to a power supply pad 106A to which a power supply potential is applied in the first wiring layer 104, and a ground pad 106B to which a ground potential is applied. The electrically connected wiring pattern is formed in a planar comb shape.
JP 2006-203215 A JP 2003-297868 A

  However, in the conventional semiconductor device, when the function as a power source is strengthened with respect to the wiring portion 104a of the first wiring layer 104 which is a power supply wiring, the wiring portion 104a of the first wiring layer 104 is used. It is necessary to provide a new layer as a so-called backing layer above or below the first wiring layer 104. Thus, when a new backing layer is provided, the wiring layer increases and the number of processes increases, which causes a problem that the manufacturing cost of the semiconductor device increases.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to realize enhancement of a power supply function without increasing a wiring layer.

  In order to achieve the above object, according to the present invention, a metal layer used for a pad electrode as a semiconductor device is used as a backing layer of a power supply wiring.

  Specifically, a semiconductor device according to the present invention is formed with a semiconductor substrate on which a plurality of semiconductor elements are formed, a first insulating film interposed on the semiconductor substrate, and a first power supply potential is applied to the semiconductor device. A first wiring layer including a wiring pattern extending vertically and horizontally on the first insulating film, and a second insulating film formed on the first wiring layer and having a plurality of openings exposing the first wiring layer And a second wiring layer formed so as to grow isotropically from an exposed portion from each opening on the first wiring layer.

  According to the semiconductor device of the present invention, the second wiring layer is formed so as to grow isotropically from the exposed portion from each opening formed in the second insulating film on the first wiring layer. Therefore, the backing wiring of the first wiring layer can be formed by the same manufacturing process as the conventional pad electrode. For this reason, the power supply function can be strengthened without newly providing a wiring layer for backing.

  In the semiconductor device of the present invention, the second wiring layer is preferably formed by an electroless plating method.

  In the semiconductor device of the present invention, it is preferable that the second wiring layer is formed by being divided into a plurality of portions in a linear portion of the first wiring layer.

  In the semiconductor device of the present invention, it is preferable that the second wiring layer is also formed on a bent portion in a plane parallel to the substrate surface in the first wiring layer.

  In the semiconductor device of the present invention, it is preferable that the second wiring layer is formed only on the linear portion of the first wiring layer.

  In the semiconductor device of the present invention, the thickness of the second wiring layer is preferably thicker than the thickness of the first wiring layer.

  In the semiconductor device of the present invention, the width of the opening formed in the second insulating film is preferably larger than the wiring width in the first wiring layer.

  In the semiconductor device of the present invention, it is preferable that the opening formed in the second insulating film is formed to be shifted outward from one side of the wiring portion in the first wiring layer.

  In the semiconductor device of the present invention, it is preferable that at least one wiring in the second wiring layer electrically connects adjacent wirings in the first wiring layer.

  In the semiconductor device of the present invention, at least one wiring in the second wiring layer connects the wirings in the first wiring layer across other wirings to which a potential different from the potential of the wiring is applied. It is preferable that

  In the semiconductor device of the present invention, the first wiring layer is preferably a backing wiring of the second wiring layer.

  In the semiconductor device of the present invention, it is preferable that the first wiring layer and the second wiring layer intersect each other.

  In the semiconductor device of the present invention, the second wiring layer is preferably made of the first metal film.

  In this case, the first metal film is preferably made of a metal whose main component is nickel or aluminum.

  In this case, the second wiring layer includes a lower wiring layer that isotropically grown on the first wiring layer, and a second metal film that isotropically grown on the lower wiring layer. It is preferable that the upper wiring layer is made of.

  In this case, it is preferable that the first metal film is made of a metal containing aluminum as a main component, and the second metal film is made of a metal containing nickel as a main component.

  In the semiconductor device of the present invention, it is preferable that a part of the first wiring layer and the second wiring layer constitute a pad portion.

  In this case, the plane area of the second wiring layer constituting the pad portion is larger than the plane area of the first wiring layer constituting the pad portion, and the opening area of the opening portion is the second area constituting the pad portion. It is preferable that it is larger than the plane area of the wiring layer.

  In this case, a part of the plurality of openings is formed to be shifted outward from the side of the first wiring layer constituting the pad part, and the remaining part of the plurality of openings is the pad part. Preferably, it is formed on the inner region of the first wiring layer constituting the.

  Further, in this case, it is preferable that each opening is formed only on a region inside the first wiring layer constituting the pad portion.

  According to the semiconductor device of the present invention, the power supply function is enhanced by using the metal layer constituting the pad electrode as the backing layer of the power supply wiring without increasing the wiring layer of the power supply wiring, that is, without increasing the manufacturing cost. can do.

(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described.

  1A and 1B show a semiconductor device according to the first embodiment of the present invention, in which FIG. 1A shows a planar configuration, and FIG. 1B shows Ib of FIG. The cross-sectional structure in line -Ib is shown. 2 and 3 show a planar configuration and a cross-sectional configuration in one step of the manufacturing process of the semiconductor device according to the first embodiment. Although not shown in FIG. 1B, a plurality of semiconductor elements such as transistors and a plurality of wiring layers (multilayer wiring) for connecting them to each other are formed on the upper and upper surfaces of the semiconductor substrate 1. These semiconductor elements and wiring layers are covered with a first interlayer insulating film 2.

  As shown in FIGS. 1A and 1B, the first wiring in which the periphery of each of the first interlayer insulating films 2 is planarized and embedded by the second interlayer insulating film 3. Layer 4 is formed. The first wiring layer 4 is partitioned into a wiring part 10 disposed in the central portion of the semiconductor substrate 1 and a pad part 11 disposed around the wiring part 10. Here, a region belonging to the wiring portion 10 of the first wiring layer 4 is referred to as a first wiring pattern 4a, and a region belonging to the pad portion 11 of the first wiring layer 4 is referred to as a first pad pattern 4b. Although not shown, the first wiring 4 is electrically connected to the multilayer wiring formed in the first interlayer insulating film 2.

  A third interlayer insulating film 5 is formed on the second interlayer insulating film 3 including the first wiring layer 4, and above the first wiring layer 4 in the third interlayer insulating film 5. In the portion, a plurality of contact holes (openings) 5a for selectively exposing the first wiring layer 4 are formed.

  From each contact hole 5a of the third interlayer insulating film 5, a second wiring layer 6 made of a nickel (Ni) layer and a gold (Au) layer isotropically grown by electroless plating is formed. . Here, a portion belonging to the wiring portion 10 of the second wiring layer 6 is referred to as a second wiring pattern 6a, and a portion belonging to the pad portion 11 of the second wiring layer 6 is referred to as a second pad pattern 6b.

  Further, as shown in FIG. 2A, the first wiring pattern 4a electrically connected to the power supply pad 6b1 to which the power supply potential is applied in the first wiring layer 4 and the ground potential are applied. The first wiring patterns 4a electrically connected to the ground pad 6b2 are formed in a comb shape.

  Hereinafter, a specific example of the manufacturing method will be described with reference to FIGS.

  First, as shown in FIGS. 2A and 2B, on the first interlayer insulating film 2, for example, FSG (fluorine-added silicate glass) having a thickness of 950 nm and TEOS having a thickness of 450 nm are formed. (Tetra-Ethyl-Ortho-Silicate) is sequentially stacked to form a second interlayer insulating film 3. Thereafter, a resist pattern (not shown) having the formation region of the first wiring layer 4 as an opening pattern is formed on the formed second interlayer insulating film 3 by lithography, and the formed resist pattern Etching using is performed to form a plurality of openings 3 a serving as a first wiring layer formation region in the second interlayer insulating film 3. Subsequently, for example, copper (Cu) or a metal film mainly composed of copper (Cu) is filled in each opening 3a by sputtering, and then the second interlayer insulating film is formed by chemical mechanical polishing (CMP). 3 and the upper surface of the metal film are flattened to form the first wiring layer 4 from the metal film. Here, the first wiring layer 4 is provided with a barrier film made of tantalum nitride (TaN) on the bottom surface and the wall surface of each opening 3a of the second interlayer insulating film 3 for preventing copper diffusion. Also good. Note that it is not always necessary to use both FSG and TEOS for the second interlayer insulating film 3, and only one of them may be used.

  Next, as shown in FIGS. 3A and 3B, on the second interlayer insulating film 3 including the first wiring layer 4, for example, silicon nitride (SiN) having a thickness of 250 nm and Then, a third interlayer insulating film 5 is formed by sequentially stacking TEOS having a thickness of 250 nm. Again, it is not always necessary to use both SiN and TEOS for the third interlayer insulating film 5, and only one of them may be used. Subsequently, a plurality of contact holes 5 a that expose the upper surfaces of the first wiring layers 4 are selectively formed in the third interlayer insulating film 5 by lithography and etching.

  Thereafter, as shown in FIGS. 1A and 1B, regions exposed from the contact holes 5a of the third interlayer insulating film 5 on the first wiring layer 4 by electroless plating. The second wiring layer 6 is grown isotropically. Specifically, the second wiring pattern 6 a of the second wiring layer 6 is formed on the first wiring pattern 4 a of the first wiring layer 4, and the first wiring pattern 4 of the first wiring layer 4 is formed. A second pad pattern 6b of the second wiring layer 6 is formed on the pad pattern 4b.

  As a specific example of the first wiring layer 4 and the second wiring layer 6, for example, a copper wiring having a thickness of about 1 μm to 2 μm is used for the first wiring layer 4, and the second wiring layer 6 includes Nickel by plating having a thickness of about 2 μm to 5 μm and gold by plating having a thickness of 0.1 μm or less are used thereon. However, the second wiring layer 6 is formed thicker than the first wiring layer 4.

  In the first embodiment of the present invention, since the second wiring pattern 6a constituting the second wiring layer 6 serves as a backing layer of the first wiring pattern 4a constituting the first wiring layer 4, The resistance of the power supply wiring can be greatly reduced. Although the resistance of nickel is larger than that of copper, the effect of strengthening the power supply can be sufficiently obtained by sufficiently increasing the thickness of nickel.

  Further, by plating a palladium (Pd) layer between the nickel layer and the gold layer, it is possible to suppress the diffusion of nickel when wire bonding is performed on the second pad pattern 6b.

  In addition, by making the second wiring layer 6 sufficiently thick, for example, an effect that stress on the semiconductor substrate 1 on which the transistor is formed is relaxed. The thickness of the wiring layer 6 is preferably set.

  In the first embodiment, the process after the formation of the second wiring layer 6 is not particularly described, but a protective film such as an oxide film is formed around the second wiring layer 6. It is also possible to form a protective film made of a resin such as polyimide or PBO (polybenzoxazole).

  Thus, according to the first embodiment, in the wiring portion 10 of the semiconductor device, the first wiring pattern 4a is formed on the third interlayer insulating film 5 that covers the first wiring pattern 4a of the first wiring layer 4. A plurality of contact holes 5a selectively exposing the upper surface is formed, and a second wiring pattern 6a constituting the second wiring layer 6 is isotropically grown by electroless plating from each of the formed contact holes 5a. Let it form. That is, the number of processes is increased by forming the second wiring pattern 6a of the second wiring layer 6 in the same process as the process of forming the second pad pattern 6b of the second wiring layer 6. In addition, the power signal line can be electrically strengthened. Thereby, the voltage drop of the power supply voltage by only the 1st wiring pattern 4a can be suppressed.

  Further, since the third interlayer insulating film 5 is provided with a plurality of contact holes 5a, the second wiring layer 6 is divided into a plurality of parts, so that the third interlayer insulating film 5 formed by the second wiring layer 6 is divided. As a result, the stress on the first interlayer insulating film 2 and the semiconductor substrate 1 can be relaxed.

  Further, the second wiring layer 6 is divided into a plurality of parts, so that, for example, when forming a protective film made of a resin in a later process, there is an effect that adhesion with the protective film is improved.

  In the first embodiment, the planar shape of the contact hole 5a is a square, but by cutting the four corners of the square at an angle of 45 ° with respect to each side to form a planar octagon, This is preferable because stress on the third interlayer insulating film 5 and the like from the plating layer constituting the second wiring layer 6 grown from the inside of each contact hole 5a can be relaxed.

  As described above, in the first embodiment, when the pad portion 11 is configured by the second pad pattern 6b of the second wiring layer 6, the same formation method as the second pad pattern 6b, that is, Through the same process, the second wiring pattern 6b is formed as a backing layer of the first wiring pattern 4a.

(One modification of the first embodiment)
A semiconductor device according to a modification of the first embodiment of the present invention will be described below with reference to the drawings. FIG. 4 shows a cross-sectional configuration of a semiconductor device according to a modification of the first embodiment. In FIG. 4, the same components as those shown in FIG. The same applies to the following embodiments.

  As shown in FIG. 4, the semiconductor device according to the present modification example isotropically grown by aluminum (Al) plating between the first wiring layer 4 and the second wiring layer 6. A third wiring layer 8 is formed as a lower wiring layer of the second wiring layer 6. Here again, a portion belonging to the wiring portion 10 in the third wiring layer 8 is referred to as a third wiring pattern 8a, and a portion belonging to the pad portion 11 is referred to as a third pad pattern 8b.

  Here, the second interlayer insulating film 3 filling the periphery of the first wiring layer 4 has, for example, a two-layer structure of an FSG layer and a TEOS layer thereon. The third interlayer insulating film 5 that forms the contact hole 5a that exposes the upper surface of the first wiring layer 4 has a two-layer structure of, for example, a SiN layer and a TEOS layer thereon.

  The fourth interlayer insulating film 7 formed on the third interlayer insulating film 5 and filling the periphery of the third wiring layer 8 has the same configuration as the second interlayer insulating film 3. The fifth interlayer insulating film 9 formed on the fourth interlayer insulating film 7 and exposing the upper surface of the third wiring layer 8 has the same configuration as the third interlayer insulating film 5.

  In this way, by providing the third wiring layer 8 mainly containing aluminum between the first wiring layer 4 mainly containing copper and the second wiring layer 6 mainly containing nickel. It is possible to prevent oxidation of the first wiring layer 4 containing copper as a main component and to easily reduce the contact resistance with the second wiring layer 6 containing nickel as a main component. effective.

  In the second and subsequent embodiments, a method for connecting the second wiring pattern 6a to the first wiring pattern 4a and a method for connecting the second pad pattern 6b to the first pad pattern 4b will be described.

(Second Embodiment)
A semiconductor device according to the second embodiment of the present invention will be described below with reference to the drawings. FIGS. 5A and 5B are a first wiring pattern 4a and a second wiring pattern 6a formed thereon in the semiconductor device according to the second embodiment of the present invention. ) Shows a plan configuration of the main part, and (b) shows a cross-sectional configuration taken along the line Vb-Vb of (a).

  As shown in FIGS. 5A and 5B, the second wiring pattern 6a of the semiconductor device according to the second embodiment is a bent portion that is bent in parallel to the substrate surface in the first wiring pattern 4a. The second wiring pattern 6a is also formed by forming the contact hole 5a along the bent portion.

  Thus, in the second embodiment, the second wiring pattern 6a is formed to be the backing layer of the first wiring pattern 4a even in the bent portion of the first wiring pattern 4a. The voltage drop can be further suppressed.

  As described in the first embodiment, the planar shape of the contact hole 5a is, for example, 45 ° cut away so that each corner does not become 90 °, and the third interlayer insulating film 5 It is preferable in order to relieve the stress against.

  In the second embodiment, the opening width of the contact hole 5a is smaller than the wiring width of the first wiring pattern. However, as shown in a later embodiment, the wiring of the first wiring pattern It is also possible to make the shape larger than the width.

(Third embodiment)
A semiconductor device according to the third embodiment of the present invention will be described below with reference to the drawings. FIGS. 6A and 6B are a first wiring pattern 4a and a second wiring pattern 6a formed thereon in the semiconductor device according to the third embodiment of the present invention. ) Shows the planar configuration of the main part, and (b) shows the cross-sectional configuration along the VIb-VIb line in (a).

  As shown in FIGS. 6A and 6B, the second wiring pattern 6a of the semiconductor device according to the third embodiment is different from the second embodiment in the first wiring pattern 4a. It is not formed in a bent portion that is bent in parallel to the substrate surface, but is formed only in a linear portion of the first wiring pattern 4a.

  As described above, the second wiring pattern 6a formed of nickel and gold by the electroless plating method is not formed in the bent portion where the stress applied to the third interlayer insulating film 5 is increased. The stress on the interlayer insulating film 5 and the like can be relaxed.

  In the second embodiment and the third embodiment, it is necessary to select such that the stress due to the thickness and hardness of the second wiring pattern 6a becomes an appropriate value.

(Fourth embodiment)
A semiconductor device according to the fourth embodiment of the present invention will be described below with reference to the drawings. FIG. 7A and FIG. 7B are a first wiring pattern 4a and a second wiring pattern 6a formed thereon in the semiconductor device according to the fourth embodiment of the present invention. ) Shows a planar configuration of the main part, and (b) shows a cross-sectional configuration taken along line VIIb-VIIb of (a).

  As shown in FIGS. 7A and 7B, the second wiring pattern 6a of the semiconductor device according to the fourth embodiment is spaced apart from the linear portion of the first wiring pattern 4a. It is formed by growing from a plurality of contact holes 5a.

  In this way, the stress on the third interlayer insulating film 5 and the like can be relaxed also in the linear portion of the first wiring pattern 4a.

  By the way, since the thickness of the second wiring pattern 6a is generally formed as relatively thick as about 5 μm, if it is formed long along the linear portion of the first wiring pattern 4a, the third interlayer insulating film 5 or the like is formed. There is a risk that stress will be strongly applied. For this reason, in the fourth embodiment, even if the first wiring pattern 4a is a linear pattern, the contact hole 5a is divided into a plurality of parts and the second wiring pattern 6a is divided into a plurality of parts. The stress caused by the second wiring pattern 6a can be relaxed.

  Specifically, the interval between the contact holes 5a adjacent to each other needs to exceed at least twice the growth distance at which the second wiring pattern 6a is grown by the plating method. The length of one divided second wiring pattern 6a is about 100 μm to 1 mm.

(Fifth embodiment)
The semiconductor device according to the fifth embodiment of the present invention will be described below with reference to the drawings. FIGS. 8A and 8B are a first wiring pattern 4a and a second wiring pattern 6a formed thereon in the semiconductor device according to the fifth embodiment of the present invention. ) Shows a plan configuration of the main part, and (b) shows a cross-sectional configuration taken along line VIIIb-VIIIb of (a).

  As shown in FIGS. 8A and 8B, in the semiconductor device according to the fifth embodiment, the opening width of the contact hole 5a formed in the third interlayer insulating film 5 is set to the first wiring pattern. It is larger than the width dimension of 4a.

  With this configuration, since the wiring width of the second wiring pattern 6a grown on the first wiring pattern 4a exposed from the third interlayer insulating film 5 is increased, the wiring becomes thicker and the voltage of the power supply voltage is increased. The descent can be further suppressed.

  Also, since the third interlayer insulating film 5 is not interposed between the second wiring pattern 6a and the first wiring pattern 4a in the portion formed on the bottom surface of the contact hole 5a, the second wiring pattern The stress applied to the third interlayer insulating film 5 from 6a does not occur. As a result, there is no possibility of causing defects such as cracks in and around the contact hole 5a in the third interlayer insulating film 5.

  Note that the distance from the side surface of the first wiring pattern 4a to the wall surface of the contact hole 5a located outside the first wiring pattern 4a needs to be larger than the growth distance at which the second wiring pattern 6a grows by plating.

(Sixth embodiment)
The semiconductor device according to the sixth embodiment of the present invention will be described below with reference to the drawings. FIG. 9A and FIG. 9B are a first wiring pattern 4a and a second wiring pattern 6a formed thereon in the semiconductor device according to the sixth embodiment of the present invention. ) Shows a plan configuration of the main part, and (b) shows a cross-sectional configuration taken along line IXb-IXb of (a).

  As shown in FIGS. 9A and 9B, in the semiconductor device according to the sixth embodiment, the opening position of the contact hole 5a formed in the third interlayer insulating film 5 is set to the first wiring pattern. It is formed by shifting outward from one side surface of 4a. Here, the other wall surface of the contact hole 5a is located on the first wiring pattern 4a.

  The sixth embodiment is effective when it is desired to form the second wiring pattern 6a so as to be shifted only to one side with respect to the first wiring pattern 4a. In particular, as in a ninth embodiment to be described later, the first wiring pattern 4a is formed by wirings having different potentials adjacent to each other, and the second wiring pattern 6a is arranged by wirings having different potentials. This is effective when it is desired to grow large on the opposite side of the wiring that is small on the other side and different in potential.

(Seventh embodiment)
The semiconductor device according to the seventh embodiment of the present invention will be described below with reference to the drawings. FIG. 10A and FIG. 10B are a first wiring pattern 4a and a second wiring pattern 6a formed thereon in the semiconductor device according to the seventh embodiment of the present invention. ) Shows a planar configuration of the main part, and (b) shows a cross-sectional configuration taken along line Xb-Xb in (a).

  As shown in FIG. 10A and FIG. 10B, the semiconductor device according to the seventh embodiment has the first wiring pattern 4a when the potentials of adjacent wirings are the same. In this configuration, adjacent wirings of the first wiring pattern 4a are electrically connected to each other by two wiring patterns 6a. Further, the adjacent contact holes 5a are formed so as to be shifted in opposite directions (outside) of the adjacent wirings of the first wiring pattern 4a as in the sixth embodiment.

  Here, the distance between the contact holes 5a or the plating amount so that the adjacent wirings of the first wiring pattern 4a of the second wiring pattern 6a are electrically connected by the second wiring pattern 6a, for example, by a plating process. Set and form. For example, the interval between the contact holes 5a formed adjacent to each other is set to be twice or less the plating growth distance.

  In this way, the second wiring pattern 6a is grown in a self-aligned manner by the plating method from the two wirings spaced apart from each other in the first wiring pattern 4a, that is, the two contact holes 5a. Can be connected.

  In the seventh embodiment, wirings of the same potential in the first wiring pattern 4a are divided so as not to cause defects such as dishing in each wiring in the CMP process at the time of manufacturing the first wiring pattern 4a. Even in such a case, the backing layer can be formed by one wiring of the second wiring pattern 6a.

(Eighth embodiment)
The semiconductor device according to the eighth embodiment of the present invention will be described below with reference to the drawings. FIG. 11A and FIG. 11B are a first wiring pattern 4a and a second wiring pattern 6a formed thereon in the semiconductor device according to the eighth embodiment of the present invention. ) Shows the plan configuration of the main part, and (b) shows the cross-sectional configuration along the line XIb-XIb in (a).

  As shown in FIG. 11A and FIG. 11B, the semiconductor device according to the eighth embodiment has the first wiring pattern 4a when the potentials of adjacent wirings are the same. In this configuration, adjacent wirings of the first wiring pattern 4a are electrically connected to each other by two wiring patterns 6a. At this time, as a formation region of the contact hole 5a, one formation region is formed so as to straddle the wirings including the region outside the adjacent wirings.

  In this case, since the portion formed inside the contact hole 5a of the second wiring pattern 6a is integrated, that is, the third interlayer insulating film 5 is not interposed, compared with the seventh embodiment, The resistance of the second wiring pattern 6a can be further reduced.

(Ninth embodiment)
A semiconductor device according to a ninth embodiment of the present invention will be described below with reference to the drawings. FIGS. 12A and 12B are a first wiring pattern 4a and a second wiring pattern 6a formed thereon in the semiconductor device according to the ninth embodiment of the present invention. ) Shows the plan configuration of the main part, and (b) shows the cross-sectional configuration of the XIIb-XIIb line in (a).

  As shown in FIGS. 12A and 12B, in the semiconductor device according to the ninth embodiment, in the first wiring pattern 4a, two wirings having the same potential are different in potential from these. In the case where one wiring is arranged so as to be sandwiched from both sides, the second wiring pattern 6a electrically connects the wirings of the same potential outside the first wiring pattern 4a.

  Here again, the distance between the contact holes 5a formed adjacent to each other is set to be twice or less the plating growth distance.

  With this configuration, the degree of freedom in electrical connection between the first wiring pattern 4a and the second wiring pattern 6a can be improved. According to the present embodiment, it is possible to realize a mesh-shaped power supply wiring configuration in which the first wiring pattern 4a and the second wiring pattern 6a intersect with each other as shown in the tenth embodiment.

(Tenth embodiment)
A semiconductor device according to a tenth embodiment of the present invention will be described below with reference to the drawings. FIGS. 13A and 13B are a first wiring pattern 4a and a second wiring pattern 6a formed thereon in the semiconductor device according to the tenth embodiment of the present invention. ) Shows a plan configuration of the main part, and (b) shows a cross-sectional configuration taken along line XIIIb-XIIIb of (a).

  As shown in FIGS. 13A and 13B, in the semiconductor device according to the tenth embodiment, different potential signal lines, for example, the power supply line H1 and the ground line L1 are alternately arranged in the first wiring pattern 4a. Is arranged. Further, the second wiring pattern 6a formed on the first wiring pattern 4a is also the power supply line H2 that is grown only from the opening 5a formed in the power supply line H1 in the first wiring pattern 4a. And a ground line L2 grown only from the opening 5a formed in the ground line L1. Here again, the distance between the contact holes 5a formed adjacent to the same potential wiring is set to be not more than twice the growth distance of plating.

  As described above, according to the tenth embodiment, since the mesh-like power supply wiring configuration in which the first wiring pattern 4a and the second wiring pattern 6a intersect can be realized, the bias of the power supply signal in the chip is greatly reduced. can do.

(Eleventh embodiment)
The semiconductor device according to the eleventh embodiment of the present invention will be described below with reference to the drawings. 14 (a) and 14 (b) are a first pad pattern 4b and a second pad pattern 6b formed thereon in the semiconductor device according to the eleventh embodiment of the present invention. ) Shows the plan configuration of the main part, and (b) shows the cross-sectional configuration of the XIVb-XIVb line in (a).

  As shown in FIGS. 14A and 14B, in the semiconductor device according to the eleventh embodiment, the contact hole 5a formed in the third interlayer insulating film 5 is formed on the first pad pattern 4b. It extends to the surrounding area.

  Thereby, the second pad pattern 6b growing from the upper surface of the first pad pattern 4b is also formed in the lateral direction, so that a pad electrode having a larger plane area can be formed. In addition, since the third interlayer insulating film 5 is not interposed between the lower portion of the second pad pattern 6b and the first pad pattern 4b, the second pad pattern 6b is applied to the third interlayer insulating film 5. No stress occurs. As a result, there is no possibility of causing defects such as cracks in the contact hole 5a of the third interlayer insulating film 5 and its vicinity.

  It should be noted that the distance from the side surface of the first pad pattern 4b to the wall surface of the contact hole 5a extended to the outside of the first pad pattern 4b needs to be larger than the growth distance at which the second pad pattern 6b grows by the plating method.

(Twelfth embodiment)
The semiconductor device according to the twelfth embodiment of the present invention will be described below with reference to the drawings. FIG. 15A and FIG. 15B are a first pad pattern 4b and a second pad pattern 6b formed thereon in the semiconductor device according to the twelfth embodiment of the present invention. ) Shows the planar configuration of the main part, and (b) shows the cross-sectional configuration along the line XVb-XVb in (a).

  As shown in FIGS. 15A and 15B, the semiconductor device according to the twelfth embodiment not only exposes the contact hole 5a entirely including the peripheral region of the first pad pattern 4b. The third interlayer insulating film 5 is formed in a ring shape on the first pad pattern 4b.

  With this configuration, by leaving the third interlayer insulating film 5 above the first pad pattern 4b, it is possible to relieve the stress applied to the first pad pattern 4b by the second pad pattern 6b.

  In the twelfth embodiment, the distance from the side surface of the first pad pattern 4b to the wall surface of the contact hole 5a extended outward is larger than the growth distance at which the second pad pattern 6b grows by the plating method. In addition, the distance between the inner contact hole 5a and the outer contact hole 5a needs to be not more than twice the growth distance at which plating grows.

(13th Embodiment)
The semiconductor device according to the thirteenth embodiment of the present invention will be described below with reference to the drawings. FIGS. 16A and 16B are a first pad pattern 4b and a second pad pattern 6b formed thereon, respectively, in a semiconductor device according to a thirteenth embodiment of the present invention. ) Shows the planar configuration of the main part, and (b) shows the cross-sectional configuration of the XVIb-XVIb line in (a).

  As shown in FIGS. 16A and 16B, in the semiconductor device according to the thirteenth embodiment, two annular contact holes 5a are formed only on the first pad pattern 4b.

  Thus, the second pad pattern 6b can be prevented from growing in the lateral direction and becoming large. Furthermore, by leaving the third interlayer insulating film 5 on the upper side of the first pad pattern 4b, the stress applied to the first pad pattern 4b by the second pad pattern 6b can be relieved.

  In the thirteenth embodiment, the distance between the inner contact hole 5a and the outer contact hole 5a needs to be not more than twice the growth distance at which plating grows.

  According to the semiconductor device of the present invention, the power supply function can be enhanced by using the metal layer constituting the pad electrode without increasing the wiring layer, which is useful for a semiconductor device having the pad electrode and the signal wiring. is there.

(A) And (b) shows the semiconductor device which concerns on the 1st Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the Ib-Ib line | wire of (a). (A) And (b) shows one process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention, (a) is a top view, (b) is the IIb-IIb line | wire of (a). FIG. (A) And (b) shows one process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention, (a) is a top view, (b) is the IIIb-IIIb line | wire of (a). FIG. It is sectional drawing which shows the semiconductor device which concerns on the modification of the 1st Embodiment of this invention. (A) And (b) shows the semiconductor device which concerns on the 2nd Embodiment of this invention, (a) is a top view of a wiring part, (b) is sectional drawing in the Vb-Vb line | wire of (a). It is. (A) And (b) shows the semiconductor device which concerns on the 3rd Embodiment of this invention, (a) is a top view of a wiring part, (b) is sectional drawing in the VIb-VIb line | wire of (a). It is. (A) And (b) shows the semiconductor device which concerns on the 4th Embodiment of this invention, (a) is a top view of a wiring part, (b) is sectional drawing in the VIIb-VIIb line | wire of (a) It is. (A) And (b) shows the semiconductor device which concerns on the 5th Embodiment of this invention, (a) is a top view of a wiring part, (b) is sectional drawing in the VIIIb-VIIIb line | wire of (a) It is. (A) And (b) shows the semiconductor device which concerns on the 6th Embodiment of this invention, (a) is a top view of a wiring part, (b) is sectional drawing in the IXb-IXb line | wire of (a) It is. (A) And (b) shows the semiconductor device which concerns on the 7th Embodiment of this invention, (a) is a top view of a wiring part, (b) is sectional drawing in the Xb-Xb line | wire of (a). It is. (A) And (b) shows the semiconductor device which concerns on the 8th Embodiment of this invention, (a) is a top view of a wiring part, (b) is sectional drawing in the XIb-XIb line | wire of (a) It is. (A) And (b) shows the semiconductor device which concerns on the 9th Embodiment of this invention, (a) is a top view of a wiring part, (b) is sectional drawing in the XIIb-XIIb line | wire of (a) It is. (A) And (b) shows the semiconductor device which concerns on the 10th Embodiment of this invention, (a) is a top view of a wiring part, (b) is sectional drawing in the XIIIb-XIIIb line | wire of (a) In (A) And (b) shows the semiconductor device which concerns on the 11th Embodiment of this invention, (a) is a top view of a pad part, (b) is sectional drawing in the XIVb-XIVb line | wire of (a) It is. (A) And (b) shows the semiconductor device which concerns on the 12th Embodiment of this invention, (a) is a top view of a pad part, (b) is sectional drawing in the XVb-XVb line | wire of (a) It is. (A) And (b) shows the semiconductor device which concerns on the 13th Embodiment of this invention, (a) is a top view of a pad part, (b) is sectional drawing in the XVIb-XVIb line | wire of (a) It is. (A) And (b) shows the conventional semiconductor device, (a) is a top view, (b) is sectional drawing in the XVIIb-XVII line of (a).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 1st interlayer insulation film (1st insulation film)
3 Second interlayer insulating film 3a Opening 4 First wiring layer 4a First wiring pattern 4b First pad pattern 5 Third interlayer insulating film (second insulating film)
5a Contact hole (opening)
6 Second wiring layer (upper wiring layer)
6a Second wiring pattern 6b Second pad pattern 6b1 Power supply pad 6b2 Ground pad 7 Fourth interlayer insulating film 8 Third wiring layer (lower wiring layer)
8a Third wiring pattern 8b Third pad pattern 9 Fifth interlayer insulating film 10 Wiring part 11 Pad part H1 Power line L1 Ground line H2 Power line L2 Ground line

Claims (20)

A semiconductor substrate on which a plurality of semiconductor elements are formed;
A first wiring layer formed on the semiconductor substrate with a first insulating film interposed therebetween and including a wiring pattern to which a power supply potential is applied and which extends vertically and horizontally on the first insulating film;
A second insulating film formed on the first wiring layer and having a plurality of openings exposing the first wiring layer;
A semiconductor device comprising: a second wiring layer formed on the first wiring layer so as to grow isotropically from an exposed portion from each opening.   The semiconductor device according to claim 1, wherein the second wiring layer is formed by an electroless plating method.   3. The semiconductor device according to claim 1, wherein the second wiring layer is formed by being divided into a plurality of portions in a linear portion of the first wiring layer.   The semiconductor device according to claim 1, wherein the second wiring layer is also formed on a bent portion in a plane parallel to the substrate surface in the first wiring layer.   3. The semiconductor device according to claim 1, wherein the second wiring layer is formed only on a linear portion of the first wiring layer.   The semiconductor device according to claim 1, wherein a thickness of the second wiring layer is larger than a thickness of the first wiring layer.   3. The semiconductor device according to claim 1, wherein a width of the opening formed in the second insulating film is larger than a wiring width in the first wiring layer.   3. The opening according to claim 1, wherein the opening formed in the second insulating film is formed so as to be shifted outward from one side of the wiring portion in the first wiring layer. Semiconductor device.   The at least one wiring in the second wiring layer electrically connects adjacent wirings in the first wiring layer. 2. A semiconductor device according to item 1.   The at least one wiring in the second wiring layer is characterized in that the wirings in the first wiring layer are connected across another wiring to which a potential different from the potential of the wiring is applied. The semiconductor device according to any one of claims 1, 2, 7, and 8.   The semiconductor device according to claim 1, wherein the first wiring layer is a backing wiring of the second wiring layer.   The semiconductor device according to claim 1, wherein the first wiring layer and the second wiring layer intersect each other.   The semiconductor device according to claim 1, wherein the second wiring layer is made of a first metal film.   The semiconductor device according to claim 13, wherein the first metal film is made of a metal whose main component is nickel or aluminum. The second wiring layer is
A lower wiring layer formed isotropically on the first wiring layer;
15. The semiconductor device according to claim 13, comprising an upper wiring layer made of a second metal film isotropically grown on the lower wiring layer.   16. The semiconductor device according to claim 15, wherein the first metal film is made of a metal containing aluminum as a main component, and the second metal film is made of a metal containing nickel as a main component.   3. The semiconductor device according to claim 1, wherein a part of each of the first wiring layer and the second wiring layer constitutes a pad portion.   The plane area of the second wiring layer constituting the pad portion is larger than the plane area of the first wiring layer constituting the pad portion, and the opening area of the opening portion constitutes the pad portion. The semiconductor device according to claim 17, wherein the semiconductor device is larger than a plane area of the second wiring layer. A part of the plurality of openings is formed so as to be shifted outward from a side portion of the first wiring layer constituting the pad portion,
18. The semiconductor device according to claim 17, wherein a remaining part of the plurality of openings is formed on a region inside a first wiring layer constituting the pad part.   3. The semiconductor device according to claim 1, wherein each of the openings is formed only on a region inside the first wiring layer constituting the pad portion.

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