JP5066928B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a lateral MOS transistor in which a source cell and a drain cell are arranged in a checkered pattern.

  A semiconductor device having a lateral MOS transistor (Lateral Diffused Metal Oxide Semiconductor, hereinafter abbreviated as LDMOS) in which source cells and drain cells are arranged in a checkered pattern is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-95761 (Patent Document 1). ).

  8 is a semiconductor device disclosed in Patent Document 1. FIG. 8A is a plan view schematically showing the structure of a semiconductor device 90 having an LDMOS 91. FIG. It is the figure which showed typically the cross section along the AA 'line in 8 (a).

  In the semiconductor device 90 shown in FIG. 8A, the main surface of the semiconductor substrate 1 is divided into meshes and divided into square cells. The divided square cells are composed of source cells 92 and 93 and drain cells 94 and 95 of an LDMOS 91, which are arranged in a checkered pattern as shown in the figure. An LDMOS 91 shown in FIG. 8B is configured from the source cell 92 and the drain cell 94, for example, as a set of adjacent cells of the source cells 92 and 93 and the drain cells 94 and 95 arranged in a checkered pattern. .

  In the LDMOS 91 shown in FIGS. 8A and 8B, reference numeral 5 is an n + type drain region, reference numeral 8 is an n + type source region, reference numeral 9a is a high concentration p + type region, reference numeral 4 is a LOCOS oxide film, Reference numeral 12 denotes an interlayer insulating film, reference numeral 13 denotes a source electrode, and reference numeral 14 denotes a drain electrode. Reference numeral 96 denotes a contact of the drain electrode 14, and reference numeral 97 denotes a contact of the source electrode 13. As shown in FIG. 8A, the contact 96 of the drain electrode 14 and the contact 97 of the source electrode 13 are both square. The area of the contact 97 of the source electrode 13 is generally larger than the area of the contact 96 of the drain electrode 14 because the high-concentration p + type region 9a and the n + type source region 8 are connected in common. .

  In the semiconductor device 90 shown in FIGS. 8A and 8B, since the source cells 92 and 93 and the drain cells 94 and 95 having the same size are arranged in a checkered pattern, for example, a stripe-shaped source cell is used. Therefore, the on-resistance of the LDMOS can be reduced. For example, when source cells and drain cells arranged in a checkered pattern are used, the on-resistance can be reduced by about 20% compared to a case where a stripe structure is used.

  A semiconductor device in which a large number of source cells 92 and 93 and drain cells 94 and 95 shown in FIGS. 8A and 8B are repeatedly arranged is an upper layer wiring on the semiconductor substrate 1 and the source cells 92 and 93 and the drain cells 94 and 95. By connecting 95 to each other in parallel, a power element for large current control can be obtained. In this case, the upper layer wiring on the semiconductor substrate 1 needs to have as low resistance as possible.

  On the other hand, an LDMOS used in an IC (Integrated Circuit) in which a memory cell or a logic circuit is configured has a small individual control current, but is required to be highly integrated by miniaturization. Therefore, it is necessary to increase the wiring density of the upper layer wiring constituting the circuit as fine wiring. As means for increasing the wiring density, for example, a plug technique using tungsten (W) is known. A semiconductor device using this W plug is disclosed in, for example, Japanese Patent Laid-Open No. 2005-142414 (Patent Document 2).

  FIG. 9 is a diagram schematically showing a cross section of the semiconductor device 80 in the semiconductor device disclosed in Patent Document 2. As shown in FIG.

  In the semiconductor device 80 shown in FIG. 9, a number of LDMOSs are formed on the surface layer portion of the semiconductor substrate 81 as shown in the figure. Contact plugs 82 are disposed in the source and drain regions of the LDMOS in the memory cell portion, and metal plugs 83 are disposed in the source and drain regions of the LDMOS in the logic circuit portion. On the interlayer insulating film 84, wiring layers WR1, WR2, WR3, and WR4 are sequentially formed, and the wiring layers are electrically connected by contact plugs PG.

As in the semiconductor device 80 shown in FIG. 9, in a microfabrication process of wiring designed to be 0.5 μm or less, a via hole that connects the wirings is usually replaced with a tungsten (W) plug instead of aluminum (Al). Is done. In order to facilitate fine processing of wiring, a thin wiring layer having an Al film thickness of about 0.4 to 0.9 μm is used.
JP 200495761 A JP 2005-142414 A

  When a semiconductor device in which a large number of source cells and drain cells are repeatedly arranged as shown in FIG. 8 is used as a power element, for example, a control IC for controlling the power element may be formed at another position on the same semiconductor substrate. This is preferable in reducing the overall size. In order to reduce the size, it is necessary to increase the wiring density of the wiring on the semiconductor substrate on which the power element and the control IC are formed as much as possible. As described above, the checkered pattern arrangement of the source cells and drain cells in the semiconductor device 90 shown in FIG. 8 is smaller and the on-resistance of the LDMOS is reduced compared to the alternate arrangement of the stripe source cells and drain cells. Is advantageous. Further, the connection between the wiring layers using the metal plug in the semiconductor device 80 shown in FIG. 9 is advantageous in increasing the wiring density and reducing the size. Therefore, the fusion of the above two technologies is very advantageous in reducing the size of a composite IC in which a power element and a control IC are formed on the same semiconductor substrate. However, the fusion of the above two techniques is generally difficult because the amounts of current handled by the power element and the control IC are greatly different. For this reason, a composite IC incorporating the above two technologies has not yet been realized. In a composite IC having a current power element and a control IC, when a metal plug is used for connection between wiring layers, a striped source The cell and drain cell must be adopted.

  Therefore, the present invention is a semiconductor device having a low on-resistance lateral MOS transistor in which source cells and drain cells are arranged in a checkered pattern, which is compatible with plug technology advantageous for high-density wiring, and is controlled. An object of the present invention is to provide a small semiconductor device suitable for combination with an IC or the like.

  The invention according to claim 1 is a semiconductor device comprising a lateral MOS transistor in which a source cell and a drain cell are arranged in a checkered pattern on a semiconductor substrate, wherein the source cell and the drain cell are in contact with each other. The source contact plug connected to the planarized first wiring layer by the plug and connected to the source cell has a minimum width smaller than the minimum width in the contact surface of the drain contact plug connected to the drain cell. It is characterized by comprising a plurality of combinations of small contact plugs.

  The lateral MOS transistor included in the semiconductor device is a lateral MOS transistor in which source cells and drain cells are arranged in a checkered pattern on a semiconductor substrate. Therefore, the lateral MOS transistor can be reduced in size as compared with, for example, a lateral MOS transistor in which striped source cells and drain cells are alternately arranged, and accordingly, the on-resistance can be reduced.

  Further, the semiconductor device employs a plug technology advantageous for high-density wiring, and the source cell and the drain cell are connected to the planarized first wiring layer by the source contact plug and the drain contact plug, respectively. Yes. In adopting this plug technology, metal embedding in the contact hole is considered to be the most problematic.

  However, when the lateral MOS transistor is used as a power element, the wiring resistance needs to be made as small as possible in order to handle a large amount of current, and for that purpose, the contact area of the contact plug needs to be made as large as possible. Further, in a lateral MOS transistor composed of source cells and drain cells arranged in a checkered pattern, the area of the contact of the source is to connect the P conductivity type region for fixing the base potential and the N conductivity type source region in common. In general, a larger area than the area of the drain contact is required. However, as the contact area is set larger, the metal filling property of the contact hole is worsened.

  In order to solve this problem, in the above semiconductor device, the source contact plug is constituted by a plurality of combinations of small contact plugs having a minimum width smaller than the minimum width in the contact surface of the drain contact plug. Thus, even if the source contact area is set larger than the drain contact area, the metal burying property does not deteriorate in each small contact plug constituting the source contact plug.

  As described above, the semiconductor device is a semiconductor device having a low on-resistance lateral MOS transistor in which source cells and drain cells are arranged in a checkered pattern, and is advantageous for high-density wiring. And a small semiconductor device suitable for combination with a control IC or the like.

  In the semiconductor device described above, for example, the shape of the drain contact plug in the contact surface and the shape of the small contact plug in the contact surface are both square. be able to. In this case, it is preferable that the source contact plug is formed of a combination of five small contact plugs.

  According to this, in each source cell and drain cell arranged in a checkered pattern, the current flowing between the drain and the source can be controlled to be a four-fold symmetric isotropic flow.

  In the semiconductor device, for example, as described in claim 4, the source contact plug can be constituted by a plurality of combinations of the small contact plugs arranged separately. According to this, reliable metal embedding can be ensured in each small contact plug.

  According to a fifth aspect of the present invention, the source contact plug may be composed of a plurality of combinations of the small contact plugs arranged in a connected manner. According to this, although the metal embedding property is inferior to the case where the small contact plugs are arranged separately, the arrangement density of the small contact plugs can be increased.

  In the semiconductor device, as described in claim 6, planarized second wiring layer and third wiring layer are formed on the first wiring layer, and the second wiring layer and the third wiring layer are formed. It is preferable that the wiring layers are connected by via hole plugs.

  The semiconductor device employs plug technology advantageous for high-density wiring not only for contact plugs but also for via-hole plugs that connect the second wiring layer and the third wiring layer. Thus, the semiconductor device can be a small semiconductor device that is more suitable for combination with a control IC or the like.

  In the semiconductor device in which the second wiring layer and the third wiring layer are formed, the second wiring layer corresponding to the source, the third wiring layer, and the first corresponding to the drain, as defined in claim 7. It is preferable that the two wiring layers and the third wiring layer cover the cell region so that the cell region composed of the source cell and the drain cell arranged in the checkered pattern is divided into two. As a result, it is possible to employ via hole plugs having various shapes and arrangements as described below.

  For example, as described in claim 8, the shape of the via hole plug in the connection surface is a stripe shape, and a plurality of gaps are formed between the second wiring layer and the third wiring layer corresponding to the source and drain, respectively. It can be set as the structure arrange | positioned side by side.

  According to this, even when the second wiring layer and the third wiring layer are thinned for miniaturization, a large current is applied from the pad portion of the third wiring layer along the stripe of the via hole plug. The effective cross-sectional area can be increased and the wiring resistance can be reduced as a whole.

  The shape of the via hole plug in the connection surface is a lattice shape, and is arranged between the second wiring layer and the third wiring layer corresponding to the source and drain, respectively. With the configuration, the current path can be further increased, and the wiring resistance can be further reduced as a whole.

  Further, in the case where a pad portion to be described later is disposed inside the cell region, the shape in the connection surface of the via hole plug is a stripe shape as described in claim 10, and the source and drain are respectively provided. It is good also as a structure which is arrange | positioned radially between the corresponding 2nd wiring layer and 3rd wiring layer.

  The pad part that exposes the third wiring layer corresponding to each of the source and the drain may be provided outside the cell region, for example, as in claim 11, or as in claim 12. It may be provided inside the cell region.

  In order to suppress the deterioration of the third wiring layer during wire bonding, it is preferable to increase the via hole plug density below the pad portion. For this reason, when the pad portion is provided outside the cell region, a stripe-shaped via hole plug or a lattice-shaped via hole plug arranged in a line is suitable. These are also suitable when a pad portion is provided inside the cell region. Further, as described above, when the pad portion is provided inside the cell region, it may be a via hole plug that is radially arranged in a stripe shape.

  As described above, the semiconductor device is a small semiconductor device having a low on-resistance lateral MOS transistor in which source cells and drain cells are arranged in a checkered pattern. The number of source cells and drain cells arranged in a checkered pattern in the semiconductor device may be arbitrary. Therefore, the semiconductor device is suitable when the lateral MOS transistor is a power element that normally connects several hundred to several thousand unit cells in parallel.

  As described above, the semiconductor device is a small semiconductor device that can be compatible with a plug technology advantageous for high-density wiring and is suitable for combination with a control IC or the like. Therefore, as described in claim 14, the semiconductor device is suitable when an IC is arranged at a position different from the lateral MOS transistor on the semiconductor substrate.

  Further, as described in claim 15, the semiconductor device requires a power element for controlling a large current, such as a motor, and is suitable as a vehicle-mounted semiconductor device that is required to be downsized.

  The present invention relates to a semiconductor device having a lateral MOS transistor (Lateral Diffused Metal Oxide Semiconductor, hereinafter abbreviated as LDMOS) in which source cells and drain cells are arranged in a checkered pattern on a semiconductor substrate, and is advantageous for high-density wiring. Integration with various plug technologies. The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a semiconductor device that is a basis for studying the semiconductor device of the present invention, and FIG. 1A is a plan view schematically showing the structure of the semiconductor device 100. 1 (b) is a diagram schematically showing a cross section taken along the two-dot chain line BB in FIG. 1 (a).

  A semiconductor device 100 illustrated in FIG. 1A is a semiconductor device having a structure similar to that of the semiconductor device 90 illustrated in FIG. That is, in the semiconductor device 100 shown in FIG. 1A, the main surface of the semiconductor substrate 1 is divided into meshes and divided into square cells, as indicated by a one-dot chain line in the drawing. The divided square cells are composed of source cells 102 and 103 and drain cells 104 and 105 of the LDMOS 101, which are arranged in a checkered pattern as shown in the figure. The adjacent cells of the source cells 102 and 103 and the drain cells 104 and 105 arranged in a checkered pattern are taken as a set, for example, from the source cell 102 and the drain cell 104 to the lateral MOS transistor (LDMOS) shown in FIG. Lateral Diffused Metal Oxide Semiconductor) 101 is configured. In the LDMOS 101, reference numeral 21 is an n + type drain region, reference numeral 22 is an n + type source region, reference numeral 23 is a high concentration p + type region, reference numeral 24 is a LOCOS oxide film, reference numeral 25 is a gate electrode, and reference numeral 26 is an interlayer insulation. It is a film. In the plan view of the semiconductor device 90 shown in FIG. 81A, the semiconductor substrate 1 is shown and the gate electrode is not shown, whereas in the plan view of the semiconductor device 100 shown in FIG. A gate electrode 25 is shown.

  The semiconductor device 100 shown in FIG. 1A and the semiconductor device 90 shown in FIG. 8A have different wiring structures connected to the source and drain regions of the LDMOSs 91 and 101, respectively. That is, in the semiconductor device 90 of FIG. 8A, the upper wiring layers 13 and 14 made of aluminum (Al) or the like are formed in the n + type source region 8, the high concentration p + type region 9a, and the n + type drain region 5, respectively. I was in direct contact. In contrast, in the semiconductor device 100 of FIG. 1A, as shown in FIG. 1B, the n + -type source region 22 and the high-concentration p + -type region 23 and the drain cells 104 and 105 in the source cells 102 and 103 are used. Are connected to flattened first wiring layers 41 and 42 made of aluminum (Al) or the like by contact plugs 31 and 32 made of tungsten (W) or the like, respectively. The contact plugs 31 and 32 may be formed of, for example, aluminum (Al) made of the same material as the first wiring layers 41 and 42. The planarized structure shown in FIG. 1B is formed by the following process. That is, after the contact hole Ch formed in the interlayer insulating film 26 is filled with W or the like, it is planarized by CMP (Chemical Mechanical Polishing), and then the first wiring layers 41 and 42 are formed. Reference numerals 31a and 32a in FIGS. 1A and 1B indicate contacts of the contact plugs 31 and 32 to the n + type source region 22, the high concentration p + type region 23, and the n + type drain region 21, respectively. Yes.

  The LDMOS 101 included in the semiconductor device 100 of FIG. 1A is the same as the LDMOS 91 included in the semiconductor device 90 of FIG. 8A, and the source cells 102 and 103 and the drain cells 104 and 105 are formed in a checkered pattern on the semiconductor substrate 20. The LDMOS is arranged. Accordingly, the LDMOS 101 included in the semiconductor device 100 of FIG. 1A can also be reduced in size as compared with an LDMOS in which, for example, stripe-shaped source cells and drain cells are alternately arranged, as described above. As a result, the on-resistance can be reduced.

  On the other hand, unlike the semiconductor device 90 of FIG. 8A, the semiconductor device 100 of FIG. 1A employs a plug technology advantageous for high-density wiring, and the source cells 102 and 103 and the drain cells 104 and 105 These are connected to the planarized first wiring layers 41 and 42 by the source contact plug 31 and the drain contact plug 32, respectively. In adopting this plug technology, it is considered that the metal embedding property of tungsten (W) or the like in the contact hole Ch is the most problematic.

  However, when the LDMOS 101 in the semiconductor device 100 of FIG. 1A is used as a power element, it is necessary to make the wiring resistance as small as possible in order to handle a large amount of current. For this purpose, the contact area of the contact plugs 31 and 32 is It needs to be as large as possible. In the LDMOS 101 including the source cells 102 and 103 and the drain cells 104 and 105 arranged in a checkered pattern, the area of the source contact 31a is a P conductivity type region (high concentration p + type region 23) for fixing the base potential. In general, a larger area than the area of the drain contact 32a is required to connect the N conductivity type source region and the N conductivity type source region (n + type source region 22) in common. However, the larger the contact area, the worse the metal filling property of the contact hole Ch described above.

  FIG. 2 is a diagram illustrating an example of the semiconductor device of the present invention that solves the above-described problem in the semiconductor device 100 illustrated in FIG. 1A, and is a plan view schematically illustrating the structure of the semiconductor device 110. In the semiconductor device 110 of FIG. 2, the same reference numerals are given to the same parts as those of the semiconductor device 100 shown in FIG. Further, the cross-sectional structure of the LDMOS 111 included in the semiconductor device 110 of FIG. 2 is basically the same as the cross-sectional structure of the LDMOS 101 included in the semiconductor device 100 illustrated in FIG.

  A semiconductor device 110 shown in FIG. 2 is similar to the semiconductor device 100 shown in FIG. 1A, and has an LDMOS 111 in which source cells 102 and 103 and drain cells 104 and 105 are arranged on a semiconductor substrate 20 in a checkered pattern. This is a semiconductor device. The source cells 102 and 103 and the drain cells 104 and 105 are connected to the planarized first wiring layers 41 and 42 by contact plugs 31 and 32, respectively.

  On the other hand, the source contact plug indicated by the contact 31b connected to the source cells 102 and 103 of the semiconductor device 110 shown in FIG. 2 is in the contact surface of the drain contact plug indicated by the contact 32a connected to the drain cells 104 and 105. 5 includes a combination of five small contact plugs indicated by contacts 31b1 to 31b5 having a minimum width W1 smaller than the minimum width W2. Thereby, even if the area of the source contact 31b is set larger than the area of the drain contact 32a, the metal embedding property does not deteriorate in the plugs of the small contacts 31b1 to 31b5 constituting the source contact plug.

  As described above, the semiconductor device 110 illustrated in FIG. 2 is a semiconductor device including the low on-resistance LDMOS 111 in which the source cells 102 and 103 and the drain cells 104 and 105 are arranged in a checkered pattern. A compact semiconductor device that can be compatible with a plug technology advantageous for high-density wiring and suitable for combination with a control IC or the like can be obtained.

  In the semiconductor device 110 shown in FIG. 2, the shape in the contact surface of the drain contact plug indicated by the contact 32a and the shape in the contact surface of the small contact plug indicated by the contacts 31b1 to 31b5 are both It is comprised so that it may be square shape. The source contact plug indicated by the contact 31b is composed of a combination of five small contact plugs indicated by the contacts 31b1 to 31b5. According to this, in each of the source cells 102 and 103 and the drain cells 104 and 105 arranged in a checkered pattern, the current flowing between the drain and the source is controlled to be a four-fold symmetric isotropic flow. be able to.

  Thus, it is preferable that both the shape in the contact surface of the drain contact plug and the shape in the contact surface of the small contact plug are square. However, the shape is not limited to this, and may be circular or hexagonal. Further, when the source cell and the drain cell are rectangular, the shape of the drain contact plug in the contact surface and the shape of the small contact plug in the contact surface may also be rectangular. Further, the number of combinations of the small contact plugs constituting the source contact plug is not limited to five and may be any plural number.

  FIG. 3 is a diagram showing another example of the semiconductor device according to the present invention, and is a plan view schematically showing the structure of the semiconductor device 120. In the semiconductor device 120 of FIG. 3 as well, the same parts as those of the semiconductor device 100 shown in FIG.

  Similar to the semiconductor device 110 shown in FIG. 2, the semiconductor device 120 shown in FIG. 3 includes an LDMOS 121 in which source cells 102 and 103 and drain cells 104 and 105 are arranged in a checkered pattern on the semiconductor substrate 20. It is a semiconductor device.

  In the semiconductor device 110 of FIG. 2, the source contact plug indicated by the contact 31b is composed of a combination of five small contact plugs indicated by the contacts 31b1 to 31b5 that are arranged separately. As a result, reliable metal embedding can be ensured in the small contact plugs indicated by the contacts 31b1 to 31b5.

  On the other hand, in the semiconductor device 120 shown in FIG. 3, the source contact plug indicated by the contact 31 c is configured by five combinations of small contact plugs indicated by the contacts 31 c 1 to 31 c 5 arranged in a connected manner. . According to this, although the metal embedding property is inferior to the case where the small contact plugs are arranged separately as in the semiconductor device 110 of FIG. 2, the arrangement density of the small contact plugs indicated by the contacts 31c1 to 31c5 is increased. be able to.

  In the semiconductor devices 110 and 120 illustrated in FIGS. 2 and 3, the upper wiring of the first wiring layers 41 and 42 shown in FIG. 1B may be arbitrary. Below, the example of the preferable upper layer wiring in the semiconductor device of this invention is shown.

  FIG. 4 is a diagram schematically showing a cross-section of the semiconductor device 200 as an example of the semiconductor device having the preferred upper layer wiring in the present invention. In the semiconductor device 200 of FIG. 4, the same reference numerals are given to the same parts as those of the semiconductor device 100 shown in FIG.

  A semiconductor device 200 shown in FIG. 4 is formed on an SOI (Silicon On Insulator) substrate 20a having a buried oxide film 27, and source cells and drain cells are arranged in a checkered pattern as shown in FIGS. This is a semiconductor device having the LDMOS 201. In FIG. 4, the source contact plug 31 of the LDMOS 201 is shown in a simplified manner. However, in the semiconductor device 200 of FIG. 4, the source contact plug 31 is formed in the drain cell in the same manner as in FIGS. The drain contact plug 32 to be connected is composed of a plurality of combinations of small contact plugs having a minimum width smaller than the minimum width in the contact surface. In the semiconductor device 200, planarized second wiring layers 51, 52 and third wiring layers 61, 62 made of aluminum (Al) or the like are formed on the first wiring layers 41, 42 of the LDMOS 201. The second wiring layers 51 and 52 and the third wiring layers 61 and 62 are connected by a via hole plug 70a made of tungsten (W) or the like. In the semiconductor device 200, the first wiring layers 41 and 42 and the second wiring layers 51 and 52 are also connected by a via hole plug 80a made of tungsten (W) or the like.

  Further, in the semiconductor device 200 of FIG. 4, not only the LDMOS 201 used as a power element but also an IC (Integrated Circuit) representatively shown by a CMOS (Complementary Metal Oxide Semiconductor, complementary MOS) 202 at another position of the SOI substrate 20a. ) Is arranged. The contact plug 30 connected to the source region and the drain region of the CMOS 202 is formed simultaneously with the contact plugs 31 and 32 connected to the source region and the drain region of the LDMOS 201. The first wiring layer 40, the second wiring layer 50, and the third wiring layer 60 of the CMOS 202 are simultaneously formed with the first wiring layers 41, 42, the second wiring layers 51, 52, and the third wiring layers 61, 62 of the LDMOS 201, respectively. It is formed. In addition, the via hole plug 70b connecting the second wiring layer 50 and the third wiring layer 60 of the CMOS 202 and the via hole plug 80b connecting the first wiring layer 40 and the second wiring layer 50 are also formed in the via hole of the LDMOS 201, respectively. The plugs 70a and 80a are formed at the same time. The first wiring layer 40, the second wiring layer 50, and the third wiring layer 60 of the CMOS 202 are generally fine multilayer wirings having a thickness of 1 μm or less. Therefore, the first wiring layers 41 and 42, the second wiring layers 51 and 52, and the third wiring layers 61 and 62 of the LDMOS 201 are also added to the first wiring layer 40 of the CMOS 202 without adding a thick wiring layer. It is preferable to use those formed simultaneously with the second wiring layer 50 and the third wiring layer 60.

  In the semiconductor device 200 shown in FIG. 4, not only the contact plugs 30, 31, and 32 but also the second wiring layers 50, 51, and 52 and the third wiring layers 60, 61, and 62 (which are advantageous for high density wiring) are used. Also, the via hole plugs 70a and 70b (and the via hole plugs 80a and 80b) for connecting the first wiring layers 40, 41, and 42) are employed. As a result, like the semiconductor device 200, a small semiconductor device suitable for combination with an IC such as a control IC represented by the LDMOS 201 and the CMOS 202 can be obtained.

  Next, a preferable shape and arrangement of the via hole plug 70a for connecting the second wiring layers 51 and 52 of the LDMOS 201 and the third wiring layers 61 and 62 will be described based on the semiconductor device 200 shown in FIG.

  FIG. 5 is a schematic plan view showing an example of a preferable shape and arrangement of the via hole plug connecting the second wiring layer and the third wiring layer of the LDMOS.

  In FIG. 5, an area indicated by reference numeral 203 surrounded by a one-dot chain line is a cell area composed of source cells and drain cells arranged in a checkered pattern. Also, the portions indicated by reference numerals 51a and 52a surrounded by broken lines are the second wiring layers corresponding to the source and drain, respectively, and the portions indicated by reference numerals 61a and 62a surrounded by solid lines correspond to the source and drain, respectively. This is the third wiring layer. A cell region composed of a source cell and a drain cell in which the second wiring layer 51a and the third wiring layer 61a corresponding to the source and the second wiring layer 51b and the third wiring layer 61b corresponding to the drain are arranged in a checkered pattern. The cell region 203 is covered so as to divide 203 into two. As a result, it is possible to employ via hole plugs having various shapes and arrangements as described below. Note that portions indicated by reference numerals 61ap and 62ap are pad portions that expose the third wiring layers 61a and 62a corresponding to the source and drain, respectively.

  In FIG. 5, the shape of the via hole plugs 71 and 72 connecting the second wiring layers 51a and 52a and the third wiring layers 61a and 62a in the connection surface is a stripe shape. A plurality of via hole plugs 71 and 72 are arranged side by side between the second wiring layers 51a and 52a and the third wiring layers 61a and 62a corresponding to the source and the drain, respectively. Note that the shortest width W3 shown in the drawing of the stripe-shaped via hole plugs 71 and 72 is appropriately set as long as the metal burying property in the via hole is not impaired.

  According to the shape and arrangement of the via hole plugs 71 and 72 shown in FIG. 5, the second wiring layers 51a and 52a and the third wiring layers 61a and 62a are thinned to 1 μm or less for miniaturization. However, a large current can flow from the pad portions 61ap and 62ap of the third wiring layers 61a and 62a along the stripes of the via hole plugs 71 and 72, and the effective cross-sectional area is increased to reduce the wiring resistance as a whole. be able to.

  FIGS. 6A and 6B are schematic plan views showing another example of preferred shapes and arrangements of via hole plugs connecting the second wiring layer and the third wiring layer of the LDMOS, respectively. In FIG. 6, the same parts as those shown in FIG.

  The via hole plugs 73 and 74 disposed between the second wiring layers 51a and 52a and the third wiring layers 61a and 62a in FIG. 6A have a lattice shape in the connection surface. The via hole plugs 73 and 74 disposed between the second wiring layers 51b and 52b and the third wiring layers 61b and 62b in FIG. 6B also have a lattice shape in the connection surface. As in the via hole plugs 73 to 76 shown in FIGS. 6A and 6B, the shape in the connection surface is a lattice shape, so that the current path can be compared with the via hole plugs 71 and 72 shown in FIG. 5. The cross-sectional area can be further increased, and the wiring resistance can be further reduced as a whole.

  In FIG. 6A, pad portions 61ap and 62ap are provided outside the cell region 203, and in FIG. 6B, pad portions 61bp and 62bp are provided outside the cell region 204. Yes. In the case where a plurality of stripe-shaped via hole plugs 71 and 72 shown in FIG. 5 are arranged side by side between the second wiring layers 51a and 52a and the third wiring layers 61a and 62a, A pad portion can be disposed inside.

  FIG. 7 is also a schematic plan view showing another example of a preferable shape and arrangement of the via hole plug that connects the second wiring layer and the third wiring layer of the LDMOS.

  The via hole plugs 77 and 78 disposed between the second wiring layers 51c and 52c and the third wiring layers 61c and 62c in FIG. 7 have the same stripe shape as that in FIG. Are arranged in a radial pattern. In FIG. 7, the pad portions 61 cp and 62 cp are arranged inside the cell region 205.

  As described above, the pad portion that exposes the third wiring layer corresponding to each of the source and the drain may be provided outside the cell region as shown in FIG. 5 and FIG. ) Or as shown in FIG. 7, it may be provided inside the cell region. When the pad portion is provided inside the cell region, the current path toward the pad is shortened, which is advantageous for reducing the wiring resistance.

  In order to suppress the deterioration of the third wiring layer during wire bonding, it is preferable to increase the strength of the lower portion of the third wiring layer by increasing the via hole plug density below the pad portion. For this reason, when the pad portion is provided outside the cell region, a stripe-shaped via hole plug or a lattice-shaped via hole plug arranged in a line is suitable. These are also suitable when a pad portion is provided inside the cell region. Further, as described above, when the pad portion is provided inside the cell region, it may be a via hole plug that is radially arranged in a stripe shape.

  As described above, the semiconductor device of the present invention is a small semiconductor device having a low on-resistance LDMOS in which source cells and drain cells are arranged in a checkered pattern. The number of source cells and drain cells arranged in a checkered pattern in the semiconductor device may be arbitrary. Therefore, the semiconductor device is suitable when the LDMOS is a power element that normally connects several hundred to several thousand unit cells in parallel. Further, as described above, the semiconductor device of the present invention is a small semiconductor device that is compatible with a plug technology advantageous for high-density wiring and suitable for combination with a control IC or the like. Therefore, the semiconductor device is suitable when an IC is disposed at a position different from the LDMOS on the semiconductor substrate. Therefore, the semiconductor device described above is suitable as a vehicle-mounted semiconductor device that requires a power element that controls a large current such as a motor and requires downsizing.

1A is a plan view schematically showing the structure of a semiconductor device 100, and FIG. 1B is a plan view showing the structure of the semiconductor device 100. FIG. It is the figure which showed typically the cross section along the dashed-two dotted line BB in. 1 is a diagram illustrating an example of a semiconductor device of the present invention, and is a plan view schematically illustrating a structure of a semiconductor device 110. FIG. It is a figure which shows the example of another semiconductor device, and is the top view which showed the structure of the semiconductor device 120 typically. FIG. 3 is a diagram schematically showing a cross section of a semiconductor device 200 as an example of a semiconductor device having a preferable upper layer wiring. It is the typical top view which showed an example of the preferable shape and arrangement | positioning of the via-hole plug which connects the 2nd wiring layer and 3rd wiring layer of LDMOS. (A), (b) is the typical top view which showed another example of the preferable shape and arrangement | positioning of the via-hole plug which connects the 2nd wiring layer and 3rd wiring layer of LDMOS, respectively. It is the typical top view which showed another example of the preferable shape and arrangement | positioning of the via-hole plug which connects the 2nd wiring layer and 3rd wiring layer of LDMOS. In the semiconductor device disclosed in Patent Document 1, (a) is a plan view schematically showing the structure of a semiconductor device 90 having an LDMOS 91, and (b) is an AA ′ line in (a). It is the figure which showed typically the cross section along. FIG. 10 is a diagram schematically showing a cross section of a semiconductor device 80 in the semiconductor device disclosed in Patent Document 2.

Explanation of symbols

80, 90, 100, 110, 120, 200 Semiconductor device 91, 101, 111, 121, 201 Horizontal MOS transistor (LDMOS)
92, 93, 102, 103 Source cell 94, 95, 104, 105 Drain cell 30-32 Contact plug 31a-31c (Source) contact 31b1-31b5, 31c1-31c5 Small contact 32a (Drain) contact 40-42 First wiring Layer 50-52, 51a-51c, 52a-52c Second wiring layer 60-62, 61a-61c, 62a-62c Third wiring layer 70a, 70b, 71-78, 80a, 80b Via hole plug

Claims (15)

A semiconductor device having a lateral MOS transistor in which source cells and drain cells are arranged in a checkered pattern on a semiconductor substrate,
The source cell and the drain cell are respectively connected to the planarized first wiring layer by contact plugs,
A semiconductor device, wherein the source contact plug connected to the source cell comprises a plurality of combinations of small contact plugs having a minimum width smaller than a minimum width in a contact surface of the drain contact plug connected to the drain cell. .   2. The semiconductor device according to claim 1, wherein a shape in a contact surface of the drain contact plug and a shape in a contact surface of the small contact plug are both square.   The semiconductor device according to claim 2, wherein the source contact plug is composed of five combinations of the small contact plugs.   4. The semiconductor device according to claim 1, wherein the source contact plug is composed of a plurality of combinations of the small contact plugs arranged separately. 5.   4. The semiconductor device according to claim 1, wherein the source contact plug includes a plurality of combinations of the small contact plugs arranged in a connected manner. 5. A planarized second wiring layer and a third wiring layer are formed on the first wiring layer,
6. The semiconductor device according to claim 1, wherein the second wiring layer and the third wiring layer are connected by a via hole plug.   The second wiring layer and the third wiring layer corresponding to the source, and the second wiring layer and the third wiring layer corresponding to the drain are arranged in the checkered pattern to form a cell region composed of the source cell and the drain cell. The semiconductor device according to claim 6, wherein the semiconductor region covers the cell region. The shape in the connection surface of the via hole plug is a stripe shape,
The semiconductor device according to claim 7, wherein a plurality of the wiring layers are arranged side by side between a second wiring layer and a third wiring layer corresponding to each of the source and the drain. The shape in the connection surface of the via hole plug is a lattice shape,
8. The semiconductor device according to claim 7, wherein the semiconductor device is disposed between a second wiring layer and a third wiring layer corresponding to each of the source and drain. The shape in the connection surface of the via hole plug is a stripe shape,
8. The semiconductor device according to claim 7, wherein the semiconductor device is arranged radially between a second wiring layer and a third wiring layer corresponding to each of the source and drain.   10. The semiconductor device according to claim 8, wherein a pad portion that exposes a third wiring layer corresponding to each of the source and the drain is provided outside the cell region. 11.   11. The semiconductor device according to claim 8, wherein a pad portion that exposes a third wiring layer corresponding to each of the source and the drain is provided inside the cell region. 11. . The semiconductor device according to claim 1, wherein the lateral MOS transistor is a power element.   The semiconductor device according to claim 1, wherein an IC is disposed at a position different from the lateral MOS transistor on the semiconductor substrate. Said semiconductor device, a semiconductor device according to any one of claims 1 to 14, characterized in that it is mounted on a vehicle.

Images