JP7318474B2 - high frequency transistor - Google Patents

Description

The present invention relates to high frequency transistors.

In general, high-frequency amplifiers capable of outputting high power are configured using high-frequency transistors with wide gate widths. However, in a high frequency band from several MHz to several 100 GHz, simply widening the gate width tends to increase the parasitic capacitance and may reduce the gain. Therefore, in recent years, developers have constructed a high-frequency amplifier capable of outputting a large amount of power by connecting a plurality of unit cells in parallel, using transistors whose gate width is designed so as not to reduce the gain.

Non-Patent Document 1 discloses a configuration example of a unit cell. A single unit cell shown in Non-Patent Document 1 has a structure in which a plurality of transistor cores are connected in parallel. The gate wiring is connected from the upper layer to the lower metal layer using vias, and is connected to the gates of a plurality of transistor cores by bifurcating from the lower metal layer in a plane.

The drain wiring is routed two-dimensionally to just above the drain region beside the gate of the transistor core using the three upper metal layers, and uses vias from the upper metal layer to the drain region of the transistor core. connected. The source wiring is routed to directly above the source region beside the gate of the transistor core using the two lower metal layers, and is connected from the lower metal layer to the source region of the transistor core using vias. ing. Non-Patent Document 1 also describes a structure in which a plurality of such unit cells are connected in parallel. A plurality of unit cells are connected by a plurality of branched, relatively elongated gate wirings and elongated drain wirings. In addition, the plurality of unit cells are connected to the source wiring using a relatively wide area in plan view.

The gate wiring and the source wiring are grouped together in the metal layer on the upper layer side. A high-frequency transistor that conducts a large current must be constructed so as to reduce the impedance of the ground region as much as possible when conducting a large current to the ground. For this reason, the ground area is formed in an upper metal layer that can be formed with a relatively large film thickness. When configuring a source-grounded high-frequency transistor, the source terminal is connected to the ground region, so the source wiring is connected to the ground region using a relatively thick upper metal layer.

Signal wirings such as gate wirings and drain wirings also use different metal layers, but are not connected to the ground area and are wired so as to intersect with the ground area. For this reason, the layout is generally configured so that the source current of the high-frequency transistor flows in the direction perpendicular to the extending direction of the signal wiring such as the gate wiring and the drain wiring.

Dixian Zhao et. al., "A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS", IEEE JSSC, pp. 2323-2337, 2013.

In the structure described in Non-Patent Document 1, the source current from the central unit cell among the plurality of unit cells connected in parallel also flows into the source wiring in the outer unit cell, so the source current flows through the source wiring. There is a risk of exceeding the allowable current of the metal layer that constitutes it.

An object of the present disclosure is to provide a high-frequency transistor capable of suppressing the source current flowing from the central unit cell to the source wiring of the outer unit cell.

According to the first aspect of the invention, the unit cells (U1...U3; U1...U4; U1...U5) have transistor cores (3; 503) with source regions (14) and drain regions (13) electrically connected in parallel. Connected. The source wires (6; 206; 306; 406; 506) are drawn out from the source regions of the transistor cores in the unit cell using the first metal layer (16s). The drain wiring (5; 505) is led out from the drain region of the transistor core in the unit cell using a second metal layer (16d) different from the source wiring. A source wiring and a drain wiring are allocated to the transistor section area (2) in plan view. A plurality of unit cells are spaced apart in the main direction of the source current flowing through the source wiring, and at least a part of the first metal layer forming the source wiring is formed in the region forming the individual unit cells. Constructed along the main direction.

In the transistor segmented area, the source wiring is spaced between the plurality of unit cells arranged side by side and outside the outermost unit cell arranged side by side. , 408, 407a, 408a, 409, 410). A slit formed in the source line is partially provided in the transistor section region along a direction crossing the main direction. According to the first aspect of the present invention, the slit cuts off the conduction path of the source current between the unit cells, so that the source current flowing from the central unit cell to the source wiring of the outer unit cell can be suppressed.

FIG. 2 is a plan view schematically showing the structure of the high-frequency transistor according to the first embodiment; FIG. 2 is a plan view showing the structure of the gate wiring according to the first embodiment; FIG. 2 is a plan view showing the structure of the drain wiring according to the first embodiment; FIG. 2 is a plan view showing the structure of the source wiring according to the first embodiment; FIG. 2 is a cross-sectional view schematically showing a parallel connection structure of transistor cores according to the first embodiment (a cross-sectional view taken along line VV in FIG. 1); FIG. 2 is a cross-sectional view schematically showing the structure of the source wiring according to the first embodiment (cross-sectional view taken along line VI-VI in FIG. 1); Usage example of the high-frequency transistor according to the first embodiment Explanatory diagram of observation points of source current according to the first embodiment Simulation results comparing cases without slits and with slits according to the first embodiment FIG. 4 is a plan view schematically showing the structure of a high-frequency transistor according to a second embodiment; A plan view schematically showing the structure of a high-frequency transistor according to a third embodiment. A plan view schematically showing the structure of a high-frequency transistor according to a fourth embodiment. Explanatory diagram of observation points of the source current according to the fourth embodiment Simulation results comparing the case where the length of the slit according to the fourth embodiment is longer toward the outside of the unit cell and the case where the length of the slit is the same A plan view schematically showing the structure of a high-frequency transistor according to a fifth embodiment.

Several embodiments are shown below. In each of the embodiments described below, the same or similar reference numerals are assigned to configurations that perform the same or similar operations, and description thereof will be omitted as necessary. The three-dimensional directions of XYZ are defined as shown in FIG. 1 and explained. The XYZ directions are three-dimensional directions that intersect each other at right angles.

(First embodiment)
As illustrated in FIG. 1, the high-frequency transistor 1 is provided in a transistor segmented region 2 (hereinafter abbreviated as segmented region 2) divided into the high-frequency transistor. A plurality of U3 are arranged side by side in the Y direction. The unit cell U1 has a structure in which a plurality of transistor cores 3 (hereinafter abbreviated as cores 3) are electrically connected in parallel. Unit cells U2 and U3 are also constructed similarly to unit cell U3.

In FIGS. 2, 3, and 4, the planar structures of the gate wiring 4, the drain wiring 5, and the source wiring 6 in the high-frequency transistor 1 shown in FIG. 1 are highlighted by hatching. sign is omitted.
As illustrated in FIG. 2, the gate wirings 4 of the plurality of unit cells U1 . to other circuit structures (not shown). The gate wirings 4 of the plurality of unit cells U1 . . . G3 from G so as to be separated in three directions in the Y direction.

As illustrated in FIG. 3, the drain wirings 5 of the plurality of unit cells U1 . It is connected to other external circuit structures (not shown). The drain wirings 5 of the plurality of unit cells U1 . . . . D3 so as to be divided into three branches in the Y direction in plan view.

As illustrated in FIG. 4, the source wirings 6 of the plurality of unit cells U1 . Also, the gate wiring 4 and the drain wiring 5 and the ground wiring are three-dimensionally arranged so as not to cross each other except for the source wiring 6 .

When the divided area 2 is viewed two-dimensionally, the source wiring 6 is provided with slits 7 and 8 between each of the plurality of unit cells U1, . are provided with slits 9 and 10 spaced apart from each other. When considered along the X-direction, the slits 7 .

As shown in cross section in FIG. 5, the high-frequency transistor 1 is constructed using a silicon substrate 11 having an n-well 11b on the surface and a p-well 11a on the inner surface of the n-well 11b. The core 3 of each unit cell U1 . are provided with an n-type drain region 13 and a source region 14, respectively. As illustrated in FIGS. 2 to 4, the gate electrode 12, drain region 13, and source region 14 of each core 3 are elongated along the Y direction of each unit cell U1 . . . U3.

As illustrated in FIG. 5, the cores 3 are spaced apart in the X direction. The adjacent cores 3 are configured to share the drain region 13 between adjacent cores 3 in the X direction. The cores 3 arranged side by side are configured to share the source region 14 between the cores 3 adjacent to each other in the X direction. The gate electrode 12, the drain region 13, and the source region 14 of each core 3 are separated from each other by keeping a predetermined distance between the unit cells U1 . . . U3 adjacent in the Y direction, as illustrated in FIGS. It is

Hereinafter, each layer obtained by stacking metal layers 16g, 16d, and 16s on the silicon substrate 11 via vias 15g, 15d, and 15s is referred to as a first layer L1 to an eighth layer L8. 5. A structural example of the source wiring 6 will be described.

As illustrated in FIG. 2, the gate electrodes 12 are configured to extend in the Y direction in each of the unit cells U1 . . . U3. is coupled to via contact 15gc at .

On the other hand, the gate lines 4 of the unit cells U1 . . . U3 are formed by stacking metal layers 16g and vias 15g from the seventh layer L7 to the first layer L1 as illustrated in FIG. connected by structure. As illustrated in FIG. 2, the gate wiring 4 is separated from the first layer L1 into two branches in the Y direction in a plan view, and extends from the separated end portion in the first layer L1 toward the other end in the X direction. are wired as follows. The gate wiring 4 is electrically connected to the gate electrodes 12 of the plurality of cores 3 through via contacts 15gc.

As illustrated in FIG. 3, the drain wirings 5 of the unit cells U1 . . . U3 are wired so as to extend from the sub-bases D1 . As illustrated in FIG. 5, the drain wiring 5 of each unit cell U1 . and is electrically connected from the fourth layer L4 to the drain region 13 of the core 3 by the laminated structure of the metal layer 16d and the via 15d. In the cross section shown in FIG. 6, the drain wiring 5 is formed from the fourth layer L4 to the seventh layer L7, but is separated from the source wiring 6 in the three-dimensional direction (Z direction).

As illustrated in FIG. 4, the source lines 6 of the unit cells U1 . It is routed to just above the side source region 14 and electrically connected to the source region 14 of the core 3 using a laminated structure of metal layers 16s and vias 15s from the first layer L1 . . . third layer L3. . In the cross section illustrated in FIG. 6, the source wiring 6 is continuously formed in the second layer L2 and the third layer L3 over substantially all directions in the Y direction, and the main current of the source wiring 6 is generally Y. flow along the direction

As illustrated in FIG. 4, the source wiring 6 has main source wiring portions 6a located at both ends in the X direction in the partitioned region 2 and extending in the Y direction. The main source wiring portion 6a is a wiring portion that passes the main current of the source current Is between the vias V(S) (see FIG. 6: not shown in FIG. 4) provided on both sides in the Y direction. .

First slit 7 .

The source wiring 6 includes a first medium-thickness source wiring portion 6b and a second medium-thickness source wiring portion 6c between each of the unit cells U1 and U2, U2 and U3 arranged side by side in the Y direction. The first medium-thick source wiring portion 6b and the second medium-thickness source wiring portion 6c extend along the X direction, respectively, and are integrally connected to the main source wiring portions 6a located at both ends in the X direction in the partitioned region 2. has been made

The source wiring 6 has a third medium-thick source wiring portion 6d outside the unit cell U1 positioned at one end in the Y direction among the unit cells U1 . The third medium-thick source wiring portion 6d extends along the X direction, and is connected to and integrated with the main source wiring portions 6a positioned at both ends in the X direction in the partitioned region 2. As shown in FIG.

The source wiring 6 has a fourth medium-thick source wiring portion 6e outside the unit cell U3 located at the other end in the Y direction among the unit cells U1 . . The fourth medium-thick source wiring portion 6e extends along the X direction and is connected to and integrated with the main source wiring portions 6a located at both ends in the X direction in the partitioned region 2 .

The source wiring 6 includes a plurality of elongated source wiring portions 6f1 along the Y direction between the first medium-thick source wiring portion 6b and the third medium-thickness source wiring portion 6d. The source wiring 6 includes a plurality of elongated source wiring portions 6f2 along the Y direction between the first medium-thick source wiring portion 6b and the second medium-thickness source wiring portion 6c. The source wiring 6 includes a plurality of elongated source wiring portions 6f3 along the Y direction between the second medium-thick source wiring portion 6c and the fourth medium-thickness source wiring portion 6e. A plurality of these elongated source wiring portions 6f1, 6f2, and 6f3 are spaced apart in the X direction in FIG.

In each unit cell U1 . . . U3, each elongated source wiring portion 6f1 . The metal layer 16s forming the elongated source wiring portions 6f1 . . . 6f3 is formed along the main direction in which the source current Is flows in the respective unit cells U1 .

6f3 of the unit cells U1 . . . U3 are arranged so that the center lines of the elongated source wiring portions 6f1 . . .

A first slit 7 and a second slit 8 are formed along the X direction in the first medium-thick source wiring portion 6b and the second medium-thickness source wiring portion 6c, respectively. The first slit 7 and the second slit 8 are configured to partially cut the source line 6 between the unit cells U1 and U2, U2 and U3, respectively.

A third slit 9 and a fourth slit 10 are formed along the X direction in the third medium-thick source wiring portion 6d and the fourth medium-thickness source wiring portion 6e, respectively. The third slit 9 is configured to be spaced outside in the Y direction of the outermost unit cells U1 juxtaposed in the segmented area 2 . The fourth slit 10 is also configured to be spaced outside in the Y direction of the outermost unit cell U3 juxtaposed in the segmented region 2 . The third slit 9 and the fourth slit 10 are configured to partially cut off the source line 6 outside each of the unit cells U1 and U3.

In this embodiment, each of the first slit 7 to the fourth slit 10 is composed of a continuous gap along the X direction. Each of the first slits 7 . . . 4th slits 10 does not need to be constituted by one continuous gap along the X direction, and may be provided with a plurality of gaps, for example, two or three.

In the cross section illustrated in FIG. 6, a laminated structure of vias 15s of the source wiring 6 and metal layers 16s is formed on the source region 14 of the silicon substrate 11 from the first layer L1 to the third layer L3. A drain wiring 5 is formed above the laminated structure of the via 15s of the source wiring 6 and the metal layer 16s. The lamination structure of the vias 15s and the metal layers 16s of the unit cells U1 . . .

On the other hand, from the seventh layer L7 below the via V(S) to the second layer L2, a via 15s and a metal layer 16s form a laminated structure. The lamination structure of the via 15s and the metal layer 16s provided below the via V(S) and the lamination structure of the via 15s and the metal layer 16s above the source region 14 are separated from each other by slits 9 and 10. ing.

The flow of the drain current Id and the source current Is of the high-frequency transistor 1 having the above structure will be described. Considering the case of application to a radar in the millimeter wave band, the high-frequency amplifier 30 has, for example, MOS transistors M1 and M2 that can be used in the millimeter wave band connected in a grounded source type, as illustrated in FIG. think. The MOS transistors M1 and M2 illustrated in FIG. 7 each have the structure of the high-frequency transistor 1 described above.

A high-frequency amplifier 30 includes high-frequency transformers 20 . . . 23 . The high-frequency transformers 20 and 21 are connected so as to pass the input differential AC signal In to the gate electrodes 12 of the pair of MOS transistors M1 and M2. A bias voltage Vgs is applied to the gate electrodes 12 of the MOS transistors M1 and M2 through high frequency transformers 20 and 21, respectively.

Also, a DC drain-source bias voltage Vds is applied to the drain wirings 5 of the MOS transistors M1 and M2 through the high frequency transformers 22 and 23, respectively. High-frequency transformers 22 and 23 output a differential AC signal Out from drain wiring 5 of a pair of MOS transistors M1 and M2. At this time, in each of the MOS transistors M1 and M2, the drain current Id and the source current Is flow according to the bias voltage Vgs applied to the gate wiring 4. FIG.

On the semiconductor device whose planar structure is illustrated in FIG. 1, when the drain current Id flows from the drain wiring 5 to the drain region 13 of the core 3 of the high frequency transistor 1, the source current Is flows out to the source wiring 6 via the core 3 . The source current Is mainly flows both upward and downward in the Y direction in FIG. However, since the first slits 7 and the second slits 8 are provided between the unit cells U1 and U2, and between the unit cells U2 and U3, the source current Is is energized along the Y direction in FIG. It will be partially blocked by the slit 7 and the second slit 8 .

Therefore, for example, the source current Is flowing through the unit cell U2 flows through the main source wiring portions 6a on both sides of the first slit 7 and the second slit 8 in the X direction in the partitioned region 2, It becomes difficult to conduct electricity to the source wiring portions 6f1 and 6f3. As a result, the source current Is flowing inside each of the unit cells U1 and U3 can be suppressed below the allowable current of the metal layer 16s forming the elongated source wiring portions 6f1 and 6f3.

<Simulation result>
The inventor obtained simulation results of current distribution flowing through the elongated source wiring portions 6f1 . . . 6f3 by performing an electromagnetic field analysis using a simulation tool. The inventor observes the source current Is at each observation point of the elongated source wiring portions 6f1 . . . 6f3 in FIG. See observations I1...I6. As for the direction of the source current Is, the upward direction in the Y direction in FIG. 8 is defined as a positive current, and the downward direction in the Y direction is defined as a negative current.

FIG. 9 shows a simulation result when the slits 7 . . . 10 are not provided (no slits) and a simulation result when the slits 7 . The identification codes of the elongated source wiring portions 6f1 . . . 6f3 shown in FIG. 9 represent the source wiring identification codes A .

As is clear from FIG. 9, according to the observed values I3 and I4 of the middle unit cell U2, the source current Is flows along the vertical direction in the Y direction regardless of the presence or absence of the slit. Also, according to the observed values I1 and I2 of the outer unit cell U1, it can be seen that the source current Is flows upward in the Y direction under the unconditional slit. In particular, the source current Is flowing through the elongated source wiring portion 6f1 of the source wiring identification code (for example, C to G) near the center of the unit cell U1 is susceptible to the current flowing upward in the Y direction from the central unit cell U2. . Therefore, it can be seen that the source current Is of the elongated source wiring portion 6f1 increases in the positive direction.

On the other hand, the observed value I2 of the unit cell U1 under the condition with slits shows a negative value in all the elongated source wiring portions 6f1 of the source wiring identification codes A to I, so that the positive value of the observed value I1 is offset. It can be observed that the That is, the slits 7, . was confirmed to be suppressed.

Also, it can be seen that the observed values I5 and I6 of the source current Is of the outer unit cell U3 flow downward in the Y direction under the slit condition. In particular, the source current Is flowing through the elongated source wiring portion 6f3 of the identification code (for example, C to G) near the center of the unit cell U3 under no slit conditions is influenced by the current flowing downward in the Y direction from the unit cell U2 on the center side. easy to receive. Therefore, it can be seen that the source current Is of the elongated source wiring portion 6f3 increases in the negative direction.

On the other hand, the observed value I5 of the unit cell U3 under the condition with slits shows a positive value in all the elongated source wiring portions 6f3 of the source wiring identification codes A . You can see it flowing. 10 are provided in the segmented region 2, the source current Is is distributed in the vertical direction in the Y direction, and as a result, the source current Is flowing through each of the elongated source wiring portions 6f3. was confirmed to be suppressed.

According to this embodiment, the slits 7 . . . 10 are partially provided in the partitioned region 2 along the X direction perpendicular to the main direction in which the source current Is flows, so that the slits 7 . . . , the conduction path of the source current Is between U3 can be interrupted. As a result, the source current Is flowing from the central unit cell U2 to the elongated source wiring portions 6f1 and 6f3 of the outer unit cells U1 and U3 can be suppressed. The current can be suppressed to less than the allowable current of the metal layer 16s forming the elongated source wiring portions 6f1 and 6f3.

(Second embodiment)
FIG. 10 illustrates the second embodiment. The high frequency transistor 201 illustrated in FIG. 10 comprises an even number of unit cells U1 . . . U4, for example four. A source wiring 206 replacing the source wiring 6 is configured as shown in FIG. In the source line 206, first slits 207, second slits 209, and third slits 210 are formed around the even number of unit cells U1 . . . U4.

The unit cells U1 . . . U4 are spaced apart in the Y direction of the segmented area 2 and arranged side by side. The first slit 207 is located in the Y-direction center of the segmented area 2 between the unit cells U2 and U3 and partially configured along the X-direction. The second slit 209 is formed at a position straddling a plurality (two) of unit cells U2 and U1 from the first slit 207 upward in the Y direction. The second slit 209 is partially configured to be spaced outside the outermost unit cell U1 in the segmented area 2 .

The third slit 210 is formed at a position straddling a plurality (two) of unit cells U3 and U4 in the downward direction in the Y direction from the first slit 207. Outwardly spaced and partially configured. Since other structures are the same as those of the first embodiment, description thereof is omitted.

The high-frequency transistor 201 of this embodiment has a plurality of unit cells U2 and U1 arranged side by side between the first slit 207 and the second slit 209 adjacent to each other. Also, the high-frequency transistor 201 has a plurality of unit cells U3 and U4 arranged side by side between the first slit 207 and the third slit 210 adjacent to each other.

According to such a high-frequency transistor 201, the number of slits 207, 209, and 210 per unit area in the segmented region 2 and the configuration area can be reduced compared to the structure of the first embodiment, for example. Therefore, the impedance of the source wiring 206 can be lowered, and the gain of the high frequency transistor 201 can be increased. Further, according to the present embodiment, the current flowing from the central unit cells U2 and U3 to the source wirings 206 of the outer unit cells U1 and U4 can be suppressed and limited in the same manner as in the previous embodiment.

(Third embodiment)
FIG. 11 illustrates the third embodiment. The high frequency transistor 301 illustrated in FIG. 11 comprises an odd number of unit cells U1 . . . U5, for example five. A source wiring 306 replacing the source wiring 6 is configured as shown in FIG. A first slit 307, a second slit 308, a third slit 309, and a fourth slit 310 are formed in the source line 306 around the odd number of unit cells U1 . . . U5.

The unit cell U3 is provided in the center of the divided area 2 in the Y direction. Further, the unit cell U2 is placed side by side with a space above the unit cell U3 in the Y direction. Further, the unit cell U1 is placed side by side with a space above the unit cell U2 in the Y direction. Further, the unit cell U4 is arranged side by side with a space under the unit cell U3 in the Y direction. Further, the unit cell U5 is arranged side by side with a space under the unit cell U4 in the Y direction. Each unit cell U1 . . . U5 has an elongated source wiring portion 6f1 . The structure of these elongated source wiring portions 6f1 . . . 6f5 conforms to the structure of the elongated source wiring portions 6f1 .

A first slit 307 . . . a fourth slit 310 are formed along the X direction. The first slit 307 and the second slit 308 are configured so as to be spaced apart on both sides in the vertical direction in the Y direction of the unit cell U3 provided in the center of the segmented area 2 .

The third slit 309 is formed in a region straddling a plurality (two) of unit cells U2 and U1 in the upward direction in the Y direction from the first slit 307, and is formed spaced outside the outermost unit cell U1. ing. In addition, the fourth slit 310 is configured in a region straddling a plurality (two) of unit cells U4 and U5 downward in the Y direction from the second slit 308, and is configured to be spaced outside the outermost unit cell U5. It is Since other structures are structures according to the first embodiment, description thereof is omitted.

According to the high-frequency transistor 301 of this embodiment, a plurality of unit cells U2 and U1 are provided side by side between the adjacent slits 307 and 309. FIG. The high-frequency transistor 301 has a plurality of unit cells U4 and U5 arranged side by side between adjacent slits 308 and 310. FIG.

According to the high-frequency transistor 301, the number and configuration of the slits 307 . area can be reduced. Therefore, the impedance of the entire source wiring 306 can be lowered, and the gain of the high frequency transistor 301 can be increased.

Further, according to the present embodiment, as in the previous embodiment, the elongated source wiring portions 6f2 and 6f1 of the unit cells U2 and U1 outside the central unit cell U3 and the elongated source wiring portions 6f4 and 6f5 of the unit cells U4 and U5 are arranged. can suppress and limit the current flowing into the

(Fourth embodiment)
FIG. 12 illustrates a fourth embodiment. The high frequency transistor 401 illustrated in FIG. 12 comprises an odd number of unit cells U1 . . . U5, for example five. A source wiring 406 replacing the source wiring 6 is configured as illustrated in FIG. In the source line 406, first slits 407, second slits 408, third slits 407a, fourth slits 408a, fifth slits 409, and sixth slits are positioned around the odd number of unit cells U1...U5. 410 is configured in the form shown.

The layout structure of the unit cells U1 . . . U5 is the same as the layout structure of the unit cells U1 . Each unit cell U1 . . . U5 has an elongated source wiring portion 6f1 . Therefore, the explanation is omitted.

These first slits 407 . . . sixth slits 410 are formed along the X direction. The first slit 407 and the second slit 408 are configured so as to be spaced apart on both sides of the unit cell U3 provided in the center of the segmented area 2 in the vertical direction in the Y direction.

The third slit 407a is formed in a region straddling one unit cell U2 from the first slit 407 upward in the Y direction. Further, the fourth slit 408a is formed in a region straddling one unit cell U4 from the second slit 408 downward in the Y direction. The fifth slit 409 is configured in a region straddling one unit cell U1 upward in the Y direction from the third slit 407a, and is configured to be spaced outside the outermost unit cell U1. The sixth slit 410 is formed in a region straddling one unit cell U5 downward in the Y direction from the fourth slit 408a, and is spaced outside the outermost unit cell U5. The first slit 407 . . . the sixth slit 410 are configured such that their respective lengths increase with increasing distance from the central portion of the segmented region 2 in the vertical direction in the Y direction. In other words, the first slit 407 . . . the sixth slit 410 are configured to be elongated toward the downstream side where the main current of the source current Is flows.

For example, the X-direction lengths of the first slit 407 and the second slit 408 are set to the first length W1. The X-direction lengths of the third slit 407a and the fourth slit 408a are set to a second length W2 longer than the first length W1. The X-direction lengths of the fifth slit 409 and the sixth slit 410 are set to a third length W3 longer than the second length W2. The relationship between the X-direction lengths of the first slit 407 . Since other structures are structures according to the first embodiment, description thereof is omitted.

FIG. 13 shows observation points of observed values I7 . . . I16, and FIG. 14 shows simulation results of observed values I7 . FIG. 14 shows both the source current Is when the structure according to the present embodiment is employed and the source current Is when all the first slits 407 to sixth slits 410 have the same length in the X direction.

According to the structure of the fourth embodiment, it was confirmed that the observed values I7 and I8, I15 and I16 of the source line identification codes A and I on the outermost side in the X direction are suppressed. This is because, when the source current Is flows from the central unit cell U3 toward the outer unit cells U1, U2, U4, and U5, it easily flows through the main source wiring portions 6a located at both ends in the X direction. This is because the source current Is flowing into the elongated source wiring portions 6f1, 6f2, 6f4 and 6f5 inside the cells U1, U2, U4 and U5 can be suppressed.

According to this embodiment, since the X-direction lengths of the first slits 407 through the sixth slits 410 formed in the source line 406 are configured to be longer toward the outside of the partitioned region 2, the configuration of the above-described embodiment is adopted. In comparison, the source current Is flowing into the elongated source wiring portions 6f1, 6f2, 6f4, and 6f5 can be suppressed.

(Fifth embodiment)
FIG. 15 illustrates the fifth embodiment. A high-frequency transistor 501 shown in FIG. 15 schematically shows a planar structure of a power CMOS transistor. In the divided area 2 of the high-frequency transistor 501, a plurality (three) of unit cells U51, . Each unit cell U51 . . . U53 has a structure in which a plurality of transistor cores 503 (hereinafter abbreviated as cores 503) are electrically connected in parallel.

The gate wiring 504 of the plurality of unit cells U1 . . . U3 has its base G provided at one end of the partitioned region 2 in the X direction. It is connected to the. The gate wires 504 of the plurality of unit cells U51 . . . U53 are wired from the base G toward the sub-bases G1 .

In the sub-bases G1...G3, the gate wiring 504 of each unit cell U1...U3 is connected from the seventh layer L7 to the first layer L1 using a laminated structure of vias 15g and metal layers 16g. The gate wiring 504 is formed in a lattice frame shape (also referred to as a mesh shape or a mesh shape) in the first layer L1. This portion of the first layer L1 is hereinafter referred to as a lattice frame portion 504ga. The grid frame portion 504ga of the gate wiring 504 is connected to the sub-bases G1 . . . G3 through vias 15g at one end in the X direction and in a partial region on the center side in the Y direction.

A drain region 13 and a source region 14 are formed on the surface layer of the silicon substrate 11 within each frame of the lattice frame-shaped portion 504ga of the gate wiring 504 . In a plan view, the drain regions 13 are arranged in a zigzag manner within the frame, and the source regions 14 are arranged in a zigzag manner within the frame other than the arranged drain regions 13 . Therefore, the surface layer of the silicon substrate 11 on one side in the X direction of the lattice frame-like gate wiring 504 is formed in the source region 14, and the surface layer of the silicon substrate 11 on the other side in the X direction of the gate wiring 504 is formed. is configured as the drain region 13 .

The cores 503 adjacent in the X direction share the source region 14 or the drain region 13 . The cores 503 adjacent in the Y direction also share the source region 14 or the drain region 13 .

Each of the unit cells U51 . . . U53 has a lattice frame-like portion 504ga of the gate wiring 504 formed in a mesh-like layout structure. Each core 503 constituting the unit cells U51 .

The drain wiring 505 of the plurality of unit cells U51 . not shown). The drain wirings 505 of the plurality of unit cells U51 . . . U53 are wired from the base D toward the sub-bases D1 .

The drain wiring 505 of each unit cell U51 . , and connected from the fourth layer L4 to the drain region 13 by the laminated structure of the metal layer 16d and the via 15d.

The source wirings 506 of the plurality of unit cells U1 . The source wiring 506 is routed to directly above the source region 14 beside the lattice frame portion 504ga of the core 503 using the metal layers 16s of the second layer L2 and the third layer L3, and From the third layer L3 to the source region 14 through the first layer L1, the metal layer 16s and the via 15s are connected by a laminated structure. Although detailed description of the cross-sectional structure of the source wiring 506 is omitted according to the description of FIGS. , and the main current of the source line 506 generally flows along the Y direction.

The source wiring 6 is located at both ends in the X direction in the partitioned region 2 and has main source wiring portions 506a along the entire Y direction. The main source wiring portion 506a conducts the main current of the source current Is between the vias V(S) (see FIG. 6, not shown in FIG. 15) provided on both sides of the Y direction of the partitioned region 2. This is the wiring section.

As shown in FIG. 4, the first slit 7 . .

The structure of the first medium-thick source wiring portion 506b . The description is omitted because it is the same as the structure.

The source wiring 506 has an elongated source wiring portion 506f1 provided between the first medium-thick source wiring portion 506b and the third medium-thickness source wiring portion 506d so that the main current of the source current Is flows along the Y direction. there is The source wiring 506 is provided with an elongated source wiring portion 506f2 between the first medium-thick source wiring portion 506b and the second medium-thickness source wiring portion 506c so that the main current of the source current Is flows along the Y direction. there is The source wiring 506 is provided with an elongated source wiring portion 506f3 between the second medium-thick source wiring portion 506c and the fourth medium-thickness source wiring portion 506e so that the main current of the source current Is flows along the Y direction. there is At least a part of the metal layer 16s that constitutes these elongated source wiring portions 506f1 to 506f3 is formed along the main direction in which the source current Is flows in the region constituting the unit cells U51 to U53.

In each unit cell U51 . . . U53, each elongated source wiring part 506f1 . It is wired across directly above the region 14 . Each elongated source wiring portion 506f1 . . . 506f3 is configured to cross-connect a plurality of elongated source wiring portions 506f1 .

A first slit 7 and a second slit 8 are formed along the X direction in the first medium-thick source wiring portion 506b and the second medium-thickness source wiring portion 506c, respectively. The first slit 7 and the second slit 8 are configured to partially cut the source line 506 between each of the unit cells U51 and U52, U52 and U53.

A third slit 9 and a fourth slit 10 are formed along the X direction in the third medium-thick source wiring portion 506d and the fourth medium-thickness source wiring portion 506e, respectively. The third slit 9 is configured to be spaced outside in the Y direction of the outermost unit cell U51 juxtaposed in the segmented area 2 . The fourth slit 10 is configured to be spaced outside in the Y direction of the outermost unit cell U53 juxtaposed in the segmented area 2 . The third slit 9 and the fourth slit 10 are configured to partially cut off the source line 506 outside each of the unit cells U51 and U53.

The first slit 7 . . . the fourth slit 10 are partially provided in the sectioned region 2 along the X direction. In this embodiment, each of the first slit 7 to the fourth slit 10 is composed of a continuous gap along the X direction. Each of the first slits 7 . . . 4th slits 10 does not need to be constituted by one continuous gap along the X direction, and may be provided with a plurality of gaps, for example, two or three.

Also in the present embodiment, the first slits 7 to the fourth slits 10 are partially provided in the partitioned area 2 along the X direction. Effective. Therefore, even when the high-frequency transistor 501 is composed of a power CMOS transistor, the source current Is flowing through the elongated source wiring portions 506f1 . . . 506f3 can be suppressed below the allowable current.

(Other embodiments)
The configuration is not limited to the configurations of the above-described embodiments, and for example, the following modifications or extensions are possible.
Although the number of cores 3 per unit cell U1 . . . U3 is 16 in the first embodiment, the number is not limited thereto. U53, U1 . . . U3, U1 . . . U4, U1 . . . U3, U1 . . . U4, U1 .

The XYZ directions in the figure are not limited to orthogonal directions as long as they intersect. Although the high-frequency transistors 1, 201, 301, 401, and 501 are used in the millimeter wave band high-frequency amplifier 30, they are not limited to this. Further, for example, it can be applied to high frequency transistors 1, 201, 301, 401, 501 used in a high frequency band from several MHz band to several hundred GHz band.

Although the present disclosure has been described in accordance with the embodiments described above, it is understood that the present disclosure is not limited to such embodiments or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations including one, more, or less elements thereof, are within the scope and spirit of this disclosure.

In the drawings, 1, 201, 301, 401, 501 are high-frequency transistors, 2 is a transistor segmented region, 3, 503 is a transistor core, 6, 206, 306, 406, 506 are source wirings, 5, 505 are drain wirings, and U1. . . U5, U51 . . . U53 indicate unit cells.

Claims (4)

unit cells (U1...U3; U1...U4; U1...U5; U51...U53) formed by electrically connecting transistor cores (3; 503) having source regions (14) and drain regions (13) in parallel;
source wiring (6; 206; 306; 406; 506) drawn from the source region of the transistor core in the unit cell using a first metal layer (16s);
a drain wiring (5; 505) drawn from the drain region of the transistor core in the unit cell using a second metal layer (16d) different from the source wiring;
in the planarly allocated transistor segmentation areas (2),
A plurality of the unit cells are spaced apart in the main direction of the source current flowing through the source wiring, and at least a portion of the first metal layer forming the source wiring is formed in a region constituting each of the unit cells. along the main direction of the sourcing current in
The source wiring is spaced apart between the plurality of unit cells arranged side by side and outside the outermost unit cells arranged side by side in the transistor segmented region. ; 307 ... 310; 407, 408, 407a, 408a, 409, 410),
A high-frequency transistor, wherein said slit formed in said source line is partially provided in said transistor segmented region along a direction crossing said main direction. 2. The high-frequency transistor according to claim 1, wherein said slit comprises a single continuous gap. 3. The high-frequency transistor according to claim 1, wherein the plurality of slits are elongated toward the outside of the transistor segmented region. 4. The high-frequency transistor according to any one of claims 1 to 3, wherein a plurality of said unit cells arranged side by side are provided between said adjacent slits in said source wiring.

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