KR20200011367A - Vertical field-effect transistor(VFET) devices including latches having cross-couple structure - Google Patents

Abstract

Provided is an integrated circuit (IC) device including a vertical field effect transistor (VFET) with increased reliability. According to the present invention, the IC device comprises: a substrate including first and second regions and a boundary region between the first and second regions, wherein the first and second regions are spaced apart from each other in a first horizontal direction parallel to the upper surface of the substrate; a first latch disposed on the first region of the substrate and including first to fourth VFETs; a second latch disposed on the second region of the substrate and including fifth to eighth VFETs, wherein the first and seventh VFETs are arranged in the first horizontal direction; and a conductive layer extended in the first horizontal direction, crossing the boundary region, and including a first portion including a gate electrode of the first VFET and a second portion including a gate electrode of the seventh VFET.

Description

Vertical field-effect transistor (VFET) devices including latches having cross-couple structure}

FIELD OF THE INVENTION The present invention relates generally to the field of electronic devices, and more particularly to vertical field effect transistor (VFET) devices.

Vertical field effect transistor (VFET) devices have been studied due to the high scalability of vertical field effect transistors. In addition, the interconnection between vertical field effect transistors may be simpler than the interconnection between planar transistors.

An object of the present invention is to provide an integrated circuit device including a vertical field effect transistor with improved reliability.

The problem to be solved by the present invention is not limited to the above-mentioned problem, another task that is not mentioned will be clearly understood by those skilled in the art from the following description.

An integrated circuit device according to some embodiments of the present invention for solving the above problems is a substrate including a first region, a second region, and a boundary region between the first region and the second region. And the second regions are spaced apart from each other in a first horizontal direction parallel to the upper surface of the substrate, and are disposed on the first region of the substrate, the first vertical field effect transistor, the second vertical field effect transistor, and the third vertical field effect transistor. And a first latch including a fourth vertical field effect transistor, disposed on a second region of the substrate, and having a fifth vertical field effect transistor, a sixth vertical field effect transistor, a seventh vertical field effect transistor, and an eighth vertical field effect. With a second latch comprising a transistor, the first vertical field effect transistor and the seventh vertical field effect transistor are arranged in a first horizontal direction, and extend in the first horizontal direction. , It includes a first conductive layer including a second portion including a first portion and a gate electrode 7 of the vertical field effect transistor crossing the boundary area, and includes a first gate electrode of the vertical field effect transistor.

An integrated circuit device according to another exemplary embodiment of the present invention for solving the above problems is a substrate including a first region, a second region, and a boundary region between the first region and the second region. The region and the second region are spaced apart from each other in a first horizontal direction parallel to the top surface of the substrate, and are disposed on the first region of the substrate, the first vertical field effect transistor, the second vertical field effect transistor, and the third vertical field effect. A first latch comprising a transistor and a fourth vertical field effect transistor, and a fifth vertical field effect transistor, a sixth vertical field effect transistor, a seventh vertical field effect transistor, and an eighth vertical disposed on a second region of the substrate; A second latch comprising a field effect transistor, the second vertical field effect transistor, the third vertical field effect transistor, the fifth vertical field effect transistor, and the eighth vertical. The field effect transistor is arranged along the first horizontal direction, and the second vertical field effect transistor, the third vertical field effect transistor, the fifth vertical field effect transistor, and the eighth vertical field effect transistor are arranged in the second vertical field effect transistor, the third The gate signal applied to the gate electrode of each of the vertical field effect transistor, the fifth vertical field effect transistor, and the eighth vertical field effect transistor is shared.

An integrated circuit device according to another exemplary embodiment of the present invention for solving the above problems is a substrate including a first region, a second region, and a boundary region between the first region and the second region. The first region and the second region are spaced apart from each other in a first horizontal direction parallel to the top surface of the substrate, and the first region of the substrate comprises an NMOS region and a PMOS region spaced in the first horizontal direction from the NMOS region, A first latch disposed on a first region and comprising a first vertical field effect transistor and a third vertical field effect transistor on a PMOS region, and a second vertical field effect transistor and a fourth vertical field effect transistor on an NMOS region, the first latch comprising: The first vertical field effect transistor includes a first channel region and a first upper source / drain sequentially stacked on the substrate, and the second vertical field effect transistor is sequentially disposed on the substrate. A third vertical field effect transistor comprising a stacked second channel region and a second upper source / drain, the third vertical field effect transistor comprising a third channel region and a third upper source / drain sequentially stacked on a substrate, and a fourth vertical electric field The effect transistor includes a fourth channel region and a fourth upper source / drain sequentially stacked on the substrate, and is disposed on the second region of the substrate, and includes a fifth vertical field effect transistor, a sixth vertical field effect transistor, A second latch comprising a seventh vertical field effect transistor and an eighth vertical field effect transistor, and an upper side in contact with the first upper source / drain, the second upper source / drain, the third upper source / drain, and the fourth upper source / drain Include source / drain contacts.

1 is a circuit diagram of an apparatus including a master latch and a slave latch.
FIG. 2 is a diagram for describing a transistor including a master latch and a slave latch shown in FIG. 1 according to some embodiments of the present disclosure.
3A, 3B, 3C and 3D are layout diagrams of an apparatus according to some embodiments of the invention.
4 is a layout diagram showing cut lines in a sectional view.
5A, 5B, and 5C are cross-sectional views taken along lines AA ′, BB ′, and CC ′ of FIG. 4, respectively, according to some embodiments of the present disclosure.
6A, 6B, 6C, 6D, 6E, 6F, 6G, and 6H illustrate lines 1-1 ', 2-2', and 3-3 of FIG. 4 in accordance with some embodiments of the present invention. Sections cut along the lines '4-4', 5-5 ', 6-6', 7-7 'and 8-8' respectively.

Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings. Many other forms and embodiments are possible without departing from the spirit and teachings of the invention, and therefore the invention should not be construed as limited to the illustrative embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough, and will convey the scope of the invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements.

Exemplary embodiments of the technical idea of the present invention are described below with reference to sectional views which are schematic diagrams of an intermediate structure of an ideal embodiment and an exemplary embodiment. As such, deformations from the shape of the illustration as a result, such as for example manufacturing techniques and / or tolerances, should be expected. Thus, exemplary embodiments of the inventive concept should not be construed as limited to the specific shapes illustrated herein, but include, for example, variations in shape resulting from manufacturing processes.

1 is a circuit diagram of an apparatus including a master latch and a slave latch. Each of the master latch and slave latch has a cross-couple structure. The device shown in FIG. 1 may be part of a flip-flop circuit. In some embodiments, the circuit shown in FIG. 1 may be part of a scan flip-flop circuit, but the inventive concept is not limited thereto. The apparatus shown in FIG. 1 may be part of different types of flip-flop circuits.

Referring to FIG. 1, the first transistor TR1, the second transistor TR2, the third transistor TR3, and the fourth transistor TR4 of the master latch form a first cross-couple structure, and The fifth transistor TR5, the sixth transistor TR6, the seventh transistor TR7, and the eighth transistor TR8 form a second cross-couple structure. Type and number of transistors between any one of first transistor TR1, third transistor TR3, fifth transistor TR5, and seventh transistor TR7 and VDD, and second transistor TR2, fourth The type and number of transistors between any one of transistor TR4, sixth transistor TR6 and eighth transistor TR8 and VSS is a type of flip-flop circuit including a master latch and a slave latch. Can change. In addition, the first feedback loop FL1 and the second feedback loop FL2 may include various types and numbers of transistors according to the type of the flip-flop circuit.

In some embodiments, each of the first, third, fifth, and seventh transistors TR1, TR3, TR5, TR7 may be a P-type transistor, and the second, fourth, sixth, and eighth transistors TR2, TR4, TR6, and TR8 may be N-type transistors as shown in FIG. 1.

Referring to FIG. 1, the clock signal CLK is applied to a plurality of transistors (for example, the second transistor TR2, the third transistor TR3, the fifth transistor TR5, and the eighth transistor TR8). The inverted clock signal / CLK may include a plurality of transistors (for example, a first transistor TR1, a fourth transistor TR4, a sixth transistor TR6, and a seventh transistor TR7). Can be applied to)). In some embodiments, the clock signal CLK may be applied to the first transistor TR1, the fourth transistor TR4, the sixth transistor TR6, and the seventh transistor TR7, and the inverted clock signal (/ The CLK may be applied to a plurality of transistors (for example, the second transistor TR2, the third transistor TR3, the sixth transistor TR5, and the eighth transistor TR8).

Since each of the clock signal CLK and the inverted clock signal / CLK is shared by a plurality of transistors, a single conductive line to which one of the clock signal CLK and the inverted clock signal / CLK is applied (for example, For example, the conductive layer 220 of Fig. 3B may be shared by a plurality of transistors, since the total number of conductive lines included in the device can be reduced by sharing one conductive line with the plurality of transistors. A single conductive line can simplify the layout of the device and reduce the amount of conductive material used to manufacture the device.

2 illustrates a transistor including the master latch and slave latch shown in FIG. 1 in accordance with some embodiments of the present invention. The master latch including the first, second, third and fourth transistors TR1, TR2, TR3, TR4 may be provided in the first latch region (ie, the master latch region), and the fifth, sixth, The slave latch including the seventh and eighth transistors TR5, TR6, TR7, and TR8 may be provided on the second latch area (ie, the slave latch area). In order to provide a common conductive line to the plurality of transistors, the master latch region and the slave latch region can be arranged along a first horizontal direction (eg, the X direction of FIG. 2), the master latch and slave latches being shown in FIG. It is possible to form a double height structure as shown in 2. It will be understood that the term "height" in "double height structure" does not mean that the master latch region and the slave latch region are stacked in the vertical direction. The master latch area and the slave latch area may be spaced apart in the first horizontal direction X, and a boundary area may be provided between the master latch area and the slave latch area.

"A component and B component arranged along the X direction" (or similar language) may mean that the A component and the B component are spaced apart from each other in the X direction and aligned along the X direction.

The master latch region may include a first NMOS region NR1 and a first PMOS region PR1 between the first NMOS region NR1 and a boundary region. The P-type transistors of the master latch (ie, the first transistor TR1 and the third transistor TR3) may be provided on the first PMOS region PR1, and the master latch (ie, the second transistor TR2 and An N-type transistor of the fourth transistor TR4 may be provided on the first NMOS region NR1. As illustrated in FIG. 2, the first transistor TR1 and the third transistor TR3 may be arranged to be spaced apart from each other in a second horizontal direction (eg, in the Y direction in FIG. The second transistor TR2 and the fourth transistor TR4 may be arranged to be spaced apart from each other in the second horizontal direction Y. In some embodiments, the first horizontal direction X is perpendicular to the second horizontal direction Y.

The slave latch region may include a second NMOS region NR2 and a second PMOS region PR2 between the second NMOS region NR2 and the boundary region. The P-type transistors of the slave latches (i.e., the fifth transistor TR5 and the seventh transistor TR7) may be provided on the second PMOS region PR2, and the slave latches (i.e., the sixth transistor TR6) and An N-type transistor of the eighth transistor TR8 may be provided on the second NMOS region NR2.

Referring to FIG. 2, the first transistor TR1 of the master latch to which the inverted clock signal / CLK is applied and the seventh transistor TR7 of the slave latch to which the inverted clock signal / CLK is applied are the first transistor. They may be arranged on the imaginary line IL_1 and may be spaced apart from each other in the first horizontal direction X. FIG. The first transistor TR1 and the seventh transistor TR7 may be provided at positions where the first virtual line IL_1 crosses the first PMOS region PR1 and the second PMOS region PR2, respectively. Therefore, a single conductive layer (eg, the conductive layer 220 of FIG. 3B) receiving the clock signal / CLK extending in the first horizontal direction X and inverted may include the first transistor TR1 and the seventh. It may be shared by transistor TR7. The first transistor TR1 and the seventh transistor TR7 may share a gate signal (eg, the inverted clock signal / CLK).

The second and third transistors TR2 and TR3 of the master latch to which the clock signal CLK is applied and the fifth and eighth transistors TR5 and TR8 of the slave latch to which the clock signal CLK is applied are the second virtual. May be arranged on the line IL_2 and spaced apart from each other in the first horizontal direction X. FIG. In the second, third, fifth and eighth transistors TR2, TR3, TR5, and TR8, the second virtual line IL_2 has a first NMOS region NR1, a first PMOS region PR1, and a second PMOS. It may be provided at positions crossing the region PR2 and the second NMOS region NR2, respectively. Accordingly, a single conductive layer (eg, the conductive layer 220 of FIG. 3B) extending in the first horizontal direction X and receiving the clock signal CLK includes second, third, fifth and eighth transistors. May be shared by (TR2, TR3, TR5, TR8). The second, third, fifth, and eighth transistors TR2, TR3, TR5, and TR8 may share a gate signal (eg, a clock signal CLK).

Thus, the double height structure allows transistors included in different latches (i.e., master and slave latches) to share a conductive layer to which either the clock signal CLK or the inverted clock signal / CLK is applied, The gate signal can be shared.

As shown in FIG. 2, the fourth transistor TR4 of the master latch to which the inverted clock signal / CLK is applied and the sixth transistor TR6 of the slave latch to which the inverted clock signal / CLK is applied They may be arranged on the third virtual line IL_3 and may be spaced apart from each other in the first horizontal direction X. The fourth transistor TR4 and the sixth transistor TR6 may be provided at positions where the third virtual line IL_3 crosses the first NMOS region NR1 and the second NMOS region NR2, respectively.

In some embodiments, the device may include dummy regions DR without a transistor. As shown in FIG. 2, the apparatus includes two dummy regions DR at respective positions where the first virtual line IL_1 crosses the first NMOS region NR1 and the second NMOS region NR2. can do. In addition, as shown in FIG. 2, the third virtual line IL_3 includes two dummy regions DR at respective positions crossing the first PMOS region PR1 and the second PMOS region PR2. can do.

In some embodiments, as shown in FIG. 2, each of the first, second and third virtual lines IL_1, IL_2, IL_3 may extend in the first horizontal direction X, and They may be spaced apart from each other in a second horizontal direction Y that is parallel and perpendicular to the first horizontal direction X. The second virtual line IL_2 may be formed between the first virtual line IL_1 and the third virtual line IL_3. It will be appreciated that each of the first, second and third virtual lines IL_1, IL_2, IL_3 may correspond to the first, second and third columns.

It will be appreciated that using vertical field effect transistors (VFETs) may further simplify the layout of the device. The vertical field effect transistor includes a vertical channel that projects from the substrate in a vertical direction (eg, a direction perpendicular to the top or bottom surface of the substrate) and an upper source / drain overlying the vertical channel. Since the top source / drain is the top of the vertical field effect transistor, the top source / drain of the vertical field effect transistor and the top source / drain of the adjacent vertical field effect transistor can be connected via a horizontal conductive pattern on the top source / drain.

3A, 3B, 3C and 3D are layout diagrams of an apparatus according to some embodiments of the invention. For simplicity of the drawings, FIGS. 3A-3D show some but not all components of the device.

Referring to FIG. 3A, a substrate (eg, the substrate 100 of FIG. 5A) may include a master latch region, a slave latch region spaced apart from the master latch region in a first horizontal direction X, and a master latch region and a slave latch region. It may include a boundary area between them. The first horizontal direction X may be parallel to the top or bottom surface of the substrate 100. Each transistor of the master latch region and the slave latch region may be a vertical field effect transistor and may include a vertical channel. The first to eighth transistors TR1, TR2, TR3, TR4, TR5, TR6, TR7, and TR8 may include a first vertical channel VC1, a second vertical channel VC2, a third vertical channel VC3, and a fourth The vertical channel VC4, the fifth vertical channel VC5, the sixth vertical channel VC6, the seventh vertical channel VC7, and the eighth vertical channel VC8 may be included.

The lower source / drain 140 may surround each of the transistors, and the isolation region 120 may be provided between the lower source / drain 140. The lower source / drain contact 160 may extend in the longitudinal direction in the second horizontal direction (Y). In some embodiments, the second horizontal direction Y may be parallel to the top or bottom surface of the substrate 100 and may be perpendicular to the first horizontal direction X.

Referring to FIG. 3B, each of the conductive layers 220 may extend in the longitudinal direction in the first horizontal direction X. FIG. One of the conductive layers 220 may be shared by the first and seventh vertical channels VC1 and VC7. The conductive layer 220 shared by the first and seventh vertical channels VC1 and VC7 may include a portion surrounding the first vertical channel VC1 and may constitute a gate electrode of the first transistor TR1. And a portion surrounding the seventh vertical channel VC7 and may form a gate electrode of the seventh transistor TR7.

In some embodiments, one of the conductive layers 220 may be shared by the second, third, fifth and eighth vertical channels VC2, VC3, VC5, VC8. The conductive layer 220 shared by the second, third, fifth, and eighth vertical channels VC2, VC3, VC5, and VC8 includes the second, third, fifth, and eighth vertical channels VC2, VC3. , VC5, VC8) may comprise a portion surrounding each. Each of the conductive layers 220 may surround one of the second, third, fifth, and eighth transistors TR2, TR3, TR5, and TR8. The two conductive layers 220 may surround the fourth and sixth vertical channels VC4 and VC6, respectively, and may configure the gate electrodes of the fourth transistor TR4 and the sixth transistor TR6, respectively.

The conductive layer 220 shared by the first and seventh vertical channels VC1 and VC7 extends in the first horizontal direction X from a portion surrounding the seventh vertical channel VC7 and is positioned on the slave latch area. The pad region 220P may be disposed on the pad region 220P. The conductive layer 220 shared by the second, third, fifth, and eighth vertical channels VC2, VC3, VC5, and VC8 may include a pad region 220P disposed on a boundary region. The gate contacts 240 may overlap and be connected to the pad region 220P to electrically connect the conductive layer 220 to each of the conductive lines (eg, 340 of FIG. 3C). The gate contact 240 may overlap and be connected to the conductive layer 220 surrounding the fourth and sixth vertical channels VC4 and VC6, as shown in FIG. 3B.

Referring to FIG. 3C, in some embodiments, via contact 320 may be provided on each of gate contacts 240. Each of the via contacts 320 may connect one of the gate contacts 240 to a corresponding conductive line 340.

Referring to FIG. 3D, an upper source / drain contact 260 may be provided that overlaps the first, second, third, and fourth vertical channels VC1, VC2, VC3, and VC4. An upper source / drain contact 260 may be provided that overlaps with the sixth, seventh, and eighth vertical channels VC5, VC6, VC7, VC8. On the master latch region, via contact 320 may be provided on top source / drain contact 260 to connect top source / drain contact 260 to conductive interconnect 340. On the slave latch region, a single via contact 320 may be provided on the top source / drain contact 260 to connect the top source / drain contact 260 to the conductive wire 340.

4 is a layout diagram showing cut lines in a sectional view. 5A, 5B, and 5C are cross-sectional views taken along the lines A-A ', B-B', and C-C ', respectively, of FIG. 4 according to some embodiments of the present invention. 6A, 6B, 6C, 6D, 6E, 6F, 6G, and 6H illustrate lines 1-1 ', 2-2', and 3-3 of FIG. 4 in accordance with some embodiments of the present invention. Sections cut along the lines '4-4', 5-5 ', 6-6', 7-7 'and 8-8' respectively.

It can be seen that the cross section taken along line 9-9 'is the same as or similar to the cross section taken along line 1-1'.

Referring to FIG. 5A, the substrate 100 may include a master latch region, a slave latch region, and a boundary region between the master latch region and the slave latch region. The master latch region may be spaced apart from the slave latch region in the first horizontal direction X. The master latch may be provided in the master latch area of the substrate 100, and the slave latch may be provided in the slave latch area of the substrate 100. The first transistor TR1 includes a first vertical channel VC1 protruding from the top surface of the substrate 100 and an upper source / drain 150 on the first vertical channel VC1. The lower source / drain 140 may be disposed on the substrate 100 and may surround the lower portion of the first vertical channel VC1. In some embodiments, bottom source / drain 140 may be formed by an epitaxial growth process, and bottom source / drain 140 may be referred to as a bottom epitaxial layer. The seventh vertical field effect transistor may have a structure similar to the first vertical field effect transistor, as shown in FIG. 5A.

The isolation region 120 may be provided between adjacent lower source / drain 140 to electrically insulate the lower source / drain 140 from each other. In some embodiments, isolation region 120 may be formed by a shallow trench isolation process, and isolation region 120 may be referred to as an STI region.

The conductive layer 220 may surround the vertical channel VC1 and extend toward the seventh vertical channel VC7. As shown in FIG. 5A, the conductive layer 220 may cross (eg, continuously cross and extend) beyond the boundary area of the substrate 100. The spacer 280 may be disposed on the lower surface and / or the upper surface of the conductive layer 220 to electrically insulate the conductive layer 220 from the lower source / drain 140. As illustrated in FIG. 5A, the spacer 280 may expose the pad region 220P of the conductive layer 220. The spacer 280 may include an insulating material (eg, silicon oxide).

The upper source / drain contact 260 may contact the upper source / drain 150 of each of the first vertical field effect transistor and the seventh vertical field effect transistor, as illustrated in FIG. 5A. Referring again to FIG. 3D, the upper source / drain contacts 260 of the master latches may contact the upper source / drain 150 of the first, second, third, and fourth transistors TR1, TR2, TR3, and TR4. The top source / drain contact 260 of the slave latch may be in contact with the top source / drain 150 of the fifth, sixth, seventh, and eighth transistors TR5, TR6, TR7, and TR8 (FIG. 6b and 6d). In some embodiments, the top source / drain contact 260 of the master latch is via a via contact 320 disposed between the top source / drain contact 260 and the conductive wiring 340, as shown in FIG. 5A. It may be electrically connected to the conductive wire 340.

The gate contact 240 may be disposed on the insulating layer 420 and may extend in a vertical direction (eg, Z direction) perpendicular to the top surface of the substrate 100. Signals (eg, clock signals and inverted clock signals) may be applied to the conductive layer 220 through the gate contact 240. The gate contact 240 may be electrically connected to the conductive wire 340 through the via contact 320 between the gate contact 240 and the conductive wire 340, as shown in FIG. 5A. Lower source / drain contacts 160 may be provided on isolation region 120.

3B and 5B, the conductive layer 220 may extend in the longitudinal direction in the first horizontal direction X and may cross the boundary region of the substrate 100. The conductive layer 220 may include a portion surrounding the second, third, fifth and eighth vertical channels VC2, VC3, VC5, and VC8, as shown in FIG. 5B, and the conductive layer 220 Each surrounding portion of) may constitute a gate (eg, a gate electrode) of one of the second, third, fifth and eighth transistors TR2, TR3, TR5, TR8. The conductive layer 220 may include a pad region 220P on a boundary region of the substrate 100 to which the gate contact 240 is connected. The gate contact 240 may extend in the vertical direction Z and may be electrically connected to the conductive wire 340 through the via contact 320 between the gate contact 240 and the conductive wire 340.

Referring to FIG. 5B, the upper source / drain 150 of the second, third, fifth, and eighth transistors TR2, TR3, TR5, and TR8 includes the second, third, fifth, and eighth vertical channels ( VC2, VC3, VC5, VC8) may be provided respectively. In some embodiments, the top source / drain contact 260 on the master latch region may be in contact with the top source / drain 150 of the second and third transistors TR2 and TR3 and may be in contact with the top source / drain 150 on the slave latch region. The contact 260 may be in contact with the upper source / drain 150 of the fifth and eighth transistors TR5 and TR8. The top source / drain contact 260 on the slave latch region may be electrically connected to the conductive line 340 through the via contact 320 between the top source / drain contact 260 and the conductive line 340.

Referring to FIG. 5C, the conductive layers 220 may be spaced apart from each other in the first horizontal direction X and may surround the fourth vertical channel VC4 and the sixth vertical channel VC6, respectively. The conductive layers 220 may be electrically connected to each other through the gate contacts 240, the via contacts 320, and the conductive lines 340. The spacer 280 may not be provided on the portion of the conductive layer 220 to which the gate contact 240 is connected.

5A and 5C, the dummy region DR is a portion of the substrate 100 where no vertical channel is formed.

Referring to FIG. 6A, the lower source / drain contact 160 may be provided on the isolation region 120 and may extend in the longitudinal direction in the second horizontal direction Y.

Referring to FIG. 6B, the sixth vertical channel VC6 and the eighth vertical channel VC8 may be spaced apart in the second horizontal direction Y, and the upper source / drain 150 may include the sixth vertical channel VC6. And an eighth vertical channel VC8. In some embodiments, the top source / drain contacts 260 may be in contact with the top source / drain 150 of the sixth and eighth transistors TR6 and TR8.

Referring to FIG. 6C, the conductive layers 220 may be provided on the isolation region 120 extending between the NMOS region and the PMOS region of the slave latch region. The pad region 220P of the conductive layer 220 may be electrically connected to the conductive wire 340 through the gate contact 240 and the via contact 320. The upper source / drain contact 260 may be electrically connected to the conductive line 340 through the gate contact 240 and the via contact 320. The conductive layer 220 may be electrically connected to the conductive line 340 through the gate contact 240 and the via contact 320.

Referring to FIG. 6D, the fifth vertical channel VC5 and the seventh vertical channel VC7 may be spaced apart in the second horizontal direction Y, and the upper source / drain 150 may include the fifth and seventh vertical channels. (VC5, VC7) may be provided on each. In some embodiments, the top source / drain contacts 260 may be in contact with the top source / drain 150 of the fifth and seventh transistors TR5 and TR7.

Referring to FIG. 6E, the conductive layers 220 may be provided on the isolation region 120 on the boundary region. The pad region 220P of the conductive layer 220 in the boundary region may be electrically connected to the conductive line 340 through the gate contact 240 and the via contact 320.

Referring to FIG. 6F, the first vertical channel VC1 and the third vertical channel VC3 may be spaced apart in the second horizontal direction Y, and the upper source / drain 150 may include the first vertical channel VC1. And the third vertical channel VC3. In some embodiments, the top source / drain contacts 260 may be in contact with the top source / drain 150 of the first and third transistors TR1 and TR3. The via contact 320 may be provided on the upper source / drain contact 260 to connect the upper source / drain contact 260 to the conductive line 340.

Referring to FIG. 6G, the conductive layer 220 may be provided on the isolation region 120 extending between the first NMOS region NR1 and the first PMOS region PR1 of the master latch region. The conductive layer 220 extending around the fourth vertical channel VC4 may be electrically connected to the conductive line 340 through the gate contact 240 and the via contact 320.

Referring to FIG. 6H, the second vertical channel VC2 and the fourth vertical channel VC4 may be spaced apart in the second horizontal direction Y, and the upper source / drain 150 may include the second vertical channel VC2. And the fourth vertical channel VC4. In some embodiments, the top source / drain contacts 260 may be in contact with the top source / drain 150 of the second and fourth transistors TR2 and TR4.

Unless otherwise defined, all terms used in the present specification (including technical and scientific terms) may be used in a sense that can be commonly understood by those skilled in the art. It is also to be understood that terms such as those defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the related art and will not be construed in an ideal or overly formal sense. Except where explicitly defined.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the spirit of the invention. In the context of describing the present invention (particularly in the context of the following claims), the terms “a”, “an”, “the” and similar terms are used in the singular and the plural unless otherwise specified or clearly contradicted by the context. All are included. The terms "comprising", "having", "including" and "containing" should be interpreted as not excluding an existence (ie, "including but not limited to"). Not ".

As used herein, "component A vertically overlapping component B" (or similar language) will be understood to mean that there is a vertical line across both component A and component B.

Terms such as first, second, etc. may be used herein to describe various components, but it will be understood that these components should not be limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component may be referred to as a second component without departing from the spirit of the present invention.

The technical spirit of the present invention described above should be considered as illustrative and not restrictive, and the appended claims are intended to cover all such modifications, improvements and other embodiments that fall within the spirit and scope of the present invention. Thus, to the maximum extent permitted by law, the scope is determined by the broadest permissible interpretation of the following claims and their equivalents, and should not be limited by the foregoing detailed description.

TR1 to TR8: first to eighth transistors
VC1 to VC8: first to eighth vertical channels
100: substrate 120: separation region
140: lower source / drain 150: upper source / drain
160: lower source / drain contact 220: conductive layer
240: gate contact 260: top source / drain contact
280: spacer 320: via contact
340: conductive wiring 420: insulating layer

Claims (20)

A substrate comprising a first region, a second region, and a boundary region between the first region and the second region, wherein the first region and the second region are parallel to an upper surface of the substrate. Spaced apart from each other in the horizontal direction;
A first latch disposed on the first region of the substrate, the first latch including a first vertical field effect transistor, a second vertical field effect transistor, a third vertical field effect transistor, and a fourth vertical field effect transistor;
A second latch disposed on the second region of the substrate, the second latch including a fifth vertical field effect transistor, a sixth vertical field effect transistor, a seventh vertical field effect transistor, and an eighth vertical field effect transistor; A vertical field effect transistor and the seventh vertical field effect transistor are arranged in the first horizontal direction; And
A first portion extending in the first horizontal direction and intersecting the boundary region, the first portion including a gate electrode of the first vertical field effect transistor and a second portion including a gate electrode of the seventh vertical field effect transistor; Integrated circuit device comprising a conductive layer comprising. The method of claim 1,
Wherein the conductive layer comprises receiving a clock signal or an inverted clock signal. The method of claim 2,
The conductive layer includes a pad region protruding from the second portion of the conductive layer and disposed on the second region of the substrate,
And a gate contact extending in a vertical direction perpendicular to an upper surface of the substrate and connected to the pad region of the conductive layer. The method of claim 3, wherein
Each of the first vertical field effect transistor and the seventh vertical field effect transistor is a P-type vertical field effect transistor,
And the conductive layer receives the inverted clock signal. The method of claim 2,
The conductive layer includes a pad region on the boundary region,
And a gate contact extending in a vertical direction perpendicular to an upper surface of the substrate and connected to the pad region of the conductive layer. The method of claim 1,
The first vertical field effect transistor includes a first channel region and a first upper source / drain sequentially stacked on the substrate, and the second vertical field effect transistor comprises a second channel sequentially stacked on the substrate. The third vertical field effect transistor comprising a region and a second upper source / drain, wherein the third vertical field effect transistor comprises a third channel region and a third upper source / drain sequentially stacked on the substrate, and the fourth vertical field effect transistor A fourth channel region and a fourth upper source / drain sequentially stacked on the substrate,
And an upper source / drain contact in contact with the first upper source / drain, the second upper source / drain, the third upper source / drain, and the fourth upper source / drain. The method of claim 6,
The first region of the substrate includes an NMOS region and a PMOS region between the NMOS region and the boundary region,
The first vertical field effect transistor and the third vertical field effect transistor are p-type vertical field effect transistors, and the first vertical field effect transistor and the third vertical field effect transistor are parallel to an upper surface of the substrate on the PMOS region. And in a second horizontal direction perpendicular to the first horizontal direction,
Each of the second vertical field effect transistor and the fourth vertical field effect transistor is an N-type vertical field effect transistor, and the second vertical field effect transistor and the fourth vertical field effect transistor are each in the second horizontal direction on the NMOS region. Integrated circuit device arranged. The method of claim 7, wherein
And the second vertical field effect transistor and the third vertical field effect transistor are arranged along the first horizontal direction. A substrate comprising a first region, a second region, and a boundary region between the first region and the second region, wherein the first region and the second region are parallel to an upper surface of the substrate. Spaced apart from each other in the horizontal direction;
A first latch disposed on the first region of the substrate, the first latch including a first vertical field effect transistor, a second vertical field effect transistor, a third vertical field effect transistor, and a fourth vertical field effect transistor; And
A second latch disposed on the second region of the substrate, the second latch including a fifth vertical field effect transistor, a sixth vertical field effect transistor, a seventh vertical field effect transistor, and an eighth vertical field effect transistor;
The second vertical field effect transistor, the third vertical field effect transistor, the fifth vertical field effect transistor, and the eighth vertical field effect transistor are arranged along the first horizontal direction,
The second vertical field effect transistor, the third vertical field effect transistor, the fifth vertical field effect transistor, and the eighth vertical field effect transistor may include a second vertical field effect transistor, the third vertical field effect transistor, and a fifth vertical field. And a gate signal applied to a gate electrode of each of the effect transistor and the eighth vertical field effect transistor. The method of claim 9,
And the gate signal is a clock signal or an inverted clock signal. The method of claim 9,
A conductive layer extending in the first horizontal direction and intersecting the boundary region;
A first portion of the conductive layer includes the gate electrode of a second vertical field effect transistor, a second portion of the conductive layer includes the gate electrode of the third vertical field effect transistor, Three portions include the gate electrode of the fifth vertical field effect transistor, and a fourth portion of the conductive layer includes the gate electrode of the eighth vertical field effect transistor. The method of claim 11,
The conductive layer includes a pad region on the boundary region,
And a gate contact extending in a vertical direction perpendicular to an upper surface of the substrate and connected to the pad region of the conductive layer. The method of claim 11,
The first vertical field effect transistor includes a first channel region and a first upper source / drain sequentially stacked on the substrate, and the second vertical field effect transistor comprises a second channel sequentially stacked on the substrate. The third vertical field effect transistor comprising a region and a second upper source / drain, wherein the third vertical field effect transistor comprises a third channel region and a third upper source / drain sequentially stacked on the substrate, and the fourth vertical field effect transistor A fourth channel region and a fourth upper source / drain sequentially stacked on the substrate,
And an upper source / drain contact in contact with the first upper source / drain, the second upper source / drain, the third upper source / drain, and the fourth upper source / drain. The method of claim 13,
And the first top source / drain is disposed between the substrate and the top source / drain contact. The method of claim 13,
The first region of the substrate includes an NMOS region and a PMOS region between the NMOS region and the boundary region,
The first vertical field effect transistor and the third vertical field effect transistor are arranged in a second horizontal direction parallel to the top surface of the substrate and perpendicular to the first horizontal direction on the PMOS region,
And the second vertical field effect transistor and the fourth vertical field effect transistor are arranged in the second horizontal direction on the NMOS region. A substrate comprising a first region, a second region, and a boundary region between the first region and the second region, wherein the first region and the second region are parallel to an upper surface of the substrate. Spaced apart from each other in a horizontal direction, the first region of the substrate including an NMOS region and a PMOS region spaced apart from the NMOS region in the first horizontal direction;
A first vertical field effect transistor and a third vertical field effect transistor on the PMOS region, and a second vertical field effect transistor and a fourth vertical field effect transistor on the NMOS region, the first vertical field effect transistor being disposed on the first region of the substrate; A first latch, wherein the first vertical field effect transistor includes a first channel region and a first upper source / drain sequentially stacked on the substrate, and the second vertical field effect transistor is sequentially disposed on the substrate. A second channel region and a second upper source / drain stacked on the substrate, wherein the third vertical field effect transistor includes a third channel region and a third upper source / drain sequentially stacked on the substrate, A fourth vertical field effect transistor includes a fourth channel region and a fourth upper source / drain sequentially stacked on the substrate. And;
A second latch disposed on the second region of the substrate, the second latch including a fifth vertical field effect transistor, a sixth vertical field effect transistor, a seventh vertical field effect transistor, and an eighth vertical field effect transistor; And
An upper source / drain contact in contact with the first upper source / drain, the second upper source / drain, the third upper source / drain, and the fourth upper source / drain. The method of claim 16,
The first vertical field effect transistor is disposed at a first position where a first imaginary line crosses the PMOS region, and the second vertical field effect transistor is located at a second position where a second imaginary line crosses the NMOS region. And the third vertical field effect transistor is disposed at a third position where the second virtual line intersects the PMOS region, and the fourth vertical field effect transistor is disposed at a third virtual line with the NMOS region. Placed in the intersecting fourth position,
Each of the first to third virtual lines extends in the first horizontal direction, and the first to third virtual lines extend in a second horizontal direction parallel to the top surface of the substrate and perpendicular to the first horizontal direction. Spaced apart from each other,
And the second virtual line is formed between the first virtual line and the third virtual line. The method of claim 17,
Further comprising a conductive layer extending in the first horizontal direction,
A first portion of the conductive layer comprises a gate electrode of the second vertical field effect transistor, and a second portion of the conductive layer comprises a gate electrode of the third vertical field effect transistor. The method of claim 18,
Wherein the conductive layer comprises receiving a clock signal or an inverted clock signal. The method of claim 16,
The second vertical field effect transistor, the third vertical field effect transistor, the fifth vertical field effect transistor, and the eighth vertical field effect transistor are arranged along the first horizontal direction,
Further comprising a conductive layer extending in the first horizontal direction,
A first portion of the conductive layer includes a gate electrode of the second vertical field effect transistor, a second portion of the conductive layer includes a gate electrode of the third vertical field effect transistor, and a third of the conductive layer A portion comprising a gate electrode of the fifth vertical field effect transistor, and a fourth portion of the conductive layer comprises a gate electrode of the eighth vertical field effect transistor.

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