JP2009170746A - Semiconductor apparatus and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a HEMT semiconductor apparatus of a normally-off type having easy productivity, ultrahigh frequency, high speed performance, and low noise property, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor apparatus includes: a first layer 130 made of first nitride semiconductor; a second layer 140 provided thereon and made of nitride semiconductor; and a drain electrode 170 provided on any one of the second layer 140 in a second region 260 not parallel to a gate electrode 150 provided on the second layer 140 in a first region 250 parallel to the c-axis 210 of the first layer 130 in an interface of the first layer 130 and the second layer 140 and to the c-axis 210, the second layer 140 in a third region 270 not parallel to the c-axis 210, of a source electrode 160 and the interface of the first layer 130 and the second layer 140, and an end portion of the third region 270. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  A high electron mobility transistor (HEMT) uses, for example, a high mobility characteristic of a two-dimensional electron gas due to a high polarization effect at an AlGaN / GaN hetero interface, so that it has a very high frequency, a high speed characteristic, a low Has noise characteristics. However, a normal HEMT is a normally-on type in which a current flows even when there is no gate voltage. From the viewpoints of power consumption and circuit design, it is desired to realize a normally-off HEMT.

As one of the methods for manufacturing a normally-off type HEMT, a method of reducing the thickness of the AlGaN layer under the gate electrode by a recess has been proposed. However, in this method, it is necessary to leave the AlGaN layer with a layer thickness on the order of several nanometers, and since the remaining amount is very sensitive to the operating characteristics, it is difficult to manufacture and is not practical.
Patent Document 1 proposes a technique for obtaining a normally-off HEMT by a planar structure using a substrate in which the c-axis direction of the crystal is parallel to the main surface of the substrate. However, in this method having a planar structure, the high mobility characteristics of the AlGaN / GaN heterojunction cannot be fully utilized, and it is necessary to dope impurities, and the advantages of ultra-high frequency, high speed characteristics, and low noise can be enjoyed. There wasn't.

Further, in the conventional structure, there is a problem that the warp of the wafer becomes large due to the film stress of the AlGaN / GaN epitaxial film, which makes it difficult to manufacture.
JP 2007-80855 A

  An object of the present invention is to provide a normally-off HEMT semiconductor device that is easy to manufacture, has ultra-high frequency, high-speed characteristics, and low noise, and a method for manufacturing the same.

  According to one aspect of the present invention, a first layer made of a first nitride semiconductor and a second layer that is provided on the first layer and has a larger band gap than the first nitride semiconductor. In a first region substantially parallel to the c-axis of the first layer, of the second layer made of the nitride semiconductor and the interface between the first layer and the second layer A second region substantially non-parallel to the c-axis among the interface between the gate electrode provided on the second layer and the first layer and the second layer. A source electrode provided on at least one of the second layer and an end of the second region, and the interface between the first layer and the second layer, The second region in a third region that is substantially non-parallel to the c-axis and interposes the first region with the second region. On the layer, and, the end of the third region, the semiconductor device being characterized in that and a drain electrode provided on at least one of is provided.

  According to another aspect of the present invention, the first surface is made of a first nitride semiconductor, is substantially parallel to the c-axis of the first nitride semiconductor, and is substantially non-existent with the c-axis. Forming a first layer having a parallel second surface and a third surface that is substantially non-parallel to the c-axis and interposes the first surface between the second surface. A second nitride semiconductor having a band gap larger than that of the first nitride semiconductor, and covering the first surface, the second surface, and the third surface. Forming a layer, forming a gate electrode on the second layer of the first surface, forming the gate electrode on the second layer of the second surface, and the first surface on the second surface. A source electrode is formed on at least one of the end portions of the interface between the second layer and the second layer, the second electrode on the third surface, and the second electrode on the third surface. End of the interface between the layer and the second layer of the method of manufacturing a semiconductor device and forming a drain electrode on at least one is provided for.

  According to the present invention, there are provided a normally-off HEMT semiconductor device that is easy to manufacture, has ultra-high frequency, high-speed characteristics, and low noise, and a method for manufacturing the same.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.
(First embodiment)
FIG. 1 is a schematic cross-sectional view illustrating the configuration of a semiconductor device according to the first embodiment of the invention.
As shown in FIG. 1, the semiconductor device 10 according to the first embodiment of the present invention is provided on a first layer 130 made of a first nitride semiconductor, the first layer 130, A second layer 140 made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor. The first nitride semiconductor can be, for example, GaN, and the second nitride semiconductor can be, for example, AlGaN.

  Further, the first layer 130 can be provided over the substrate 110 with the buffer layer 120 interposed therebetween. The substrate 110 can be made of, for example, sapphire, and the buffer layer 120 can be made of, for example, an aluminum nitride (AlN) film.

  As illustrated in FIG. 1, in the case of the semiconductor device 10, the c-axis 210 of the first layer 130 (GaN layer) is perpendicular to the main surface 114 of the substrate 110. Since the crystal axis of the second layer 140 (AlGaN layer) and the crystal axis of the first layer 130 (GaN layer) are substantially parallel to each other, the second layer 140 (AlGaN layer) The c-axis is substantially parallel to the c-axis 210 of the first layer 130 (GaN layer).

  The semiconductor device 10 further includes a gate electrode 150. The gate electrode 150 includes a first region 250 having a first interface 251 substantially parallel to the c-axis 210 of the first layer 130 among the interfaces of the first layer 130 and the second layer 140. Provided on the second layer 140. Note that an insulating film (not shown) may be provided between the gate electrode 150 and the second layer 140.

  The semiconductor device 10 further includes a source electrode 160. The source electrode 160 is provided on the second layer 140 in the second region 260 in the interface between the first layer 130 and the second layer 140. The second region 260 is a region having a second interface 261 that is substantially non-parallel to the c-axis 210 of the first layer 130 among the interfaces of the first layer 130 and the second layer 140. Note that, as will be described later, the source electrode 160 is in contact with the second interface 261 of the second region 260, that is, on the end of the second interface 261, that is, the end of the second region 260. May be provided.

  The semiconductor device 10 further includes a drain electrode 170. The drain electrode 170 is provided on the second layer 140 in the third region 270 in the interface between the first layer 130 and the second layer 140. The third region 270 is substantially non-parallel to the c-axis 210 of the first layer 130 of the interface between the first layer 130 and the second layer 140, and is different from the second interface 261. The region has an interface 271 and is opposed to the second region 260 with the first region 250 interposed therebetween. That is, the first region 250 is interposed between the third region 270 and the second region 260. Note that, as will be described later, the drain electrode 170 is in contact with the third interface 271 of the third region 270, that is, on the end portion of the third interface 271, that is, the end portion of the third region 270. May be provided.

In other words, in the semiconductor device 10 illustrated in FIG. 1, the step portion 131 is provided in the first layer 130. Note that a stepped portion 141 is also provided in the second layer 140 in the stepped portion 131. The step portions 131 and 141 are the first region 250. In the first region 250, the first interface 251 between the first layer 130 and the second layer 140 is the c-axis 210. Become parallel. As a result, the gate electrode 150 is provided on the second layer 140 parallel to the c-axis 210.
Note that when the first interface 251 is parallel to the c-axis 210 of the first layer 130, the first interface 251 is substantially relative to any of the m-planes of the first layer 130. Can be parallel. However, the present invention is not limited to this, and the first interface 251 may be substantially non-parallel to the m-plane of the first layer 130.

  Further, in the semiconductor device 10 illustrated in FIG. 1, portions other than the first region 250 corresponding to the step portions 131 and 141, that is, the second interface 261 between the first layer 130 and the second layer 140. The third interface 271 is substantially perpendicular to the c-axis 210 of the first layer 130. However, this is an example, and the second interface 261 and the third interface 271 may not be substantially perpendicular to the c-axis 210 and are substantially non-parallel.

  Such a structure can be formed as follows, for example. That is, first, the c-axis of, for example, a sapphire crystal used for the substrate 110 is set to be perpendicular to the main surface 114 of the substrate 110, and the first layer 130 is formed thereon via the buffer layer 120. A first nitride semiconductor layer is formed by epitaxial growth. Then, after providing a predetermined resist mask thereon, the step portion 131 is formed by etching the first nitride semiconductor layer. Then, the step part 141 is formed by forming the 2nd layer 140 on it. A gate electrode 150, a source electrode 160, and a drain electrode 170 are formed thereon, whereby the structure of the semiconductor device 10 illustrated in FIG. 1 is obtained. However, the present invention is not limited to this, and other methods may be used.

Thereby, in the first region 250, the two-dimensional electron gas is not formed at the interface 251 between the first layer 130 and the second layer 140, and there is no carrier. Further, in the second region 260 and the third region 270, two-dimensional electron gas is formed at the interfaces 261 and 271 between the first layer 130 and the second layer 140, and carriers of high mobility can be included. .
As a result, the semiconductor device 10 can realize a normally-off HEMT semiconductor device having ultrahigh frequency, high speed characteristics, and low noise.

FIG. 2 is a schematic view illustrating the crystal structure of a nitride semiconductor used in the semiconductor device according to the first embodiment of the invention.
FIG. 2A is a schematic view illustrating the crystal structure of a nitride semiconductor.
As shown in FIG. 2A, the nitride semiconductor used in the semiconductor device according to the first embodiment of the present invention has a hexagonal crystal structure, and includes a c-plane 212, an a-plane 213, An m-plane 214 is provided. And it has crystal axes of [0001], [1000], [0100] and [0010]. At this time, the axial direction of [0001] perpendicular to the c-plane 212 is the c-axis.
2A, at the interface between the first nitride semiconductor (for example, GaN) and the second nitride semiconductor (for example, AlGaN) used in this embodiment, piezoelectric polarization 410 is performed. Is induced, and an electric field 411 caused by the piezoelectric polarization 410 is generated.

FIG. 2B is a plan view illustrating the crystal orientation on the nitride semiconductor wafer.
As shown in FIG. 2B, the nitride semiconductor (first nitride semiconductor 113) used in the semiconductor device according to the first embodiment of the present invention is within the plane of the wafer 117 that becomes the substrate 110 ( In this example, the crystal axes [1000], [0100], and [0010] are arranged in parallel to the paper surface, and the crystal axis is [0001] perpendicular to the paper surface. Thereby, the c-axis 210 of the first layer 130 can be perpendicular to the main surface 114 of the substrate 110 (wafer 117). Note that the substrate 110 in FIG. 2B has an orientation flat 118, whereby the direction of the crystal axis in the plane of the substrate 110 can be specified.
Note that the direction of the c-axis 210 of the first layer 130 can be arbitrarily set by setting the direction of the crystal axis of the substrate 110 with respect to the main surface 114 of the substrate 110 (for example, sapphire) used. In other words, in the semiconductor device 10 illustrated in FIG. 1, the c-axis 210 is perpendicular to the main surface 114 of the substrate 110, but can also be horizontal or have any other angle. Can do.

FIG. 3 is a band schematic view illustrating the band structure of a nitride semiconductor used in the semiconductor device according to the first embodiment of the invention.
As shown in FIG. 3, an electric field 411 is generated in the second layer 140, and a two-dimensional electron gas 413 is generated at the interface 412 between the first layer 130 and the second layer 140. This two-dimensional electron gas 413 has a high mobility when the impurities in the first layer 130 are small, since the impurity scattering when electrons move is small. Thereby, the semiconductor device 10 according to the present embodiment has the features of ultra-high frequency, high-speed characteristics, and low noise.
In the semiconductor device 10 according to the present embodiment, the first interface 251 between the first layer 130 and the second layer 140 in the first region 250 facing the gate electrode 150 is connected to the c-axis 210. On the other hand, the electric field 411 caused by the piezo polarization 410 is not generated because it is substantially parallel to the piezoelectric element. Therefore, the two-dimensional electron gas 413 is not generated. Therefore, the semiconductor device 10 can be normally off.

Further, in the second region 260 and the third region 270 corresponding to the source electrode 160 and the drain electrode 170, respectively, the second interface 261 between the first layer 130 and the second layer 140 and the third region The interface 271 is not parallel to the c-axis 210 (perpendicular to the c-axis in the example of FIG. 1). As a result, the second interface 261 and the third interface 271 are not parallel to the electric field 411 caused by the piezoelectric polarization 410 (perpendicular in the example of FIG. 1). For this reason, two-dimensional electron gas 413 is generated at the second interface 261 and the third interface 271, whereby the contact resistance between the source electrode 160 and the drain electrode 170 can be lowered.
Note that when the first interface 251 is parallel to the c-axis 210 of the first layer 130, the first interface 251 is either parallel or non-parallel to the m-plane of the first layer 130. Although it is good, when it is substantially parallel to the m-plane of the first layer 130, the electric field 411 caused by the piezoelectric polarization 410 can be generated most efficiently, which is more desirable. However, the present invention is not limited to this.

Hereinafter, a comparative example will be described.
FIG. 4 is a schematic cross-sectional view illustrating the configuration of the semiconductor devices of the first to third comparative examples.
(First comparative example)
As shown in FIG. 4A, the semiconductor device 91 of the first comparative example includes the substrate 110, the buffer layer 120, the first layer 130, and the second layer 140, and is provided thereon. The gate electrode 150 includes a source electrode 160 and a drain electrode 170 on both sides of the gate electrode 150. In this example, the c-axis 210 of the first layer 130 is perpendicular to the main surface 114 of the substrate 110. The first layer 130 and the second layer 140 are not provided with a stepped portion, and the gate electrode 150, the source electrode 160, and the drain electrode 170 are provided in the same plane. At this time, the interface between the first layer 130 and the second layer 140 in the fourth region 350 corresponding to the gate electrode 150 is perpendicular to the c-axis 210. The interface between the first layer 130 and the second layer 140 of the fifth region 360 and the sixth region 370 corresponding to the source electrode 160 and the drain electrode 170 is also perpendicular to the c-axis 210. It has become.

  For this reason, the two-dimensional electron gas 413 is generated in the fifth region 360 and the sixth region 370, and high mobility is obtained. However, since the interface of the fourth region 350 corresponding to the gate electrode 150 is also perpendicular to the c-axis 210, two-dimensional electron gas is generated and the current applied even when the voltage applied to the gate voltage is equal to or lower than the threshold voltage. Flows and becomes a normally-on operation.

(Second comparative example)
As shown in FIG. 4B, in the semiconductor device 92 of the second comparative example, the substrate 110, the buffer layer 120, the first layer 130, and the second layer 140 are similarly provided. The gate electrode 150, the source electrode 160, and the drain electrode 170 are provided on the same plane. However, the c-axis 210 of the first layer 130 is parallel to the main surface 114 of the substrate 110. At this time, the interface between the first layer 130 and the second layer 140 of the fourth region 350 corresponding to the gate electrode 150 is parallel to the c-axis 210 and is connected to the source electrode 160 and the drain electrode 170, respectively. The corresponding interface between the first layer 130 and the second layer 140 in the fifth region 360 and the sixth region 370 is also parallel to the c-axis 210.

  In the case of this comparative example, two-dimensional electron gas is not generated at the interface of the fourth region 350 corresponding to the gate electrode 150, and a normally-off operation is possible. However, even in the fifth region 360 and the sixth region 370, the two-dimensional electron gas 413 is not generated at the interface between the first layer 130 and the second layer 140, and contact is sufficient in the source region and the drain region. Or the contact resistance becomes high. That is, in the semiconductor device 92 of the second comparative example, a normally-off operation can be realized, but the element resistance of the FET becomes high.

  In this structure, in order to lower the contact resistance in the source region and the drain region, a method of injecting an impurity into the semiconductor layer is also conceivable. However, if the fourth to sixth regions 350, 360, and 370 are entirely doped When OFF is injected, the off characteristics deteriorate. In addition, the method of implanting impurities only in the fifth and sixth regions 360 and 370 corresponding to the source electrode 160 and the drain electrode 170 is disadvantageous in that the number of manufacturing steps increases.

(Third comparative example)
As shown in FIG. 4C, the semiconductor device 93 of the third comparative example similarly includes the substrate 110, the buffer layer 120, the first layer 130, the second layer 140, the gate electrode 150, and the source electrode 160. In this example, the drain electrode 170 is provided, but the first layer 130 is provided with an inclined surface 132 (stepped portion). The c-axis 210 of the first layer 130 is perpendicular to the main surface 114 of the substrate 110. The slope 132 has a crystal plane orientation of (1-101), for example. Accordingly, the interface between the first layer 130 and the second layer 140 in the fifth region 360 and the sixth region 370 corresponding to the source electrode 160 and the drain electrode 170 is perpendicular to the c-axis 210. It has become.
In addition, the interface between the first layer 130 and the second layer 140 in the fourth region 350 corresponding to the gate electrode 150 has an angle of (1-101) plane orientation and is relative to the c-axis 210. And non-parallel. In this structure, since the inclined surface 132 has a crystal plane orientation of (1-101), when the second layer 140 is grown on the first layer 130, the growth rate becomes slow, As a result, the layer thickness of the second layer 140 in the portion of the slope 132 can be made thinner than other regions (the fifth region 360 and the sixth region 370). Thereby, the characteristic of normally-off operation is obtained. However, since the interface between the first layer 130 and the second layer 140 is non-parallel to the c-axis 210 in the portion of the slope 132 (fourth region 350), the two-dimensional electron gas 413 is also generated. appear. For this reason, in the third comparative example, a normally-off operation is possible, but the off-resistance is low, and there is room for improvement from the viewpoint of power consumption and circuit design.

  On the other hand, as in the semiconductor device 10 according to the present embodiment, in the first region 250 corresponding to the gate electrode 150, the interface between the first layer 130 and the second layer 140 is relative to the c-axis 210. Therefore, the off-resistance is higher than that of the third comparative example. For this reason, a normally-off HEMT semiconductor device having low power consumption and advantageous in circuit design can be obtained.

Hereinafter, another example of the semiconductor device according to the present embodiment will be described.
FIG. 5 is a schematic cross-sectional view illustrating the configuration of another semiconductor device according to the first embodiment of the invention.
As shown in FIG. 5, in another semiconductor device 11 according to the first embodiment of the present invention, a step portion is provided in the substrate 110 and the buffer layer 120. That is, in the semiconductor device 10 illustrated in FIG. 1, the step portion 131 is provided in the first layer 130, the step portion 141 is provided in the second layer 140, and the step portion is provided in the substrate 110 and the buffer layer 120. In the semiconductor device 11 illustrated in FIG. 5, the stepped portion 111 is formed on the substrate 110 corresponding to the stepped portion 131 of the first layer 130 and the stepped portion 141 of the second layer 140. A step portion 121 is provided in the layer 120.
The semiconductor device 11 can be formed as follows. First, for example, the substrate 110 is prepared by appropriately setting the c-axis of a sapphire crystal, a predetermined resist mask is provided on the substrate 110, and then the step 110 is provided on the substrate 110 by etching the substrate 110. . Thereafter, the buffer layer 120 is provided thereon, the stepped portion 121 is formed, and the first layer 130 and the second layer 140 are further formed thereon. Thereby, the step parts 131 and 141 can be formed. Then, the structure of the semiconductor device 11 illustrated in FIG. 5 is obtained by forming the gate electrode 150, the source electrode 160, and the drain electrode 170 on the second layer 140. However, the present invention is not limited to this, and other methods may be used. Further, an insulating film (not shown) may be provided between the gate electrode 150 and the second layer 140.

  Also in the semiconductor device 11, the gate electrode 150 has a first interface 251 having a first interface 251 substantially parallel to the c-axis 210 of the first layer 130 among the interfaces of the first layer 130 and the second layer 140. One region 250 is provided on the second layer 140. The source electrode 160 and the drain electrode 170 are provided corresponding to the second region 260 and the third region 370, respectively, in which the interface between the first layer 130 and the second layer 140 is perpendicular to the c-axis 210. It has been.

  As a result, the two-dimensional electron gas is not formed in the first region 250 corresponding to the gate electrode 150, and in the second region 260 and the third region 270 corresponding to the source electrode 160 and the drain electrode 170, respectively. A two-dimensional electron gas is formed. As a result, a normally-off HEMT semiconductor device that is easy to manufacture, has a low contact resistance in the source / drain region, and has an ultrahigh frequency, high speed characteristics, and low noise can be realized.

  In the semiconductor devices 10 and 11 according to this embodiment illustrated in FIGS. 1 and 5, the first interface 251 between the first layer 130 and the second layer 140 in the first region 250 is the first It was substantially parallel to the c-axis 210 of the layer 130. This is because the c-axis 210 is substantially perpendicular to the main surface 114 of the substrate 110, and the stepped portion 131 of the first layer 130 and the stepped portion 141 of the second layer 140 become the main surface 114 of the substrate 110. It was realized by providing it vertically. However, the present invention is not limited to this, and various modifications are possible.

  In the semiconductor devices 10 and 11, the first interface 251 and the c-axis 210 are substantially the same even when the stepped portion 131 and the stepped portion 141 are inclined with respect to the main surface 114 of the substrate 110. As long as they are parallel. That is, even if the stepped portions 131 and 141 are tapered (inclined) with respect to the main surface 114 of the substrate 110 due to requests from manufacturing conditions, etc., the first interface 251 and the c-axis 210 Are substantially parallel and the second interface 261 and the third interface may be non-parallel to the c-axis 210. This also applies to various embodiments described below.

(Second Embodiment)
In the second embodiment, the source electrode 160 and the drain electrode 170 are provided in contact with the second interface 261 of the second region 260 and the third interface 271 of the third region 270, respectively. It is.

FIG. 6 is a schematic cross-sectional view illustrating the configuration of a semiconductor device according to the second embodiment of the invention.
The semiconductor devices 20 and 21 illustrated in FIGS. 6A and 6B have structures similar to the semiconductor devices 10 and 11 illustrated in FIGS. 1 and 5, respectively. However, in the semiconductor devices 20 and 21 according to the second embodiment illustrated in FIGS. 6A and 6B, the source electrode 160 and the drain electrode 170 are respectively connected to the second interface of the second region 260. 261 and the third interface 271 of the third region 270, that is, the end of the second interface 261 (end of the second region 260), the end of the third interface 271 (third Of the region 270). As a result, the source electrode 160 and the drain electrode 170 can be in direct contact with carriers due to the two-dimensional electron gas existing at these interfaces, and the two-dimensional electron gas can be easily taken out.
Also in these structures, the two-dimensional electron gas is not formed in the first region 250 corresponding to the gate electrode 150, and the second region 260 and the third region 270 corresponding to the source electrode 160 and the drain electrode 170 are not formed. Since a two-dimensional electron gas is formed, the semiconductor devices 20 and 21 can realize a normally-off HEMT semiconductor device that is easy to manufacture, has a low contact resistance, has an ultra-high frequency, high speed characteristics, and low noise.

  Note that one of the source electrode 160 and the drain electrode 170 is provided over the second layer 140, and the other is in contact with the interface between the first layer 130 and the second layer 140, that is, the first layer. It may be provided on the end portion of the interface between 130 and the second layer 140. That is, a structure in which FIG. 1 and FIG. 6A or FIG. 5 and FIG.

  Further, in the semiconductor device illustrated in FIGS. 1, 5, and 6, the first layer 130 and the second layer 270 in the second region 260 and the third region 270 corresponding to the source electrode 160 and the drain electrode 170, respectively. The interfaces 261 and 271 of the layer 140 are substantially perpendicular to the c-axis. However, the present invention is not limited to this, and it may be substantially non-parallel to the c-axis.

FIG. 7 is a schematic cross-sectional view illustrating the configuration of another semiconductor device according to the second embodiment of the invention.
As shown in FIG. 7A, another semiconductor device 21a according to this embodiment includes the first region 260 and the third region 270 corresponding to the source electrode 160 and the drain electrode 170, respectively. In this example, the interfaces 261 and 271 between the layer 130 and the second layer are oblique to the c-axis. The interface 251 between the first layer 130 and the second layer in the first region 250 corresponding to the gate electrode 150 is substantially parallel to the c-axis 210. Also in this structure, since the two-dimensional electron gas is formed at the second interface 261 and the third interface 271, the semiconductor device 21 a is easy to manufacture, has low contact resistance, ultrahigh frequency, high speed characteristics, low A noisy normally-off HEMT semiconductor device can be realized.

  As shown in FIGS. 7B and 7C, in another semiconductor device 21 b or 21 c according to this embodiment, one of the second interface 261 and the third interface 271 is connected to the c-axis 210. It is substantially perpendicular to the other and the other is inclined with respect to the c-axis. Also in this case, since the two-dimensional electron gas is formed at the second interface 261 and the third interface 271, the semiconductor devices 21 b and 21 c are easy to manufacture, have low contact resistance, ultrahigh frequency, high speed characteristics, A low-noise normally-off type HEMT semiconductor device can be realized.

As illustrated in FIG. 7D, in another semiconductor device 21 d according to this embodiment, the source electrode 160 and the drain electrode 170 are each a second interface that is substantially non-parallel to the c-axis 210. 261 and the third interface 271. That is, the source electrode 160 and the drain electrode 170 are on the end portion of the interface between the first layer 130 and the second layer 140 (that is, the end portion of the second region 260 and the end portion of the third region 270). Is provided. Even in this structure, the source electrode 160 and the drain electrode 170 can be electrically connected to the second interface 261 and the third interface 271, respectively. The semiconductor device 21d can realize a normally-off HEMT that is easy to manufacture, has a lower contact resistance, and has an ultra-high frequency, high-speed characteristics, and low noise.
In the structure illustrated in FIGS. 7B and 7C, either the source electrode 160 or the drain electrode 170 is provided over the second layer 140, and the other is connected to the second interface 261 or the third interface. May be provided in contact with the interface 271.

  Further, in the example of the semiconductor device according to the embodiment described above, the c-axis 210 of the first layer 130 is substantially perpendicular to the main surface 114 of the substrate 110. The angle between the c-axis 210 of one layer 130 and the main surface 114 of the substrate 110 can be an arbitrary angle.

FIG. 8 is a schematic cross-sectional view illustrating the configuration of another semiconductor device according to the second embodiment of the invention.
As shown in FIG. 8A, in another semiconductor device 22 a according to the second embodiment of the present invention, the c-axis 210 of the first layer 130 is oblique with respect to the main surface 114 of the substrate 110. It has become. The gate electrode 150 is provided on the second layer 140 in the first region 250. In the first region 250, the first interface 251 between the first layer 130 and the second layer 140 is oblique with respect to the main surface 114 of the substrate 110 and substantially with respect to the c-axis 210. It is parallel to. In addition, in the second region 260 and the third region 270, which have a second interface 261 and a third interface 271 that are substantially non-parallel to the c-axis 210, respectively, the source electrode 160 and the drain An electrode 170 is provided on the second layer 140. Also with the semiconductor device 22a having this structure, it is possible to realize a normally-off HEMT semiconductor device that is easy to manufacture, has a low contact resistance, and has an ultrahigh frequency, high speed characteristics, and low noise.

In addition, as illustrated in FIG. 8B, in another semiconductor device 22 b according to the second embodiment of the present invention, the source electrode 160 and the drain electrode 170 have a second interface 261 and a third interface, respectively. In contact with the interface 271, that is, on the end of the interface between the first layer 130 and the second layer 140. Also with the semiconductor device 22b having this structure, it is possible to realize a normally-off HEMT semiconductor device that is easy to manufacture, has a low contact resistance, and has an ultrahigh frequency, high speed characteristics, and low noise.
Note that one of the source electrode 160 and the drain electrode 170 may be provided over the second layer 140 and the other may be provided in contact with the second interface 261 or the second interface 271.

In addition, the c-axis 210 of the first layer 130 may be parallel to the main surface 114 of the substrate 110. Hereinafter, a third embodiment will be described.
(Third embodiment)
FIG. 9 is a schematic cross-sectional view illustrating the configuration of a semiconductor device according to the third embodiment of the invention.
As shown in FIG. 9, in another semiconductor device 30 according to the ninth embodiment of the present invention, the substrate 110 is provided with a trench 180, and the first layer 130 and the first layer 130 are formed inside the trench 180. Two layers 140 are provided. Note that the buffer layer 120 may be provided between the substrate 110 and the first layer 130.

  The c-axis 210 of the first layer 130 is substantially parallel to the bottom surface of the trench 180. In the example illustrated in FIG. 9, the side surface of the trench 180 is substantially perpendicular to the bottom surface of the trench 180. For this reason, the c-axis 210 of the first layer 130 is substantially perpendicular to the side surface of the trench 180.

The portion corresponding to the bottom surface of the trench 180 is the first region 250, and in the first region 250, the interface between the first layer 130 and the second layer 140 (first interface 251) and the c-axis 210 is substantially parallel. A gate electrode 150 is provided on the second layer 140 in the first region 250 (the bottom portion of the trench 180).
In addition, the side portions of the trench 180 that face each other through the first region 250 become the second region 260 and the third region 270. That is, the second interface 261 and the third interface in the second region 250 and the third region where the interface between the first layer 130 and the second layer 140 is perpendicular (non-parallel) to the c-axis 210. A source electrode 160 and a drain electrode 170 are provided in contact with 271, respectively. In this case, the source electrode 160 is formed on the end portion of the second interface 261 and the end portion of the third interface 271 (that is, the end portion of the second region 260 and the end portion of the third region 270), respectively. And a drain electrode 170 are provided.

  Also in the semiconductor device 30 having such a structure, the two-dimensional electron gas is not formed in the first region 250 corresponding to the gate electrode 150, and the second regions 260 corresponding to the source electrode 160 and the drain electrode 170, respectively. In the third region 270, a two-dimensional electron gas is formed. Thereby, the semiconductor device 30 can realize a normally-off type HEMT semiconductor device that is easy to manufacture, has low contact resistance, and has an ultra-high frequency, high-speed characteristics, and low noise.

  In the semiconductor device 30 illustrated in FIG. 9, the first layer 130 and the second layer 140 are provided inside the trench 180. Thereby, the film stress generated in the first layer 130 and the second layer 140 is relieved. Thereby, the warp of the substrate 110 can be reduced, and a semiconductor device that can be stably manufactured and has stable performance can be obtained. In addition, the trench structure has an advantage that the chip area can be reduced.

Further, the semiconductor device 30 according to the third embodiment illustrated in FIG. 9 can be variously modified.
FIG. 10 is a schematic cross-sectional view illustrating the configuration of another semiconductor device according to the third embodiment of the invention.
As shown in FIG. 10A, in another semiconductor device 31 a according to this embodiment, the source electrode 160 and the drain electrode 170 are provided inside the trench 180. In other words, the interface between the first layer 130 and the second layer 140 is formed on the second layer 260 in the second region 260 and the third region 270 in which the interface is not parallel (perpendicular) to the c-axis 210, respectively. An electrode 160 and a drain electrode 170 are provided. Note that the buffer layer 120 can be provided between the substrate 110 and the first layer 130. The same applies to FIGS. 10B to 10E below.

  Further, as illustrated in FIG. 10B, in another semiconductor device 31 b according to the present embodiment, the source electrode 160 is provided in contact with the interface between the first layer 130 and the second layer 140, The drain electrode 170 is provided on the second layer 140 in the third region 270.

  In addition, as illustrated in FIG. 10C, in another semiconductor device 31 c according to the present embodiment, the side surface of the trench 180 is inclined with respect to the bottom surface of the trench 180 and has a tapered shape. In addition, the interface between the first layer 130 and the second layer 140 in the second region 260 and the third region 270, that is, the second interface 261 and the third interface 271 are relative to the c-axis 210. Substantially non-parallel. A source electrode 160 and a drain electrode 170 are provided in contact with the second interface 261 and the third interface 271, respectively.

In addition, as illustrated in FIG. 10D, in another semiconductor device 31 d according to this embodiment, the side surface of the trench 180 is tapered, and the first region in the second region 260 and the third region 270 is the first. The interface between the layer 130 and the second layer 140, that is, the second interface 261 and the third interface 271 are substantially non-parallel to the c-axis 210. A source electrode 160 is provided in contact with the second interface 261, and a drain electrode 170 is provided on the second layer 140 (inside the trench) in the third region 270.
In the figure, the source electrode 160 and the drain electrode 170 may be replaced with each other.

In addition, as illustrated in FIG. 10E, in another semiconductor device 31 e according to the present embodiment, the side surface of the trench 180 is tapered, and the first region in the second region 260 and the third region 270 is the first. The interface between the layer 130 and the second layer 140, that is, the second interface 261 and the third interface 271 are substantially non-parallel to the c-axis 210. A source electrode 160 is provided on the second layer 140 in the second region 260 in contact with the second interface 261. A drain electrode 170 is provided on the second layer 140 (inside the trench) in the third region 270.
In the figure, the source electrode 160 and the drain electrode 170 may be replaced with each other.

  Also in these semiconductor devices 31a to 31e, the two-dimensional electron gas is not formed in the first region 250 corresponding to the gate electrode 150, and the second region 260 corresponding to the source electrode 160 and the drain electrode 170, respectively. In the third region 270, a two-dimensional electron gas is formed. As a result, the semiconductor devices 31a to 31e can realize a normally-off HEMT semiconductor device that is easy to manufacture, has low contact resistance, has an ultra-high frequency, high-speed characteristics, and low noise.

FIG. 11 is a schematic cross-sectional view illustrating the configuration of another semiconductor device according to the third embodiment of the invention.
As shown in FIG. 11A, in another semiconductor device 32 a according to the present embodiment, a convex portion 181 is provided on the substrate 110. The upper surface portion of the convex portion 181 is the first region 250, and the interface between the first layer 130 and the second layer 140 in the first region 250, that is, the first interface 251 is the first region 250. The layer 130 is substantially parallel to the c-axis 210. A gate electrode 150 is provided on the second layer 140 in the first region 250.

In the example of FIG. 11A, the two opposite side surfaces of the convex portion 181 are substantially perpendicular to the upper surface of the convex portion 181. These side portions correspond to the second region 260 and the third region 270. That is, the interface between the first layer 130 and the second layer 140 in the second region 260 and the third region 270, that is, the second interface 261 and the third interface 271 are in relation to the c-axis 210. Vertical (non-parallel). A source electrode 160 and a drain electrode 170 are provided on the second layer 140 of the second region 260 and the third region 270, respectively.
With this structure, in the semiconductor device 32a, the two-dimensional electron gas is not formed in the first region 250 corresponding to the gate electrode 150, and the second region 260 and the second region corresponding to the source electrode 160 and the drain electrode 170, respectively. A two-dimensional electron gas is formed in the third region 270. Thereby, the semiconductor device 32a can realize a normally-off HEMT semiconductor device that is easy to manufacture, has a low contact resistance, and has an ultra-high frequency, high speed characteristics, and low noise.

Various modifications can be made to the structure of the semiconductor device 32a illustrated in FIG. This will be described below.
For example, as shown in FIG. 11B, in another semiconductor device 32b according to this embodiment, the structure of the source electrode 160 and the drain electrode 170 is different from that of the semiconductor device 32a illustrated in FIG. It has been changed. That is, the source electrode 160 and the drain electrode 170 are provided in contact with the second interface 261 of the second region 260 and the third interface 271 of the third region 270, respectively.

In addition, as illustrated in FIG. 11C, in another semiconductor device 32 c according to the present embodiment, the source electrode 160 is provided in contact with the second interface 261 of the second region 260, and the drain The electrode 170 is provided on the second layer 140 in the third region 270.
In the figure, the source electrode 160 and the drain electrode 170 may be replaced with each other.

  In addition, as illustrated in FIG. 11D, in another semiconductor device 32 d according to this embodiment, the side surface of the convex portion 181 has a tapered shape. Also in this case, the second interface 261 and the third interface 271 are non-parallel (oblique) to the c-axis 210. The source electrode 160 and the drain electrode 170 are provided on the second layer 140 in the second region 260 and the third region 270, respectively.

  As shown in FIG. 11E, in another semiconductor device 32e according to this embodiment, the side surface of the convex portion 181 is tapered, and the source electrode 160 and the drain electrode 170 each have a second interface 261. And in contact with the third interface 271.

In addition, as illustrated in FIG. 11F, in another semiconductor device 32 f according to the present embodiment, the side surface of the convex portion 181 is tapered, and the source electrode 160 is the second layer of the second region 260. The drain electrode 170 is provided in contact with the third interface 271.
In the figure, the source electrode 160 and the drain electrode 170 may be replaced with each other.

  Also in these semiconductor devices 32b to f, the two-dimensional electron gas is not formed in the first region 250 corresponding to the gate electrode 150, and the second region 260 and the second region corresponding to the source electrode 160 and the drain electrode 170, respectively. A two-dimensional electron gas is formed in the third region 270. Thereby, the semiconductor devices 32b to f can realize a normally-off HEMT semiconductor device that is easy to manufacture, has a low contact resistance, and has an ultra-high frequency, high speed characteristics, and low noise.

(Fourth embodiment)
FIG. 12 is a schematic view illustrating the configuration of a semiconductor device according to the fourth embodiment of the invention. FIG. 12A is a schematic plan view illustrating the configuration of the semiconductor device according to the fourth embodiment, and FIG. 12B is a cross-sectional view taken along line AA in FIG.
As illustrated in FIG. 12A, the semiconductor device 40 according to the fourth embodiment of the present invention includes a comb-shaped gate electrode 150, a comb-shaped source electrode 160, and a comb-shaped drain electrode 170. Then, as shown in FIG. 12B, the first layer 130 has a convex portion 181 and a concave portion 182. And the 2nd layer 140 is provided on it. Since the convex portion 181 and the concave portion 182 are relative to each other, either one may be provided.

  As illustrated in FIG. 12B, in the semiconductor device 40, the c-axis 210 of the first layer 130 is perpendicular to the upper surface of the convex portion 181 and the bottom surface of the concave portion 182. The gate electrode 150 is provided on the second layer 140 on the side surfaces of the convex portion 181 and the concave portion 182. The side portions of the convex portion 181 and the concave portion 182 are the first region 250, and the first interface 251 of the first region 250 is substantially parallel to the c-axis 210.

  A source electrode 160 is provided on the second layer 140 in the second region 260 that is the bottom surface of the recess 182. The second interface 261 of the second region 260 is perpendicular (non-parallel) to the c-axis 210. A drain electrode 170 is provided on the second layer 140 in the third region 270 that is the upper surface of the convex portion 181. The third interface 271 of the third region 270 is perpendicular (non-parallel) to the c-axis 210.

  Even in such a structure, the two-dimensional electron gas is not formed in the first region 250 corresponding to the gate electrode 150, and the second region 260 and the third region corresponding to the source electrode 160 and the drain electrode 170, respectively. In the region 270, a two-dimensional electron gas is formed. As a result, the semiconductor device 40 can realize a normally-off HEMT semiconductor device that is easy to manufacture, has low contact resistance, and has an ultra-high frequency, high-speed characteristics, and low noise.

Various modifications are also possible when such a comb-shaped electrode is provided. An example will be described.
FIG. 13 is a schematic view illustrating the configuration of another semiconductor device according to the fourth embodiment of the invention.
FIG. 13A is a schematic plan view illustrating the configuration of another semiconductor device according to the fourth embodiment, and FIG. 13B is a cross-sectional view taken along the line AA in FIG. .
As shown in FIG. 13A, another semiconductor device 41 according to the fourth embodiment of the present invention includes a comb-shaped gate electrode 150, a comb-shaped source electrode 160, and a comb-shaped drain electrode 170. One layer 130 has a convex portion 181 and a concave portion 182. And the 2nd layer 140 is provided on it.

  As shown in FIG. 13B, the c-axis 210 of the first layer 130 is parallel to the top surface of the convex portion 181 and the bottom surface of the concave portion 182. The gate electrode 150 is provided on the second layer 140 on the top surface of the protrusion 181 and the bottom surface of the recess 182. That is, the upper surface portion of the convex portion 181 and the bottom surface portion of the concave portion 182 are the first region, and the first interface 251 of the first region 250 is substantially parallel to the c-axis 210. Yes.

  A source electrode 160 and a drain electrode 170 are provided on the second layer 140 on the side surfaces of the convex portion 181 and the concave portion 182. The second interface 261 of the second region 260 is perpendicular (non-parallel) to the c-axis 210. The third interface 271 of the third region 270 is also perpendicular (non-parallel) to the c-axis 210.

  Even in such a structure, the two-dimensional electron gas is not formed in the first region 250 corresponding to the gate electrode 150, and the second region 260 and the third region corresponding to the source electrode 160 and the drain electrode 170, respectively. In the region 270, a two-dimensional electron gas is formed. As a result, the semiconductor device 40 can realize a normally-off HEMT semiconductor device that is easy to manufacture, has low contact resistance, and has an ultra-high frequency, high-speed characteristics, and low noise.

  In FIG. 13B, the side surfaces of the convex portion 181 and the concave portion 182 are side surfaces perpendicular to the top surface of the convex portion 181 and the bottom surface of the concave portion 182. The upper surface and the bottom surface of the concave portion 182 may be tapered side surfaces that are oblique.

(Fifth embodiment)
FIG. 14 is a schematic view illustrating the configuration of a semiconductor device according to the fifth embodiment of the invention. FIG. 14A is a schematic plan view illustrating the configuration of the semiconductor device according to the fifth embodiment, and FIG. 14B is a cross-sectional view taken along line AA in FIG.
As shown in FIG. 14A, the semiconductor device 50 according to the fifth embodiment of the present invention includes a hexagonal annular gate electrode 150, a hexagonal source electrode 160, and a hexagonal annular drain. An electrode 170 is provided. And as represented to FIG.14 (b), the 1st layer 130 has the hexagonal recessed part 182 by planar view. The depth direction of the recess 182 is substantially parallel to the c-axis 210. In the example shown in FIGS. 14A and 14B, in the hexagonal recess 182, the three side surfaces 219 a, 219 b, and 219 c that are not substantially parallel to each other are three of the crystals of the first layer 130. Each of them is substantially parallel to the m-plane 214.

  A second layer 140 is provided inside the recess 182. A portion on the inner side surface of the recess 182 is the first region 250, and an interface between the first layer 130 and the second layer 140 on the side surface of the recess 182 becomes the first interface 251. That is, the first interface 251 is substantially parallel to the c-axis 210, and each side surface of the hexagonal recess 182 is parallel to the m-plane 214 of the first layer 130. .

On the other hand, the bottom portion of the recess 182 is the second region 260, and the interface between the first layer 130 and the second layer 140 in the second region 260, that is, the second interface 261 is c-axis. It is perpendicular (non-parallel) to 210. A source electrode 160 is provided on the second layer 140 in the second region 260.
Further, a portion of the surface on the first layer 130 other than the concave portion 182 becomes a third region 270. The interface between the first layer 130 and the second layer 140 in the third region 270, that is, the third interface 271 is perpendicular (non-parallel) to the c-axis. A hexagonal annular drain electrode 170 is provided on the second layer 140 in the third region 270.
In the semiconductor device 50 of this embodiment, the source electrode 160 and the drain electrode 170 may be interchanged.

  Even in the semiconductor device 50 having such a configuration, the two-dimensional electron gas is not formed in the first region 250 corresponding to the gate electrode 150, and the second region 260 corresponding to the source electrode 160 and the drain electrode 170 respectively. In the third region 270, a two-dimensional electron gas is formed. Thereby, the semiconductor device 50 can realize a normally-off HEMT semiconductor device that is easy to manufacture, has a low contact resistance, and has an ultra-high frequency, high speed characteristics, and low noise.

In the above semiconductor device FIG. 50, a convex portion 181 may be formed instead of the concave portion 182. This will be described below.
FIG. 15 is a schematic cross-sectional view illustrating the configuration of another semiconductor device according to the fifth embodiment of the invention.
The planar structure of another semiconductor device 51 according to the fifth embodiment illustrated in FIG. 15 is the same as that in FIG. FIG. 15 is a cross-sectional view taken along line AA in FIG.
As shown in FIG. 15, in another semiconductor device 51 according to the fifth embodiment of the present invention, the first layer 130 has a hexagonal convex portion 181 in plan view. The height direction of the convex portion 181 is substantially parallel to the c-axis 210. In the example shown in FIG. 15, in the hexagonal columnar convex portion 181, the three side surfaces 219 a, 219 b, and 219 c that are not substantially parallel to the three m-planes 214 of the crystal of the first layer 130, respectively. Are substantially parallel to each other.

  Then, the second layer 140 is provided on the first layer 130 around the upper surface and side surfaces of the convex portion 181 and the convex portion 181. Then, the side portion of the convex portion 181 is the first region 250, and the interface between the first layer 130 and the second layer 140 on the side surface of the convex portion 181 becomes the first interface 251. That is, the first interface 251 is substantially parallel to the c-axis 210, and each side surface of the hexagonal convex portion 181 is respectively defined with respect to the m-plane 214 of the first layer 130. Parallel.

On the other hand, the upper surface portion of the convex portion 181 is the second region 260, and the interface between the first layer 130 and the second layer 140 in the second region 260, that is, the second interface 261 is c It is perpendicular (non-parallel) to the axis 210. A source electrode 160 is provided on the second layer 140 in the second region 260.
In addition, a portion that is not the upper surface and the side surface of the convex portion 181, that is, a portion around the convex portion 181 becomes the third region 270. In addition, the interface between the first layer 130 and the second layer 140 in the third region 270, that is, the third interface 271 is perpendicular (non-parallel) to the c-axis 210. A hexagonal annular drain electrode 170 is provided on the second layer 140 in the third region 270.
In the semiconductor device 51 of this embodiment, the source electrode 160 and the drain electrode 170 may be interchanged.

  Also in the semiconductor device 51 having such a configuration, the two-dimensional electron gas is not formed in the first region 250 corresponding to the gate electrode 150, and the second region 260 corresponding to the source electrode 160 and the drain electrode 170, respectively. In the third region 270, a two-dimensional electron gas is formed. Thereby, the semiconductor device 51 can realize a normally-off HEMT semiconductor device that is easy to manufacture, has a low contact resistance, and has an ultrahigh frequency, high speed characteristics, and low noise.

(Sixth embodiment)
FIG. 16 is a flowchart illustrating the method for manufacturing the semiconductor device according to the sixth embodiment of the invention.
As shown in FIG. 16, in the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention, first, the first nitride semiconductor 113 is used, and the c-axis 210 of the first nitride semiconductor 113 The first surface is between a first surface that is substantially parallel, a second surface that is substantially non-parallel to the c-axis 210, and a second surface that is substantially non-parallel to the c-axis 210. A first layer 130 having a third surface to be interposed is formed (step S110). Here, for example, GaN can be used for the first nitride semiconductor 113.

This is done as follows. For example, first, the c-axis of, for example, a sapphire crystal used for the substrate 110 is appropriately set with respect to the main surface 114 of the substrate 110, and a layer of the first nitride semiconductor 113 to be the first layer 130 is formed by epitaxial growth. Form. And after providing a predetermined resist mask on it, it can implement | achieve by etching the layer of the 1st nitride semiconductor 113, and forming the level | step-difference part 131. FIG.
Alternatively, for example, by preparing the substrate 110 in which the c-axis of the sapphire crystal is appropriately set, providing a predetermined resist mask on the substrate 110, and etching the substrate 110, first, the step portion 111 is formed on the substrate 110. Is provided. And it can implement | achieve by forming the 1st layer 130 so that the level | step-difference part 111 may be covered.
In the above, the buffer layer 120 can be formed on the main surface 114 of the substrate 110, and the first layer 130 can be formed thereon.

  The second layer 140 is made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor 113 and covers the first surface, the second surface, and the third surface. Form (step S120). The first surface, the second surface, and the third surface are synonymous with the first interface 251, the second interface 261, and the third interface 271 already described.

  Then, the gate electrode 150 is formed on the second layer 140 in the first region 250 (step S130).

  And at least on the second layer 140 in the second region 260 and at the end of the interface between the first layer 130 and the second layer 140 (second interface 261) on the second surface. A source electrode 160 is formed on either of them (step S140).

  And at least on the second layer 140 in the third region 270 and at the end of the interface between the first layer 130 and the second layer 140 (third interface 271) on the third surface. A drain electrode 170 is formed on either of them (step S150).

  In the manufactured semiconductor device, the two-dimensional electron gas is not formed in the first region 250 corresponding to the gate electrode 150, and the second region 260 and the second region corresponding to the source electrode 160 and the drain electrode 170, respectively. A two-dimensional electron gas is formed in the third region 270. As a result, the semiconductor device is capable of a normally-off operation with ultra-high frequency, high speed characteristics, and low noise. That is, with the manufacturing method of this embodiment, a normally-off HEMT semiconductor device with low contact resistance, ultra-high frequency, high speed characteristics, and low noise can be easily manufactured.

  Note that the order of steps S110 to S150 illustrated in FIG. 16 may be changed within a technically feasible range, and steps S110 to S150 may be performed simultaneously. For example, step S130 for forming the gate electrode 150 may be performed after step S140 or step S150, and step S140 for forming the source electrode 160 and step S150 for forming the drain electrode 170 may be performed simultaneously. good. In addition, various modifications are possible.

(First embodiment)
Hereinafter, as a first example of the present embodiment, a method for manufacturing the semiconductor device 30 illustrated in FIG. 9 will be described.
FIG. 17 is a schematic cross-sectional view in order of the processes, illustrating the method for manufacturing the semiconductor device according to the first example of this invention.
First, a substrate 110 made of sapphire is prepared. At this time, the c-axis 211 of the sapphire crystal is made substantially parallel to the main surface 114 of the substrate 110. For example, a wafer 117 whose side surface of a trench 180 described later is (0001) (000-1) may be used. Then, as illustrated in FIG. 17A, a mask material 190 made of, for example, an oxide film is formed in a predetermined shape on the main surface 114 of the substrate 110.
Next, as illustrated in FIG. 17B, the substrate 110 is etched by the RIE (Reactive Ion Etching) method, for example, using the mask material 190 as a mask to form the trench 180.
Then, as shown in FIG. 17C, after AlN is formed as the buffer layer 120 in the trench 180, for example, GaN is 3 μm as the first layer 130, and AlGaN is 20 nm as the second layer, for example. Sequentially epitaxially grow with a thickness of. Thereby, step S110 and step S120 are implemented. The c-axis 210 of the first layer 130 is parallel to the c-axis 211 of the substrate 110 made of sapphire.

Then, after removing the mask material 190, as shown in FIG. 17D, a resist 191 is formed in a predetermined shape on the main surface 114 and the trench 180 of the substrate 110.
Then, for example, a Ti / Al film is formed thereon, and the resist 191 is peeled off to form the source electrode 160 and the drain electrode 170 as shown in FIG. At this time, the source electrode 160 and the drain electrode 170 are formed in contact with the interface between the first layer 130 and the second layer 140, that is, on the end portion of the interface. Thereby, it becomes easy to take out the two-dimensional electron gas.

  Then, after providing an appropriate resist (not shown), for example, a Pt / Au film to be the gate electrode 150 is formed, and the resist is removed to form the gate electrode 150 as shown in FIG. To do.

  In this way, the interface between the first layer 130 and the second layer 140 is parallel to the c-axis in the portion of the gate electrode 150 (first region 250), and the source electrode 160 and the drain electrode 170 The portions (second region 260 and third region 270) can be perpendicular (non-parallel) to the c-axis. Thereby, the two-dimensional electron gas is not formed in the first region 250 corresponding to the gate electrode 150, and 2 in the second region 260 and the third region 270 corresponding to the source electrode 160 and the drain electrode 170, respectively. A three-dimensional electron gas is formed, and the semiconductor device according to the present embodiment has a low contact resistance, and can operate in a normally-off type with ultrahigh frequency, high speed characteristics, and low noise.

(Second embodiment)
FIG. 18 is a schematic cross-sectional view in order of the process, illustrating the method for manufacturing the semiconductor device according to the second example of this embodiment.
In the second embodiment, the steps of forming the trench 180 in the substrate 110 and forming the buffer layer 120, the first layer 130, and the second layer 140 therein are shown in FIGS. 17A to 17C. Since it can be the same as that of the first embodiment described above, the description is omitted.
After removing the mask material 190, as shown in FIG. 18A, as the insulating film 192, for example, silicon nitride is formed to a thickness of, for example, 10 nm on the main surface 114 of the substrate 110 and the trench 180. . Note that the insulating film 192 is not limited to the above, and various materials such as silicon oxide can be used.

  Then, after a resist having a predetermined shape (not shown) is formed on the insulating film 192, the insulating film 192 is subjected to wet etching or dry etching to remove the insulating film 192 in the source / drain electrode formation portion. Thereafter, similarly to the first embodiment, for example, a Ti / Al film is formed, and the source electrode 160 and the drain electrode 170 are formed by the lift-off method as shown in FIG. 18B.

  Then, after providing an appropriate resist (not shown), for example, a Pt / Au film to be the gate electrode 150 is formed, and the resist is removed to form the gate electrode 150 as shown in FIG. To do.

  Thus, also in the second embodiment, the interface between the first layer 130 and the second layer 140 is parallel to the c-axis in the part of the gate electrode 150 (first region 250). The portions of the source electrode 160 and the drain electrode 170 (the second region 260 and the third region 270) can be perpendicular (non-parallel) to the c-axis. Thereby, the two-dimensional electron gas is not formed in the first region 250 corresponding to the gate electrode 150, and 2 in the second region 260 and the third region 270 corresponding to the source electrode 160 and the drain electrode 170, respectively. A three-dimensional electron gas is formed, and the semiconductor device according to the present embodiment has a low contact resistance, and can operate in a normally-off type with ultrahigh frequency, high speed characteristics, and low noise. In this embodiment, since the insulating film 192 is provided between the gate electrode 150 and the second layer 140, a semiconductor device with high operational stability and high reliability can be obtained.

In the first and second embodiments described above, an example in which sapphire is used as the substrate 110 is shown, but the substrate 110 is not limited to this. That is, for example, when a cubic crystal such as silicon is used as a substrate, a (011) wafer having a trench side surface of (111) (-1-1-1) may be used. Further, when hexagonal crystals such as sapphire and GaN are used, a wafer in which the side surfaces of the trench 180 are (0001) (000-1) may be used.
In addition, the substrate 110 used in the embodiment of the present invention is prepared so that the angle formed between the first to third interfaces 251, 261, 271 and the c-axis 210 of the semiconductor device to be manufactured is appropriately set. Any material may be used.

  Throughout the present specification, “parallel” includes a strict deviation from parallel due to variations in manufacturing processes and the like, and may be substantially parallel. Similarly, throughout the present specification, “vertical” includes a deviation from strict vertical and may be substantially vertical.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, with regard to the specific configuration of each element constituting the semiconductor device and the method for manufacturing the same, the present invention can be similarly implemented by appropriately selecting from a known range and a similar effect can be obtained. Are included within the scope of the present invention.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, all semiconductor devices and manufacturing methods that can be implemented by those skilled in the art based on the above-described semiconductor device and manufacturing method described above as embodiments of the present invention include the gist of the present invention. As long as it belongs to the scope of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

1 is a schematic cross-sectional view illustrating the configuration of a semiconductor device according to a first embodiment of the invention. 1 is a schematic view illustrating a crystal structure of a nitride semiconductor used in a semiconductor device according to a first embodiment of the invention. 1 is a band schematic diagram illustrating a band of a nitride semiconductor used in a semiconductor device according to a first embodiment of the invention. It is a schematic cross section which illustrates the structure of the semiconductor device of the 1st-3rd comparative example. FIG. 6 is a schematic cross-sectional view illustrating the configuration of another semiconductor device according to the first embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of a semiconductor device according to a second embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of another semiconductor device according to the second embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of another semiconductor device according to the second embodiment of the invention. FIG. 6 is a schematic cross-sectional view illustrating the configuration of a semiconductor device according to a third embodiment of the invention. FIG. 10 is a schematic cross-sectional view illustrating the configuration of another semiconductor device according to the third embodiment of the invention. FIG. 10 is a schematic cross-sectional view illustrating the configuration of another semiconductor device according to the third embodiment of the invention. FIG. 10 is a schematic view illustrating the configuration of a semiconductor device according to a fourth embodiment of the invention. FIG. 10 is a schematic view illustrating the configuration of another semiconductor device according to the fourth embodiment of the invention. FIG. 10 is a schematic view illustrating the configuration of a semiconductor device according to a fifth embodiment of the invention. FIG. 10 is a schematic cross-sectional view illustrating the configuration of another semiconductor device according to the fifth embodiment of the invention. FIG. 10 is a flowchart illustrating a method for manufacturing a semiconductor device according to a sixth embodiment of the invention. FIG. 6 is a schematic cross-sectional view in order of the process, illustrating the method for manufacturing the semiconductor device according to the first example of this invention. It is a schematic cross section of order of a process which illustrates the manufacturing method of the semiconductor device of the 2nd Example of this invention.

Explanation of symbols

10, 11, 20, 21, 21a-d, 22a-b, 30, 31a-e, 32a-f, 40, 41, 50, 51, 91-93 Semiconductor device 110 Substrate 111, 121, 131, 141 Stepped portion 113 First nitride semiconductor 114 Main surface 117 Wafer 118 Orientation flat 120 Buffer layer 130 First layer 132 Slope 140 Second layer 150 Gate electrode 160 Source electrode 170 Drain electrode 180 Trench 181 Convex part 182 Concave part 190 Mask material 191 Resist 192 Insulating film 210, 211 c-axis 212 c surface 213 a surface 214 m surface 219a-c side surface 250 first region 251 first interface 260 second region 261 second interface 270 third region 271 third Interface 350 350 fourth region 37 Sixth region 410 piezoelectric polarization 411 field 412 interface 413 two-dimensional electron gas 414 Fermi level

Claims (5)

A first layer made of a first nitride semiconductor;
A second layer made of a second nitride semiconductor provided on the first layer and having a band gap larger than that of the first nitride semiconductor;
Of the interface between the first layer and the second layer, the first region substantially parallel to the c-axis of the first layer is provided on the second layer. A gate electrode;
Of the interface between the first layer and the second layer, on the second layer in the second region substantially non-parallel to the c-axis, and the second region A source electrode provided on at least one of the end portions of
Of the interface between the first layer and the second layer, the third region is substantially non-parallel to the c-axis and interposes the first region with the second region. A drain electrode provided on at least one of the second layer in the region and an end of the third region;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the first region is substantially parallel to any one of m-planes of the first layer. The first layer has a stepped portion,
The first region is provided in any one of the stepped portion and a region adjacent to the stepped portion,
3. The semiconductor device according to claim 1, wherein the second and third regions are provided in any one of the stepped portion and a region adjacent to the stepped portion. The step portion is a side surface portion of the trench,
The first region is provided on a bottom surface of the trench;
The semiconductor device according to claim 3, wherein the second region and the third region are provided in the side surface portion of the trench. A first surface made of a first nitride semiconductor, substantially parallel to the c-axis of the first nitride semiconductor, a second surface substantially non-parallel to the c-axis, and the c-axis And a third surface that is substantially non-parallel to the second surface and interposes the first surface,
A second layer made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor, and covering the first surface, the second surface, and the third surface. Form the
Forming a gate electrode on the second layer of the first surface;
A source electrode is formed on at least one of the second layer on the second surface and an end portion of the interface between the first layer and the second layer on the second surface. ,
A drain electrode is formed on at least one of the second layer on the third surface and an end of the interface between the first layer and the second layer on the third surface. A method for manufacturing a semiconductor device.

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