CN105393359B - HEMT device and method - Google Patents

HEMT device and method Download PDF

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Publication number
CN105393359B
CN105393359B CN201480031378.6A CN201480031378A CN105393359B CN 105393359 B CN105393359 B CN 105393359B CN 201480031378 A CN201480031378 A CN 201480031378A CN 105393359 B CN105393359 B CN 105393359B
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layer
iii
substrate
groove
planar wall
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CN105393359A (en
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萨迈赫·G·卡里尔
安德里亚·科林
卡里姆·S·布特罗斯
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HRL Laboratories LLC
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HRL Laboratories LLC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788—Vertical transistors
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30612—Etching of AIIIBV compounds
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7789—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Abstract

HEMT device includes III-nitride material substrate, and the surface of the III-nitride material substrate is along the plane not parallel with the face C- of III-nitride material；The epitaxial layer of the III-nitride material grown over the substrate；The groove etched in the epitaxial layer has at least one planar wall parallel with the polar plane of III-nitride material；The carrier accommodating layer formed on a part of planar wall of groove, so that the part planar wall along groove forms the area 2DEG；The doping source region formed at the surface of the epitaxial layer separates the doping source region by the channel region of epitaxial layer with the area 2DEG；The gate insulating layer formed on the channel region of epitaxial layer；With the gate contact layer formed on gate insulating layer.

Description

HEMT device and method
Related application
This application claims the priority for the U.S.Application Serial Number 61/846,489 submitted on July 15th, 2013 and requirements The equity of this application is protected, all the contents of the application are herein incorporated by reference.The application was also required July 11 in 2014 The priority for the U.S.Application Serial Number 14/329,745 day submitted and the equity of claimed this application, in the whole of this application Hold and is merged in this article by reference.
Technical field
This technology relates generally to integrated circuit or device with the element using two-dimensional electron gas (2DEG) operation, and And particularly utilize the vertical HEMTS of group III-nitride high voltage of 2DEG operation.This technology is proposed to have and be vertically formed Two-dimensional electron gas vertical Group III nitride semiconductor device.Term " HEMT " refers to HEMT devices.
Background technique
In the known group III-nitride HEMT device in electric power application, there are on-state resistances and breakdown Design compromise between voltage (BV).Known high voltage gan HEMT device uses technology and work based on lateral device structure Sequence process, the off state voltage being laterally extended, and wherein high mobility 2DEG are supported in big drift region in lateral device structure Face is horizontally oriented.
Fig. 1 illustrates the cross section of a part of prior art high voltage HEMT 10, HEMT 10 includes for example buffering The narrow band gap channel layer 12 or carrier bearing bed (carrier of the undoped GaAs or GaN that are formed on the top of structure 14 Carrying layer), the buffer structure 14 is formed itself on the top of such as silicon substrate of substrate 16.Broad-band gap carrier Supplying layer 18 or barrier layer, such as the n-type AlGaAs or AlGaN layer of high doped, form on the top of channel layer 12. HEMT 10 includes in the channel region formed between conductive source contact zone 22 and conductive drain contact area 24 in channel layer 12 20, conductive source contact zone 22 and conductive drain contact area 24 both pass through carrier supplying layer 18 and are formed in channel layer 12 In.The gate contact region 28 that passivation layer 26 covers the carrier supplying layer 18 of 20 top of channel region and insulated body layer 30 insulate, It is entered in carrier layer 18 across passivation layer 26.Optionally, the gate contact region 28 that insulated body layer 30 insulate can be worn Transpassivation layer 26 is contacted with the surface of carrier layer 18.In addition to this, HEMT 10 includes field plate 32,34, the field plate 32,34 It is connected respectively to gate contact region 28 and source contact area 22.
In HEMT 10, during off-state operation, the drift of drain contact region is extended to from the edge of gate regions 28 Area is horizontally oriented, and has the function of supporting high drain-source voltage and high drain-gate voltage.Second important feature of HEMT 10 is two Dimensional electron gas layer 36, interface of the layer 36 just between carrier accommodating layer 18 (AlGaN) and carrier bearing bed (GaN layer) Lower section is formed.This layer has high carrier mobility, and the high carrier mobility for example can achieve 2100cm2/ V.sec.If AlGaN layer thickness increases to above certain value, 2DEG will be formed below the interface, wherein the density of 2DEG Increase with the increase of both the molar fraction of the thickness and aluminium of AlGaN layer.
HEMT based on horizontal 2DEG HV GaN such as transverse direction HEMT 10 faces since its preferable material property is such as high Boundary's electric field, broad-band gap and high saturated velocity and utilization can be with the high density piece charges that high mobility moves in 2DEG layers Ability and be considered as the preferred candidates for leading power electronics route map at present.However, for rated value for example higher than The higher voltage devices of 600V, horizontal drift area become quite big, this cause again biggish unit grid away from and on state it is electric The larger product Ron.A of resistance and chip area, wherein A is the area of device chip.
Product Ron.A is quality factor critically important in power device, because it directly affects the cost of mold.To mold From associated with biggish die area compared with low-yield, this is particularly significant for lateral GaN for the further influence of cost 's.
Although still more advantageous than their silicon form, off-state is supported to leak electricity due to needing longer drift region Pressure, as the increase of blocking voltage is not so good as the device more attractive based on vertical GaN based on the lateral HEMT of high voltage gan.
In arranged perpendicular (vertical power device), unit grid is away from being substantially reduced, because drift region vertical extends.In this way Structure in transverse dimensions only limited by process constraint and to the considerations of punch-through breakdown.This means that compared with transversal device, it is right Ron.A product will be much lower for vertical devices, and especially true for higher voltage rating.
Fig. 2 illustrates the cross section of a part of known vertical GaN FET 40, and the vertical GaN FET 40 includes Substrate 42, such as be made of N+GaN, it is configured with drift layer 44 on top of this, such as drift layer 44 is by low-doped N-GaN system At.FET 40 does not include 2DEG.Such as the channel layer 46 undoped with GaN, configuration connect on the top of drift region 44 and by source electrode Area 48 is touched to cover.The gate trench 50 that source contact area 48 and channel region 46 are extended in drift region 44 traverses.Gate insulator Layer 52 fills the space left in gate trench by gate insulating layer 52 along gate trench 50 and gate contact layer 54.Leakage Electrode 56 is configured on the bottom surface of substrate 42；On the top surface of FET 40, source electrode and gate electrode contact source contact area and Gate contact region.FET40 includes the drift region 58 vertically extended in drift layer 44, and the thus electric current conduction in FET40 is It is vertical and supported in entire vertically oriented drift region across the voltage for the device being in an off state.
The arranged perpendicular of FET40 is converted into the unit grid of the transistor with high voltage-rated away from significantly reducing.For such as The unit grid of the vertical devices of FET40 by photoetching process, the process constraint to realize vertical structure and is examined break-through away from main Consider to determine.It is all for vertical power device such as GaN FET40 and the lateral power of given technical maturity level Such as Gan HEMT 10, the breakeven point of load voltage value is set for value proposition.Below breakeven point, laterally Configuration has more commercial spirit, and then arranged perpendicular is more advantageous above breakeven point.Breakeven point can pass through the head of district that drifts about (it is related to design), unit grid are spent away from every kind of mask in the cost of raw material and two kinds of configurations in addition to process complexity It counts to determine.
The known device based on vertical GaN depends on the drift region ontology GaN, and there is no height in the drift region ontology GaN Electron density and high mobility layer.Ontology GaN device depends on ontology mobility, this is significantly less than 2DEG mobility.The present invention People has been noted that the high voltage device for being greater than 600V for voltage rating, with lateral GaN HEMT and vertical ontology GaN phase Than vertical GaN HEMT is often more preferable.
The U.S. Patent number in authorization on May 2nd, 2006 of Furukawa: 7,038,253 B2 of US is disclosed a kind of normal The field effect transistor based on GaN of closed form has very small conducting resistance during operation, and being capable of high current behaviour Make comprising source electrode and drain electrode；The channel portion made of the first semiconductor material based on GaN, described first is based on The semiconductor material of GaN is the semiconductor material based on i-GaN or the semiconductor material based on p-GaN.It is thusly-formed groove Divide to be electrically connected with source electrode and drain electrode.The first and second electronics made of the second semiconductor material based on GaN supply The band-gap energy that partially should have the semiconductor material than first based on GaN bigger, the first and second electronics supply section quilt It is added to channel portion and the positioning that is separated from each other.The insulating layer formed on the surface of channel portion, in the first and second electricity Extend between sub- supply section；And gate electrode is arranged on the insulating layer.
The rom of entitled " nitride compound semiconductor device and the method for preparing nitride compound semiconductor device " of Hirotaka is public During department (Rohm Co.) U.S. Patent Application Publication No. US 2009/0057684 discloses a kind of nitride-based semiconductor, packet It includes: having half made of the conductive Group III nitride semiconductor of the principal plane limited nonpolar plane or semi-polar plane Conducting base layer；The insulating layer formed on the principal plane of base semiconductor, the hole with partially exposed principal plane；Nitride Semiconductor multilayer structure part is formed extending on the region on insulating layer from the hole, semiconductor-based with being parallel to The parallel surfaces of the principal plane of layer and the first inclined-plane of principal plane inclined+c- axis side relative to base semiconductor and-c- axis The second inclined-plane of side and the two kinds of Group III nitride semiconductor layer including at least having different lattice constants；Be formed as The gate electrode opposite with the second inclined-plane；It is arranged to the source electrode being electrically connected with Group III nitride semiconductor layer；It is put down with main The drain electrode formed on the back side of the opposite base semiconductor in face.
The U.S. Patent number 7,098,093 of Clarke discloses HEMT type device, with pillar, the pillar have with The vertical wall of substrate transverse.Pillar has the semiconductor material of insulation, such as GaN.Being arranged on the side of pillar is semiconductor The barrier layer of material such as AlGaN has the band gap of the band gap of the insulating materials greater than pillar.Electron stream is limited in two kinds The narrow channel of the interface of material.It is operated comprising suitable source electrode, drain and gate contact for HEMT.
Summary of the invention
This disclosure relates to the structure of vertical HEMT, wherein at least part of the drift region between grid and drain electrode is depended on 2DEG mobility, and it is related to the method for manufacturing this vertical HEMT.
One embodiment of the disclosure is related to HEMT device, comprising: III-nitride material substrate, the III group nitrogen The surface of compound material substrate is along the plane not parallel with the face C- of the III-nitride material；It gives birth to over the substrate The epitaxial layer of long III-nitride material；The groove etched in the epitaxial layer, the groove have and the substrate At least one planar wall of the uneven surface row；The polarity of described at least one planar wall and the III-nitride material Plane is parallel；At least one carrier supply formed at least part of at least one planar wall described in the groove Layer, so that described at least part along at least one planar wall described in the groove forms the area 2DEG；In the epitaxial layer The surface at the doping source region that is formed make the doping source region and the area 2DEG by the channel region of the epitaxial layer every It opens；The gate insulating layer formed on the channel region of the epitaxial layer；The grid formed on the gate insulating layer Contact layer.
According to the embodiment of the disclosure, the surface that grid and channel region are parallel to substrate extends.
According to the embodiment of the disclosure, at least one described planar wall that grid and channel region are parallel to groove extends.
According to the embodiment of the disclosure, described at least one carrier accommodating layer at least one plane described in groove It is formed such that the channel region along epitaxial layer forms another area 2DEG in a part of wall.
According to the embodiment of the disclosure, at least one described planar wall of groove is parallel to III-nitride material The face C-.
According to the embodiment of the disclosure, the surface of at least one planar wall of groove perpendicular to substrate.
According to the embodiment of the disclosure, the surface of substrate along III-nitride material the face M-.Surface.
According to the embodiment of the disclosure, the surface of substrate along III-nitride material the face A-.Surface.
According to the embodiment of the disclosure, III-nitride material substrate is self-supporting III-nitride material substrate.
According to the embodiment of the disclosure, III-nitride material is GaN.
According to the embodiment of the disclosure, carrier accommodating layer includes epitaxy single-crystal AlGaN, epitaxy single-crystal GaN/AlGaN One of with epitaxy single-crystal AlN.
According to the embodiment of the disclosure, carrier accommodating layer includes being formed on III-nitride material epitaxial layer Separate layer and the barrier layer formed on separate layer.
According to the embodiment of the disclosure, carrier accommodating layer grown on III-nitride material epitaxial layer so that The area 2DEG is in the III-nitride material of extension along at least part of table of at least one planar wall described in groove Face is formed.
One embodiment of the disclosure is related to a kind of method for preparing HEMT device, which comprises provides III group Nitride material substrate, the surface of the III-nitride material substrate is along not parallel with the face C- of III-nitride material Plane；The epitaxial layer of III-nitride material is grown over the substrate；The etched recesses in the epitaxial layer are described recessed Slot has at least one planar wall with the uneven surface row of substrate；At least one described planar wall and III-nitride material Polar plane it is parallel；The supply of at least one carrier is formed at least part of at least one planar wall described in groove Floor makes at least part of surface along at least one planar wall described in groove form the area 2DEG；In the epitaxial layer Surface at formed doping source region so that the doping source region is separated with the area 2DEG by the channel region of the epitaxial layer；? Gate insulating layer is formed on the channel region of the epitaxial layer；Gate contact layer is formed on the gate insulating layer.
According to the embodiment of the disclosure, the surface that grid and channel region are parallel to substrate extends.
According to the embodiment of the disclosure, at least one described planar wall that grid and channel region are parallel to groove extends.
According to the embodiment of the disclosure, at least one described carrier accommodating layer be configured in the groove it is described extremely So that the channel region along the epitaxial layer forms another area 2DEG in a part of a few planar wall.
According to the embodiment of the disclosure, at least one described planar wall is parallel to the C- of the III-nitride material Face.
According to the embodiment of the disclosure, the table of at least one described planar wall of the groove perpendicular to the substrate Face.
According to the embodiment of the disclosure, the surface of the substrate along the III-nitride material the face M-.
According to the embodiment of the disclosure, the surface of the substrate along the III-nitride material the face A.
According to the embodiment of the disclosure, the III-nitride material substrate is self-supporting III-nitride material lining Bottom.
According to the embodiment of the disclosure, the III-nitride material is GaN.
According to the embodiment of the disclosure, the carrier accommodating layer includes epitaxy single-crystal AlGaN, epitaxy single-crystal GaN/ One of AlGaN and epitaxy single-crystal AlN.
According to the embodiment of the disclosure, forms the carrier accommodating layer and be included in outside the III-nitride material Prolong and forms separate layer on layer and form barrier layer on the separate layer.
According to the embodiment of the disclosure, formed at least part of at least one planar wall described in the groove At least one described carrier accommodating layer includes that the carrier accommodating layer is grown on the III-nitride material epitaxial layer So that along the described at least part of of at least one planar wall described in the groove in the III-nitride material of extension Surface forms 2DEG.
Detailed description of the invention
The present invention may be better understood by reference to the following figure.Component in attached drawing is not drawn necessarily to scale, but weight Point is the principle illustrated the present invention.In the accompanying drawings, same reference number indicates corresponding portion through different views Point.
Fig. 1 illustrates the cross sections of a part of the high voltage lateral HEMT of the prior art.
Fig. 2 illustrates the cross section of a part of the vertical FET of high voltage of the prior art.
Fig. 3 a and 3B illustrate the chip of the face the C- substrate of III-nitride material, and the shape on the substrate of the face C- At 2DEG.
Fig. 4 is the projection of crystal view of III-nitride material.
Fig. 5 A and 5B illustrate the chip of the face the M- substrate of III-nitride material, and in the implementation according to the disclosure The 2DEG formed on the face the M- substrate of scheme.
Fig. 6 and 6A illustrates the cross section of a part of the vertical HEMT of high voltage according to the embodiment of the disclosure.
Fig. 7 and 7A illustrates the transversal of a part of the high voltage vertical trench HEMT according to the embodiment of the disclosure Face.
Fig. 8 and 8A illustrates the transversal of a part of the high voltage vertical trench HEMT according to the embodiment of the disclosure Face.
Specific embodiment
Fig. 3 a illustrates the chip of the face the C- substrate 16 of III-nitride material (such as GaN).III-nitride material Crystal structure be such that its face C- is polar；That is, showing in a direction perpendicular to its surface significant spontaneous And piezoelectricity polarity effect.As illustrated in figure 3b, if forming barrier layer or carrier confession on the top on the surface Layer 18 is answered, then the polarization field 60 generated can generate two-dimentional carrier confinement 62, also referred to as 2DEG 62 along the surface of substrate 16.
Fig. 4 is the projection of crystal view of III-nitride material (such as GaN), shows in particular group III-nitride Material includes two non-polar planes: the face M- and the face A-, they are perpendicular to one another and also are normal to the polar face C-.
According to the embodiment of the disclosure, group III-nitride substrate is preferably configured to so that the surface of substrate is parallel In the face M- or the face A- of III-nitride material.As disclosed below, this configuration allows to form vertical trench in the substrate (groove vertical with surface), the vertical trench have the trench wall in the face C- for being parallel to III-nitride material.This makes Fine and close 2DEG is formed along trench wall.
However, group III-nitride substrate is also configured to so that relative to III group according to the embodiment of the disclosure The surface of substrate described in the face M- or the face A- of nitride material forms certain angle (not being 90 ° of angles).This configuration permission is serving as a contrast Vertical trench is formed in bottom, the vertical trench has the trench wall in the face C- for being not orthogonal to III-nitride material, due to ditch Angle between cell wall and the face C- this allow to be formed the 2DEG of reduced density along trench wall.
Fig. 5 A illustrates the chip of the face the M- group III-nitride substrate 64 according to the embodiment of the disclosure.III group nitridation The crystal structure of object substrate 64 is such that its face M- is nonpolar；The polarization field 66 of group III-nitride substrate 64 is interior Portion and it is parallel to the surface of group III-nitride substrate 64.
Fig. 5 B illustrates the multiple grooves 68 etched in group III-nitride substrate 64.According to the embodiment of the disclosure, Each groove 68 includes at least one perpendicular to the surface of group III-nitride substrate 64 and is parallel to III-nitride material The planar wall 70 in the face C-.The polarization field 66 presented at the surface of planar wall 70 is then perpendicular to the surface of planar wall 70.According to this Disclosed embodiment, if carrier accommodating layer 74 is formed on the surface of planar wall 70, at the surface of planar wall 70 The polarization field 66 of presentation can generate two-dimentional carrier confinement 72 along the surface of planar wall 70 in group III-nitride substrate 64, Or 2DEG 72.
According to the optional embodiment of the disclosure, each groove 68 may include being not orthogonal to group III-nitride lining The planar wall 70 on the surface at bottom 64, and the planar wall 70 is angled relative to the face C- of III-nitride material.In It is the surface that the polarization field 66 presented at the surface of planar wall 70 is not orthogonal to planar wall 70, if on the surface of planar wall 70 Upper formation carrier accommodating layer 74 then generates along the surface of planar wall 70 in group III-nitride substrate 64 and reduces density 2DEG 72。
Fig. 6 illustrates the cross section of a part of the vertical HEMT 75 of high voltage according to the embodiment of the disclosure, wherein Group III-nitride substrate 64 includes self-supporting ontology III-nitride material substrate 76, and the III grown on substrate 76 The epitaxial layer 78 of group nitride material.For the sake of clarity, there is no illustrate in detail in this figure for the polarization field 66 of substrate 64.According to this Disclosed embodiment, polarization field 66 perpendicular to planar wall 70 surface, as shown in Figure 5 B.According to the embodiment of the disclosure, The surface of group III-nitride substrate 76 along the face C- for being not parallel to III-nitride material plane.For example, III group nitrogenizes Object substrate 76 can be the face n+M- Free-standing GaN substrate.Epitaxial growth of the layer 78 in the bulk substrate of identical material ensure that Epitaxial layer 78 has and the similar crystal arrangement of group III-nitride substrate 76.According to the embodiment of the disclosure, epitaxial layer 78 can To be made of unintentional dopant material.For example, when group III-nitride substrate 76 is the face n+M- Free-standing GaN substrate, epitaxial layer 78 can be the n-GaN epitaxial layer of the unintentional doping with m- faceted crystal similar with group III-nitride substrate 76 arrangement.
According to the embodiment of the disclosure as shown in Figure 6, HEMT 75 includes at least one etched in epitaxial layer 78 A groove 68.According to the embodiment of the disclosure, groove 68 can be vertical groove, and the vertical groove passes through epitaxial layer 78 extend but terminate at the interface between epitaxial layer 78 and group III-nitride substrate 76, as shown in solid in Fig. 6.According to The embodiment of the disclosure, groove 68 can be groove, and the groove extends by epitaxial layer 78 and penetrates group III-nitride Substrate 76, as shown in the dotted line for having label 77 in Fig. 6.According to the embodiment of the disclosure, groove 68 can be groove, described Groove is extended through epitaxial layer 78 without reaching group III-nitride substrate 76, as shown in the dotted line for having label 79 in Fig. 6.
According to the embodiment of the disclosure, groove 68 includes that at least one is not parallel to the table of group III-nitride substrate 76 The planar wall 70 in face.According to the embodiment of the disclosure, planar wall 70 is parallel to the polar plane of III-nitride material.When When group III-nitride substrate 76 is the face M- substrate and groove 68 is vertical trench, planar wall 70 can be parallel to III group nitridation The face C- of the material of object substrate 76 and epitaxial layer 78.According to the embodiment of the disclosure, carrier accommodating layer 74 is in groove It is grown at least part of 68 planar wall 70, so that the area 2DEG 72 is in the extension III-nitride material of epitaxial layer 78 Surface along planar wall 70 is formed, and the surface of planar wall 70 is covered by carrier accommodating layer 74.The embodiment illustrated in Fig. 6 In, carrier accommodating layer 74 completely covers planar wall 70, therefore the area 2DEG 72 extends along entire planar wall 70.According to the disclosure Embodiment, passivation layer 80 can be formed on carrier accommodating layer 74.
According to the embodiment of the disclosure, carrier accommodating layer 74 can be epitaxy single-crystal AlGaN, epitaxy single-crystal GaN/ AlGaN or epitaxy single-crystal AlN.
According to the embodiment of the disclosure, as shown in Figure 6, HEMT 75 includes being formed at the surface of epitaxial layer 78 Doping source region 82, for example, by adulterate be parallel to substrate 76 surface extend epitaxial layer 78 surface region so that doping The area source region 82 and 2DEG 72 is separated by the channel region 84 of epitaxial layer 78.According to the embodiment of the disclosure, channel region 84 is also parallel Extend in the surface of substrate 76.According to the embodiment of the disclosure, HEMT 75 includes being formed on the channel region 84 of epitaxial layer 78 Gate insulating layer 86, and the gate contact layer 88 formed on gate insulating layer 86.According to the embodiment of the disclosure, grid Pole insulating layer 86 and gate contact layer 88 cover a part of source region 82 and a part of carrier accommodating layer 74.According to the reality of the disclosure Scheme is applied, HEMT 75 includes the drain contact region 89 on the bottom surface of substrate 76.At least part of the drift region of HEMT 75 Including the area 2DEG 72.
According to the embodiment of the disclosure, HEMT 75 works as follows: during on state operation, by gate voltage (VG) Gate contact layer 88 is applied to by gate electrode, wherein the pinch-off voltage (Vp) of VG > device.If VG is far longer than Vp, in ditch Channel is formed under gate contact layer 88 in road area 84.The channel formed in channel region 84 under gate contact layer 88 is current-carrying Son provides the low resistance path from source region 82 to the area 2DEG 72.Initial current in HEMT 75 be it is lateral, in gate contact The lower section of layer 88, be then in the area 2DEG 72 it is vertical, carrier flows to substrate 76 with high mobility herein, and final Flow out drain contact region 89.
During off-state, gate voltage is applied to gate electrode, wherein VG < Vp (more negative than pinch-off voltage).In source region Channel is not formed between the area 82 and 2DEG 72.Then the positive drain voltage across drift region is supported (to be similarly to by the area 2DEG exhausted The case where traditional lateral HEMT).According to the embodiment of the disclosure, the thickness of the epitaxial layer 78 of growth is designed to support complete Drain voltage, that is, device drift region length LD is substantially equal to the thickness of layer 78.
Fig. 6 A illustrates the cross section of a part of the vertical HEMT91 of high voltage according to the embodiment of the disclosure, with figure The vertical HEMT 75 of 6 high voltage is essentially identical, but wherein the sub- bearing bed 93 of other intermediate current-carrying is raw on the surface of planar wall 70 It is long, carrier accommodating layer 74 is then grown on carrier bearing bed 93, so that being formed in the sub- bearing bed 93 of intermediate current-carrying The area 2DEG 72.This sub- bearing bed 93 of intermediate current-carrying can have material identical with epitaxial layer 78.Carrier bearing bed 93 can For example to grow the interface to provide with carrier accommodating layer 74, defect concentration, which is lower than, does not use the sub- bearing bed 93 of intermediate current-carrying The case where.According to the embodiment of the disclosure, separate layer 95 can be formed optionally before carrier accommodating layer 74, carrier Accommodating layer 74 is then grown on separate layer.For example, if carrier accommodating layer 74 is made of AlGaN, separate layer 95 can be with Such as it is made of AlN, such as preventing the interface between carrier accommodating layer 74 and the sub- bearing bed 93 of intermediate current-carrying Alloy disorder effect.According to the embodiment of the disclosure, separate layer 95 can also be formed in HEMT 75 to prevent in carrier The alloy disorder effect of interface between accommodating layer 74 and epitaxial layer 78.
Fig. 7 illustrates a part of the high voltage vertical HEMT 90 or groove HEMT 90 according to the embodiment of the disclosure Cross section, high voltage vertical HEMT 90 or groove HEMT 90 is made in group III-nitride substrate 64, the III group nitrogen Compound substrate 64 includes the group III-nitride that self-supporting ontology III-nitride material substrate 76 and is grown on substrate 76 The epitaxial layer 78 of material, as discussed previously with respect to described in Fig. 6.According to the embodiment of the disclosure, HEMT 90 is included in epitaxial layer 78 At least one groove 68 of etching, as discussed previously with respect to described in Fig. 6.For the sake of clarity, the polarization field 66 of substrate 64 does not illustrate In detail in this figure.According to the embodiment of the disclosure, as shown in figure 5, surface of the polarization field 66 perpendicular to planar wall 70.
According to the embodiment of the disclosure, carrier accommodating layer 74 is grown on a part of planar wall 70 of groove 68, is made The area 2DEG 72 is obtained in epitaxial layer 78 along the partially formed of planar wall 70.
According to the embodiment of the disclosure, carrier accommodating layer 74 can be epitaxy single-crystal AlGaN, epitaxy single-crystal GaN/ AlGaN or epitaxy single-crystal AlN.
According to the embodiment of the disclosure, HEMT 90 includes the doping source region 92 formed at the surface of epitaxial layer 78, example Such as by the region on the surface of doped epitaxial layer 78, and the surface for being parallel to substrate 76 extends up to the edge of groove 68.Root According to the embodiment of the disclosure, HEMT 90 includes gate insulating layer 94, in not covered by carrier supply layer 74 for planar wall 70 Part on formed.The insulating layer can also cover the top surface of carrier accommodating layer 74 in groove 68.According to the implementation of the disclosure Scheme, HEMT 90 include the gate contact layer 96 formed in groove 68 on gate insulating layer 94, thus in epitaxial layer 78 Vertical channel region 98 is formed along gate contact layer 96 below source region 92.According to the embodiment of the disclosure, HEMT 90 is included in Drain contact region 89 on the bottom surface of substrate 76.At least part drift region of HEMT90 includes the area 2DEG 72.
According to the embodiment of the disclosure, HEMT 90 is substantially operated such as HEMT 75, the difference is that in conducting shape In state operation, if VG (voltage of grid) is far longer than Vp (pinch-off voltage of HEMT90), along grid in channel region 98 Contact layer 96 forms vertical-channel, and the channel provides the low resistance path that the area 2DEG 72 is flowed to from source region 92 for carrier.? Electric current in HEMT 90 along gate contact layer 96 be it is vertical, be then in the area 2DEG 72 it is vertical, carried at the area 2DEG 72 It flows sub- high mobility and flows to substrate 76, and finally flow out drain contact region 89.
During off-state, gate voltage is applied to gate electrode, wherein VG < Vp (more negative than pinch-off voltage).In source region Channel is not formed between the area 92 and 2DEG 72.Then the positive drain voltage across drift region is supported (to be similarly to by the area 2DEG exhausted The case where traditional lateral HEMT).According to the embodiment of the disclosure, the thickness of the epitaxial layer 78 of growth is designed to support complete Drain voltage, that is, device drift region length LD is substantially equal to the thickness of layer 78.
Fig. 7 A illustrates the cross section of a part of the vertical HEMT 97 of high voltage according to the embodiment of the disclosure, HEMT 90 vertical with the high voltage of Fig. 7 is essentially identical, but wherein the sub- bearing bed 99 of other intermediate current-carrying on the surface of planar wall 70 Then upper growth grows carrier accommodating layer 74 on the bottom of carrier bearing bed 99.In HEMT 97,72 edge of the area 2DEG Carrier accommodating layer 74 formed in the sub- bearing bed 99 of intermediate current-carrying.This sub- bearing bed 99 of intermediate current-carrying can have with outside Prolong the identical material of layer 78.The sub- bearing bed 99 of intermediate current-carrying can be grown to provide the interface with carrier accommodating layer 74, be lacked Fall into the case where density is lower than bearing bed without using intermediate current-carrying.According to the embodiment of the disclosure, can be supplied in carrier The separate layer 95 for being similar to the separate layer described in Fig. 6 A is formed before layer 74, carrier accommodating layer 74 is then in separate layer 95 Upper growth.
According to the embodiment of the disclosure, process flow below can be used for manufacturing one in HEMT 75,90,91 or 97 It is a:
The face n+M- Free-standing GaN substrate 76 is provided, which serves as the drain region of high doped and provide template with life The GaN layer 78 of long one layer of unintentional doping, realizes the rest part of device architecture in GaN layer 78.Because of unintentional doping (UID) GaN layer 78 is in the grown on top of the face n+M- GaN substrate 76, therefore there is similar m- faceted crystal to arrange for it.
Then at least one groove 68 is etched, such as perpendicular to substrate plane, in 78 layers of UID GaN layer, and from layer 78 surface extends vertically up to n+ substrate 76.This groove can or cannot extend dearly is enough to reach n+ substrate 76.It takes Certainly in device optimization, groove can penetrate n+ substrate 76, or terminate at n+ substrate/interface UID, or even before reaching interface eventually Only.The groove has at least one side wall 70.
(groove can such as be reacted by being used to form a kind of known method of high aspect ratio trench in groove 68 Ion(ic) etching is formed), Ill-nitride layer 74 (or multilayer) grows on side wall 70, this final will have formed it is vertical The function of hetero-epitaxy knot.Electric current supplying layer (typical AlGaN is provided in the conventional lateral HEMT structure of Fig. 1 to be similar to Potential barrier) composition and growth conditions to provide these in a manner of correct condition is arranged for both piezoelectricity and spontaneous polarizations heterogeneous The composition and growth conditions of epitaxy junction layer are to be arranged correct condition for both piezoelectricity and spontaneous polarizations.
According to the embodiment of the disclosure, one or more hetero-epitaxy knot layers can be made of any number of layer, example As their growth can only relate to AlGaN layer regeneration to form the heterojunction structure with side wall 70.In another embodiment, One or more hetero-epitaxy knot layers can be made so that in GaN/AlGaN stacking of the GaN/AlGaN growing on side wall 70 The GaN layer of regrowth is by the good quality with lower defect concentration.In another embodiment, one or more heterogeneous Epitaxy junction layer can be the laterally stacked of GaN/AlN/AlGaN.According to the embodiment of the disclosure, one or more hetero-epitaxies Knot layer can be any combination of layer or the single layer of III-nitride material, this will lead to high quality interface and minimum The vertically oriented hetero-epitaxy knot layer of defect concentration, and will to form required vertical 2DEG at hetero-epitaxy junction interface Area 72.
In the step of no matter which layer will be used to form one or more hetero-epitaxy knot layers, final result is that had The high quality regrown material of low-defect-density, the 2DEG of high mobility and sufficiently high 2DEG density.For example, 5e12-1e13/ The 2DEG density of cm2 is considered sufficiently high.
As shown in fig. 6, can complete to close after the growth of one or more group III-nitride hetero-epitaxy knot layers The deposition of suitable passivation layer 80 or regeneration are to terminate regeneration zone.PECVD, LPCVD or MOCVD nitride (Si3N4) contribute to The suitable candidate of the passivation step of passivation layer 80 is formed, however, the disclosure should not be limited to any one of these materials, and And any suitable passivating material for having high resistance to current collapse (leakage) problem all will be suitable.
Hereafter, low ohm contact zone is formed to implement source contact 82 or 92.High agent to donor type species such as silicon Amount masking ion implanting, which then carries out RTA step, can be used to form source contact.Next, on the surface of epitaxial layer 78 or side wall It is deposited in 70 a part or grows insulating materials, to form gate insulating layer 86 or 94.Then after insulated gate electrode process And then with grid material appropriate (or grid stacking) 88 or 96 depositions/evaporation.Back-end process process, including gold are completed in next step Dielectric deposition and evaporation of metal or sputtering process are between category to realize low resistance source, drain interconnection network.It should be noted that at this In vertical structure, drain metal is deposited on the back side of chip.To reduce drain parasitic resistance, the face n+m- substrate 76 can be thinned To suitable thickness, the then drain metal 89 at the redeposited back side.
Fig. 8 illustrates the transversal of a part of the high voltage vertical trench HEMT 100 according to the embodiment of the disclosure Face.HEMT 100 and the HEMT 90 described about Fig. 7 are essentially identical, the difference is that not being to include only in planar wall 70 The carrier accommodating layer 74 grown on bottom, HEMT 100 include the carrier supply grown in the major part of planar wall 70 Layer 102, so that the channel region 98 along epitaxial layer forms another area 2DEG 104, such as consistent with the area 2DEG 72.In order to clearly rise See, the polarization field 66 of substrate 64 does not illustrate in detail in this figure.According to the embodiment of the disclosure, polarization field 66 is perpendicular to planar wall 70 surface, as shown in Figure 5.
According to the embodiment of the disclosure, carrier accommodating layer 102 includes surface groove 106, the shape in surface groove 106 At gate insulating layer 94 and gate contact layer 96 so as to vertical channel region 98, as being described in detail about Fig. 7.It should be noted that It is that, due to another area 2DEG 104 in channel region 98, HEMT 100 is with depletion-mode operation rather than if HEMT 90 is to enhance Mode operation.
Fig. 8 A illustrates the cross section of a part of the vertical HEMT 103 of high voltage according to the embodiment of the disclosure, with The vertical HEMT 100 of the high voltage of Fig. 8 is essentially identical, but wherein the sub- bearing bed 105 of other intermediate current-carrying on the surface of planar wall 70 Upper growth, then carrier accommodating layer 102 is grown on carrier bearing bed 105, so that the area 2DEG 72 is held in intermediate current-carrying Along the formation of carrier accommodating layer 102 in carrier layer 105.The sub- bearing bed 105 of intermediate current-carrying can have material identical with epitaxial layer 78 Material.The sub- bearing bed 105 of intermediate current-carrying can be grown to provide the interface with carrier accommodating layer 102, and defect concentration is not lower than The case where bearing bed 105 sub- using intermediate current-carrying.It, can be before carrier accommodating layer 102 according to the embodiment of the disclosure It is formed separate layer 107 (similar to the separate layer 95 described before), carrier accommodating layer 102 is then grown on separate layer 107.
Concept
This disclosure relates at least following concept:
A kind of semiconductor devices of concept 1., including vertically oriented 2DEG layer, comprising: the face ontology M- self-supporting III group nitrogen Compound material substrate (nonpolarity)；The face the M- group III-nitride grown on the III-nitride material substrate of the face the ontology M- Epi layers of material；Along the groove of III-nitride material Epi layers of the polarity C- facet etch in the face M-；Using monocrystalline AlGaN (or GaN/AlGaN the 2DEG that selective epitaxial regrowth) vertically forms beside the groove.
The semiconductor devices of 2. concept 1 of concept, wherein the III-nitride material is GaN.
The semiconductor devices of 3. concept 1 of concept, including horizontal-extending channel and grid.
The semiconductor devices of 4. concept 1 of concept, including vertically extending channel and grid.
A kind of method for preparing semiconductor devices of concept 5., the semiconductor devices have vertically oriented 2DEG layer, institute The method of stating includes: to provide the face n+M- Free-standing GaN substrate；Outside the unintentional doping GaN of grown on top of the face n+M- GaN substrate Prolonging layer makes UID epitaxial gan layers that there is similar m- faceted crystal to arrange；Groove, the groove are etched in UID epitaxial gan layers Extend along the face C- from the surface of the UID epitaxial gan layers to n+ substrate transverse；At least one III group is formed in the groove The regrowth of nitride layer；Deposition or the suitable passivation layer deposition of regrowth are so that the layer of regrowth stops；Form low ohm connect Touching area is to realize that source contacts；Deposition or regrowth insulating materials are on the surface of stacked structure to form gate insulating layer；In grid The suitable grid material of the deposited on top of pole insulating layer makes the grid material and n+ source region and UID epitaxial gan layers and edge The overlapping of both interfaces between at least one Ill-nitride layer of the wall regrowth of the groove.
Concept 6: the method for concept 5, wherein the depth that the groove extends is enough to penetrate the n+ substrate.
Concept 7: the method for concept 5, wherein the depth that the groove extends was enough at the n+ substrate/interface UID end Only.
Concept 8: the method for concept 5, wherein the groove does not reach the n+ substrate/interface UID.
Concept 9: the method for concept 5, wherein the regrowth includes that AlGaN layer is heterogeneous to be formed with the side wall of n-GaN Structure.
Concept 10: the method for concept 5, wherein the regrowth includes the GaN/AlGaN grown on the side wall in the area n-GaN So that the GaN layer of regrowth will be with the good quality compared with low-defect-density in GaN/AlGaN stacked structure.
Concept 11: the method for concept 5, wherein the regrowth includes the laterally stacked structure of GaN/AlN/AlGaN.
Concept 12: the method for concept 5, wherein the passivation step includes PECVD, LPCVD or MOCVD nitride One of (Si3N4).
Concept 13: the method for concept 5, wherein to the injection of the high dose of donor type species such as silicon masking particle then into Row RTA step is used to form source contact.Optionally, patterned region, and the selective epitaxial of n+GaN are etched in source region Regrowth is used to form source contact.
Concept 14: the method for concept 5 further comprises forming drain contact on the bottom surface of substrate.
A kind of HEMT device of concept 15., comprising: III-nitride material substrate, the III-nitride material substrate Surface along the plane not parallel with the face C- of the III-nitride material；The III group nitridation grown over the substrate The epitaxial layer of object material；The groove etched in the epitaxial layer, the groove have the uneven surface with the substrate At least one capable planar wall；At least one described planar wall is parallel with the polar plane of the III-nitride material；Institute At least one the carrier accommodating layer formed at least part of at least one planar wall of groove is stated, so that along described Described at least part of at least one planar wall of groove forms the area 2DEG；The shape at the surface of the epitaxial layer At doping source region the doping source region is separated with the area 2DEG by the channel region of the epitaxial layer；In the epitaxial layer The channel region on the gate insulating layer that is formed；The gate contact layer formed on the gate insulating layer.
The HEMT device of 16. concept 15 of concept, wherein the grid and channel region are parallel to the surface of the substrate Extend.
The HEMT device of 17. concept 15 of concept, wherein the grid and channel region be parallel to the groove it is described at least One planar wall extends.
The HEMT device of 18. concept 16 or 17 of concept, wherein at least one described carrier accommodating layer is in the groove It is formed such that the channel region along the epitaxial layer forms another area 2DEG in a part of at least one planar wall.
The HEMT device of 19. concept 15-18 of concept, wherein at least one described planar wall of the groove be parallel to it is described The face C- of III-nitride material.
The HEMT device of 20. concept 15-19 of concept, wherein at least one described planar wall of the groove is perpendicular to described The surface of substrate.
The HEMT device of 21. concept 20 of concept, wherein the surface of the substrate is along the III-nitride material The face M-.
The HEMT device of 22. concept 20 of concept, wherein the surface of the substrate is along the III-nitride material The face A-.
The HEMT device of 23. concept 15-22 of concept, wherein the III-nitride material substrate is self-supporting III group nitrogen Compound material substrate.
The HEMT device of 24. concept 15-23 of concept, wherein the III-nitride material is GaN.
The HEMT device of 25. concept 15-24 of concept, wherein the carrier accommodating layer includes epitaxy single-crystal AlGaN, extension One of monocrystalline GaN/AlGaN and epitaxy single-crystal AlN.
The HEMT device of 26. concept 15-25 of concept, wherein the carrier accommodating layer is included in the group III-nitride The separate layer formed on material epitaxial layers and the barrier layer formed on the separate layer.
The HEMT device of 27. concept 15-26 of concept, wherein the carrier accommodating layer is in the III-nitride material Growth on epitaxial layer so that the area 2DEG in the III-nitride material of extension along at least one is flat described in the groove At least part of surface faced the wall and meditated is formed.
A kind of method for preparing HEMT device of concept 28., which comprises III-nitride material substrate, institute are provided The surface of III-nitride material substrate is stated along the plane not parallel with the face C- of the III-nitride material；Described The epitaxial layer of III-nitride material is grown on substrate；The etched recesses in the epitaxial layer, the groove have and the lining At least one planar wall of the uneven surface row at bottom；At least one described planar wall and the III-nitride material Polar plane is parallel；The confession of at least one carrier is formed at least part of at least one planar wall described in the groove Answer floor that at least part of surface along at least one planar wall described in the groove is made to form the area 2DEG；Described Doping source region is formed at the surface of epitaxial layer, so that the doping source region and the area 2DEG are by the channel of the epitaxial layer It separates out；Gate insulating layer is formed on the channel region of the epitaxial layer；Grid is formed on the gate insulating layer Contact layer.
The method of 29. concept 28 of concept, wherein the surface that the grid and channel region are parallel to the substrate extends.
The method of 30. concept 28 of concept, wherein the grid and channel region be parallel to the groove it is described at least one Planar wall extends.
The method of 31. concept 28-30 of concept, in a part including at least one planar wall described in the groove At least one described carrier accommodating layer makes the channel region along the epitaxial layer form another area 2DEG.
The method of 32. concept 28-31 of concept, wherein at least one described planar wall is parallel to the group III-nitride material The face C- of material.
The method of 33. concept 28-32 of concept, wherein at least one described planar wall of the groove is perpendicular to the substrate The surface.
The method of 34. concept 28-33 of concept, wherein the surface of the substrate is along the III-nitride material The face M-.
The method of 35. concept 28-33 of concept, wherein the surface of the substrate is along the III-nitride material The face A.
The method of 36. concept 28-35 of concept, wherein the III-nitride material substrate is self-supporting group III-nitride Material substrate.
The method of 37. concept 28-36 of concept, wherein the III-nitride material is GaN.
The method of 38. concept 28-37 of concept, wherein the carrier accommodating layer includes epitaxy single-crystal AlGaN, epitaxy single-crystal One of GaN/AlGaN and epitaxy single-crystal AlN.
The method of 39. concept 28-38 of concept, wherein forming the carrier accommodating layer is included in the group III-nitride Separate layer is formed on material epitaxial layers and forms barrier layer on the separate layer.
The method of 40. concept 28-39 of concept, wherein at least part of at least one planar wall described in the groove At least one carrier accommodating layer described in upper formation includes growing the carrier on the III-nitride material epitaxial layer Accommodating layer makes in the III-nitride material of extension along described at least one planar wall described in the groove at least one Partial surface forms 2DEG.
It should be noted compared with known transverse direction HEMT, as unit grid away from reduction as a result, according to the pole HEMT of the disclosure The earth improves the scalability to high current bearing capacity.In fact, due to current capacity, defect concentration and blocking ability In conjunction with expanding to high current ability not in lateral GaN HEMT is a minor issue.It can be seen that broad area device cannot It enough supports high-breakdown-voltage, and utilizes identical design rule/technology, according to the relatively small-area devices of the embodiment of the disclosure It can support high-breakdown-voltage.
It should be noted that will apply suitable for high voltage gan device according to the HEMT of the embodiment of the disclosure includes electronic vapour Vehicle, truck, traction application, ultra-high-tension power transmission line and the naval's application for wherein requiring efficient power to switch.Discrete power device Overall market capacity expects the year two thousand twenty and reaches 20,000,000,000 dollars.Wherein HV GaN HEMT can be used as the market HV of target to 2020 Year is estimated as 8,000,000,000 dollars.Due to the elite clone characteristic of GaN HEMT, it is inserted into the power device based on GaN in the applications described above Part has significant interest for automaker and the energy and national defense industry.Further, recognized based on the power device of GaN To be the prime candidate for leading the future route figure of energy-conserving product.1300V blocking ability is being required according to the HEMT of the disclosure Application in it is especially useful, for example, the electrification for next-generation vehicle.Reduced requirement and beauty are discharged for CO2 in the whole world State, which is reduced, is driving to the energy-saving semiconductor for being better than existing silicon device in performance the motive force of the dependency degree of foreign oil The market motive force of device, the energy-saving semiconductor device will be cannot be by the smaller strip gaps of the power device based on silicon (Eg=1.1eV) it is operated under the higher temperature born.
Itd is proposed above to the description of the preferred embodiments of the invention for the purpose of illustration and description.It is not It is intended to exhausted or limits the invention to disclosed precise forms or exemplary implementation scheme.It is special clearly for this field Many remodeling and variation will be apparent for industry technical staff.Similarly, any process steps can be with it He exchanges to reach identical result at step.Selection and description embodiment so as to best explain the principle of the present invention and its The best mode of practical application so that others skilled in the art it will be appreciated that various embodiments of the present invention and Various remodeling suitable for the concrete application or embodiment that are considered.
For example, being normally closed device about Fig. 6 and Fig. 7 HEMT illustrated.However, the embodiment of the disclosure further includes normal open (depletion-mode) HEMT.
The scope of the present invention is intended to by attached claims and its equivalents.It is no except non-clearly illustrating It then refers to that the element of odd number is not intended to indicate " one and only one ", but indicates " one or more ".Moreover, in the disclosure Whether any element, component or method and step are not intended to contribute to the public, no matter clearly state in the following claims The element, component or method and step.Any claim elements of this paper should not according to 35U.S.C.Sec.112, the 6th section Regulation is explained, unless the element technically uses phrase " device being used for ... " to state.
It should be understood that the attached drawing illustrated in attachment only proposes to highlight function of the invention for illustrative purpose It can property and the advantages of endeavouring.Framework of the invention is sufficiently flexible and can configure, and is made it possible to be different from attached drawing Shown in mode be utilized (and manipulation).
In addition, the purpose that front is made a summary is so that U.S.Patent & Trademark Office and being unfamiliar with patent or law term or wording General public, and especially scientist, engineer and this field practitioner can quickly move through rough close examination energy really Determine the essence and marrow of the technology disclosure of the application.Abstract is not intended to have limitation to the scope of the present invention in any way Property.It is also to be understood that the method and process quoted from the claims do not need to execute by given order.
In addition, should be noted that embodiment can be described as being plotted as flow chart, flow diagram, structure chart or block diagram Process.Although flow chart can describe the operations as sequential process, many operations can concurrently or be performed simultaneously.Separately Outside, the order of operation can rearrange.A process terminates when its operations are completed.Process can correspond to method, function, Step, subroutine, subprogram etc..When process corresponds to function, terminates to be back to corresponding to function and call function or main letter Number.
Under the premise of without departing substantially from the present invention, the various features of invention as described herein can be real in different systems It applies.It should notice that the embodiment of front is only embodiment and is not necessarily to be construed as the limitation present invention.Embodiment is retouched It states and is intended to be illustrative, and do not limit the scope of the claims.Similarly, this introduction can be readily applied to other classes The device of type and many alternatives, remodeling and version are obvious to those skilled in the art.It is excellent Selection of land includes all component, assembly unit and step as described herein.It should be understood that each of these component, assembly units and step It can be replaced by other elements, component and step or remove together, as would be apparent to one skilled in the art.
Broadly, disclosed herein is HEMT devices comprising III-nitride material substrate, the group III-nitride material Expect the surface of substrate along the plane not parallel with the face C- of the III-nitride material；The III grown over the substrate The epitaxial layer of group nitride material；The groove etched in the epitaxial layer, the groove have and the group III-nitride material At least one parallel planar wall of the polar plane of material；The carrier supply formed on a part of planar wall of the groove Layer, so that the part planar wall along the groove forms the area 2DEG；The doped source formed at the surface of the epitaxial layer Area separates the doping source region by the channel region of the epitaxial layer with the area 2DEG；In the channel of the epitaxial layer The gate insulating layer formed in area；The gate contact layer formed on the gate insulating layer.

Claims (20)

1. a kind of HEMT device, comprising:
III-nitride material substrate, the surface of the substrate is along not parallel with the face C- of the III-nitride material Plane；
The extension list material layer of the III-nitride material grown on the surface of the substrate；
The groove etched in the extension list material layer, the groove have at least one with the uneven surface row of the substrate A planar wall；At least one described planar wall is parallel with the polar plane of the III-nitride material；
At least one carrier accommodating layer formed in a part of at least one planar wall described in the groove, so that edge Partially formed first area 2DEG of at least one planar wall of the groove；
The doping source region formed at the surface of the extension list material layer, so that the doping source region and the first area 2DEG It is separated by the channel region of the extension list material layer, the surface that the doping source region is parallel to the substrate extends up to described recessed At least one described planar wall of slot；
The gate insulating layer formed on the channel region of the extension list material layer；With
The gate contact layer formed on the gate insulating layer；
Wherein, shape on another part of at least one carrier accommodating layer at least one planar wall described in the groove At so that the channel region along the extension list material layer forms another area 2DEG.
2. HEMT device described in claim 1, wherein the gate contact layer is along described in the groove, at least one is flat The a part faced the wall and meditated is arranged in the groove, and the channel region is along at least one planar wall described in the groove Described a part is parallel to the gate contact layer and extends.
3. HEMT device of any of claims 1 or 2, wherein at least one described planar wall of the groove be parallel to it is described The face C- of III-nitride material.
4. HEMT device as claimed in claim 3, wherein at least one described planar wall of the groove is perpendicular to the substrate Surface.
5. HEMT device as claimed in claim 4, wherein M- of the surface of the substrate along the III-nitride material Face.
6. HEMT device as claimed in claim 4, wherein A- of the surface of the substrate along the III-nitride material Face.
7. HEMT device of any of claims 1 or 2, wherein the III-nitride material substrate is the nitridation of self-supporting III group Object material substrate.
8. HEMT device of any of claims 1 or 2, wherein the III-nitride material is GaN.
9. HEMT device of any of claims 1 or 2, wherein the carrier accommodating layer includes epitaxy single-crystal AlGaN, extension list One of brilliant GaN/AlGaN and epitaxy single-crystal AlN.
10. HEMT device of any of claims 1 or 2, wherein the carrier accommodating layer is included in the group III-nitride material Expect the separate layer formed and the barrier layer formed on the separate layer on epitaxial layer.
11. a kind of method for preparing HEMT device, which comprises
III-nitride material substrate is provided, the surface of the substrate is along the III-nitride material with the substrate The not parallel plane in the face C-；
The extension list material layer of III-nitride material is grown on the surface of the substrate；
The etched recesses in the extension list material layer, the groove have at least one with the uneven surface row of the substrate Planar wall；At least one described planar wall is parallel with the polar plane of the III-nitride material of the substrate；
At least one carrier is formed in a part of at least one planar wall described in the groove
Accommodating layer makes the surface of described a part along at least one planar wall described in the groove
Form the first area 2DEG；
Doping source region is formed at the surface of the extension list material layer, the surface that the doping source region is parallel to the substrate is prolonged It stretches at least one planar wall described in the groove, so that the doping source region and the first area 2DEG are by the extension The channel region of single material layer separates；
Gate insulating layer is formed on the channel region of the extension list material layer；With
Gate contact layer is formed on the gate insulating layer；
Wherein the method includes described at least one is formed on another part of at least one planar wall described in the groove A carrier accommodating layer makes the channel region along the extension list material layer form another area 2DEG.
12. method described in claim 11, wherein the gate contact layer is along at least one plane described in the groove A part of wall is arranged in the groove, and the channel region is along the institute of at least one planar wall described in the groove It states a part and is parallel to the gate contact layer extension.
13. method described in claim 11 or 12, wherein at least one described planar wall is parallel to the group III-nitride material The face C- of material.
14. method described in claim 11 or 12, wherein at least one described planar wall of the groove is perpendicular to the lining The surface at bottom.
15. method of claim 14, wherein M- face of the surface of the substrate along the III-nitride material.
16. method of claim 14, wherein A face of the surface of the substrate along the III-nitride material.
17. method described in claim 11 or 12, wherein the III-nitride material substrate is the nitridation of self-supporting III group Object material substrate.
18. method described in claim 11 or 12, wherein the III-nitride material is GaN.
19. method described in claim 11 or 12, wherein the carrier accommodating layer includes epitaxy single-crystal AlGaN, extension list One of brilliant GaN/AlGaN and epitaxy single-crystal AlN.
20. method described in claim 11 or 12, wherein forming the carrier accommodating layer is included in the group III-nitride Separate layer is formed on material epitaxial layers and forms barrier layer on the separate layer.
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