JP2009168901A - Image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify manufacturing processes of a display device and to reduce manufacturing costs thereof which inverts the polarity of a display signal at a specified period. <P>SOLUTION: The display device 10A includes a gate line drive circuit 11 driving a gate line GL to which a pixel 25 is connected, a capacity line drive circuit 12 performing capacitive coupling driving of the pixel 25 using the capacity line CCL, and a frequency dividing circuit 20 generating polarity control signals VFR and /VFR as control signals for making the capacity line drive circuit 12 perform operation corresponding to the polarity of the display data signal D. All the transistors constituting the gate line drive circuit 11, capacity line drive circuit 12, and frequency dividing circuit 20 are of the same conductivity type. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image display device that performs pixel drive control that makes it possible to reduce the amplitude of a display signal, and more particularly, to an image display device that includes a display panel that includes field effect transistors of the same conductivity type. Is.

  As a pixel driving method for reducing power consumption of a liquid crystal display device, a “capacitive coupling driving technique” is known. In capacitive coupling driving, the pixel electrode in each pixel is capacitively coupled to a predetermined signal line, and a display signal (display data) is written to the pixel electrode, and then the potential of the predetermined signal line is changed to change the potential of the pixel electrode. Is adjusted appropriately (for example, Patent Documents 1 and 2 below).

  For example, the potential of the pixel electrode to which the positive polarity (+) display signal is written is increased (changes in the positive direction), and the potential of the pixel electrode to which the negative polarity (−) display signal is written is decreased (in the negative direction). Display signal can be amplified. As a result, the amplitude of the display signal supplied to the data line (source line) can be reduced, and the power consumed by the data line can be reduced. In addition, since the amplitude of the display signal is reduced, the amplitude of the drive signal for the scanning line (gate line) can also be reduced.

  Patent Document 1 shows an example in which a capacitor line (CC) for exclusively performing capacitive coupling driving of pixels is used as the predetermined signal line. Further, from the viewpoint of simplification of the process and cost reduction, all the transistors constituting the driving circuit (compensation signal driving circuit) for driving the capacitor line used for capacitive coupling driving of the pixels are all of the same conductivity type (P type). ) Is suggested.

  Patent Document 2 shows an example in which a gate line of a pixel line (pixel row) adjacent to the pixel is used as the predetermined signal line. That is, the capacitive coupling drive of Patent Document 2 is executed by changing the inactive level potential of the gate line drive signal of the adjacent pixel line.

  In a liquid crystal display device, in general, the polarity of a display signal is inverted at a constant period in order to prevent deterioration of a liquid crystal element. That is, the polarity of the display signal supplied to the data line is changed in an alternating manner with reference to the potential of the common electrode (common electrode) to which one end of the liquid crystal element of each pixel is connected. In a display device that performs capacitive coupling driving, when the polarity of a display signal is inverted at a constant period, the direction in which the potential of the predetermined signal line is changed (positive direction or in accordance with the period at which the polarity of the display signal is inverted). It is necessary to reverse the negative direction.

  As a driving method for inverting the polarity of a display signal at a constant period, a “common inversion driving technique” in which the potential of the common electrode itself is changed in an alternating manner is known (for example, Patent Documents 3 and 6 below). In this method, before writing a display signal to the pixel electrode, the voltage applied to the liquid crystal element connected between the pixel electrode and the common electrode is changed by appropriately changing the potential of the common electrode in accordance with the polarity of the display signal. Adjust appropriately.

  For example, when a display signal is written by writing a positive (+) display signal to a pixel, the common electrode is set to a negative polarity, and a common electrode for writing a negative (−) display signal is set to a positive polarity. In addition, the voltage applied to the liquid crystal element can be increased. As a result, the amplitude of the display signal supplied to the data line can be reduced, and the amplitude of the gate line drive signal can also be reduced.

  Patent Documents 3 and 4 disclose “line-independent common AC drive method” in which the potential of the common electrode is changed in an AC manner independently for each pixel line (each gate line) as one of the common inversion drives. Yes. The independent common AC driving technology for each line is mainly used in an IPS (In Plane Switching) liquid crystal display panel, and the potential of the common electrode is set independently for each gate line in accordance with the polarity of the display signal written to the pixel. Is. This technique is known as a technique that can reduce the power consumption by reducing the amplitude of the display signal and the gate line driving signal, and can improve the reliability of the transistors used in the gate line driving circuit.

  In addition, as prior art relevant to this invention, the following patent documents 5 and 6 are mentioned, for example.

JP 2003-228345 A JP-A-2-913 JP 2006-276541 A JP-A-10-31464 JP 2004-103226 A JP 2003-295157 A

  As described above, in the liquid crystal display device, the polarity of the display signal is inverted at a constant period. In that case, in both the capacitive coupling driving technique and the common AC driving technique, the positive / negative (polarity) of the potential of the pixel electrode with respect to the potential of the common electrode is switched (alternated) in that cycle. Therefore, it is necessary to supply a control signal (polarity control signal) for performing an operation corresponding to a change in the polarity of the display signal to a circuit that performs such a driving method. More generally, the polarity of the display signal is inverted every frame, and a signal whose level is inverted every frame can be used as the polarity control signal in that case.

  Such a polarity control signal can be supplied from the outside of the display device, but it is necessary to set the level of the polarity control signal so as to match the operating voltage of the display device. For this reason, a level shifter for performing the setting is required separately, which causes a problem of increasing the manufacturing cost of the display device.

  It is conceivable to install a polarity control signal generation circuit inside the display device. In that case, from the viewpoint of simplification of the process and cost reduction, the transistor used in the generation circuit is a pixel or gate line driving circuit. It is desirable that they are all of the same conductivity type as used in the above. Furthermore, it is more preferable that the drive circuit that performs capacitive coupling drive and common AC drive is also configured using only the same conductivity type transistors.

  The present invention has been made to solve the above problems, and in a display device in which the polarity of a display signal is inverted at a specific period, capacitive coupling driving or common AC driving according to a change in the polarity of the display signal. And a generation circuit of a control signal (polarity control signal) for causing the drive circuit to perform an operation in accordance with the polarity of the display signal are realized by a circuit using only transistors of the same conductivity type. With the goal.

  The image display device according to the first aspect of the present invention includes a plurality of scanning lines arranged in parallel to each other, a plurality of signal lines arranged orthogonal to the plurality of scanning lines, A plurality of capacitance lines disposed along each of the plurality of scanning lines, a plurality of pixels disposed near intersections of the scanning lines and the signal lines, and the plurality of scanning lines for each frame. A scanning line driving circuit that scans and drives in order, and a capacitive line driving circuit that drives the plurality of capacitive lines, and generates a control signal having a period obtained by dividing the start signal corresponding to the start of the frame. And a pixel active element having a control circuit connected to the corresponding scanning line and one current electrode connected to the corresponding signal line, and the other current electrode of the pixel active element. A pixel electrode, a corresponding capacitor line and the image Each of the plurality of pixels corresponding to each of the plurality of pixels at a predetermined timing after an active period of the pixel active element. The active elements that change the potential of the capacitor line based on the control signal and constitute the scanning line driver circuit, the capacitor line driver circuit, and the frequency divider circuit are all of the same conductivity type as the pixel active element. It is characterized by that.

  An image display device according to a second aspect of the present invention includes a plurality of scanning lines arranged in parallel to each other, a plurality of signal lines arranged orthogonal to the plurality of scanning lines, and the scanning line. And a plurality of pixels arranged in the vicinity of each intersection of the signal lines, a scanning line driving circuit for sequentially scanning the plurality of scanning lines for each frame, and a start signal corresponding to the start of the frame A pixel active element having a frequency dividing circuit for generating a control signal having a frequency divided, and the pixel having a control electrode connected to the corresponding scanning line and one current electrode connected to the corresponding signal line A pixel electrode connected to the other current electrode of the pixel active element, and a capacitive element connected between the scanning line adjacent to the corresponding scanning line and the pixel electrode, the scanning line driving circuit For each frame For each pixel, at a predetermined timing after the active period of the pixel active element, the potential of the inactive level of the adjacent scanning line is changed based on the control signal, and the scanning line driving circuit and the frequency dividing circuit are changed. The active elements constituting the circuit are all of the same conductivity type as the pixel active element.

  An image display device according to a third aspect of the present invention includes a plurality of scanning lines arranged in parallel to each other, a plurality of signal lines arranged orthogonal to the plurality of scanning lines, A plurality of common electrode lines disposed along each of the plurality of scanning lines, a plurality of pixels disposed in the vicinity of intersections of the scanning lines and the signal lines, and the plurality of scanning lines for each frame A control signal having a period obtained by dividing the start signal corresponding to the start of the frame, and a scanning line driving circuit that sequentially scans and drives the common electrode line driving circuit that drives the plurality of common electrode lines. A frequency dividing circuit to be generated, a pixel active element having a control electrode connected to the corresponding scanning line and one current electrode connected to the corresponding signal line, and the other current electrode of the pixel active element The pixel electrode connected to the A display element connected between the common electrode line and the pixel electrode, the common electrode line driving circuit for each of the plurality of pixels for each frame before the active period of the pixel active element. At a predetermined timing, the potential of the corresponding common electrode line is changed based on the control signal, and the active elements constituting the scanning line driving circuit, the common electrode line driving circuit, and the frequency dividing circuit are all active in the pixel. It is of the same conductivity type as the element.

  According to the present invention, a driving circuit (capacitive line driving circuit, gate line driving circuit or common electrode line driving circuit) that performs capacitive coupling driving or common AC driving, and a frequency dividing circuit that generates a control signal that defines the operation thereof are provided. Since it is realized by using only a transistor having the same conductivity type as the pixel active element, it becomes easy to form the driving circuit and the frequency dividing circuit on the same insulating substrate as the pixel. As a result, the number of display panel formation steps can be reduced, which can contribute to simplification of the manufacturing process of the image display device and reduction of manufacturing costs.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in order to avoid duplication and redundant description, elements having the same or corresponding functions are denoted by the same reference symbols in the respective drawings.

<Embodiment 1>
Hereinafter, specific embodiments of the present invention will be described. To facilitate the understanding of the present invention, first, a conventional drive control circuit and a gate line drive circuit will be described. FIG. 1 is a block diagram illustrating a configuration example of a conventional liquid crystal display device 10.

  In the display device 10, liquid crystal pixels 25 (PX) formed on an insulating substrate such as glass or resin are arranged in a matrix. FIG. 2 shows a specific configuration example of the pixel 25. As shown in the figure, the pixel 25 is a liquid crystal pixel in which a liquid crystal element 28 is used as a display element. Further, an N-channel TFT (Thin Film Transistor) is used for the pixel transistor 26 (active element in a broad sense) included in the pixel 25.

  The N-type TFT is activated (ON) when the gate is at the H (High) level relative to the source, and is also deactivated (OFF) at the L (Low) level. Therefore, in the following description, the signal H level is described as an active level and the L level is described as an inactive level. In the case of a P-type transistor, an active (ON) state is obtained when the gate is at the L level with respect to the source, and an inactive (OFF) state is also obtained at the H level (the relationship between signal activation and inactivation is reversed). .

The pixel 25 is orthogonal to a plurality (m) of gate lines (scan lines in a broad sense) GL ₁ , GL ₂ ,..., GL _m (generically “gate lines GL”) arranged in parallel to each other. , DL _r (generally “data lines DL”) are provided in the vicinity of intersections of a plurality of (r) data lines (signal lines in a broad sense) DL ₁ , DL ₂ ,. The gate lines GL ₁ , GL ₂ ,..., GL _m are respectively driven by gate line drive signals G ₁ , G ₂ ,..., G _m (generic name “gate line drive signal G”) generated by the gate line drive circuit 101. The The data lines DL _1, DL _2, ..., the DL _r, viewed from the drive control circuit 110 the data signals _{D 1, D 2, ...,} D r ( collectively, "display data signal D") are supplied. That is, each of the pixels 25 is driven by the gate line GL generated by the gate line driving circuit 101, and performs display according to the display data signal D from the drive control circuit 110.

  As shown in FIG. 2, the gate of the pixel transistor 26 is connected to the gate line GL, and the drain of the pixel transistor 26 is connected to the data line DL. The source of the pixel transistor 26 is connected to the pixel electrode Np. A storage capacitor element 27 and a liquid crystal element 28 are connected to the pixel electrode Np. The storage capacitor element 27 is connected between the pixel electrode Np and the storage electrode Nh, and the liquid crystal element 28 is connected between the pixel electrode Np and a common electrode (common electrode) Nc.

  In the pixel 25, when the gate line driving signal G for driving the corresponding gate line GL becomes the active level (H (High) level), the pixel transistor 26 is turned on, and at that time, the display data signal D supplied to the data line DL. Is held in the holding capacitor element 27. The orientation of the liquid crystal in the liquid crystal element 28 changes according to the data (voltage) held in the holding capacitor element 27, and the display luminance of the pixel changes.

  That is, in the pixel 25, the orientation of the liquid crystal in the liquid crystal element 28 changes according to the potential difference between the pixel electrode Np and the common electrode Nc, and the display luminance of the liquid crystal element 28 changes in response to this. Therefore, the luminance of each pixel can be controlled by the voltage (display voltage) of the display data signal D supplied to the pixel electrode Np. That is, intermediate luminance can be obtained by applying an intermediate potential difference between the pixel electrode Np and the common electrode Nc between the potential difference corresponding to the maximum luminance and the potential difference corresponding to the minimum luminance. Therefore, gradational luminance can be obtained by setting the voltage of the display data signal D in a stepwise manner.

Referring to FIG. 1 again, the drive control circuit 110 is composed of a single or a plurality of LSIs formed using a single crystal silicon substrate. The drive control circuit 110 is a source driver circuit (data signal output circuit) for outputting display data signals D ₁ , D ₂ , D ₃ ,... To be written to the pixels 25 to the data lines DL ₁ , DL ₂ , DL ₃ ,. The circuit includes a drive control signal generation circuit necessary for operating the line drive circuit 101, a power supply circuit for generating a power supply voltage, and the like.

  The drive control circuit 110 also includes a level shifter 111 that is also formed using a single crystal silicon substrate. The level shifter 111 shifts the level of the drive control signal (start signal st and clock signals clk, / clk) generated by the drive control circuit 110 to have a voltage level signal suitable for driving the gate line drive circuit 101 ( Start signal ST and clock signals CLK, / CLK).

  The drive control signal supplied to the gate line drive circuit 101 by the drive control circuit 110 including the level shifter 111 (hereinafter simply referred to as “drive control circuit 110”) includes the start signal ST and the clock signals CLK and / CLK. Yes. The start signal ST is a pulse signal that is activated at a timing corresponding to the start of each frame of the image signal. The clock signals CLK and / CLK are complementary signals (the active periods do not overlap), and the operation timing of the gate line driving circuit 101 is defined by the clock signals CLK and / CLK.

That is, when the pixel matrix of the liquid crystal array unit 15 is driven by the gate line driving circuit 101, the drive control circuit 110 activates the start signal ST at the timing when the scanning of the gate line GL is started. The gate line driving circuit 101 activates the start signal ST and activates the gate line driving signals G ₁ , G ₂ , G ₃ ,... In this order in synchronization with the activation timing of the clock signals CLK, / CLK. Make it.

  FIG. 3 is a timing chart showing the relationship between the drive control signal output from the drive control circuit 110 and the operation of the gate line drive circuit 101. As shown in FIG. 3, each of the clock signals CLK and / CLK is a pulse signal that is activated with a period of two horizontal periods (2H) of the display device 10, and both are in phase with each other by one horizontal period (1H). Is shifted. That is, the two clock signals CLK and / CLK constitute a two-phase clock that is shifted in phase by one horizontal period.

As shown in FIG. 3, the drive control circuit 110 activates the start signal ST at time t ₀ corresponding to the start of the frame period. The start signal ST is inactivated at time t ₁ immediately after that, and is maintained in an inactive state until the next frame period. The drive control circuit 110 activates the clock signal CLK at a time t ₂ delayed by one horizontal period (1H) from the time t ₀ , and further at a time t ₄ delayed by one horizontal period (1H) from the time t _2. Activate CLK. Thereafter, the clock signals CLK and / CLK are alternately activated every horizontal period.

The gate line driving circuit 101 includes a plurality of cascade-connected shift registers (multi-stage shift registers), and gate line driving signals G ₁ , G ₂ , G ₃ ,. Hereinafter, each stage of the multistage shift register is referred to as a “unit shift register”). The start signal ST is input to the first stage unit shift register. The signals are sequentially transmitted from the first stage to the subsequent stage while being temporally shifted in synchronization with the clock signals CLK and / CLK. As a result, gate line drive signals G ₁ , G ₂ , G ₃ ,... Are output in this order from the gate line drive circuit 101 at a timing synchronized with the clock signals CLK, / CLK. As a result, the operation of activating the gate lines GL ₁ , GL ₂ , GL ₃ ,... In this order is repeated every horizontal period.

  As a specific example of the unit shift register constituting the gate line driving circuit 101 (multistage shift register), an example of a unit shift register composed of transistors of the same conductivity type is disclosed in FIG. Has been.

  From here, the display device according to the present invention will be described. Embodiment 1 shows an example in which the present invention is applied to a display device using a capacitive coupling driving technique. As described above, as a capacitive coupling driving technique, a system using a capacitive line dedicated for capacitive coupling driving as a wiring for driving the capacitive coupling (Patent Document 1) and a system using both gate lines of adjacent pixel lines (Patent Document 1) Patent Document 2) is known, but this embodiment is applied to the former.

  That is, in this embodiment, a display line data signal written to the pixel electrode is provided by providing a capacitor line capacitively coupled to the pixel electrode of the pixel and supplying a signal (capacitor line drive signal) having a predetermined amplitude to the capacitor line. Adjust the level. Since the display data signal can be amplified by capacitive coupling driving, the amplitude of the display signal supplied to the data line can be reduced, and the power consumed by the data line can be reduced.

  FIG. 4 is a schematic block diagram showing the configuration of the display device 10A according to Embodiment 1 of the present invention. Here, a liquid crystal display device is shown as a representative example of a display device to which capacitive coupling driving can be applied.

The display device 10A includes a liquid crystal array unit 15, a gate line driving circuit (scanning line driving circuit in a broad sense) 11, a frequency dividing circuit 20, a drive control circuit 110, and a level shifter 111. The liquid crystal array unit 15 is composed of a plurality of pixels 25 arranged in a matrix, and gate lines GL ₁ , GL ₂ ,..., GL _m are arranged corresponding to each row (pixel line) of pixels. In addition, data lines DL ₁ , DL ₂ ,... Are arranged corresponding to each of the pixel columns (pixel columns). Further, the gate lines GL _1, GL _2, ..., along the respective GL _m, capacitance lines CCL _1, CCL _2, ..., CCL _m (collectively, "capacitance line CCL") is provided. In FIG. 4, the gate lines GL ₁ , GL ₂ , GL _{m of} the first row, the second row, and the last row, the capacitance lines CCL ₁ , CCL ₂ , CCL _m , the first column, The data lines DL ₁ and DL _{2 in} the second column and the six pixels 25 arranged at the intersections are representatively shown.

  In the present embodiment, as shown in FIG. 4, the gate line driving circuit 11 is disposed on one side (left side) of the liquid crystal array section 15, and the capacitance line driving circuit 12 is disposed on the other side (right side). The gate line driving circuit 11 and the capacitor line driving circuit 12 are configured by using TFTs formed on an insulating substrate in the same manner as the pixels 25. The arrangement of the gate line driving circuit 11 and the capacitor line driving circuit 12 is an example, and is not limited to this arrangement. For example, the gate line driving circuit 11 and the capacitor line driving circuit 12 may be integrated and disposed only on one side (left side or right side) of the liquid crystal array unit 15.

  When a circuit (integrated circuit) in which the gate line driving circuit 11 and the capacitor line driving circuit 12 are integrated is used, when the area of each pixel 25 is reduced in order to increase the resolution of the display device, It is also conceivable that the pitch of the unit circuits is larger than the pitch of the pixels 25. In that case, an integrated circuit is disposed on both sides of the liquid crystal array unit 15, and for example, when pixels in odd rows are driven by one integrated circuit and pixels in even rows are driven by the other integrated circuit. Good.

The basic operation of the gate line driving circuit 11 is the same as that of the conventional gate line driving circuit 101 of FIG. 1 (FIG. 3). However, the gate line driving circuit 11 in FIG. 4 is provided with unit shift registers SR _{m + 1} and SR _{m + 2 in} two stages following the m-th unit shift register (not shown) as the last stage. It has been. Since these unit shift registers SR _{m + 1} and SR _{m + 2} do not drive the gate line GL, they are hereinafter referred to as “dummy shift registers”. The output signals G _{m + 1} and G _{m + 2} of the dummy shift registers SR _{m + 1} and SR _{m + 2} do not drive the gate line GL, but are the same quality as the normal gate line driving signals G _{1 to} G _m. Therefore, they are referred to as “driving signals”.

  The drive control circuit 110 (including the level shifter 111) in FIG. 4 is configured by an LSI formed using a single crystal silicon substrate, similar to that shown in FIG. 1, and includes a drive control signal (start signal ST). And clock signals CLK and / CLK) are supplied to the gate line driving circuit 11. The drive control circuit 110 supplies a high potential side power supply potential VDD and a low potential side power supply potential VSS to each of these circuits as a power source for the gate line drive circuit 11, the capacitor line drive circuit 12 and the frequency divider circuit 20. .

The display device 10A has a frequency dividing circuit 20 that divides the frequency of the signal. The frequency dividing circuit 20 is configured by using a TFT formed on an insulating substrate like the pixel 25. As shown in FIG. 4, a start signal ST and clock signals CLK and / CLK are input from the drive control circuit 110 and a drive signal G _{m + 1} is input from the gate line drive circuit 11 to the frequency divider circuit 20. . The frequency dividing circuit 20 is driven by these four signals, and outputs a signal VFR having a doubled cycle of the start signal ST (that is, a frequency divided by 1/2) and a signal / VFR having its opposite phase. . As will be described later, the signals VFR and / VFR are used for capacitive line driving in accordance with the switching of the polarity of the potential of the pixel electrode Np of each pixel 25 (the polarity of the display data signal D written to the pixel 25). Since it is used as a control signal for causing the circuit 12 to perform, the signals VFR and / VFR are referred to as “polarity control signals”.

  Note that the number of phases of the clock signal generated by the drive control circuit 110 depends on the circuit configuration of the shift register included in the gate line drive circuit 11. In the present embodiment, description will be made assuming that the gate line driving circuit 11 is configured by a shift register driven by two-phase clock signals CLK and / CLK. However, three-phase or more clock signals are used. There may be. Basically, the power consumption of the clock signal generation circuit can be reduced as the number of phases of the clock signal is increased, but the number of level shifters 111 required naturally increases.

  In the following, an example in which a constant interval is provided between the active period of clock signal CLK (the period when it becomes H level) and the active period of clock signal / CLK as in FIG. 3 is shown. There is no need. That is, a two-phase clock may be used in which the clock signal / CLK falls simultaneously with the rise of the clock signal CLK, and the clock signal / CLK rises simultaneously with the fall of the clock signal CLK.

Since the start signal ST is a signal activated at a timing corresponding to the start of each frame period of the image signal, the polarity control signals VFR and / VFR obtained by doubling the start signal ST are generated every frame period of the image signal. The signal is inverted. The polarity control signals VFR and / VFR are both input to the capacitor line driving circuit 12. The capacity line drive circuit 12 is a circuit that generates capacity line drive signals CC _{1 to} CC _m (generally “capacitance line drive signal CC”) for driving the capacity lines CCL _{1 to} CCL _m . In the capacitor line drive circuit 12, the polarity control signals VFR and / VFR are used as control signals for switching the polarity of the capacitor line drive signal CC in accordance with the change in the polarity of the display data signal D.

  Next, the frequency dividing circuit 20 will be described. FIG. 5 is a circuit diagram showing a basic configuration of the frequency dividing circuit 20, and FIG. 6 is a timing chart showing its operation. First, the operation principle of the frequency dividing circuit 20 will be described based on these drawings.

  As shown in FIG. 5, the frequency dividing circuit 20 has switches SW1 and SW2 and circuits (inverters in a narrow sense) IV1, IV2, IV3 (first and second) having a function of outputting an output signal having a level inverted with respect to the input signal. 2 and the third inverter), and a holding circuit having a function of holding the levels of the nodes NA and NB, respectively. In FIG. 5, holding capacitors CH1 and CH2 are used as holding circuits. The holding capacitor CH1 is connected to the input node NA of the inverter IV1, and the holding capacitor CH2 is connected to the input node NB of the inverter IV2. Note that the holding capacitors CH1 and CH2 may be parasitic capacitors.

  In FIG. 5, input signals IS1 and IS2 are signals having the same period and different phases. The switches SW1 and SW2 operate so as to be turned on while the input signals IS1 and IS2 are at the H level, respectively.

Referring to FIG. 6, assume that node NE is at the H level at time t ₀ . At this time, when the input signal IS1 becomes H level and the switch SW1 is turned on at time t ₀ , the node NA becomes H level and the output node NB of the inverter IV1 becomes L level. That is, the inverter IV1 operates to output a signal obtained by inverting the output signal of the inverter IV3 to the node NB in synchronization with the input signal IS1. Although subsequent input signal IS1 at time t ₁ is back to L level switch SW1 is turned off, the node NA by the storage capacitor CH1 is held at H level. Therefore, node NB is held at the L level.

When the input signal IS2 at time t ₂ becomes the H level, the switch SW2 is turned on, the level of the node NC is the same L level as the node NB. As a result, the output node ND of the inverter IV2 becomes H level, and the output node NE of the inverter IV3 becomes L level. That is, the inverter IV2 operates to output a signal obtained by inverting the output signal of the inverter IV1 to the node ND in synchronization with the input signal IS2. Although the input signal IS2 at subsequent time t ₃ is back to L level switch SW2 is turned off, the node NC by the storage capacitor CH2 is because it is held at L level, node ND H level, the node NE is held at the L level The

After that, the relationship between the levels of the nodes is reversed, but the same operation as the above-described times t _{0 to} t ₃ is performed. That is, the switch SW1 input signal IS1 at time t ₄ becomes H level again is the turned on, the node NA becomes L level, the node NB becomes H level. The switch SW1 is input signal IS1 returns to L level at time t ₅ is also turned off, the holding capacitor CH1 holds the L level of the node NA. Therefore, node NB is held at the H level.

When the input signal IS2 at time t ₆ is H level, node NC H level switch SW2 is turned on, the node ND is at the L level, the node NE becomes H level. The switch SW2 input signal IS2 at time t ₇ is returned to L level even when turned off, the holding capacitor CH2 holds the node NC to the H level. Therefore, the nodes ND and NE are maintained at the L level and the H level, respectively.

Time t ₇ after the same operation as the time t ₀ ~t ₇ described above is repeated.

  Thus, according to the frequency dividing circuit 20 of FIG. 5, the levels of the nodes NA and NB are inverted every time the level of the input signal IS1 becomes H level, and the levels of the nodes ND and NE are respectively changed to the input signal IS2. Is inverted every time the level becomes H level. As a result, signals having a period twice that of the input signals IS1 and IS2 appear at the nodes NA to NE, respectively. In particular, the signals appearing at the nodes NA and NB are in phase with the input signal IS1, and the signals appearing at the nodes NC to NE are in phase with the input signal IS2.

  FIG. 7 is a diagram illustrating an example of a more specific circuit configuration of the frequency divider circuit 20 described in FIG. As shown in the figure, the frequency dividing circuit 20 is configured by using a single conductivity type (here, N type) TFT (hereinafter referred to as “transistor”).

  Note that the transistor used in the present invention is an insulated gate field effect transistor. In the insulated gate field effect transistor, the electric conductivity between the drain region and the source region in the semiconductor layer is controlled by the electric field in the gate insulating film. As a material of the semiconductor layer in which the drain region and the source region are formed, an organic semiconductor such as polysilicon, amorphous silicon, or pentacene, a compound semiconductor such as single crystal silicon or ZnO, or the like can be used.

  As is well known, each transistor has a control electrode (gate (electrode) in the narrow sense), one current electrode (drain (electrode) or source (electrode) in the narrow sense)), and the other current electrode (in the narrow sense, the drain (electrode) or the source (electrode)). In a narrow sense, it is an element having at least three electrodes including a source (electrode) or a drain (electrode). The transistor functions as a switching element in which a channel is formed between the drain and the source by applying a predetermined voltage to the gate. The drain and source of the transistor have basically the same structure, and their names are interchanged depending on the applied voltage condition. For example, in the case of an N-type transistor, an electrode having a relatively high potential is referred to as a drain, and a low electrode is referred to as a source (in the case of a P-type transistor, the opposite is true).

  In this specification, “connection” between two elements, between two nodes, or between one element and one node is a connection through other elements (elements, switches, etc.). Will be described as including a state that is substantially equivalent to a direct connection. For example, even if two elements are connected via a switch, if they can function in the same way as when they are directly connected, the two elements are “connected”. Express.

A configuration of the frequency dividing circuit 20 in FIG. 7 will be described. As described with reference to FIG. 4, the frequency dividing circuit 20 is supplied with the start signal ST, the drive signal G _{m + 1} and the clock signals CLK and / CLK, and the polarity control signals VFR, / CLK having a cycle twice that of the start signal ST. Outputs VFR. In addition to the above, a power-on reset signal POR is input to the frequency dividing circuit 20 in FIG. 7, and the signal will be described later.

Transistor Q1 and start signal ST correspond to switch SW1 and input signal IS1 in FIG. 5, respectively. The transistor Q1 functions to transmit the level of the node N8 to the node N1 based on the start signal ST input from the drive control circuit 110. In the present embodiment, as in the example of FIG. 3, the start signal ST is activated at the activation timing of the clock signal / CLK (as a result, the gate line drive signal G ₁ activates the clock signal CLK. Activated at the timing).

  The transistors Q2 to Q5 constitute a latch inverter 201 having both functions of an inverter that inverts the level of the node N1 and outputs it to the node N2, and a latch that holds the levels of the nodes N1 and N2. More specifically, the transistors Q4 and Q5 constitute an inverter having the node N1 as an input terminal and the node N2 as an output terminal, which corresponds to the inverter IV1 (first inverter) in FIG. The transistors Q2 and Q3 constitute an inverter having the node N2 as an input end and the node N1 as an output end. In other words, two inverters connected in a loop are formed by the transistors Q2 to Q5, and they function as a latch. The latch including the transistors Q2 to Q5 functions as a holding circuit similarly to the holding capacitor CH1 in FIG.

  In the frequency divider circuit 20 of FIG. 7, the holding circuit is not a capacitor element but a latch so that the levels of the nodes N1 and N2 can be stably held even when the operating cycle of the frequency divider circuit 20 is long. is there. The transistors Q7 and Q8 constitute a buffer 202 that is provided at the output stage of the inverter composed of the transistors Q5 and Q6 and increases the drive capability (current flow capability) of the inverter.

  The inverter 209 connected to the output node of the buffer 202 is an element that is not included in the basic configuration of the frequency divider shown in FIG. 5 and does not directly affect the logical operation of the frequency divider 20. Inverter 209 includes transistors Q27 and Q28, and outputs a signal obtained by inverting the output signal of buffer 202 to node N11.

The transistor Q9 corresponds to the switch SW2 in FIG. 5, and the drive signal _{Gm + 1} is input to the gate of the transistor Q9 (that is, the drive signal Gm _{+ 1} corresponds to the input signal IS2 in FIG. 5). . Transistor Q9 transmits the level of node N3 to node N4 based on drive signal Gm _{+ 1} . In this embodiment, it is assumed that the drive signal G _{m + 1} is activated at a timing synchronized with the clock signal CLK (that is, the gate line GL ₁ is activated in synchronization with the clock signal / CLK).

  Transistors Q10 to Q13 constitute a latch inverter 203 including an inverter that inverts the level of node N4 and outputs the inverted signal to node N5, and a latch that holds the levels of nodes N4 and N5. More specifically, the transistors Q12 and Q13 function as inverters corresponding to the inverter IV2 (second inverter) in FIG. 5, and the entire transistors Q10 to Q13 function as latches. The latch composed of the transistors Q10 to Q13 functions as a holding circuit similarly to the holding capacitor CH2 in FIG. Also in this case, the reason why the holding circuit is a latch rather than a capacitor is to stably hold the levels of the nodes N4 and N5 even when the operation cycle of the frequency dividing circuit 20 is long.

  Transistors Q14 and Q15 constitute a buffer 204 provided at the output stage of the inverter composed of transistors Q12 and Q13. The buffer 204 functions to increase the drive capability of the inverter composed of the transistors Q12 and Q13.

  On the other hand, the transistors Q22 and Q23 also constitute a buffer 208 provided at the output stage in order to increase the drive capability of the inverter composed of the transistors Q12 and Q13. In particular, the output buffer 208 functions as an output buffer for outputting the polarity control signal VFR from the frequency dividing circuit 20 (hereinafter, the buffer 208 is referred to as “output buffer 208”).

  The transistors Q16 and Q17 function as an inverter 205 that inverts the level of the node N6 and outputs it to the node N7. The inverter 205 serves as the inverter IV3 (third inverter) in FIG. Transistors Q18 and Q19 constitute a buffer 206 provided at the output stage in order to increase the drive capability of inverter 205.

  On the other hand, the transistors Q20 and Q21 also constitute a buffer 207 provided in the output stage in order to increase the drive capability of the inverter 205. In particular, the inverter 205 functions as an output buffer for outputting the polarity control signal / VFR from the frequency divider circuit 20 (hereinafter, the buffer 207 is referred to as “output buffer 207”).

  Here, the gate of the transistor Q4 that charges the node N2 in the latch inverter 201 and the gate of the transistor Q27 that charges the node N11 in the inverter 209 are connected to the input terminal of the clock signal / CLK. The gate of the transistor Q12 that charges the node N5 in the latch inverter 203 and the gate of the transistor Q16 that charges the node N7 in the inverter 205 are connected to the input terminal of the clock signal CLK.

  Further, the gate of the transistor Q2 charging the node N1 in the latch inverter 201 is connected to the output node (node N11) of the inverter 209, and the gate of the transistor Q10 charging the node N4 in the latch inverter 203 is connected to the inverter 205. Connected to the output node (node N7).

  A capacitive element C3 is connected between the input terminal of the clock signal CLK and the node N2 (the gate of the transistor Q7), and a capacitive element C4 is connected between the input terminal of the clock signal CLK and the node N11 (the gate of the transistor Q2). Is connected. The capacitive elements C3 and C4 function to boost the gate voltage of the transistor Q7 that charges the node N3 and the gate voltage of the transistor Q2 that charges the node N1 when the clock signal CLK rises.

  Capacitance element C1 is connected between the input terminal of clock signal / CLK and node N7 (the gates of transistors Q10, Q18, Q20), and the input terminal of clock signal / CLK and node N5 (the gates of transistors Q14, Q22) ) Is connected to the capacitive element C2. These capacitive elements C1 and C2 have the gate voltages of the transistors Q10, Q18, and Q20 charging the nodes N4, N8, and N9 and the gate voltages of the transistors Q14 and Q22 that charge the nodes N6 and N10 when the clock signal / CLK rises. Functions to boost. (Hereinafter, the capacitive elements C1 to C4 are respectively referred to as “boost capacitors”).

  Transistors Q24 and Q25 are both controlled by a power-on reset signal POR. Transistor Q24 discharges node N4 in response to activation of power-on reset signal POR, and transistor Q25 functions to charge node N5 in response to activation of power-on reset signal POR.

  Next, the operation of the frequency dividing circuit 20 in FIG. 7 will be described. For convenience of explanation, the potential of the low potential side power supply (VSS) as the reference potential of the frequency dividing circuit 20 is 0 V, and the potential of the high potential side power supply is VDD. Assume that The L level and H level potentials of the start signal ST and the clock signals CLK and / CLK are also set to 0 and VDD, respectively. Further, it is assumed that the threshold voltages of the transistors are all equal to Vth.

  In actual use, since the reference potential is set according to the level of the display data signal D written to the pixel, the potentials of the low-potential side power source and the high-potential side power source are set to, for example, −5V, + 10V, respectively. The Of course, the levels of the potential source and the signal may be different from those within the range in which the circuit of the present invention operates normally.

  Here, it is assumed that the power-on reset signal POR is maintained at the L level. Therefore, the transistors Q24 and Q25 are kept off and do not affect the operation of the frequency dividing circuit 20.

  FIG. 8 is a timing chart showing the operation of the frequency dividing circuit 20 of FIG. Hereinafter, the operation of the frequency dividing circuit 20 will be described with reference to FIG.

Immediately before the time t _30, the polarity control signal VFR (node N10) is L level, the polarity control signal / VFR (node N9) is assumed to be H level. At this time, the node N8 is at the H level (VDD), and the node N1 is at the L level (0).

For convenience of explanation, first, the level change of the nodes N1 to N3 and N11 will be described. At the same time at time t ₃₀ the clock signal / CLK and become H level, when the start signal ST becomes H level (VDD), the transistor Q1 is the H-level on to the node N8 is transferred to the node N1. As a result, the level of the node N1 becomes the H level of VDD-Vth which is lower than the level of the node N8 by the threshold voltage (Vth) of the transistor Q1.

  When node N1 becomes H level, transistor Q5 is turned on. At this time, since the clock signal / CLK is at the H level, the transistor Q4 is turned on. However, since the on-resistance of the transistor Q4 is set sufficiently higher than the on-resistance of the transistor Q5, the node N2 is at the L level. become. That is, the node N2 is at the L level that is higher than the low-potential-side power supply potential (0) by the voltage ΔV1 (see FIG. 8) determined by the on-resistance ratio between the transistors Q4 and Q5.

  Thus, when the node N1 becomes H level and the node N2 becomes L level, the transistors Q7 and Q3 are turned off and the transistor Q8 is turned on. Therefore, the node N3 becomes L level (0), and the transistor Q28 is turned off accordingly. At this time, since the clock signal / CLK is at the H level, the transistor Q27 is turned on, the node N11 is at the H level (VDD−Vth), and the transistor Q2 is turned on. As a result, the nodes N1 and N2 are held at the H level and the L level, respectively, by the transistors Q2 to Q4 constituting the flip-flop (latch).

The start signal ST and the clock signal / CLK at time t ₃₁ is back to L level, the transistor Q1 is that the off and node N8 and node N1 is separated. However, since the transistor Q3 is off, the level of the node N1 does not change from VDD-Vth. Further, since the transistor Q4 is turned off, the node N2 does not increase by the voltage ΔV1 and becomes a potential of 0V.

  The level of the node N3 does not change and maintains the L level. Although the transistor Q27 is turned off, the transistor Q28 is also turned off, so that the node N11 is held by the parasitic capacitance and becomes the H level (VDD−Vth) in the floating state.

When the time t ₃₂ in the clock signal CLK becomes H level, the node N11 is boosted by capacitive coupling through the step-up capacitor C4 (VDD + Vth or higher). As a result, the transistor Q2 operates in a non-saturated region (non-saturated operation), and the H level potential of the node N1 rises to VDD.

  At this time, the node N2 is also boosted by capacitive coupling via the boosting capacitor C3. However, since the transistor Q5 is on, the rise is slight (ΔV2 shown in FIG. 8), and when the clock signal CLK completely rises. Return to 0V. That is, since the node N2 is maintained at the L level, the node N3 maintains the L level (0).

When at time t ₃₃ the clock signal CLK becomes L level, the node N11 by capacitive coupling through the step-up capacitor C4 is the transistor Q2 is turned off and drops to the voltage VDD-Vth before the boost. However, since the level of the node N1 is held by the parasitic capacitance associated with the node N1, VDD is maintained. The node N2 also drops by a specific voltage ΔV4 due to capacitive coupling via the boost capacitor C3. However, since the transistor Q5 is also turned on here, it returns to 0 V when the clock signal CLK completely falls. That is, since the node N2 is maintained at the L level, the node N3 maintains the L level (0).

Again, when the clock signal / CLK becomes H level at time t _34, the transistor Q4 is turned on, the node N2 becomes the higher than by a voltage ΔV1 low potential side power supply potential (0), to maintain the L level . The transistor Q27 is also turned on, but the level of the node N11 (VDD−Vth) does not change.

When the clock signal / CLK returns to L level at time t _35, the node N2 and the transistor Q4 is turned off the voltage increase ΔV1 minutes eliminated becomes the potential of 0V. Further, the transistor Q27 is also turned off, and the node N11 becomes the H level (VDD−Vth) in the floating state.

Thereafter, until the start signal ST is activated again, the operations at the times t _{32 to} t ₃₅ are repeated at the nodes N 1 to N 3 and N 11 each time the clock signals CLK and / CLK are input. Is called. In other words, the logical values (H level or L level) of the nodes N1 to N3 and N11 are maintained during that time.

Here will be described a node N4~N10 between the time t ₃₀ ~t _35. In node N4～N10, changes in logical value between the time t ₃₀ ~t ₃₅ (H level or L level) is not. Node N10 is L level immediately before time t ₃₀ as described above, the node N8, N9 although is H level, then the node N4, N7 is H level as shown in FIG. 8, the node N5, N6 Is L level.

At time t ₃₀ to the clock signal / CLK becomes H level, the node N7 which is the floating H level, is boosted by capacitive coupling through the step-up capacitor C1, node N4 transistor Q10 and non-saturation operation H Maintained at the level (VDD). The node N5 at the L level (0) is boosted by capacitive coupling via the boosting capacitor C2. However, since the transistor Q13 is on, the rise is slight (ΔV5 shown in FIG. 8), and the clock signal / CLK When it completely stands up, it returns to 0V. Accordingly, the transistor Q14 is kept off and the transistor Q15 is kept on, so that the node N6 maintains the L level (0). Accordingly, the transistors Q19 and Q21 are kept off, and the level of the node N7 is boosted, so that the transistors Q18 and Q20 are turned on in a non-saturated operation, and the nodes N8 and N9 are kept at the H level (VDD). At this time, since the transistor Q22 is off and the transistor Q23 is on, the node N10 is maintained at the L level (0).

At time t ₃₁ when the clock signal / CLK returns to the L level, the level of the node N7 is lowered to VDD−Vth due to capacitive coupling via the boost capacitor C1, and the transistor Q10 is turned off, but the level of the node N4 (VDD) Is held by the parasitic capacitance associated with the node N4. Similarly, the transistors Q18 and Q20 are also turned off, but the levels of the nodes N8 and N9 are respectively held at VDD by the parasitic capacitances associated therewith. The level of the node N5 changes by a predetermined voltage ΔV7 to the negative side due to capacitive coupling via the boost capacitor C2, but returns to 0V when the clock signal / CLK completely falls because the transistor Q13 is on. Thus, since the node N5 is maintained at the L level and the node N8 is maintained at the H level, the node N10 is maintained at the L level (0).

At time t ₃₂ the clock signal CLK becomes H level, the transistor Q12 is turned on, node N5 and higher than by a voltage ΔV8 determined by the on resistance ratio of the transistor Q12 and the transistor Q13 low potential side power supply potential (0) However, it is maintained at the L level. The transistor Q16 is also turned on, but the level of the node N7 (VDD-Vth) does not change. The behavior of the nodes N5 and N7 does not change the levels of the nodes N4 and N8 to N10.

Then at time t ₃₃ the clock signal CLK returns to L level, the node N5 and the transistor Q12 is turned off is a potential of 0V there is no increase in the voltage ΔV8 minutes. The transistor Q16 is also turned off, and the node N7 becomes the H level (VDD−Vth) in the floating state. The levels of the nodes N4, N8 to N10 are not changed by the behavior of the nodes N5 and N7.

Time t ₃₄ after, until the drive signals G _{m + 1} is activated, the node N4～N10, the clock signal CLK, / CLK operation of the time t ₃₀ ~t ₃₃ whenever the input Repeatedly. In other words, the logical values (H level or L level) of the nodes N4 to N10 are maintained during that time.

Then, at time t ₄₀ after one frame period from the time t ₃₀ has passed, the drive signals G _{m + 1} becomes the H level (VDD). Hereinafter, the operation of the frequency dividing circuit 20 at this time will be described.

As mentioned previously, nodes N1 to N3, N11 is until the next start signal ST is activated since the operation of the time t ₃₂ ~t ₃₅ is repeated, the nodes N1 to N3, the logical value of N11 ( (H level or L level) is maintained. On the other hand, in the node N4～N10, time t ₄₀ after the following operation is performed.

When the drive signals G _{m + 1} becomes the H level at time t _40, L level of the node N3 transistor Q9 is turned on is transmitted to the node N4, the transistor Q13, Q15 is turned off. At this time, since the clock signal CLK is at the H level, the transistors Q12 and Q16 are turned on. Therefore, the node N5 becomes H level (VDD−Vth), and the transistor Q11 is turned on. At the same time, the transistor Q14 is turned on and the node N6 becomes H level (VDD-2 × Vth). At this time, the transistors Q16 and Q17 are both turned on, but the on-resistance of the transistor Q16 is set sufficiently higher than the on-resistance of the transistor Q17, and the node N7 becomes L level. That is, the node N7 at this time is at the L level in a state higher than the low-voltage power supply potential VSS (0) by a predetermined voltage ΔV9 determined by the on-resistance ratio of the transistors Q16 and Q17.

  As a result, the transistor Q10 is turned off, so that the nodes N4 and N5 are held at the L level (0) and the H level (VDD-Vth) by the transistors Q10 to Q13 constituting the flip-flop (latch), respectively. .

  Further, since the node N6 is at the H level and the node N7 is at the L level, the transistor Q19 is turned on, the transistor Q18 is turned off, and the node N8 is at the L level. Similarly, since the transistor Q21 is turned on and the transistor Q20 is turned off, the node N9 (/ VFR) is also at the L level. Since the node N5 is at the H level and the node N8 is at the L level, the transistor Q22 is turned on, the transistor Q23 is turned off, and the node N10 (VFR) is at the H level (VDD−2 × Vth).

At time t ₄₁ , when the drive signal G _{m + 1} and the clock signal CLK become L level (0), the transistor Q16 is turned off, so that the node N7 does not increase by the voltage ΔV9 and becomes the potential of 0V. At this time, the levels of the nodes N4 to N6 and N8 to N10 do not vary.

Then the clock signal / CLK at time t ₄₂ and is becomes H level, the level of the node N5 by capacitive coupling through the boosting capacitor C2 rises from VDD-Vth. As a result, the transistors Q14 and Q22 operate in a non-saturated state, and the levels of the nodes N6 and N10 (VFR) become VDD. Similarly, the node N7 is boosted by capacitive coupling via the boost capacitor C1, but since the transistor Q17 is on, the rise is slight (ΔV10 shown in FIG. 8), and the clock signal / CLK rises completely. And return to 0V. Thus, since the node N7 is maintained at the L level, the transistors Q10, Q18, and Q20 are maintained off, and the L level (0) of the nodes N4, N8, and N9 is maintained.

When the clock signal / CLK becomes L level at time t _43, the level of the node N5 drops VDD-Vth by capacitive coupling through the step-up capacitor C2. Thereby, the transistors Q14 and Q22 are turned off, but the levels (VDD) of the nodes N6 and N10 are held by the parasitic capacitance associated with each of the nodes, and both are held at the H level. On the other hand, the level of the node N7 changes to the negative side by a predetermined voltage ΔV12 due to capacitive coupling via the boost capacitor C1, but returns to 0V when the clock signal / CLK completely falls. Thus, since node N6 is maintained at H level and node N7 is maintained at L level, node N9 is maintained at L level (0).

And again when the clock signal CLK becomes H level at time t _44, the transistor Q12 is turned on, the level of the node N5 (VDD-Vth) is not changed. The transistor Q16 is also turned on, and the node N7 is higher than the low-potential power supply potential (0) by the voltage ΔV9, but is maintained at the L level. At this time, the levels of the nodes N4, N8 to N10 do not change.

When the clock signal CLK returns to L level at time t _45, the node N5 and the transistor Q12 is turned off becomes H level (VDD-Vth) of the floating state. Further, the transistor Q16 is also turned off, and the node N7 is not increased by the voltage ΔV9 and becomes a potential of 0V. At this time, the levels of the nodes N4, N8 to N10 are not changed.

Thereafter, until the drive signal G _{m + 1} is activated again, the operations at the times t _{42 to} t ₄₅ are repeated at the nodes N 4 to N 10 every time the clock signals CLK and / CLK are input. Is called. In other words, the logical values (H level or L level) of the nodes N4 to N10 are maintained during that time.

When the next start signal ST becomes an H level, the level of the node N8 is at the L level (0), the buffer 202, the waveform and levels shown in the time t ₃₀ ~t ₃₅ in FIG. 8 reversed It becomes operation. Therefore, when the drive signal G _{m + 1 further} becomes H level after one frame period, the operation is reversed from the waveform and level shown at times t _{40 to} t ₄₅ in FIG.

That is, as shown in FIG. 9, the frequency dividing circuit 20 operates to invert the polarity control signals VFR and / VFR each time the drive signal G _{m + 1} is activated. Therefore, the polarity control signals VFR, / VFR are inverted every frame period (the cycle is 2 frame periods). That is, the polarity control signals VFR, / VFR are signals having a cycle twice that of the start signal ST.

  As described above, the frequency dividing circuit 20 in FIG. 7 outputs the polarity control signals VFR and / VFR obtained by dividing the start signal ST by 1/2. However, the initial level of the polarity control signals VFR and / VFR when starting the operation cannot be controlled only by the above operation. In the embodiment described below, since the levels of the polarity control signals VFR and / VFR need to correspond to the polarities of the display data signal D written to the pixels 25, the levels of the polarity control signals VFR and / VFR are set appropriately. Must be set to

  The transistors Q24 and Q25 of the frequency dividing circuit 20 of FIG. 7 are provided for setting initial levels of the polarity control signals VFR and / VFR at the start of the operation (when the high potential side power supply (VDD) is turned on). It is. The power-on reset signal POR is activated at almost the same time as the rising of the high-potential-side power supply (VDD) (becomes H level) and deactivated after a predetermined time (becomes L level). It is a pulse.

  For example, FIG. 1 of JP-A-63-246919 can be configured using only one high potential side power source (VDD), one low potential side power source (VSS), and transistors of the same conductivity type (N type). An example of a power-on reset signal generation circuit is disclosed. In the circuit of FIG. 1, two N-type transistors and four inverters are shown. As the inverters, for example, an inverter in which both the driver element and the load element are N-type transistors, or the driver element is N If an inverter in which a type transistor and a load element are constituted by resistance elements is employed, the transistor constituting the generation circuit can be limited to an N-type transistor. If a generation circuit for the power-on reset signal POR configured using only transistors of the same conductivity type is employed, the process for forming the generation circuit on the same insulating substrate as the pixel 25 is facilitated. Is obtained.

  Since the power-on reset signal POR is a single pulse that is activated for a certain period when the high-potential side power supply potential VDD rises, in the frequency divider circuit 20 of FIG. 7, the transistors Q24 and Q25 are turned on when the high-potential side power supply potential VDD rises. The node N4 of the latch inverter 203 is set to L level and the node N5 is set to H level. When the clock signals CLK and / CLK are activated from this state, the polarity control signal VFR is initialized to the H (VDD) level and / VFR is initialized to the L (VSS) level. As described above, according to the frequency dividing circuit 20 of FIG. 7, the initial values of the polarity control signals VFR and / VFR can be set to specific values, so that the levels of the polarity control signals VFR and / VFR and the pixel 25 are written. The polarity of the display data signal D to be displayed can be made to correspond appropriately.

  Both the transistors Q24 and Q25 are not necessarily provided. If the initial values of the nodes N4 and N5 of the latch inverter 203 can be set, only one of them may be provided.

  Contrary to the above example, when the initial value of the polarity control signal VFR is L level and the initial value of the polarity control signal / VFR is H level, the transistor Q24 is connected to the node N5 with respect to the circuit of FIG. And the transistor Q25 may be connected between the node N4 and the power supply terminal of the potential VDD.

  Of course, the power-on reset signal POR generation circuit is not configured by the TFT formed on the same insulating substrate as the pixel 25, and the power-on reset signal POR may be input from the outside of the circuit on the insulating substrate. Good. For example, the drive control circuit 110, which is an LSI configured using a single crystal silicon substrate, may generate the power-on reset signal POR. However, in that case, it is necessary to newly provide a power-on reset signal POR generation circuit in the control circuit 110, and a circuit for adjusting the level of the power-on reset signal POR is also required in the level shifter 111. It should be noted that it can hinder scale reduction.

As shown in FIGS. 4 and 7, in this embodiment, the dummy shift register SR _{m +} provided separately from the signal for driving the gate line GL connected to the pixel 25 as a signal for driving the frequency divider circuit 20. ₁ output signal (drive signal G _{m + 1} ) was used. However, instead of that form, any _one of the output signals (gate line drive signals G _{1 to} G _m ) of the unit shift register that drives the gate line GL may also be used for driving the frequency divider circuit 20. However, it should be noted that since the load of the unit shift register that drives the frequency divider circuit 20 increases, the driving speed of the gate line GL that it drives decreases.

  As can be seen from the operation of the frequency dividing circuit 20 of FIG. 7 shown in FIG. 9, the polarity control signals VFR, / VFR are inverted every cycle of the start signal ST (that is, every frame period of the image signal). . That is, the polarity control signals VFR, / VFR are signals having a cycle twice that of the start signal ST. Therefore, the polarity control signals VFR and / VFR can be used as signals for switching the polarity of the capacitance line drive signal CC output from the capacitance line drive circuit 12 in accordance with the polarity of the display data signal D that is switched for each frame. it can.

  In the frequency dividing circuit 20 of FIG. 7, the clock signal CLK is used for the purpose of recharging (refreshing) the nodes N5 and N7, and the clock signal / CLK is used for the purpose of recharging the nodes N2 and N11. Other clock signals may be used as long as the signal becomes. If the leakage current is large and the level of the nodes N2, N5, N7, and N11 is likely to decrease even after refreshing based on a one-phase clock signal, the node N2 is used by using two or more phase clock signals. , N5, N7, and N11 may be refreshed.

  For example, when the node N2 is refreshed with a two-phase clock, another transistor may be provided in parallel with the transistor Q4, and both may be driven with clock signals having different phases. When the node N11 is refreshed with a two-phase clock, another transistor may be provided in parallel with the transistor Q27 and both may be driven with clock signals having different phases. Similarly, when the node N5 is refreshed with a two-phase clock, another transistor may be provided in parallel with the transistor Q12, and both may be driven by clock signals having different phases. Further, when the node N7 is refreshed with a two-phase clock, another transistor may be provided in parallel with the transistor Q16 and both may be driven with clock signals having different phases.

  As described above, in the display device according to the present embodiment, the control signals (polarity control signals VFR, / VFR) for switching the polarity of the capacitance line drive signal CC output from the capacitance line drive circuit 12 for each frame are It is generated by the frequency dividing circuit 20. The transistors constituting the frequency dividing circuit 20 are all of the same conductivity type as shown in FIG. The transistors constituting the frequency dividing circuit 20 are formed on the same insulating substrate as the liquid crystal array unit 15 and the gate line driving circuit 11 and have the same conductivity type as those used for the liquid crystal array unit 15 and the gate line driving circuit 11. Transistor. Accordingly, the number of steps for forming the display panel including the gate line driving circuit 11 and the frequency dividing circuit 20 can be reduced, the manufacturing process of the image display device using the capacitive line driving method can be simplified, and the manufacturing cost can be reduced. Can contribute.

  For example, FIG. 1 to FIG. 6 of the above-mentioned Patent Document 1 show a configuration example and operation of the capacitor line driving circuit 12 that can be configured using the same conductivity type transistor. In Patent Document 1, the capacitor line drive signal CC is coupled to the pixel electrode via the storage capacitor of the pixel. As shown in FIG. 2 of Patent Document 1, the capacitor line drive signal CC (n) connected to the pixel in the nth row is the active period (nth row) of the gate line drive signal Vg (n) in that row. The level changes with a delay of 2H (horizontal period) from the signal writing period to the pixel), and the potential of the pixel electrode is adjusted by the level change of the capacitance line drive signal CC (n).

  The level of the capacitive line drive signal CC (n) alternates for each frame, thereby realizing adjustment of capacitive coupling drive according to an image signal whose polarity also changes every frame. As shown in FIG. 1 of Patent Document 1, the switching of the level of the capacitance line drive signal CC (n) is controlled by a frame switching normal phase signal FR (hereinafter “signal FR”) and a frame switching reverse phase. This is performed by a signal FRB (hereinafter, “signal FRB”). These two signals FR and FRB are opposite phase signals whose levels are inverted every frame.

  That is, as the signals FR and FRB of Patent Document 1, the polarity control signals VFR and / VFR that are the output signals of the frequency dividing circuit 20 according to the present invention can be used. By doing so, it is not necessary to supply the signals FR and FRB (polarity control signals VFR and / VFR) from the outside, and a capacitively coupled display device including only transistors of the same conductivity type can be realized. . However, since the circuit of Patent Document 1 is configured using a P-type transistor, when applied to a circuit using an N-type transistor as in this embodiment, each signal, power supply voltage, and polarity of the transistor Must be reversed from that described in Patent Document 1.

<Embodiment 2>
In the second embodiment, a modification of the display device of the first embodiment is shown. FIG. 10 is a block diagram showing a schematic configuration of a liquid crystal display device 10B according to the second embodiment. The display device 10B is also provided with _m gate lines GL ₁ , GL ₂ ,..., GL _m as in the display device 10A (FIG. 4) of the _first embodiment, and these are connected by the gate line drive circuit 11. Driven.

In the display device 10B of FIG. 10, the frequency divider circuit 20 is driven using drive signals G _{m + 1} and G _{m + 2} . That is, in the display device 10A of FIG. 4, the start signal ST input to the frequency divider circuit 20 is replaced with the drive signal _{Gm + 2} . The drive signal G _{m + 1} and the drive signal G _{m + 2} are both a set of signals having a period of one frame period and having different phases. Therefore, also in the present embodiment, the frequency dividing circuit 20 can generate the polarity control signals VFR and / VFR having one frame period as a cycle based on the theory described with reference to FIG. The operation waveform is shown in FIG. The polarity control signals VFR and / VFR output from the frequency divider circuit 20 are repeatedly inverted in level each time the drive signal G _{m + 1} is activated.

In FIG. 10, the drive signal G _{m + 1} and the drive signal G _{m + 2} may be exchanged and input to the frequency divider circuit 20. That is, in the frequency dividing circuit 20 of FIG. 7, the drive signal G _{m + 1} may be input to the gate of the transistor Q1, and the drive signal G _{m + 2} may be input to the gate of the transistor Q9. In that case, the levels of the polarity control signals VFR, / VFR are inverted every time the drive signal G _{m + 2} is activated.

Further, in FIG. 10, instead of the set of the drive signal G _{m + 1} and the drive signal G _{m + 2} , the output signals of two predetermined unit shift registers for driving the gate line GL are also used for driving the frequency divider circuit 20. It may be used also. However, it should be noted that the load of the two predetermined unit shift registers that drive the frequency divider circuit 20 is increased, which causes a disadvantage that the driving speed of the gate line GL that drives them is reduced. That is, in the frequency divider circuit 20 of FIG. 7, one output signal (gate line drive signal) of the two predetermined unit shift registers SR is input to the gate of the transistor Q1, and the other output signal is input to the gate of the transistor Q9. May be input. In that case, the levels of the polarity control signals VFR, / VFR are inverted every time the other output signal is activated.

<Embodiment 3>
FIG. 12 is a block diagram showing a schematic configuration of a display device 10C according to Embodiment 3 of the present invention. In the display device 10A of the first embodiment, the power-on reset signal POR is input to the frequency divider circuit 20 (see FIG. 7), thereby setting the initial values of the polarity control signals VFR, / VFR, thereby controlling the polarity. The level of the signals VFR, / VFR and the polarity of the display data signal D are matched.

  In the display device 10C of the present embodiment, initial setting of the polarity control signals VFR, / VFR by the power-on reset signal POR is not performed. Instead, the drive control circuit 110 (data signal output circuit) is configured to determine the polarity of the display data signal D based on the levels of the polarity control signals VFR, / VFR.

  The display device 10C includes a level shifter 21 that generates a signal synchronized with the polarity control signals VFR and / VFR, and outputs a data polarity control signal POL whose amplitude is reduced to a level that can be input to the drive control circuit 110. ing.

The drive control circuit 110 is the same as the conventional one in that it has a function of controlling the polarities of the display data signals D ₁ , D ₂ ,. However, unlike the conventional _one , the polarities of the display data signals D ₁ , D ₂ ,... Are determined based on the data polarity control signal POL. That is, the drive control circuit 110 of the present embodiment changes the polarity of the display data signal D in accordance with the levels of the polarity control signals VFR and / VFR generated by the frequency divider circuit 20.

  When the initial values of the polarity control signals VFR and / VFR are set to match the levels of the polarity control signals VFR and / VFR and the polarity of the display data signal D as in the first embodiment, the following Problems can arise. For example, during a display operation, when an instantaneous power failure occurs in the system power supply and the voltage source VDD decreases instantaneously, the power-on reset signal POR is generated and the levels of the polarity control signals VFR and / VFR are initialized at the time of recovery. The At this time, there is a possibility that the correspondence between the polarity control signals VFR, / VFR and the polarity of the display data signal cannot be taken.

  On the other hand, in the display device 10C of the present embodiment, since the drive control circuit 110 determines the polarity of the display data signal D in accordance with the levels of the polarity control signals VFR, / VFR, the polarity of the display data signal D is always constant. Matching to the level of the polarity control signals VFR, / VFR, the above problem does not occur.

  FIG. 13 is a circuit diagram illustrating a configuration example of the level shifter 21 included in the display device 10C. The level shifter 21 includes transistors Q29 and Q30 connected in series between a high-potential-side power supply (potential VDD1) and a low-potential voltage source (potential VSS4). The H level and L level potentials of the data polarity control signal POL are defined by potentials VDD1 and VSS4, respectively. That is, the values of the potentials VDD1 and VSS4 are set so that the level of the data polarity control signal POL can be input to the drive control circuit 110.

  One of the polarity control signals VFR and / VFR (here, VFR) is input to the gate of the transistor Q29, and the other (here, / VFR) is input to the gate of the transistor Q30. A connection node (node N12) between the transistors Q26 and Q27 serves as an output terminal for the output signal POL of the data polarity control signal POL. Since the polarity control signals VFR and / VFR are complementary signals (the active periods do not overlap), the level shifter 21 in FIG. 13 performs a push-pull operation. That is, according to the level shifter 21 of FIG. 13, a direct through current does not occur in the level shifter 21, and an increase in power consumption due to the provision of the level shifter 21 can be prevented.

  Consider each power supply potential based on the drive control circuit 110 of FIG. The low potential side power supply potential VSS4 of the level shifter 21 in FIG. 13 is set to the same level (for example, 0 V) as the low potential side power supply potential (reference potential source) of the drive control circuit 110. Similarly, the high potential side power supply potential VDD1 of the level shifter 21 in FIG. 13 is set to the same level (eg, 3.3 V) as the high potential side power supply potential of the drive control circuit 110. At this time, the H level and L level of the polarity control signals VFR, / VFR are set to 10 V (VDD) and −5 V (VSS), for example. Under these conditions, the transistors Q29 and Q30 operate in the non-saturated region, and the H level of the data polarity control signal POL is 3.3V and the L level is 0V, which matches the operation level of the internal circuit of the drive control circuit 110. This method can be similarly applied to the frequency dividing circuit 20 in other embodiments.

  In the present embodiment, the level shifter 21 generates the data polarity control signal POL based on the polarity control signals VFR and / VFR. However, if the same signal can be generated, the level shifter 21 is not necessarily required. The signals input to the level shifter 21 may not be the polarity control signals VFR and / VFR. That is, the signals input to the gates of the transistors Q29 and Q30 in FIG. 13 can be switched at substantially the same timing as the polarity control signals VFR and / VFR, and the transistors Q29 and Q30 can be operated in the non-saturated region. If so, a signal other than the polarity control signals VFR, / VFR may be used. Even in that case, the level shifter 21 can generate the data polarity control signal POL suitable for the signal level of the drive control circuit 110. For example, instead of the polarity control signals VFR and / VFR, the signals of the nodes N6 and N8 in FIG. 7 may be used.

<Embodiment 4>
As described above, Patent Document 1 shows an example of a unit circuit that can be applied to the capacitor line driving circuit 12, but in the fourth embodiment, the capacitor line driving circuit 12 devised by the present inventor is described. explain.

  The capacitive coupling driving method using the capacitor line CCL includes a gate line inversion driving method for inverting the polarity of the display data signal D for each gate line GL, and a polarity of the display data signal D for each pixel 25 (for each data line DL). In this embodiment, the structure of the capacitor line driving circuit 12 used in the gate line inversion driving method will be described.

  14 and 15 are circuit diagrams for explaining the configuration of the capacitive line driving circuit 12 for performing capacitive coupling driving using the capacitive line CCL. The capacitance line drive circuit 12 is composed of a plurality of unit circuits that drive each of the capacitance lines CCL. FIG. 14 shows a unit circuit for driving the capacitor line CCL connected to the odd-numbered pixel line (odd row), and FIG. 15 shows a unit circuit for driving the capacitor line CCL connected to the even-numbered pixel line (even row). is there.

As shown in FIG. 4, the capacity line driving circuit 12 receives the gate line driving signals G _{1 to} G _m , the clock signals CLK and / CLK, and the polarity control signals VFR and / VFR, and the capacity is based on these signals. Capacitance line drive signals CC _{1 to} CC _m for driving the line CCL are generated. In addition to the high-potential-side power supply potential VDD and the low-potential-side power supply potential VSS, potentials VCCH and VCCL that respectively define the H-level and L-level of the capacitor-line drive signal CC are supplied to the capacitor line drive circuit 12 as the power supply potential. Is done.

In the following, the odd-numbered gate line drive signals (G ₁ , G ₃ ,..., G _{n + 2} ,...) Are activated in synchronization with the clock signal CLK, and the even-numbered gate line drive signals (G ₂ , G _4). ,..., G _{n + 3} ,...) Are assumed to be activated in synchronization with the clock signal / CLK. 14 and 15, it is assumed that the clock signal / CLK is input to the clock terminals CK100 of the odd-numbered unit circuits and the clock signal CLK is input to the clock terminals CK100 of the even-numbered unit circuits. To do.

  First, the unit circuits in the odd rows will be described. FIG. 14 typically shows a unit circuit in the n-th row (n is an odd number).

As shown in FIG. 14, the unit circuit is configured by using only transistors of the same conductivity type, a polarity switching circuit for determining the polarity of the capacitor line drive signal CC _n, the polarity of the polarity switching circuit A level holding circuit for holding the levels of the switching signals PC and / PC and holding those levels with low impedance for one frame, and a capacitance line driving signal having a higher driving capability for the polarity switching signals PC and / PC It consists of an output circuit that converts it to CC _n and outputs it. Here, an example in which an N-type transistor is used in the same manner as the pixel 25 in FIG. 4 is shown, but it is possible to use a P-type transistor as a matter of course.

The output circuit of the unit circuit as shown in FIG. 14, the output terminal OUT100 capacitance line drive signal CC _n, the transistor Q109 supplies an H-level potential VCCH capacitance line drive signal CC _n, to the output terminal OUT100, capacity and a supplying transistor Q110 the L level potential VCCL line drive signal CC _n. That is, the transistor Q109 is connected between the power supply terminal S104 supplied with the potential VCCH and the output terminal OUT100, and the transistor Q110 is connected between the power supply terminal S103 supplied with the potential VCCL and the output terminal OUT100. Yes. Here, nodes connected to the gate of the transistor Q109 and the gate of the transistor Q110 are defined as nodes N101 and N102, respectively.

The polarity switching circuit supplies polarity control signals VFR and / VFR to the nodes N101 and N102, respectively, according to the gate line driving signal G _{n + 2} input to the input terminal IN101. In other words, the polarity switching circuit is connected between the transistor Q101 connected between the input terminal IN102 to which the polarity control signal VFR is input and the node N101, and between the input terminal IN103 to which the polarity control signal / VFR is input and the node N102. The gates of the transistors Q101 and Q102 are both connected to an input terminal IN101 to which a gate line drive signal _{Gn + 2} is input.

Gate line driving signal G _{n + 2} is a signal for driving the gate line GL n _{+ 2} are two lines after the gate line GL _n corresponding to the unit circuit in the n-th row. Here, an easily obtainable gate line drive signal G _{n + 2} is used as a signal input to the input terminal IN101. However, any other signal can be used as long as it is activated at the same timing and has a predetermined potential level. A signal may be used.

  A signal corresponding to the polarity control signal VFR supplied to the node N101 via the transistor Q101 becomes the polarity switching signal PC, and a signal corresponding to the polarity control signal / VFR supplied to the node N102 via the transistor Q102 Polarity switching signal / PC. Since the polarity control signals VFR and / VFR are complementary to each other, the polarity switching signals PC and / PC are also complementary to each other.

  The level holding circuit for holding the levels of the polarity switching signals PC and / PC is in principle a flip-flop (latch). As shown in FIG. 14, the level holding circuit includes six transistors Q103 to Q108 and two capacitive elements C101 and C102. The transistor Q103 is connected between the node N101 and the power supply terminal S1 to which the low potential side power supply potential VSS is supplied, and the gate thereof is connected to the node N102. Transistor Q104 is connected between node N102 and power supply terminal S1, and has its gate connected to node N101.

  The transistor Q105 is connected between the power supply terminal S2 to which the high potential side power supply potential VDD is supplied and the node N101, and the transistor Q106 is connected between the second power supply terminal S2 and the node N102. A node to which the gate of the transistor Q105 is connected is defined as “node N103”, and a node to which the gate of the transistor Q106 is connected is defined as “node N104”. The node N103 is connected to the clock terminal CK100 to which the clock signal / CLK is input via the capacitive element C101, and the node N104 is connected to the clock terminal CK100 via the capacitive element C102.

  Transistor Q107 is connected between nodes N103 and N101, and transistor Q108 is connected between nodes N104 and N102. The gates of the transistors Q107 and Q108 are both connected to the power supply terminal S2.

  For example, when this level holding circuit holds the state where the node N101 (polarity switching signal PC) is at the H level and the node N102 (polarity switching signal / PC) is at the L level, the transistor Q103 is turned off and the transistor Q104 is turned on. At this time, the node N103 is charged through the transistor Q107 and becomes H level, and the node N104 is discharged through the transistor Q108 and becomes L level. As a result, the transistor Q105 is turned on and the transistor Q106 is turned off. Thereby, the H level of the polarity switching signal PC and the L level of the polarity switching signal / PC are maintained.

  At this time, since both the nodes N101 and N103 are at the H level, the transistor Q107 is off, and the node N103 is maintained at the H level in the floating state. Therefore, when the clock signal / CLK becomes H level, the node N103 is boosted by the coupling through the capacitive element C101, and the transistor Q105 is turned on in the non-saturated region. As a result, the polarity switching signal PC is maintained at the H level of the same potential VDD as that of the power supply terminal S2.

  On the other hand, the potential of the node N104 also tends to rise due to coupling through the capacitor C102 when the clock signal / CLK becomes H level. However, since the transistors Q108 and Q104 are on, the potential rise at the node N104 is instantaneous and is maintained at almost the L level. That is, since the transistor Q106 is almost kept off, almost no through current flows through the transistors Q104 and Q106.

  Note that the instantaneous increase in potential of the node N104 can be reduced by appropriately setting the on-resistance values of the transistors Q104 and Q108 and the capacitance value of the capacitor C102, and the transistor Q106 can be more reliably maintained in the off state. Can do.

  Conversely, when the unit circuit holds the state in which the level holding circuit has the node N101 (polarity switching signal PC) at the L level and the node N102 (polarity switching signal / PC) at the H level, the transistor Q104 is turned on, Q103 turns off. Node N104 attains H level, transistor Q106 is turned on, and polarity switching signal / PC is maintained at H level. When the clock signal / CLK rises, the node N104 is boosted and the transistor Q106 is turned on in the non-saturated region, so that the polarity switching signal / PC becomes the H level of the potential VDD. On the other hand, since node N103 is substantially maintained at the L level and transistor Q105 is substantially maintained off, almost no through current flows through transistors Q105 and Q103.

  As described above, in the level holding circuit included in the unit circuit of FIG. 14, only the node that maintains the H level is pulled up while consuming almost no power, and the node that maintains the L level is pulled up. A selective pull-up operation is performed.

  Next, the unit circuits in even-numbered rows of the capacitor line driving circuit 12 will be described. FIG. 15 typically shows unit circuits in the (n + 1) th row (n is an odd number).

As shown in FIG. 15, the configuration of the unit circuit of the even-numbered row is almost the same as the unit circuit of the odd-numbered row (FIG. 14), but the capacity line drive signal CC _{n + 1} of the even-numbered row is the capacity line drive signal of the odd-numbered row. Since the level needs to be inverted with respect to CC _n , the gate connections of the transistors Q109 and Q110 are interchanged with each other with respect to FIG. Alternatively, the circuit configuration is not changed from that in FIG. 14, and the unit circuits in the even rows may be replaced with the polarity control signals VFR and / VFR inputted to the input terminals IN102 and IN103 (not shown).

  Note that the signals input to the clock terminal CK100 in FIGS. 14 and 15 may be signals other than the clock signals CLK and / CLK as long as they are repetitive signals that alternate at a constant period. The clock signal input to the clock terminal CK100 is used to turn on the transistor Q105 (or Q106) in a non-saturation region at a constant period, whereby the potential of the H level of the node N101 (or N102) due to the leakage current. The drop is compensated. As long as this leakage current can be sufficiently compensated, a clock signal having a lower frequency may be used, thereby reducing power consumption. However, the clock signal input to the clock terminal CK100 preferably has an active period that does not overlap with the active period of the signal input to the input terminal IN101.

Here, the gate line drive signals (G ₁ , G ₃ ,..., G _{n + 2} ,...) In the odd rows are activated in synchronization with the clock signal CLK, and the gate line drive signals (G ₂ , G ₄ ,. .., G _{n + 3} ,...) Are assumed to be activated in synchronization with the clock signal / CLK, so that the clock signal / CLK is input to the clock terminal CK100 of the odd-numbered unit circuit and the even-numbered row The clock signal CLK was input to the clock terminal CK100 of the unit circuit.

  Subsequently, the operation of the capacitor line driving circuit 12 according to the present embodiment will be described. Here, for simplicity of explanation, it is assumed that the threshold voltages of the transistors are all the same value Vth. The reference potential of the display device is generally set based on the potential of the display data signal written to the pixel. Here, the low-potential power supply potential VSS of the capacitor line driving circuit 12 is used as the reference potential. The H level of the polarity control signals VFR, / VFR is equal to the potential VDD supplied to the power supply terminal S2, and the L level is equal to the potential VSS. Furthermore, the H level potential of the clock signals CLK and / CLK is also VDD, and the L level potential is also VSS.

  As described above, the potentials VCCL and VCCH supplied to the power supply terminals S103 and S104 are for defining the L level and H level potentials of the capacitor line drive signal CC, respectively. Since the capacitive line drive signal CC gives a constant potential change to the pixel electrode by capacitive coupling, the potentials VCCH and VCCL are equal to the potential change that the potential difference (amplitude of the capacitive line drive signal CC) gives to the pixel electrode. As long as they are equal and the transistors Q109 and Q110 operate in the non-saturated region.

FIG. 16 is a signal waveform diagram showing the operation of the capacitance line driving circuit 12. As described in the first embodiment, the polarity control signals VFR, / VFR are complementary signals generated by the frequency dividing circuit 20 of FIG. 4 and have a cycle twice that of the start signal ST. As shown in FIG. 9, the polarities of the polarity control signals VFR, / VFR alternate at the rising edge of the drive signal G _{m + 1} output next to the gate line drive signal Gm for driving the gate line GL _m in the last row. . That is, the levels of the polarity control signals VFR, / VFR alternate in the blanking period for each frame of the display device. Here, the period in which the polarity control signal VFR is at the H level is defined as “odd frame”, and the period at the L level is defined as “even frame”.

  Hereinafter, the operation of the capacitive line driving circuit 12 according to the present embodiment will be described. First, the operation of the unit circuit in the odd-numbered row will be described. Here, the operation of the unit circuit in the n-th row (FIG. 14) will be representatively described.

Referring to FIG. 16, when the polarity control signals VFR and / VFR change to the H level and the L level, respectively, and become an odd frame at time t ₁ within the blanking period, the input terminal IN102 becomes the potential VDD, and the input terminal IN103. Are set to the potential VSS. The levels of the nodes N101 to N104 and the output terminal OUT100 are determined by the operation in the immediately preceding frame period. Here, the nodes N101 and N103 and the output terminal OUT100 are at the L level, and the nodes N102 and N104 are at the H level.

In time t _2, the corresponding gate line driving signal G _n for driving the gate line GL _n becomes H level, the display data signal D is written in the n-th row of pixels 25. Then, at time t ₃ 1H after time t ₂ , the gate line drive signal G _n becomes L level.

Further at time t ₄ after 1H of time t _3, the gate line drive signal G _{n + 2} line after two becomes H level (VDD). Accordingly, the transistors Q101 and Q102 are turned on, and the levels of the polarity control signals VFR and / VFR are supplied to the nodes N101 and N102. More specifically, first, the node N102 (polarity switching signal / PC) becomes L level (VSS), and the transistors Q103 and Q110 are turned off. Since the transistor Q103 is turned off, the node N101 is charged through the transistor Q101, and the polarity switching signal PC becomes H level (VDD-Vth). In response, the transtransistors Q104 and Q109 are turned on.

The node N104 is discharged through the transistors Q108 and Q104 and becomes L level (VSS), and the node N103 is charged through the transistor Q107 and becomes H level (VDD−Vth). The potential VCCH as mentioned above, the polarity switching signal / PC is set to a value in the range of saturation operation transistor Q109 ratio when it is H level, the capacitance line drive signal CC _n is H potential VCCH Become a level.

When the gate line drive signal G _{n + 2} becomes L at time t ₅ , the transistors Q101 and Q102 are turned off, so that the nodes N101 and N102 and the input terminals IN102 and IN103 are electrically separated. However, at this time, the H level of the polarity switching signal PC and the L level of the polarity switching signal / PC are held (latched) by the action of the level holding circuit described above.

At time t ₅ , the clock signal / CLK rises to the H level, so that the node N103 is boosted by the coupling through the capacitive element C101. Since the node N103 is already charged to VDD-Vth, the potential of the node N103 becomes approximately 2 · VDD-Vth by this boosting action. Accordingly, transistor Q105 is turned on in the non-saturated region, and node N101 rises to potential VDD.

When the clock signal / CLK becomes L level at time t ₆ , the level of the node N103 returns to VDD−Vth again, and the transistor Q105 is turned off, but the node N101 is maintained at the H level of the potential VDD in the high impedance state.

After time t ₆ , whenever the clock signal / CLK changes to the H level, the potential of the node N103 is boosted to approximately 2 · VDD−Vth, and the transistor Q105 is turned on in the non-saturated region to charge the node N101 to the potential VDD. The operation is repeated. Thereby, a decrease in the level of node N101 due to the leakage current is compensated, and polarity switching signal PC can be maintained at the H level of potential VDD. As a result, the transistor Q109 is maintained in the ON state in the non-saturation region, the said unit circuit can be maintained for one frame period, the H level (VCCH) of the capacitance line drive signal CC _n with low impedance.

At time t ₇ in the next blanking period, the polarity control signals VFR and / VFR change to L level and H level, respectively, and become even frames, but at this time, the transistors Q101 and Q102 are off. node N101 H level (polarity switching signal PC), without L-level change of the node N102 (polarity switching signal / PC), remains capacitance line drive signal CC _n is H level (VCCH).

Thereafter, at time t ₈ , the gate line drive signal G _n becomes H level, and the display data signal D is written to the pixels 25 in the nth row. The gate line drive signal G _n becomes L level at time t ₉ 1H after time t ₈ .

In addition the time t ₁₀ after the 1H time t _9, the gate line drive signal G _{n + 2} becomes the H level (VDD). Accordingly, the transistors Q101 and Q102 are turned on, and the levels of the polarity control signals VFR and / VFR are supplied to the nodes N101 and N102. At this time, the polarity switching signal PC is set to L level (VSS) and the polarity switching signal / PC is set to H level (VDD−Vth) by the operation opposite to the time t ₄ described above. Correspondingly transistor Q109 is turned off, the transistor Q110 is turned on, the capacitance line drive signal CC _n changes to the L level (VCCL).

When the gate line drive signal G _{n + 2} becomes L at time t ₁₁ , the transistors Q101 and Q102 are turned off, so that the nodes N101 and N102 and the input terminals IN102 and IN103 are electrically separated. However, at this time, the L level of the polarity switching signal PC and the H level of the polarity switching signal / PC are held (latched) by the action of the level holding circuit described above.

At time t ₁₁ , the clock signal / CLK rises to the H level, so that the node N104 is boosted by the coupling through the capacitive element C102. By this boosting action, the potential of the node N104 becomes approximately 2 · VDD−Vth. Accordingly, transistor Q106 is turned on in the non-saturated region, and node N102 rises to potential VDD.

When the clock signal / CLK at time t ₁₂ becomes L level, the transistor Q106 back to level again VDD-Vth of the node N104 is turned off, the node N101 is maintained in a high impedance state to the H-level potential VDD.

Time t ₆ after the clock signal / CLK potential of the node N103 every time changes to the H level is raised to approximately 2 · VDD-Vth, operation transistor Q106 charges the node N101 to the potential VDD is repeated. As a result, the node N101 (polarity switching signal PC) maintains the H level of the potential VDD at the potential VDD. As a result, the transistor Q109 is maintained in the ON state in the non-saturation region, the said unit circuit can be maintained for one frame period, the L level (VCCL) of the capacitor line drive signal CC _n with low impedance.

  As described above, each of the odd-row unit circuits (FIG. 14) of the capacitor line driving circuit 12 writes the display data signal D to the pixel 25 in the corresponding row in the odd-numbered frame (the activation of the corresponding gate line GL). After 1H from the (period), the capacitance line drive signal CC is changed from the L level to the H level. In an even frame, the capacitor line drive signal CC is changed from H level to L level after 1 H from the writing period of the display data signal D to the pixels 25 in the corresponding row.

  On the other hand, the operation of the unit circuit in the even-numbered row (FIG. 15) is almost the same as the operation of the unit circuit in the odd-numbered row described above. However, each of the even-numbered unit circuits changes the capacitance line drive signal CC from the H level to the L level 1H after the writing period of the display data signal D to the pixel 25 of the corresponding row in the odd-numbered frame. . In an even frame, the capacitor line drive signal CC is changed from the L level to the H level after 1 H of the writing period of the display data signal D to the pixels 25 in the corresponding row.

FIG. 17 is a signal waveform diagram showing the operation of the capacitor line drive circuit 12 and summarizes the behavior of the capacitor line drive signals CC in the odd and even rows. It can be seen that the level of each of the capacitance line drive signals CC changes 2H behind the rise of the gate line drive signal G corresponding to the same row (after 1H from the fall of the gate line drive signal G). . For example, the capacitance line drive signal CC _n corresponding to the n-th row (odd row) is delayed by 2H from the rise time of the gate line drive signal G _n corresponding to the same row (when the gate line drive signal G _n falls). After 1H, the level is reversed. Similarly, the level of the capacitor line drive signal CC _{n + 1} corresponding to the (n + 1) th row (even number row) is inverted with a delay of 2H from the rising edge of the gate line drive signal _{Gn + 1} . It can also be seen from the same figure that the direction of the level change of the capacitance line drive signal CC is reversed between the even-numbered rows and the several-hour rows within the same frame period.

  In the case of performing capacitive coupling driving of the gate line inversion driving method using the capacitive line driving signal CC whose level changes as shown in FIG. 17, when writing the display data signal D to each pixel 25, in the odd frame, the positive electrode is connected to the odd row. In the even frame, negative polarity is written in odd rows and positive polarity is written in even rows in even frames. To do. As a result, the potential of the pixel electrode Np to which the positive display data signal D is written is increased, the potential of the pixel electrode Np to which the negative display data signal D is written is decreased, and each display data signal D is amplified. Will be.

  As can be seen from the above description, the polarity control signals VFR and / VFR are used for the purpose of controlling the level of each capacitance line drive signal CC. Since they are signals having a period twice that of the start signal ST, they are fixed at a constant level in each frame period. However, since the unit circuit of the capacitive line drive circuit 12 shown in FIGS. 14 and 15 includes the level holding circuit for the polarity switching signals PC and / PC, strictly speaking, the polarity control signals VFR and / VFR are It is sufficient that each unit circuit has an appropriate value even at least for the active period of the signal input to the input terminal IN101, and it is not always necessary to maintain a constant level for one frame period. However, it should be noted that the power consumption increases when the alternating cycle of the polarity control signals VFR, / VFR is shortened (frequency is increased).

<Embodiment 5>
In the fourth embodiment, the frequency dividing circuit 20 and the capacitor line driving circuit 12 according to the present invention are applied to a display device using a gate line inversion driving method. However, the present invention also applies to a display device using a dot inversion driving method. Applicable. In the dot inversion driving method, since the polarity of the display data signal is inverted for each pixel (that is, for each data line), display data signals having different polarities are written to adjacent pixels along the gate line.

  Therefore, when the present invention is applied to the dot inversion driving method, adjacent pixels along the gate line may be capacitively coupled using different capacitance lines. That is, in each pixel line, odd-numbered columns and even-numbered columns need only be capacitively coupled using different capacitance lines (odd-numbered pixels and even-numbered columns of pixels are capacitively coupled to different capacitive lines. ) Examples of the connection form are disclosed in FIG. 1 and FIG.

<Embodiment 6>
As one of capacitive coupling driving methods, a driving method (frame inversion driving method) is also conceivable in which the polarities of display data signals written to all the pixels are the same and the display data polarities of all the pixels are inverted for each frame. The present invention is also applicable to a display device that performs such a driving method. In that case, since the polarity is not inverted for each gate line, all the unit circuits of the capacitor line driving circuit 12 may be unified (FIG. 14 or FIG. 15).

<Embodiment 7>
As described above, in Patent Document 2 (FIGS. 8 and 10), a gate line (GL) is also used as a signal line used for capacitive coupling driving of a pixel, and a capacitance dedicated to capacitive coupling driving is used. A technique that does not use lines (CCL) is disclosed.

  In this method, the pixel electrode of each pixel is capacitively coupled to a gate line (adjacent gate line) that drives a pixel (adjacent pixel) of a pixel line adjacent to the pixel electrode. Then, the level of the pixel electrode to which the display signal (display data) is written is adjusted by changing the inactive level potential of the gate line drive signal. In the seventh embodiment, the present invention is applied to capacitive coupling driving of the method.

  FIG. 18 is a schematic block diagram showing a configuration of a display device 10D which is a liquid crystal display device according to the seventh embodiment. Since the display device 10D performs capacitive coupling driving using the gate line GL, the gate line driving circuit 11 also has a function of performing capacitive coupling driving, and a separate capacitive line driving circuit is not provided. Therefore, the gate line driving circuit 11 is only disposed on one side (left side) of the pixel 25.

  However, if the pitch of the unit circuits (unit shift register) of the gate line driving circuit 11 is larger than the pitch of the pixels 25 when the area of each pixel 25 is reduced, the gate line driving circuit 11 is replaced with a liquid crystal array. For example, the odd-numbered pixels may be driven by the left gate line driving circuit 11 and the even-numbered pixels may be driven by the right gate line driving circuit 11.

  In this embodiment, since capacitive coupling driving is performed using the gate line GL, the storage capacitor element 27 of each pixel 25 has a gate line GL (adjacent gate) for driving the pixel electrode Np of the pixel 25 and its adjacent pixel. Line). That is, in each pixel 25, the storage capacitor element 27 capacitively couples the pixel electrode Np and the adjacent gate line.

Here, the capacitive coupling drive using the gate line GL in this embodiment will be briefly described. The gate line driving circuit 11 sequentially selects and drives the gate lines GL ₁ , GL ₂ ,... By sequentially activating the gate line driving signals G ₁ , G ₂ ,. .

  In a certain pixel, when the corresponding gate line GL is activated, the pixel transistor 26 becomes conductive, and the display data signal D from the data line DL is written to the pixel electrode Np through it.

  Thereafter, when the gate line is deactivated, the pixel transistor 26 is turned off, and the display data signal D is held by the holding capacitor element 27. In the present embodiment, the potential of the pixel electrode Np is adjusted by changing the L level potential of the adjacent gate line at a predetermined timing thereafter.

Hereinafter, a more specific configuration example of the gate line driving circuit 11 according to the present embodiment will be described. 19 and 20 are diagrams showing an overall configuration of the gate line driving circuit 11 according to the present embodiment. Figure 19 shows the unit shift register SR ₁ to SR ₄ of the first four stages of the gate line driver circuit, FIG. 20 is a unit shift register two stages driving the last two lines of pixel column SR _m-1 , SR _m, and two-stage unit shift registers (dummy shift registers) SR _{m + 1} and SR _{m + 2} provided subsequently thereto. The gate line GL, the data line DL, and the dummy shift registers SR _{m + 1} and SR _{m + 2} shown in FIGS. 19 and 20 correspond to those shown in FIG. The pixel P in FIGS. 19 and 20 corresponds to the pixel 25 in FIG. Hereinafter, the unit shift registers SR _{1 to} SR _m and the dummy shift registers SR _{m + 1} and SR _{m + 2} may be collectively referred to as “unit shift register SR”.

  As shown in FIG. 18, in the present embodiment, the other end of the storage capacitor element 27 connected to the pixel electrode Np of each pixel P (pixel 25) is activated at the next gate line GL (next activation). Gate line GL). In other words, each pixel P is capacitively coupled using the next-stage gate line GL.

  As shown in FIGS. 19 and 20, each unit shift register SR includes an input terminal IN, first and second output terminals OUT and OUTS, first and second clock terminals CK1 and CK2, first and second polarity control. Terminals CTA and CTB and a reset terminal RST are provided. A gate line GL is connected to the first output terminal OUT of each unit shift register SR. That is, the signal G output from the first output terminal OUT is a vertical (horizontal) scanning pulse for activating the gate line GL.

The dummy shift register SR _{m + 1} is a shift register having the same configuration as the other unit shift registers SR, and a dummy line GL _{m + 1} that is a dummy gate line is connected to the first output terminal OUT. The dummy line GL _{m + 1} is not connected to the gate of the pixel transistor 26 of any pixel P, and is connected to the holding capacitor elements 27 of the pixels P _{m1 to} P _mr driven by the gate line drive signal G _m , It is capacitively coupled to the pixel electrode Np via the capacitive element 27.

The dummy shift register SR _{m + 2} may be the same as the unit shift register SR, but does not need to have the first output terminal OUT and the first and second polarity control terminals CTA and CTB (details will be described later). ), They are omitted.

  The clock signal generator 131 generates six clock signals CLKG1, CLKG2, CLKG3, CLKS1, CLKS2, and CLKS3. The clock signals CLKG1 to CLKG3 are three-phase clock signals having different phases. The clock signals CLKS1 to CLKS3 are also three-phase clock signals having different phases, and the phases are aligned with the clock signals CLKG1 to CLKG3, respectively. However, the clock signals CLKS1 to CLKS3 and the clock signals CLKG1 to CLKG3 have different L level (inactive level) potentials. When the L level potential of the clock signals CLKS1 to CLKS3 is defined as VSS1 and the L level potential of the clock signals CLKG1 to CLKG3 is defined as VSS2, the potential VSS2 is set higher than the potential VSS1 (VSS1 <VSS2). Further, it is assumed that all the H level potentials of the clock signals CLKG1 to CLKG3 and CLKS1 to CLKS3 are the potential VDD.

  One of the clock signals CLKG1 to CLKG3 is supplied to the first clock terminal CK1 of each unit shift register SR, and one of the clock signals CLKS1 to CLKS3 (of the first clock terminal CK1) is supplied to the second clock terminal CK2. Clock signal and phase). Specifically, the first and second clock terminals CK1 and CK2 of each unit shift register SR are input with a clock signal that is activated next to the first clock terminal CK1 and CK2, respectively.

In this embodiment, the clock signals CLKG1 to CLKG3 are repeatedly activated in the order of CLKG1, CLKG2, CLKG3, CLKG1,... Shall be activated. In this case, for example, if the clock signals CLKG1 and CLKS1 are input to the _k-th unit shift register SR _k , the clock signals CLKG2 and CLKS2 are input to the next unit shift register SR _{k + 1.} Further, clock signals CLKG3 and CLKS3 are input to the next unit shift register SR _{k + 2} . That is, the first and second clock terminals CK1 and CK2 of the unit shift register SR are activated in the order of SR ₁ , SR ₂ , SR ₃ ,.

  Similarly to the first embodiment, the frequency dividing circuit 20 outputs the polarity control signals VFR and / VFR obtained by dividing the start signal ST by a double period. One of the polarity control signals VFR and / VFR is input to the first and second polarity control terminals CTA and CTB of each unit shift register SR. The polarity control signals VFR and / VFR define the operation of capacitive coupling driving of adjacent pixels. Therefore, in each unit shift register SR, which of the polarity control signals VFR and / VFR is input to the first and second polarity control terminals CTA and CTB is written in the pixel P driven by the adjacent gate line GL. Determined by the polarity of the signal.

In the present embodiment, a gate line inversion driving method is assumed in which the polarity is inverted for each pixel line (for each gate line). In this case, as shown in FIGS. 19 and 20, the polarity control signals VFR and / VFR are exchanged for each stage and inputted to each of the unit shift registers SR. That is, in the odd stages (unit shift registers SR ₁ , SR ₃ ,...), The polarity control signal VFR is input to the first polarity control terminal CTA, and the polarity control signal / VFR is input to the second polarity control terminal CTB. Conversely, in the even-numbered stage, the polarity control signal / VFR is input to the first polarity control terminal CTA, and the polarity control signal VFR is input to the second polarity control terminal CTB.

  Although not shown, in the case of the frame inversion driving method in which the polarity of the display signal of all the pixels is inverted every frame, the polarity control signal VFR (or / VFR) is supplied to the first polarity control terminal CTA in all stages. ) And the polarity control signal / VFR (or VFR) is input to the second polarity control terminal CTB.

As described above, the signal G output from the first output terminal OUT of each unit shift register SR is used to drive the corresponding gate line GL. On the other hand, the second output terminal OUTS of each unit shift register SR is connected to its own next-stage input terminal IN and its own two-stage previous stage (previous stage) reset terminal RST. In other words, the input terminal IN of each unit shift register SR is connected to the second output terminal OUTS of its own previous stage, and the reset terminal RST is connected to the second output terminal OUTS of its own second stage (next stage). However, the start signal ST is input to the input terminal IN of the unit shift register SR ₁ which is the foremost stage.

The signal GS output from the second output terminal OUTS is not used for driving the gate line GL, but is used for the purpose of controlling the signal shift operation in the gate line driving circuit. Hereinafter, the signal G output from the first output terminal OUT is referred to as a “gate line drive signal”, and the signal GS output from the second output terminal OUTS is referred to as a “shift signal”. Also in this embodiment, the signal G _{m + 1} output from the first output terminal OUT of the dummy shift register SR _{m + 1} does not drive the gate line, but is referred to as “drive signal G _{m + 1} ”.

Further, the reset signal GS _{m + 1} output from the second output terminal OUTS of the dummy shift register SR _{m + 1} that is the second stage after the reset terminal RST of the unit shift register SR _m-1 that is the second stage from the end. Enter. Similarly, the shift signal GS _{m + 2} output from the second output terminal OUTS of the dummy shift register SR _{m + 2} that is the second stage is input to the reset terminal RST of the unit shift register SR _m of the last stage. .

On the other hand, the dummy shift registers SR _{m + 1} and SR _{m + 2} do not have their own second stage. Therefore, the shift signal GS _{m + 1} is input to the reset terminal RST of the dummy shift register SR _{m + 1} . Further, the reset terminal RST of the dummy shift register SR _{m + 2} has a clock signal (here, the clock signal having a phase different from that of the clock signal (here, the clock signal CLKS1) inputted to the first and second clock terminals CK1 and CK2 thereof. The clock signal CLKS2) delayed by 1H (one horizontal period) from the clock signal CLKS1 is input.

FIG. 21 is a specific circuit diagram of the unit shift register SR according to the present embodiment, which has been devised by the present inventor. Since all the unit shift registers SR constituting the gate line driving circuit have basically the same configuration, FIG. 21 representatively shows the _kth unit shift register SR _k .

  As a transistor used in the unit shift register SR, any of a metal-oxide semiconductor (MOS) transistor, a polysilicon thin film transistor (TFT), an amorphous silicon TFT, and an organic TFT can be used. In this embodiment, it is assumed that all the transistors constituting the unit shift register SR are N-type TFTs. Further, it is assumed that the pixel transistor 26 of each pixel P shown in FIGS. 19 and 20 is also an N-type TFT. Thus, by making the transistor of the unit shift register SR and the pixel transistor 26 have the same conductivity type, the number of manufacturing steps can be reduced.

  Hereinafter, the configuration of the unit shift register SR according to the seventh embodiment will be described. As shown in FIG. 21, in addition to the signal terminals shown in FIG. 19, the unit shift register SR is supplied with the low potential side power supply potential VSS1 (that is, the L level potential of the clock signals CLKS1 to CLKS3). The first power supply terminal S1, the second power supply terminal S2 to which the high potential side power supply potential VDD1 is supplied, the third power supply terminal S3 to which the low potential side power supply potential VSS3 is supplied, and the high potential side power supply potential VDD2 are supplied. A fourth power supply terminal S4 is provided.

  The reference potential of the display device is generally set based on the potential of the display signal written to the pixel. In the following description, the potential VSS1 is defined as the reference potential for simplicity. The potential VSS3 is set higher than the potential VSS1 and the potential VSS2 (that is, the L level potential of the clock signals CLKG1 to CLKG3). That is, the relationship VSS1 <VSS2 <VSS3 is established.

  Further, the potentials of the high-potential side power supply potentials VDD1 and VDD2 may be arbitrary as long as each transistor of the unit shift register SR can perform a predetermined operation. The same as the H level of the clock signals CLKG1 to CLKG3 and CLKS1 to CLKS3).

  As shown in FIG. 21, the unit shift register SR includes a gate line drive signal output unit 141, a shift signal output unit 142, a pull-up control unit 143, a first pull-down control unit 144, a second pull-down control unit 145, and a pull-down control signal holding. Part 146.

  The gate line drive signal output unit 141 is a circuit for outputting the gate line drive signal Gk from the first output terminal OUT, and includes transistors Q31, Q32A, Q32B, and a capacitive element C31. The transistor Q31 is connected between the first output terminal OUT and the first clock terminal CK1, and receives the clock signal CLKGi (any one of the clock signals CLKG1 to CLKG3) input to the first clock terminal CK1 as the first output terminal OUT. To supply. Therefore, the H level of the gate line drive signal Gk becomes the potential VDD corresponding to the H level of the clock signal CLKGi.

  The transistor Q32A is connected between the first output terminal OUT and the first power supply terminal S1, and the transistor Q32B is connected between the first output terminal OUT and the third power supply terminal S3. That is, the transistor Q32A supplies the potential VSS1 to the first output terminal OUT, and the transistor Q32B supplies the potential VSS3 to the first output terminal OUT. Therefore, the L level (inactive level) potential of the gate line drive signal Gk changes to the potential VSS1 or VSS3 depending on which of the transistors Q32A and Q32B is turned on.

  Here, a node to which the gate (control electrode) of the transistor Q31 is connected is defined as “node N31”. A capacitive element C31 is provided between the gate and source of the transistor Q31, that is, between the node N31 and the output terminal OUT. The capacitive element C31 is for capacitively coupling the output terminal OUT and the node N31 to enhance the boosting effect of the node N31 accompanying the increase in the level of the output terminal OUT. However, if the gate-channel capacitance of the transistor Q31 is sufficiently large, the capacitive element C31 can be replaced with it, and in that case, it may be omitted.

Shift signal output unit 142 is a circuit for outputting a shift signal GS _k from the second output terminal OUTS, consists transistor Q31S, Q32AS, from Q32BS. The transistor Q31S is connected between the second output terminal OUTS and the second clock terminal CK2, and receives the clock signal CLKSi (any one of the clock signals CLKS1 to CLKS3) input to the second clock terminal CK2 as the second output terminal OUTS. To supply. Therefore H-level shift signal GS _k is a potential VDD corresponding to the H level of the clock signal CLKSi.

The transistors Q32AS and Q32BS are both connected between the second output terminal OUTS and the first power supply terminal S1. That is, both the transistors Q32AS and Q32BS set the potential of the second output terminal OUTS to VSS1. Thus, L-level shift signal GS _k output from the second output terminal OUTS is always a potential VSS1.

  The gate of transistor Q31S is connected to the gate (node N31) of transistor Q31. The gate of transistor Q32AS is connected to the gate of transistor Q32A, and the gate of transistor Q32BS is connected to the gate of transistor Q32B. Here, a node to which the gates of the transistors Q32A and Q32AS are connected is defined as “node N32A”, and a node to which the gates of the transistors Q32B and Q32BS are connected is defined as “node N32B”.

Pull-up control unit 143 drives the transistor Q31, Q31S by controlling the level of the node N31, thereby controlling the H level output of the gate line driving signals Gk and the shift signal GS _k. The pull-up controller 143 includes transistors Q33 and Q34. The transistor Q33 has a gate connected to the input terminal IN, and is connected between the node N31 and the second power supply terminal S2. That is, the transistor Q33 charges the node N31 in response to the activation of the preceding stage shift signal GS _k-1 input to the input terminal IN. The transistor Q34 has a gate connected to the reset terminal RST, and is connected between the node N31 and the first power supply terminal S1. That is, the transistor Q34 discharges the node N31 in response to the activation of the shift signal GS _{k + 2 in} the second stage.

By the operation of the pull-up control unit 143, the transistors Q31 and Q31S are turned on in response to the activation of the preceding shift signal GS _k-1 , and are turned off in response to the activation of the shift signal GS _{k + 2 in} the subsequent second stage. To be driven.

The first and second pull-down control units 144 and 145 drive the transistors Q32A, Q32B, Q32AS, and Q32BS by controlling the levels of the nodes N32A and N32B, respectively. Thereby controlling the L level output of the gate line driving signals Gk and the shift signal GS _k. FIG. 21 shows an example in which the polarity control signal VFR is input to the first polarity control terminal CTA and the polarity control signal / VFR is input to the second polarity control terminal CTB. Which of the polarity control signals VFR and / VFR is input to the first and second polarity control terminals CTA and CTB is determined by the polarity of the display signal written to the pixel P driven by the adjacent gate line.

  The first pull-down controller 144 drives the transistors Q32A and Q32AS by charging and discharging the node N32A, and includes transistors Q35A, Q36A, and Q37A. The transistor Q35A has a gate connected to the node N32A, and is connected between the node N31 and the first power supply terminal S1. The transistor Q36A has a gate connected to the node N31, and is connected between the node N32A and the first power supply terminal S1. Therefore, transistor Q35A operates to discharge node N31 when node N32A is at H level, and transistor Q36A operates to discharge node N32A when node N31 is at H level. Therefore, when one of the nodes N31 and N32A is set to H level, the other is set to L level.

The transistor Q37A has a gate connected to the reset terminal RST, and is connected between the node N32A and the first polarity control terminal CTA. Therefore, the transistor Q37A operates to supply the level of the first polarity control terminal CTA to the node N32A in response to the activation of the shift signal GS _{k + 2 in} the second stage and the subsequent stage. That is, the node N32A is charged when the polarity control signal (VFR or / VFR) input to the first polarity control terminal CTA is at the H level, but is not charged when it is at the L level.

  The second pull-down control unit 145 drives the transistors Q32B and Q32BS by charging and discharging the node N32B, and includes transistors Q35B, Q36B, and Q37B. The transistor Q35B has a gate connected to the node N32B, and is connected between the node N31 and the first power supply terminal S1. The transistor Q36B has a gate connected to the node N31, and is connected between the node N32B and the first power supply terminal S1. Thus, transistor Q35B operates to discharge node N31 when node N32B is at H level, and transistor Q36B operates to discharge node N32B when node N31 is at H level. Accordingly, when one of the nodes N31 and N32B is set to H level, the other is set to L level.

The transistor Q37B has a gate connected to the reset terminal RST, and is connected between the node N32B and the second polarity control terminal CTB. Therefore, the transistor Q37B operates to supply the level of the second polarity control terminal CTB to the node N32B in response to the activation of the shift signal GS _{k + 2 at} the second stage. That is, the node N32B is charged if the control signal (VFR or / VFR) input to the second polarity control terminal CTB is H level, but not charged if it is L level.

  Since the polarity control signals VFR and / VFR input to the first and second polarity control terminals CTA and CTB are complementary signals, one of the nodes N32A and N32B is charged. That is, the polarity control signals VFR and / VFR function as control signals for selecting which of the nodes N32A and N32B is charged, that is, which of the transistors Q32A and Q32AS and the transistors Q32B and Q32BS is turned on.

  In the following, for the sake of simplicity, the polarity of the polarity control signals VFR, / VFR is assumed to be VDD (that is, the same as the H level of the clock signals CLKG1 to CLKG3, CLKS1 to CLKS3), and the L level potential is VSS1 (reference). Potential).

  The pull-down holding unit 146 is a circuit that holds the levels of the nodes N32A and N32B set by the first and second pull-down control units 144 and 145. The pull-down holding unit 146 includes transistors Q38A, Q38B, Q39A, Q39B, Q40A, and Q40B.

  Transistor Q38A has a gate connected to node N32B, and is connected between node N32A and first power supply terminal S1. The transistor Q39A is connected between the node N32A and the fourth power supply terminal S4, and the gate is connected to the fourth power supply terminal S4. That is, the transistor Q39A is diode-connected so that the fourth power supply terminal S4 side is an anode and the node N32A side is a cathode. Transistor Q38A is set to have a sufficiently lower on-resistance than transistor Q39A. Therefore, when the node N32B becomes H level and the transistor Q38A is turned on, the node N32A becomes L level. That is, the transistors Q38A and Q39A constitute a ratio type inverter having the transistor Q38A as a drive element, the transistor Q39A as a load element, the node N32B as an input terminal, and the node N32A as an output terminal.

  On the other hand, the transistor Q38B has a gate connected to the node N32A and is connected between the node N32B and the first power supply terminal S1. The transistor Q39B is connected between the node N32B and the fourth power supply terminal S4, and the gate is connected to the fourth power supply terminal S4. That is, the transistor Q39B is diode-connected so that the fourth power supply terminal S4 side is an anode and the node N32B side is a cathode. Transistor Q38B is set to have a sufficiently lower on-resistance than transistor Q39B. Therefore, when the node N32A becomes H level and the transistor Q38B is turned on, the node N32B becomes L level. That is, the transistors Q38B and Q39B constitute a ratio type inverter having the transistor Q38B as a drive element, the transistor Q39B as a load element, the node N32A as an input terminal, and the node N32B as an output terminal.

  In other words, the two inverters are connected on a loop to form a flip-flop circuit. Thus, the transistors Q39A and Q39B play a role of compensating for the potential drop of the H level caused by the leakage current when the nodes N32A and N32B which are output nodes of the flip-flop circuit hold the H level in a high impedance state. ing.

  The transistor Q40A has a gate connected to the node N31, and is connected between the node N32A and the first power supply terminal S1, and the transistor Q40B has a gate connected to the node N31. It is connected between the power supply terminal S1. Transistors Q40A and Q40B are set to have sufficiently lower on-resistance than transistors Q39A and Q39B, respectively. Normally, two output nodes of the flip-flop circuit are held in a state where one is at the H level and the other is at the L level. In this pull-down holding unit 146, the transistor Q40A is maintained while the node N31 is at the H level. , Q40B is turned on, both of the nodes N32A and N32B become L level.

FIG. 22 shows the unit shift register SR of this embodiment, which is cascaded in four stages, and more specifically, the first stage (first stage) to the fourth stage unit shift register SR ₁ to SR ₄ is shown. A start signal ST is input to the input terminal IN in the foremost stage, and the activation of the start signal ST triggers the gate line drive signals G ₁ , G ₂ , G ₃ , and G ₄ in order from the foremost stage. Operates to be activated.

Hereinafter, the operations of the unit shift registers SR _{1 to} SR ₄ shown in FIG. 22 will be described in detail. FIG. 23 is a waveform diagram for explaining the operation. The levels of the complementary polarity control signals VFR and / VFR alternate in the blanking period for each frame of the display device (time t ₁ and time t _{7 in} FIG. 23). Again, the period when the polarity control signal VFR is at the H level is defined as an odd frame, the period at the L level is defined as an even frame, and the threshold voltages of all the transistors are assumed to be equal, and the value thereof is Vth.

  In FIG. 23, for simplicity of illustration, the falling timing (deactivation timing) of a certain clock signal and the rising timing (activation timing) of the clock signal to be activated next are shown to be simultaneous. Has been. Actually, in consideration of signal delay and the like, as shown in FIG. 24, there is a predetermined interval between the active period of each clock signal (the period when it becomes H level) and the active period of the clock signal to be activated next. An interval Δt (hereinafter referred to as “clock time interval”) is provided.

Times t _{1 to} t ₆ in FIG. 24 correspond to those shown in FIG. In FIG. 24, times t _{1 to} t ₆ correspond to the falling timing of each clock, and then the clock signal activated next rises when the clock time interval Δt elapses. Hereinafter, description will be made using FIG. 23 ignoring Δt.

Referring to FIGS. 22 and 23, assume that an odd frame is reached at time t ₁ . That is, the polarity control signals VFR and / VFR change to the H level and the L level, respectively. In each unit shift register SR, the voltages of the control terminals CTA and CTB change. At this time, the transistors Q37A and Q37B are off, and the levels of the nodes N32A and N32B are held by the pull-down holding unit 146. Therefore, there is no level change of the nodes N32A and N32B.

At this time, in the unit shift registers SR ₁ and SR ₃ which are odd stages, the node N32A is at the L level and the node N32B is at the H level. Conversely, in the unit shift registers SR ₂ and SR ₄ that are even stages, the node N32A is at the H level and the node N32B is at the L level. Accordingly, in the unit shift registers SR ₁ and SR ₃ , the transistor Q32B of the gate line drive signal output unit 141 is on, and their first output terminals OUT (gate line drive signals G ₁ and G ₃ ) are at the potential VSS3. L level. Conversely, in the unit shift registers SR ₂ and SR ₄ , the transistor Q32A of the gate line drive signal output unit 141 is on, and the first output terminal OUT (shift signals GS ₂ and GS ₃ ) is at the L level of the potential VSS1. ing.

On the other hand, in the shift signal output unit 142 of the unit shift registers SR ₁ and SR ₃ , the transistor Q32BS is turned on, and the second output terminal OUTS (shift signals GS ₁ and GS ₃ ) is at the L level of the potential VSS1. In the shift signal output unit 142 of the unit shift registers SR ₂ and SR ₄ , the transistor Q32AS is turned on, and the second output terminal OUTS (shift signals GS ₁ and GS ₃ ) is also at the L level of the potential VSS1.

Although the shift signals GS _{1 to} GS ₄ are not shown in FIG. 23, their L-level potential is a constant value VSS ₁ , and except for this, the gate line drive signals G _{1 to} G ₄ and It should be noted here that the level transition is similarly performed.

At time t ₂ , the start signal ST input to the input terminal IN of the unit shift register SR ₁ becomes H level. The operation of the unit shift register SR ₁ at this time will be described. When the start signal ST becomes H level, the pull-up control unit 143 turns on the transistor Q33. At this time, since the node N32B is at the H level, the transistor Q35B is on. However, since the on-resistance of the transistor Q33 is set sufficiently lower than that of the transistor Q35B, the node N31 is at the H level (VDD−Vth). Hereinafter, a state in which the node N31 of each unit shift register SR is at the H level is referred to as a “set state”.

By unit shift register SR ₁ of the node N31 becomes H level, the transistor Q36B, Q40B is turned on, the node N32B becomes L level (VSS1). When the node N32B becomes L level, the transistor Q38A is turned off. However, when the node N31 becomes H level, the transistors Q36A and Q40A are turned on, so that the node N32A is maintained at L level. With such unit shift register SR ₁ is in the set state, the node N32A, N32B are both at the L level, the transistor Q32A for pulling down the first output terminal OUT, Q32B, and Q32AS to pull down a second output terminal OUTS, All Q32BSs are turned off.

At time t ₂ , the node N31 of the unit shift register SR ₁ becomes H level, so that the transistor Q31 is turned on in the gate line drive signal output unit 141. So the clock signal CLKG1 is supplied to the first output terminal OUT of the order unit shift register SR _1. Since the clock signal CLKG1 At time t ₂ is the L level, the gate line driving signals G1 remains at L level, the potential thereof changes to the same VSS2 the L level of the clock signal CLKG1.

The unit shift register SR ₁ of the shift signal output unit 142, the transistor Q31S is turned on, the clock signal CLKS1 to the second output terminal OUTS is to be supplied, L-level potential of the clock signal CLKS1 is the VSS1 Therefore, there is no change in the L level potential of the shift signal GS ₁ .

At time t _3, after the start signal ST has become L level, the clock signal CLKG1 becomes the H level. The operation of the unit shift register SR ₁ at this time will be described. In the gate line driving signal output unit 141 of the unit shift register SR _1, H level of the clock signal CLKG1 to the first output terminal OUT through the transistor Q31 is transmitted. That gate line drive signal G1 becomes H level, the gate lines GL ₁ becomes active (selected).

On the other hand, in the gate line drive signal output unit 142, the H level of the clock signal CLKS1 is transmitted to the second output terminal OUTS through the transistor Q31S. That is, the shift signal GS ₁ becomes H level.

Note that the transistor Q33 is turned off when the start signal ST becomes L level, and at this time, the node N31 is in a floating state. Therefore, when the levels of the first and second output terminals OUT and OUTS rise, the potential of the node N31 also rises due to the coupling between the gate-channel capacitances of the transistors Q31 and Q31S and the capacitive element C31. As a result, the transistors Q31 and Q31S operate in the non-saturated region while their gate-source potential is kept large. Therefore, the H level potential of the gate line drive signal G ₁ is the same VDD as the H level of the clock signal CLKG1, and the H level potential of the shift signal GS ₁ is also the same VDD as the H level of the clock signal CLKS1.

When the shift signal GS ₁ output from the unit shift register SR ₁ becomes H level, the input terminal IN of the unit shift register SR ₂ to which it is input becomes H level. The operation of the unit shift register SR ₂ at this time will be described. When the shift signal GS ₁ becomes the H level at time t _3, the unit shift register SR _2, transistor Q33 node N31 turned on becomes H level (i.e., the unit shift register SR ₂ is set state).

As a result, the transistors Q36A and Q40A are turned on, the node N32A becomes L level, and the transistors Q32A and Q32AS are turned off. At this time, the transistors Q36B and Q40B are also turned on, the node N32B is maintained at the L level, and the transistors Q32B and Q32BS are maintained off. Further, since the transistors Q31, Q31S is turned on, the gate line drive signal G ₂ is becomes L level of well potential VSS2 the clock signal CLKG2, shift signal GS ₂ is also at the L level potential VSS1 clock signal CLKS2.

Subsequently, the clock signal CLKG1 becomes L level (VSS2) at time t _4. The operation of the unit shift register SR ₁ at this time will be described. The transistor Q31 of the unit shift register SR ₁ is turned on, the first output terminal OUT by the transistor Q31 is discharged, the gate line drive signal G ₁ is also at the L level potential VSS2 the clock signal CLKG1. Thereby, the selection period of the gate line GL ₁ ends. Since this time becomes the clock signal CLKS1 also L level (VSS1), the second output terminal OUTS is discharged by the transistor Q31S, shift signal GS ₁ becomes L level (VSS1).

In addition the time t _4, after the clock signal CLKG1 becomes L level, the clock signal CLKG2 supplied to the first clock terminal CK1 of the unit shift register SR ₂ becomes the H level. The operation of the unit shift register SR ₂ at this time will be described. Since the transistor Q31 of the unit shift register SR ₂ is on, the H level of the clock signal CLKG2 is transmitted to the first output terminal OUT, and the gate line drive signal G ₂ becomes the H level (VDD). As a result, the gate line GL ₂ is selected. Since the clock signal CLKS2 also becomes H level, it is transmitted to the second output terminal OUTS through the transistor Q31S, will shift signal GS ₂ is H level (VDD).

When the shift signal GS ₂ output from the unit shift register SR ₂ becomes H level, the input terminal IN of the unit shift register SR ₃ to which it is input becomes H level. The operation of the unit shift register SR ₃ at this time will be described. In the unit shift register SR ₃ , when the input terminal IN becomes H level, the transistor Q 33 is turned on and the node N 31 becomes H level (that is, the unit shift register SR ₃ is set).

As a result, transistors Q36B and Q40B are turned on, node N32B goes to L level, and transistors Q32B and Q32BS are turned off. At this time, the transistors Q36A and Q40A are also turned on, the node N32A is maintained at the L level, and the transistors Q32A and Q32AS are maintained off. Further, since the transistors Q31, Q31S is turned on, the gate line drive signal G ₃ are become L level also potential VSS2 the clock signal CLKG3, shift signal GS ₃ is also at the L level potential VSS1 clock signal CLKS3.

At time t _5, the clock signal CLKG2 becomes L level (VSS2). The operation of the unit shift register SR ₂ at this time will be described. Since the transistor Q31 in the unit shift register SR ₂ is turned on, the first output terminal OUT is discharged through it, the gate line drive signal G ₂ is also at the L level potential VSS2 the clock signal CLKG2. Thereby, the selection period of the gate line GL ₂ ends. Since this time becomes the clock signal CLKS2 also L level (VSS1), the second output terminal OUTS is discharged by the transistor Q31S, shift signal GS ₂ becomes L level (VSS1).

In addition the time t _5, after the clock signal CLKG2 becomes L level, the clock signal CLKG3 inputted to the first clock terminal CK1 of the unit shift register SR ₃ becomes the H level. The operation of the unit shift register SR ₃ at this time will be described. Since the transistor Q31 of the unit shift register SR ₃ is ON, the first output terminal OUT is H level of the clock signal CLKG3 is transmitted, a gate line driving signal G ₃ becomes H level (VDD) therethrough. As a result, the gate line GL ₃ is selected. Since the clock signal CLKS3 also becomes H level, it is transmitted to the second output terminal OUTS through the transistor Q31S, will shift signal GS ₃ is H level (VDD).

When the shift signal GS ₃ output by the unit shift register SR ₃ becomes the H level, the input terminal IN of the unit shift register SR ₄ becomes H level. The operation of the unit shift register SR ₄ at this time will be described. In the unit shift register SR ₄ , when the input terminal IN becomes H level, the transistor Q 33 is turned on and the node N 31 becomes H level (that is, the unit shift register SR ₄ is set).

As a result, the transistors Q36A and Q40A are turned on, the node N32A becomes L level, and the transistors Q32A and Q32AS are turned off. At this time, the transistors Q36B and Q40B are also turned on, the node N32B is maintained at the L level, and the transistors Q32B and Q32BS are maintained off. Further, since the transistors Q31, Q31S is turned on, the gate line driving signal G ₄ are become L level also potential VSS2 the clock signal CLKG1, also becomes L level potential VSS1 shift signal GS ₄ the clock signal CLKS1.

The shift signal GS ₃ output by the unit shift register SR _3, since also input to the reset terminal RST of the unit shift register SR _1, the reset terminal RST of the time t ₅ the unit shift register SR ₁ is H level . The operation of the unit shift register SR ₁ at this time will be described. The unit shift register SR _1, the reset terminal RST becomes the H level, the transistor Q34 is turned on, the node N31 is discharged to L level (VSS1). Hereinafter, a state in which the node N31 of each unit shift register SR is at the L level is referred to as a “reset state”. When node N31 becomes L level, transistors Q31, Q31S, Q36A, Q36B, Q40A, Q40B are turned off.

Further, when the reset terminal RST becomes H level, the transistors Q37A and Q37B are also turned on. The unit shift register SR _1, the polarity control signal VFR to the first polarity control terminal CTA is inputted, the polarity control signal / VFR is input to the second polarity control terminal CTB. In the odd frame, the polarity control signal VFR is at the H level and the polarity control signal / VFR is at the L level. At this time, the control terminal CTA of the unit shift register SR ₁ is at the H level (VDD), and the second polarity control terminal CTB is L level. Therefore, the node N32A is charged through the transistor Q37A and becomes the H level (VDD-Vth), but the node N32B remains at the L level. As a result, transistor Q32A, only the transistor Q32A of Q32B is turned on, the potential VSS1 of the first power supply terminal S1 is supplied to the first output terminal OUT, L-level potential of the gate line drive signal G ₁ is changed to VSS1 (Descent).

  Thus, when the node N32A becomes H level and the node N32B becomes L level, in the pull-down holding unit 146, the transistor Q38A is turned off and the transistor Q38B is turned on. As a result, the flip-flop circuit composed of transistors Q38A, Q38B, Q39A, and Q39B holds the H level of node N32A and the L level of node N32B.

The state of the unit shift register SR ₁ is continued for about one frame period until the signal (start signal ST) input to the input terminal IN in the next frame becomes H level (until time t _{8 in} FIG. 23). .

At time t _6, the clock signal CLKG3 becomes L level (VSS2). The operation of the unit shift register SR ₃ at this time will be described. The transistor Q31 of the unit shift register SR ₃ is ON, the first output terminal OUT is discharged through it, the gate line drive signal G ₃ are also at the L level potential VSS2 the clock signal CLKG3. As a result, the selection period of the gate line GL ₃ ends. Since this time becomes the clock signal CLKS3 also L level (VSS1), the second output terminal OUTS is discharged by the transistor Q31S, shift signal GS ₃ becomes L level (VSS1).

In addition the time t _6, after the clock signal CLKG2 becomes L level, the clock signal CLKG1 becomes H level again. At this time, the unit shift register SR ₁ is in the reset state, and the transistors Q31 and Q31S are off, so the potentials of the gate line drive signal G ₁ and the shift signal GS ₁ do not change.

On the other hand, the unit shift register SR ₄ is set state. The operation of the unit shift register SR ₄ at this time will be described. In the unit shift register SR ₄ , since the transistor Q 31 is on, the H level of the clock signal CLKG 4 is transmitted to the first output terminal OUT through the transistor Q 31, and the gate line drive signal G 4 becomes the H level (VDD). As a result, the gate line GL ₄ is selected. Since the clock signal CLKS4 also becomes H level, it is transmitted to the second output terminal OUTS through the transistor Q31S, comprising shift signal GS ₄ to H level (VDD).

The shift signal GS ₄ output from the unit shift register SR ₄ is input to the input terminal IN of the unit shift register SR ₅ (not shown). Thus at time t ₆ shift signal GS ₄ becomes H level, the same operation as the unit shift register SR ₃ in the unit shift register SR ₁ or time t _4, at time t _2, the a unit shift register SR ₅ in a set state Become.

The shift signal GS _4, since also input to the reset terminal RST of the unit shift register SR _2, reset terminal RST of the time t ₆ the unit shift register SR ₂ becomes the H level. The operation of the unit shift register SR ₂ at this time will be described. In the unit shift register SR ₂ , when the reset terminal RST becomes H level, the transistor Q 34 is turned on, and the node N 31 is discharged to L level (VSS 1) (that is, the unit shift register SR ₂ is reset). When node N31 becomes L level, transistors Q31, Q31S, Q36A, Q36B, Q40A, Q40B are turned off.

Further, when the reset terminal RST becomes H level, the transistors Q37A and Q37B are also turned on. In the unit shift register SR ₂ , the polarity control signal / VFR is input to the first polarity control terminal CTA and the polarity control signal VFR is input to the second polarity control terminal CTB. At this time, the control of the unit shift register SR ₂ is performed. The terminal CTA is at L level, and the second polarity control terminal CTB is at H level. Therefore, the node N32A remains at the L level, but the node N32B is charged through the transistor Q37B and becomes the H level (VDD−Vth). As a result, transistor Q32A, only the transistor Q32B of Q32B is turned on, the potential VSS3 the third power supply terminal S3 is supplied to the first output terminal OUT, L-level potential of the gate line drive signal G ₃ are changed in VSS3 (To rise.

  Thus, when the node N32A becomes L level and the node N32B becomes H level, the transistor Q38A is turned on and the transistor Q38B is turned off in the pull-down holding unit 146. As a result, the flip-flop circuit composed of transistors Q38A, Q38B, Q39A, and Q39B holds the L level of node N32A and the H level of node N32B.

The state of the unit shift register SR ₂ is continued for about one frame period until the signal (shift signal GS ₁ ) input to the input terminal IN becomes H level in the next frame (until time t _{9 in} FIG. 23). The

Thereafter, in the odd-numbered frame, the same operation as that of the unit shift registers SR _{1 to} SR ₄ described above is performed in the unit shift registers SR _{5 to} SR _m .

As a result, the gate line drive signal G and the shift signal GS are sequentially transmitted from the unit shift registers SR _{1 to} SR _m in synchronization with the clock signals CLKG _{1 to} CLKG _{3 and} CLKS _{1 to} CLKS 3 (unit shift registers SR ₁ , SR ₂ ,. , SR _m in this order) are activated. However, in the odd-stage gate line drive signals G ₁ , G ₃ , G ₅ ,..., An L level potential drop (change from VSS2 to VSS1) occurs after the active period (H level period). In the even-numbered gate line drive signals G ₂ , G ₄ , G ₆ ,..., An L level potential rise (change from VSS2 to VSS3) occurs after the active period.

And when moving to an even frame, the polarity control signal VFR is L level, the polarity control signal / VFR switched to H level at time t _7. At this time, since the levels of the nodes N32A and N32B of each unit shift register SR are held by the pull-down control signal holding unit 146, the level of the gate line drive signals G _{1 to} G _n does not change.

As mentioned earlier, the H level of the node N32A in the unit shift register SR _1, L level of the node N32B is the start signal ST in the next even frame is maintained until time t ₈ becomes H level. This state is the same as that of the unit shift register SR ₂ before the time t ₃ . Accordingly, the operation of the unit shift register SR ₁ after time t ₈ is the same as that of the unit shift register SR ₂ after time t ₃ described above.

Therefore, as shown in FIG. 23, the gate line drive signal G ₁ becomes H level (VDD) at time t ₉ when the clock signal CLKG ₁ next becomes H level, and becomes L level at time t ₁₀ when the clock signal CLKG 1 becomes L level. (VSS2). The shift signal GS ₃ the unit shift register SR ₃ outputs is at time t ₁₁ becomes H level, L level of the potential of the gate line drive signal G ₁ is to vary (increase) to VSS3 from VSS2.

On the other hand, L level, H level of the node N32B node N32A in the unit shift register SR ₂ is shifted signal GS ₁ with the next even frame is maintained until time t ₉ becomes H level. This state is the same as that of the unit shift register SR ₁ before the time t ₂ . Therefore, the operation of the unit shift register SR ₂ after time t ₉ is the same as that of the unit shift register SR ₁ after time t ₂ described above.

Therefore, as shown in FIG. 23, the gate line drive signal G ₂ becomes H level (VDD) at time t ₁₀ when the clock signal CLKG ₂ next becomes H level, and becomes L level at time t ₁₁ when the clock signal CLKG 2 becomes L level. (VSS2). The shift signal GS ₄ the unit shift register SR ₄ outputs is at time t ₁₂ becomes H level, L level of the potential of the gate line drive signal G ₂ is changed to VSS1 from VSS2 (descending).

As described above, in the case of the even frame, the operation in the unit shift register SR is interchanged between the even stage and the odd stage as compared to the case of the odd frame. That is, even in an even frame, the unit shift registers SR ₁ , SR ₂ ,..., SR _m still activate the gate line driving signal G and the shift signal GS in this order, but the odd-numbered gate line driving signals are not changed. In G ₁ , G ₃ , G ₅ ,..., An L level potential rise (change from VSS 2 to VSS 3) occurs after the active period, and even-numbered gate line drive signals G ₂ , G ₄ , G ₆ ,. In ..., an L-level potential drop (change from VSS2 to VSS1) occurs after the active period.

Hereinafter, operations and effects of capacitive coupling driving of the pixel will be described. Here, attention is paid to the gate line GL ₁ shown in FIG. In the active period (time t ₃ to time t _{4 in} FIG. 23) of the gate line driving signal G ₁ in the odd frame, the pixel switch elements (hereinafter “pixel transistors”) 26 of the pixels P _{11 to} P _1r are turned on, Display signals (display data) are written from the data lines DL _{1 to} DL _m to the pixel electrodes Np of the pixels P _{11 to} P _1r . In the present embodiment, positive display data VD (+) is written to each pixel electrode Np of the pixels P _{11 to} P _1r in the odd frame. Pixel P ₁₁ storage capacitor 27 of each end of the to P _1r is connected to the gate line GL _2, as shown in FIG. 23, the gate line GL ₂ (gate line drive signal G ₂₎ at this time is L potential VSS2 It is a level.

When the writing of the pixels P _{11 to} P _{1r to} the pixel electrode Np is completed at time t ₄ and the gate line drive signal G ₁ becomes the L level of the potential VSS2, the pixel transistors 26 of the pixels P _{11 to} P _1r are turned off. Thus, the pixel electrodes Np of the pixels P _{11 to} P _1r are separated from the data line DL ₁ and are in a floating state.

At time t ₄ , the gate line drive signal G ₂ subsequently becomes the H level of the potential VDD. Since the pixel electrodes Np of the pixels P _{11 to} P _1r are capacitively coupled to the data line DL ₂ via the storage capacitor element 27, when the potential of the gate line drive signal G ₂ rises, the rise is a predetermined ratio ( The potential of the pixel electrodes Np of the pixels P _{11 to} P _1r is increased by a ratio of the parasitic capacitance value associated with the pixel electrode Np and the capacitance value of the storage capacitor element 27).

At time t ₅ , the gate line drive signal G ₂ returns to the L level of the potential VSS2. The size of the descent of the gate line drive signal G ₂ potential are the same as the size of the increase of the gate line drive signal G ₂ in the time t _4, the level of the pixel P ₁₁ to P _1r of the pixel electrode Np data Return to the level at the time of writing. As described above, the potentials of the pixel electrodes Np of the pixels P _{11 to} P _1r rise between the times t ₄ to t ₅ , but the response speed of the liquid crystal element 28 is not so fast, and thus such a short period ( The potential change of 1H) does not affect the screen display.

Then at time t _6, when the L-level potential of the gate line drive signal G ₂ rises VSS3 from VSS2, the rise raises the potential of the pixel P ₁₁ to P _1r pixel electrode Np in a predetermined ratio. Because what is written in the time the pixel P ₁₁ to P _1r pixel electrode Np is a positive polarity of the display data VD (+), the display by the potential of the pixel P ₁₁ to P _1r pixel electrode Np rises The signal will be amplified. Since then is no potential of the gate line drive signal G ₂ to the next frame changes, the level of the pixel P ₁₁ to P _1r of the pixel electrode Np is kept high by a predetermined potential than the time of data writing.

In the active period (time t ₉ to time t ₁₀ ) of the gate line driving signal G _{1 in} the next frame (even frame), the data lines DL _{1 to} DL _{m are connected} to the pixel electrodes Np of the pixels P _{11 to} P _1r. The negative display data VD (−) is written. As shown in FIG. 23, the gate line GL ₂ (gate line drive signal G ₂ ) at this time is at the L level of the potential VSS2.

When the writing of the pixels P _{11 to} P _{1r to} the pixel electrode Np is completed at time t ₁₀ and the gate line drive signal G ₁ becomes the L level of the potential VSS2, the pixel transistors 26 of the pixels P _{11 to} P _1r are turned off. Thus, the pixel electrodes Np of the pixels P _{11 to} P _1r are separated from the data line DL ₁ and are in a floating state. At time t ₁₀ , the gate line drive signal G ₂ subsequently becomes the H level of the potential VDD. The gate line potential rise of the drive signal G ₂ is, increasing the potential of the pixel P ₁₁ to P _1r pixel electrode Np in a predetermined ratio.

At time t _11, the gate line drive signal G ₂ returns to the L level potential VSS2. The size of the descent of the gate line drive signal G ₂ potential are the same as the size of the increase of the gate line drive signal G ₂ at the time t _10, the level of the pixel P ₁₁ to P _1r of the pixel electrode Np data Return to the level at the time of writing.

At time t ₁₂ , when the L level potential of the gate line drive signal G ₂ falls from VSS ₂ to VSS 1, the fall amount lowers the potentials of the pixel electrodes Np of the pixels P _{11 to} P _1r at a predetermined ratio. It is what is written in the time the pixel P ₁₁ to P _1r pixel electrode Np negative polarity display data VD (-) because it is, displayed by the potential of the pixel P ₁₁ to P _1r pixel electrode Np is lowered The signal will be amplified. Since then are not the potential change the gate line drive signal G ₂ to the next frame, the level of the pixel P ₁₁ to P _1r of the pixel electrode Np is maintained than when the data is written by a predetermined potential low.

Here, the capacitive coupling driving of the pixels P _{11 to} P _1r driven by using the gate line GL ₁ is described as a representative, but the same operation is performed for the other pixels P.

  As described above, the display signal amplification effect can be obtained by performing capacitive coupling driving of the pixels, so that the amplitude of the display signal supplied to the data line (source line) can be reduced and consumed by the data line. Power can be reduced.

Although not described above, the dummy shift register SR _{m + 1} performs substantially the same operation as the unit shift registers SR _{1 to} SR _m . In other words, the shift signal GS _{m + 1} output from the second output terminal OUTS is used to reset the unit shift register SR _m-1 in the preceding two stages and is output from the first output terminal OUT. The signal G _{m + 1} is used for capacitive coupling driving of the pixels P _{m1 to} P _mr .

The dummy shift register SR _{m + 2} is provided only for the purpose of setting the dummy shift register SR _{m + 2} in a reset state. Therefore, the dummy shift register SR _{m + 2} only needs to be able to output the shift signal GS _{m + 2} from the second output terminal OUTS, and the shift signal GS _{m + 2} is input to the reset terminal of the dummy shift register SR _{m + 1} . Therefore, the dummy shift register SR _{m + 2} does not need to have the first output terminal OUT and the first and second polarity control terminals CTA and CTB for determining the L level potential. In the dummy shift register SR _{m + 2 of the} present embodiment, they are omitted.

  As described above, according to the unit shift register of this embodiment, it is possible to perform capacitive coupling driving of pixels, and it is possible to configure only with transistors of the same conductivity type. Therefore, it is possible to reduce the number of manufacturing steps when the gate line driver circuit configured using the unit shift register is formed over the same substrate as the pixel. As a result, in addition to the reduction in power consumption of the image display device by capacitive coupling driving, it is possible to contribute to cost reduction and reduction of the area occupied by the gate line driving circuit.

  In the circuit of FIG. 21, the transistors Q36A and Q40A all have the same gate, source, and drain, and either of them may be omitted. Similarly, since the transistors Q36B and Q40B all have the same gate, source and drain, either of them may be omitted. In FIG. 21, for the purpose of facilitating the explanation of the functions of the first and second pull-down control units 144 and 145 and the pull-down holding unit 146, both the transistors Q36A and Q40A and the transistors Q36B and Q40B are provided. showed that.

In the present embodiment, the pixel electrode Np of each pixel P is capacitively coupled to the gate line GL at the next stage of the gate line GL corresponding to the pixel P via the storage capacitor element 27. That is, capacitive coupling driving of each pixel P is performed using the gate line driving signal G for driving the next-stage gate line GL. Therefore, the pixel line in the first row is not used for capacitive coupling driving of the other pixels P. Therefore, the L level of the change in the L level of the gate line drive signal G ₁ may be a constant potential.

  Furthermore, in the present embodiment, the timing for performing capacitive coupling driving of each pixel (change in the level of the display signal written to the pixel electrode Np) is when the gate line GL in the second stage is activated. That is, the signal input to the reset terminal RST of each unit shift register SR is the shift signal GS in the second stage after itself. However, the timing of capacitive coupling driving is not limited thereto. The timing may be after the display signal is written to the pixel electrode Np of the pixel and the pixel transistor 26 is turned off. Therefore, the timing may be the timing at which the gate line GL at three or more stages is activated.

  For example, the timing when the gate line GL at the third stage is activated may be used. In this case, the shift signal GS at the third stage after the third stage may be input to the reset terminal RST of each unit shift register SR. However, in this case, when the multi-stage shift register is driven using the three-phase clock signals (clock signals CLKG1 to CLKG3 and clock signals CLKS1 to CLKS3) as in the present embodiment, the reset terminal RST of the unit shift register SR becomes H Since the clock signal of the first clock terminal CK1 is activated at the same time as the level is reached (that is, before the transistors Q31 and Q31S are completely turned off), an error signal is generated in the gate line drive signal G and the shift signal GS. Therefore, in this case, it is necessary to drive the multistage unit shift register SR using a clock signal having four or more phases. That is, when the capacitive coupling drive of each pixel is performed at the timing when the gate line GL after n stages is activated, a clock signal of n + 1 phase or more is required. When increasing the number of clock signals, it should be noted that the number of external input terminals and the formation area of the clock wiring increase.

<Eighth embodiment>
Embodiment 8 shows an example in which the present invention is applied to a display device that performs common AC driving. FIG. 25 is a schematic block diagram showing a configuration of a display device 10E which is a liquid crystal display device according to the eighth embodiment. The display device 10E performs common AC driving in which the potential of the common electrode (common electrode) is changed in an AC manner.

  In the present embodiment, as shown in FIG. 25, the gate line driving circuit 11 is disposed on one side (left side) of the liquid crystal array unit 15, and the common electrode line driving circuit 13 is disposed on the other side (right side). Both the gate line driving circuit 11 and the common electrode line driving circuit 13 are configured by using TFTs formed on an insulating substrate like the pixels 25.

  The arrangement of the gate line driving circuit 11 and the common electrode line driving circuit 13 shows an example. For example, the gate line driving circuit 11 and the common electrode line driving circuit 13 are integrated, and only one side of the liquid crystal array unit 15 (the left side) Alternatively, it may be disposed only on the right side). When a circuit in which the gate line driving circuit 11 and the common electrode line driving circuit 13 are integrated (integrated circuit) is used, when the unit circuit pitch of the integrated circuit is larger than the pitch of the pixels 25, the integrated circuit is For example, the odd-numbered pixels may be driven by the left integrated circuit, and the even-numbered pixels may be driven by the right integrated circuit.

The basic operation of the gate line driving circuit 11 of this embodiment is the same as that shown in FIG. 4 in the first embodiment. However, the gate line driving circuit 11 of FIG. 25 is further provided with a dummy shift register SR _{m + 1 of} one stage following the last stage (m-th stage). Output signals G _{m + 1} of the dummy shift register SR m _{+ 1} does not drive the gate lines GL, since the usual gate line drive signal G ₁ ~Gm the same quality of the signal, the "drive signal G _{m + 1"} Called. The drive control circuit 110 (including the level shifter 111) in FIG. 25 may be the same as that shown in FIG.

Each pixel 25 of the liquid crystal array unit 15 is disposed in the vicinity of the intersection of the gate line GL and the data line DL, as in the first embodiment. In FIG. 25, the gate lines GL ₁ , GL ₂ , GL _{m of} the first row, the second row, and the last row, the data lines DL ₁ , DL _{2 of} the first column and the second column, and the intersections thereof are arranged. These six pixels 25 are representatively shown. In the present embodiment, the common electrode line COML _1, COML _2, ..., COML _m (collectively, "the common electrode line COML") are respectively the gate lines GL _1, GL _2, ..., disposed in parallel to GL _m The These common electrode lines COML ₁ , COML ₂ ,..., COML _m are common electrode line drive signals COM ₁ , COM 2,..., COM _m (generic name “common electrode line drive signal COM”) generated by the common electrode line drive circuit 13. Respectively. Incidentally illustrates representatively the common electrode line COML _1, COML _2, COML _m respectively corresponding to FIG. 25, gate lines _{GL 1, GL 2, GL m} .

  The configuration of each pixel 25 is substantially the same as that shown in FIG. 2 except that the common electrode Nc that is one end of the liquid crystal element 28 is connected to the common electrode line COML. That is, in the pixel 25 of the present embodiment, the liquid crystal element 28 is connected between the pixel electrode Np and the common electrode line COML.

  In the pixel 25 of FIG. 25, the storage capacitor element 27 is also connected between the pixel electrode Np and the common electrode line COML in the same way as the liquid crystal element 28, but this is due to the layout design. Common AC driving is a technique for adjusting the voltage applied to the liquid crystal element 28 by changing the potential of the common electrode Nc (see FIG. 2), which is one end of the liquid crystal element 28. Therefore, one end of the storage capacitor element 27 (the storage electrode Nh in FIG. 2) is not necessarily connected to the common electrode line COML, and may be connected to a constant potential source having a predetermined impedance, for example. In this case, the load capacity of the common electrode line drive circuit 13 can be reduced by the amount that the storage capacitor element 27 is not connected to the common electrode line COML. However, a separate wiring for connecting the holding electrode Nh to the constant voltage source is required.

  The display device 10E according to the present embodiment also includes the frequency divider circuit 20 (FIG. 7) according to the present invention, and the frequency divider circuit 20 has a polarity control signal having a cycle twice that of the start signal ST. VFR and / VFR are output to the common electrode line drive circuit 13.

  The common electrode line driving circuit 13 performs common AC driving by changing the level of each common electrode line COML (common electrode line driving signal COM) at a predetermined timing. As described above, in common AC driving, it is necessary to change the potential of the common electrode in accordance with the polarity of the display data signal that is inverted at a constant period. Therefore, the common electrode line drive circuit 13 needs to change the level (polarity) of each common electrode line COML according to the polarity of the display data signal D written to the corresponding pixel 25.

  As shown in Patent Document 4 above, gate line inversion driving and frame inversion driving are possible even in common AC driving. For example, in the display device 10E of FIG. 25, when the polarities of the display data signal D written to the pixels are reversed in the odd and even rows and inverted for each frame, the gate line inversion drive is performed. In this case, the common electrode line driving circuit 13 controls the polarity of the level of each common electrode line COML so that the odd rows and the even rows are opposite in accordance with the polarity of the display data signal D. On the other hand, if display data signals D to be written in pixels in all rows are aligned and inverted for each frame, frame inversion driving is performed. In this case, the direction of the level change of each common electrode line COML is all aligned. In the present embodiment, a case where the present invention is applied to gate line inversion driving type common AC driving, that is, line-by-line independent common AC driving will be described.

  The common electrode line driving circuit 13 is preferably configured using only a transistor having the same conductivity type as that of the pixel transistor 26 in order to facilitate formation on the same insulating substrate as the pixel 25. For example, FIG. 4 and FIG. 5 of the above-mentioned Patent Document 3 show a drive circuit (corresponding to a unit circuit of the common electrode line drive circuit 13) formed by only transistors of the same conductivity type and performing independent common AC drive for each line and its operation. A waveform diagram is shown.

  The output signal OUT of the drive circuit shown in FIG. 4 changes its level 1H (horizontal period) before the corresponding gate line is activated, that is, 1H before the display data signal is written to the corresponding pixel. The voltage of the common electrode CM is set. The output signal OUT is a signal that takes a positive H level (VCOMH) or a negative L level (VCOML), and the level alternates every frame. At this time, the level of each output signal OUT is set according to the polarity of the display data signal written to the corresponding pixel. Specifically, when the display data signal D written to the corresponding pixel is positive, it is set to L level (VCOML), and when it is negative, it is set to H level (VCOMH). By doing so, the voltage applied to the liquid crystal element when the display data signal is written to the pixel is increased, so that the amplitude of the display data signal can be reduced.

  The level of the output signal OUT in FIG. 4 of Patent Document 3 is controlled by the alternating signals M and MB shown in FIG. The alternating signals M and MB are complementary to each other and have opposite levels in the preceding and following frame periods. That is, instead of the alternating signals M and MB, polarity control signals VFR and / VFR (a signal having a cycle twice the start signal ST) output from the frequency dividing circuit 20 according to the present invention can be used. By doing so, it is not necessary to supply the AC signals M and MB from the outside, and a line-by-line independent common AC drive type display device constituted only by transistors of the same conductivity type can be realized.

  In the form of Patent Document 3, as shown in FIGS. 5 and 15, the AC signals M and MB used for the line-by-line independent common AC drive are set to be repeated signals that are activated in a 2H cycle. The level of the electrode is inverted for each pixel line (the AC signals M and MB have the opposite levels because the phase with respect to the gate line driving signal is inverted in the preceding and following frames). That is, in the method of Patent Document 3, if the circuit of FIG. 4 is used as it is as all unit circuits, the level of the output signal OUT is inverted for each pixel line (for each common electrode CM), and independent common AC driving for each line is performed. Realized.

  However, when the polarity control signals VFR and / VFR are used instead of the AC signals M and MB, the polarity control signals VFR and / VFR are inverted only for each frame, so the polarity is reversed for each pixel line and the common AC drive is performed. To do this, some circuit changes are required. That is, for each pixel line (for each common electrode CM), the polarity control signals VFR, / VFR (alternating signals M, MB) supplied to the circuit of FIG. 4 are reversed, or the voltages VCOMH, VCOML are reversed. Thus, the level of the output signal OUT needs to be reversed for each pixel line even if the polarity control signals VFR and / VFR do not change. In the case of using the alternating signals M and MB of Patent Document 3 and the case of using the polarity control signals VFR and / VFR according to the present invention, the polarity control signal VFR, The power consumption can be reduced when / VFR is used.

  In the case of frame inversion driving, the polarities of all the common electrodes CM are made uniform, so even when the polarity control signals VFR and / VFR are used, unit circuits corresponding to all the common electrodes CM are shown in FIG. The circuit may be used as it is.

<Embodiment 9>
As described above, Patent Document 3 shows an example of a unit circuit applicable to the common electrode line driving circuit 13, but in the ninth embodiment, the common electrode line driving circuit devised by the present inventor is disclosed. 13 will be described. Here again, an example applied to line-by-line independent common AC driving will be described.

  26 and 27 are circuit diagrams for explaining the configuration of the common electrode line driving circuit 13 for driving the common electrode line COML (common AC driving). The common electrode line drive circuit 13 includes a plurality of unit circuits that drive each of the common electrode lines COML. 26 shows a unit circuit for driving the common electrode line COML connected to the odd-numbered pixel lines (odd rows), and FIG. 27 shows a unit for driving the common electrode line COML connected to the even-numbered pixel lines (even rows). Circuit. As can be seen from FIGS. 26 and 27, the unit circuit of the common electrode line drive circuit 13 can be realized by a circuit having the same configuration as the unit circuit (FIGS. 14 and 15) of the capacitor line drive circuit 12 of the fourth embodiment.

As shown in FIG. 25, the common electrode line driving circuit 13 receives gate line driving signals G _{1 to} Gm, clock signals CLK and / CLK, and polarity control signals VFR and / VFR, and is based on these signals. Common electrode line drive signals COM _{1 to} COM _m for driving the electrode lines COML are generated. In the common electrode line driving circuit 13, in addition to the high potential side power supply potential VDD and the low potential side power supply potential VSS, the potentials VCOMH and VCOML that respectively define the H level and the L level of the common electrode line drive signal COM as the power supply potential. Is supplied.

In the following description, the odd-numbered gate line drive signals (G ₁ , G ₃ ,..., G _n ,...) Are activated in synchronization with the clock signal CLK, and the even-numbered gate line drive signals (G ₂ , G ₄ ,. , G _n−1 ,...) Are assumed to be activated in synchronization with the clock signal / CLK. 26 and 27, it is assumed that the clock signal CLK is input to the clock terminal CK300 of the odd-numbered unit circuit, and the clock signal / CLK is input to the clock terminal CK300 of the even-numbered unit circuit. To do.

  First, the unit circuits in the odd rows will be described. FIG. 26 typically shows a unit circuit in the n-th row (n is an odd number).

As shown in FIG. 26, the unit circuit is configured using only transistors of the same conductivity type, and a polarity switching circuit for determining the polarity of the common electrode line drive signal COM _n , A level holding circuit for holding the levels of the polarity switching signals PC and / PC and holding them at a low impedance for one frame, and a common electrode line having a higher driving capability for the polarity switching signals PC and / PC And an output circuit that converts the drive signal COM _n to output. Here, an example is shown in which an N-type transistor is used in the same manner as the pixel 25 in FIG. 25, but it is of course possible to use a P-type transistor.

As shown in FIG. 26, the output circuit of the unit circuit includes a transistor Q309 that supplies an H level potential VCOMH of the common electrode line drive signal COM _{n to} the output terminal OUT300 of the common electrode line drive signal COM _n , and an output terminal OUT300. , and a supply transistor Q310 the L level potential VCOML of the common electrode line drive signal COM _n. That is, the transistor Q309 is connected between the power supply terminal S304 supplied with the potential VCOMH and the output terminal OUT300, and the transistor Q310 is connected between the power supply terminal S303 supplied with the potential VCOML and the output terminal OUT300. Yes. Nodes connected to the gate of the transistor Q309 and the gate of the transistor Q310 are defined as nodes N301 and N302, respectively.

The polarity switching circuit supplies polarity control signals VFR and / VFR to the nodes N301 and N302, respectively, in accordance with the gate line drive signal G _n−1 input to the input terminal IN301. The polarity switching circuit is connected between the input terminal IN302 to which the polarity control signal VFR is input and the node N301, and between the input terminal IN103 to which the polarity control signal / VFR is input and the node N302. The gates of these transistors Q301 and Q302 are both connected to an input terminal IN301 to which a gate line drive signal _Gn-1 is input.

Gate line driving signal G _n-1 is a signal for driving the gate line GL _n-1 is a preceding row of the gate line GL _n corresponding to the unit circuit of the n-th row. Here, an easily obtainable gate line drive signal G _n-1 is used as a signal input to the input terminal IN301. However, any other signal can be used as long as it is activated at the same timing and has a predetermined potential level. A signal may be used.

  A signal corresponding to the polarity control signal VFR supplied to the node N301 via the transistor Q301 becomes the polarity switching signal PC, and a signal corresponding to the polarity control signal / VFR supplied to the node N302 via the transistor Q302 Polarity switching signal / PC. Since the polarity control signals VFR and / VFR are complementary to each other, the polarity switching signals PC and / PC are also complementary to each other.

  The level holding circuit for holding the levels of the polarity switching signals PC and / PC is in principle a flip-flop (latch). As shown in FIG. 26, the level holding circuit includes six transistors Q303 to Q308 and two capacitive elements C301 and C302. The transistor Q303 is connected between the node N301 and the power supply terminal S1 to which the low potential side power supply potential VSS is supplied, and its gate is connected to the node N302. Transistor Q304 is connected between node N302 and power supply terminal S1, and has its gate connected to node N301.

  The transistor Q305 is connected between the power supply terminal S2 to which the high potential side power supply potential VDD is supplied and the node N301, and the transistor Q306 is connected between the second power supply terminal S2 and the node N302. A node to which the gate of the transistor Q305 is connected is defined as “node N303”, and a node to which the gate of the transistor Q306 is connected is defined as “node N304”. The node N303 is connected to the clock terminal CK300 to which the clock signal CLK is input via the capacitor C301, and the node N304 is connected to the clock terminal CK300 via the capacitor C302.

  Transistor Q307 is connected between nodes N303 and N301, and transistor Q308 is connected between nodes N304 and N302. The gates of these transistors Q307 and Q308 are both connected to the power supply terminal S2.

  For example, when this level holding circuit holds the state where the node N301 (polarity switching signal PC) is at the H level and the node N302 (polarity switching signal / PC) is at the L level, the transistor Q303 is turned off and the transistor Q304 is turned on. At this time, the node N303 is charged through the transistor Q307 and becomes H level, and the node N304 is discharged through the transistor Q308 and becomes L level. As a result, transistor Q305 is turned on and transistor Q306 is turned off. Thereby, the H level of the polarity switching signal PC and the L level of the polarity switching signal / PC are maintained.

  At this time, since both the nodes N301 and N303 are at the H level, the transistor Q307 is off, and the node N303 is maintained at the H level in the floating state. Therefore, when the clock signal CLK becomes H level, the node N303 is boosted by coupling through the capacitor C301, and the transistor Q305 is turned on in the non-saturated region. As a result, the polarity switching signal PC is maintained at the H level of the same potential VDD as that of the power supply terminal S2.

  On the other hand, the potential of the node N304 also tends to rise due to coupling through the capacitor C302 when the clock signal CLK becomes H level. However, since the transistors Q308 and Q304 are on, the potential rise at the node N304 is instantaneous and is maintained at the L level. That is, since the transistor Q306 is almost kept off, almost no through current flows through the transistors Q304 and Q306.

  Note that the instantaneous potential increase at the node N304 can be reduced by appropriately setting the on-resistance values of the transistors Q304 and Q308 and the capacitance value of the capacitor C302, and the transistor Q306 can be more reliably maintained in the off state. Can do.

  Conversely, when the unit circuit holds the state where the level holding circuit is at the node N301 (polarity switching signal PC) at the L level and the node N302 (polarity switching signal / PC) is at the H level, the transistor Q303 is turned on. Q304 is turned off. Node N304 goes to H level, transistor Q306 turns on and maintains polarity switching signal / PC at H level. When the clock signal CLK rises, the node N304 is boosted and the transistor Q306 is turned on in the non-saturated region, so that the polarity switching signal / PC becomes the H level of the potential VDD. On the other hand, since node N303 is substantially maintained at the L level and transistor Q305 is substantially kept off, almost no through current flows through transistors Q305 and Q303.

  In this way, in the level holding circuit provided in the unit circuit of FIG. 26, only the node that maintains the H level is pulled up without consuming almost any power, and the node that maintains the L level is pulled up. A selective pull-up operation is performed.

  Next, the unit circuits in the even-numbered rows of the common electrode line driving circuit 13 will be described. FIG. 27 representatively shows unit circuits in the (n + 1) th row (n is an odd number).

As shown in FIG. 27, the configuration of the unit circuit in the even-numbered row is almost the same as the unit circuit in the odd-numbered row (FIG. 26), but the common electrode line drive signal COM _{n + 1} in the even-numbered row is the odd-numbered common electrode line. Since it is necessary to make the level inverted with respect to the drive signal COM _n , the connections of the gates of the transistors Q309 and Q310 are exchanged with respect to FIG. Alternatively, the circuit configuration is not changed from that in FIG. 26, and the unit circuits in the even rows may be replaced with the polarity control signals VFR and / VFR input to the input terminals IN302 and IN303 (not shown). A clock signal / CLK is input to the clock terminal CK300.

  The signals input to the clock terminal CK300 in FIGS. 26 and 27 may be signals other than the clock signals CLK and / CLK as long as they are repetitive signals that alternate with a constant period. As described above, the clock signal input to the clock terminal CK300 is used to turn on the transistor Q305 (or Q306) in a non-saturation region at a constant period, thereby causing the node N301 (or N302) due to the leakage current. The potential drop at the H level is compensated. As long as this leakage current can be sufficiently compensated, a clock signal having a lower frequency may be used, thereby reducing power consumption. However, it is preferable that the clock signal input to the clock terminal CK300 does not overlap with the active period of the signal input to the input terminal IN301.

Here, the gate line drive signals (G ₁ , G ₃ ,..., G _n ,...) In the odd rows are activated in synchronization with the clock signal CLK, and the gate line drive signals (G ₂ , G ₄ ,. G _n−1 ,...) Are assumed to be activated in synchronization with the clock signal / CLK. Therefore, the clock signal CLK is input to the clock terminal CK100 of the odd-numbered unit circuit, and the even-numbered unit circuit The clock signal / CLK is input to the clock terminal CK100.

  Subsequently, the operation of the common electrode line driving circuit 13 according to the present embodiment will be described. Here, for simplicity of explanation, it is assumed that the threshold voltages of the transistors are all the same value Vth. Further, the low potential side power supply potential VSS of the common electrode line driving circuit 13 is used as a reference potential, the H level of the polarity control signals VFR, / VFR is equal to the potential VDD supplied to the power supply terminal S2, and the L level is equal to the potential VSS. And Furthermore, the H level potential of the clock signals CLK and / CLK is also VDD, and the L level potential is also VSS.

  As described above, the potentials VCOML and VCOMH supplied to the power supply terminals S303 and S304 are for defining the L-level and H-level potentials of the common electrode line drive signal COM, respectively. Since the common electrode line drive signal COM gives a constant potential change to the pixel electrode by capacitive coupling, the potentials VCOMH and VCOML change the potential that the potential difference (amplitude of the common electrode line drive signal COM) gives to the pixel electrode. As long as the transistors Q309 and Q310 operate in the non-saturated region.

FIG. 28 is a signal waveform diagram showing the operation of the common electrode line driving circuit 13. As described in the first embodiment, the polarity control signals VFR, / VFR are complementary signals generated by the frequency dividing circuit 20 of FIG. 25 and have a cycle twice that of the start signal ST. As shown in FIG. 9, the polarity control signals VFR and / VFR have alternating levels when the drive signal G _{m + 1} output next to the gate line drive signal G _m for driving the gate line GL _m in the last row rises. To do. That is, the levels of the polarity control signals VFR, / VFR alternate in the blanking period for each frame of the display device. Again, the period when the polarity control signal VFR is at the H level is defined as “odd frame”, and the period at the L level is defined as “even frame”.

  Hereinafter, the operation of the common electrode line driving circuit 13 according to the present embodiment will be described. First, the operation of the unit circuit in the odd-numbered row will be described. Here, the operation of the unit circuit in the n-th row (FIG. 26) will be representatively described.

Referring to FIG. 28, when the polarity control signals VFR and / VFR change to the H level and the L level, respectively, and become an odd frame at time t ₁ within the blanking period, the input terminal IN302 becomes the potential VDD, and the input terminal IN303. Are set to the potential VSS. The levels of the nodes N301 to N304 and the output terminal OUT300 are determined by the operation in the previous frame period. Here, the nodes N301 and N303 and the output terminal OUT300 are at the L level, and the nodes N302 and N304 are at the H level.

In time t _2, the corresponding gate line driving signal G _n-1 for driving the gate line GL _n-1 corresponding to the previous row of the gate line GL _n becomes H level. Accordingly, the transistors Q301 and Q302 are turned on, and the levels of the polarity control signals VFR and / VFR are supplied to the nodes N301 and N302. More specifically, first, the node N302 (polarity switching signal / PC) becomes L level (VSS), and the transistors Q303 and Q310 are turned off. Since the transistor Q303 is turned off, the node N301 is charged through the transistor Q301, and the polarity switching signal PC becomes H level (VDD-Vth). In response, the transtransistors Q304 and Q309 are turned on.

Node N304 is discharged through transistors Q308 and Q304 to L level (VSS), and node N303 is charged through transistor Q307 to H level (VDD-Vth). Note that, as described above, the potential VCOMH is set to a value within a range in which the transistor Q309 performs a saturation operation when the polarity switching signal / PC becomes H level, and the common electrode line drive signal COMn is _equal to the potential VCOMH. Becomes H level.

At time t ₃ 1H after time t ₂ , the gate line drive signal G _n−1 becomes L and the transistors Q301 and Q302 are turned off, so that the nodes N301 and N302 and the input terminals IN302 and IN303 are electrically connected. To be separated. However, at this time, the H level of the polarity switching signal PC and the L level of the polarity switching signal / PC are held (latched) by the action of the level holding circuit described above.

At time t ₃ , since the clock signal CLK rises to the H level, the node N303 is boosted by the coupling through the capacitive element C301. Since the node N303 is already charged to VDD-Vth, the potential of the node N303 becomes approximately 2 · VDD-Vth by this boosting action. Accordingly, transistor Q305 is turned on in the non-saturated region, and node N301 rises to potential VDD.

In addition the time t _3, the corresponding gate line driving signal G _n for driving the gate line GL _n is activated, the display data signal D is written in the n-th row of pixels 25. The gate line drive signal G _n becomes L level at time t ₄ 1H after time t ₃ .

At time t ₄ , since the clock signal CLK becomes L level, the level of the node N303 returns to VDD−Vth again, and the transistor Q305 is turned off, but the node N301 is maintained at the H level of the potential VDD in a high impedance state.

After time t ₅ , whenever the clock signal CLK changes to H level, the potential of the node N303 is boosted to about 2 · VDD−Vth, and the transistor Q305 is turned on in the non-saturated region to charge the node N301 to the potential VDD. The operation is repeated. Thereby, a decrease in the level of node N301 due to the leakage current is compensated, and polarity switching signal PC can be maintained at the H level of potential VDD. As a result, the transistor Q309 is maintained in the ON state in the non-saturation region, the said unit circuit can be maintained for one frame period, the common electrode line drive signal COM _n of H level (VCOMH) with low impedance.

At time t ₇ in the next blanking period, the polarity control signals VFR and / VFR change to the L level and the H level, respectively, to become an even frame, but at this time, the transistors Q301 and Q302 are off. node N301 H level (polarity switching signal PC), L level of the node N302 (polarity switching signal / PC) is not changed, even the common electrode line drive signal COM _n remains at H level (VCOMH).

Thereafter, at time t ₈ , the gate line drive signal G _n-1 becomes H level (VDD). Accordingly, the transistors Q301 and Q302 are turned on, and the levels of the polarity control signals VFR and / VFR are supplied to the nodes N301 and N302. At this time, the polarity switching signal PC is set to L level (VSS) and the polarity switching signal / PC is set to H level (VDD−Vth) by the operation opposite to the time t ₂ described above. Correspondingly transistor Q309 is turned off, the transistor Q310 is turned on, the common electrode line drive signal COM _n changes to the L level (VCOML).

At time t ₈ from the post-1H time t _9, the gate line drive signal G _n-1 becomes L, and the transistor Q301, so Q302 is turned off, the node N301, N302 and the input terminal IN302, IN303 and is electrically To be separated. However, at this time, the L level of the polarity switching signal PC and the H level of the polarity switching signal / PC are held (latched) by the action of the level holding circuit described above.

At time t ₉ , since the clock signal CLK rises to the H level, the node N304 is boosted by the coupling through the capacitive element C302. By this boosting action, the potential of the node N304 becomes approximately 2 · VDD−Vth. Accordingly, transistor Q306 is turned on in the non-saturated region, and node N302 rises to potential VDD.

Also at time t _9, the corresponding gate line driving signal G _n for driving the gate line GL _n is activated, the display data signal D is written in the n-th row of pixels 25. The gate line drive signal G _n becomes L level at time t ₁₀ 1H after time t ₉ .

In addition the time t _10, the clock signal CLK is the transistor Q306 back to the level of the node N304 is again VDD-Vth since the L level to turn off, the node N301 is maintained in a high impedance state to the H-level potential VDD.

Time t ₁₁ after the clock signal CLK is time the potential of the node N303 is raised to approximately 2 · VDD-Vth in which changes to the H level, operation of the transistor Q306 charges the node N301 to the potential VDD is repeated. As a result, the node N301 (polarity switching signal PC) maintains the H level of the potential VDD at the potential VDD. As a result, the transistor Q309 is maintained in the ON state in the non-saturation region, the said unit circuit can be maintained for one frame period, the common electrode line drive signal COM _n of L level (VCOML) with low impedance.

  In this way, each of the odd-row unit circuits (FIG. 26) of the common electrode line driving circuit 13 writes the display data signal D to the pixels 25 in the corresponding row (in the corresponding gate line GL) in the odd-numbered frame. The common electrode line drive signal COM is changed from the L level to the H level 1H before the active period. In the even frame, the common electrode line drive signal COM is changed from the H level to the L level 1H before the writing period of the display data signal D to the pixels 25 in the corresponding row.

  On the other hand, the operation of the unit circuit in the even-numbered row (FIG. 27) is almost the same as the operation of the unit circuit in the odd-numbered row described above. However, each of the even-numbered unit circuits changes the common electrode line drive signal COM from the H level to the L level 1H before the writing period of the display data signal D to the pixel 25 of the corresponding row in the odd frame. Change. In the even frame, the common electrode line drive signal COM is changed from the L level to the H level 1H before the writing period of the display data signal D to the pixels 25 in the corresponding row.

FIG. 29 is a signal waveform diagram showing the operation of the common electrode line drive circuit 13, and summarizes the behavior of the common electrode line drive signals COM in the odd and even rows. It can be seen that the level of each common electrode line drive signal COM changes 1H before the rise of the gate line drive signal G corresponding to the same row. For example, the level of the common electrode line drive signal COM _n corresponding to the n-th row (odd row) is inverted 1H before the rise of the gate line drive signal G _n corresponding to the same row. Similarly, the level of the common electrode line drive signal COM _{n + 1} corresponding to the (n + 1) th row (even number row) is inverted 1H before the rise of the gate line drive signal G _{n + 1} . It can also be seen from the same figure that the direction of the level change of the common electrode line drive signal COM is reversed between the even-numbered rows and the several-hour rows within the same frame period.

  In the case of performing capacitive coupling driving of the gate line inversion driving method using the common electrode line driving signal COM whose level changes as shown in FIG. 29, when writing the display data signal D to each pixel 25, the odd-numbered frame is set to the odd-numbered row. Writes negative polarity (-) and writes positive polarity (even) to even rows, and writes even polarity to odd rows and negative polarity to even rows in even frames. Try to write things. As a result, the common electrode line COML of the pixel 25 to which the positive display data signal D is written has a negative polarity, and the common electrode line COML of the pixel 25 to which the negative display data signal D is written has a positive polarity. The voltage applied to each liquid crystal element 28 becomes larger than the amplitude of the display data signal D. As a result, the effect of independent common AC driving for each line that the amplitude of the display data signal D supplied to the data line DL can be reduced can be obtained.

  As can be seen from the above description, the polarity control signals VFR and / VFR are used for the purpose of controlling the level of each common electrode line drive signal COM. Since they are signals having a period twice that of the start signal ST, they are fixed at a constant level in each frame period. However, since the unit circuit of the common electrode line drive circuit 13 shown in FIGS. 26 and 27 includes a level holding circuit for the polarity switching signals PC and / PC, strictly speaking, the polarity control signals VFR and / VFR are In each unit circuit, it is only necessary to take an appropriate value even at least for the active period of the signal input to the input terminal IN301, and it is not always necessary to maintain a constant level for one frame period. However, it should be noted that the power consumption increases when the alternating cycle of the polarity control signals VFR, / VFR is shortened (frequency is increased).

<Embodiment 10>
In the ninth embodiment, an example of independent common AC driving for each line in which the polarity of the display data signal D is inverted for each gate line is shown. However, in the common AC driving method, display data signals to be written to all the pixels are also displayed. A driving method (frame inversion driving method) in which the polarities are the same and the polarity of the display data of all the pixels is inverted every frame is also conceivable. The present invention is also applicable to a display device that performs such a driving method. In that case, since the polarity is not inverted for each gate line, all the unit circuits of the capacitor line driving circuit 12 may be unified (FIG. 26 or FIG. 27).

It is a block diagram which shows the structural example of the conventional display apparatus. It is a figure which shows the specific structural example of the conventional liquid crystal pixel. It is a figure for demonstrating operation | movement of the conventional drive control circuit. 1 is a schematic block diagram illustrating a configuration of a display device according to Embodiment 1. FIG. FIG. 3 is a circuit diagram showing a basic configuration of a frequency divider circuit according to the first embodiment. FIG. 3 is a timing diagram illustrating a basic operation of the frequency divider circuit according to the first embodiment. FIG. 3 is a diagram illustrating an example of a specific circuit configuration of a frequency divider circuit according to the first embodiment. FIG. 8 is a timing chart showing the operation of the frequency dividing circuit of FIG. 7. FIG. 8 is a timing chart showing the operation of the frequency dividing circuit of FIG. 7. 5 is a schematic block diagram illustrating a configuration of a display device according to Embodiment 2. FIG. FIG. 10 is a timing diagram illustrating an operation of the frequency divider circuit according to the second embodiment. 6 is a schematic block diagram illustrating a configuration of a display device according to Embodiment 3. FIG. FIG. 6 is a circuit diagram illustrating a configuration of a level shifter according to a third embodiment. FIG. 6 is a circuit diagram of a unit circuit of a capacitive line driving circuit according to a fourth embodiment. FIG. 6 is a circuit diagram of a unit circuit of a capacitive line driving circuit according to a fourth embodiment. FIG. 10 is a timing diagram illustrating an operation of the capacitive line driving circuit according to the fourth embodiment. FIG. 10 is a timing diagram illustrating an operation of the capacitive line driving circuit according to the fourth embodiment. FIG. 10 is a schematic block diagram illustrating a configuration of a display device according to a seventh embodiment. FIG. 10 is a block diagram showing a configuration of a gate line driving circuit according to a seventh embodiment. FIG. 10 is a block diagram showing a configuration of a gate line driving circuit according to a seventh embodiment. FIG. 20 is a circuit diagram of a unit shift register of a gate line driving circuit according to a seventh embodiment. FIG. 10 is a circuit diagram showing a configuration of a gate line driving circuit according to a seventh embodiment. FIG. 23 is a timing diagram illustrating an operation of the gate line driving circuit according to the seventh embodiment. FIG. 23 is a timing diagram illustrating an operation of the gate line driving circuit according to the seventh embodiment. FIG. 10 is a schematic block diagram illustrating a configuration of a display device according to an eighth embodiment. FIG. 20 is a circuit diagram of a unit circuit of a common electrode line driving circuit according to a ninth embodiment. FIG. 20 is a circuit diagram of a unit circuit of a common electrode line driving circuit according to a ninth embodiment. FIG. 30 is a timing diagram illustrating an operation of the capacitor line driving circuit according to the ninth embodiment. FIG. 30 is a timing diagram illustrating an operation of the capacitor line driving circuit according to the ninth embodiment.

Explanation of symbols

  11 gate line driving circuit, 12 capacitance line driving circuit, 13 common electrode line driving circuit, 20 frequency dividing circuit, 25 pixels, GL gate line, DL data line, CCL capacitance line, COML common electrode line.

Claims (22)

A plurality of scanning lines arranged in parallel to each other;
A plurality of signal lines arranged orthogonal to the plurality of scanning lines;
A plurality of capacitance lines each disposed along each of the plurality of scanning lines;
A plurality of pixels disposed near each intersection of the scanning line and the signal line;
A scanning line driving circuit that sequentially scans and drives the plurality of scanning lines for each frame;
A capacitor line driving circuit for driving the plurality of capacitor lines;
A frequency dividing circuit for generating a control signal having a period obtained by dividing the start signal corresponding to the start of the frame;
The pixel is
A pixel active element having a control electrode connected to the corresponding scan line and one current electrode connected to the corresponding signal line;
A pixel electrode connected to the other current electrode of the pixel active element;
A capacitor element connected between the corresponding capacitor line and the pixel electrode;
The capacitive line driving circuit is provided for each frame.
For each of the plurality of pixels, at a predetermined timing after the active period of the pixel active element, the potential of the corresponding capacitor line is changed based on the control signal,
Active elements constituting the scanning line driving circuit, the capacitance line driving circuit, and the frequency dividing circuit are:
An image display device characterized in that all are of the same conductivity type as the pixel active element. A plurality of scanning lines arranged in parallel to each other;
A plurality of signal lines arranged orthogonal to the plurality of scanning lines;
A plurality of pixels disposed near each intersection of the scanning line and the signal line;
A scanning line driving circuit that sequentially scans and drives the plurality of scanning lines for each frame;
A frequency dividing circuit for generating a control signal having a period obtained by dividing the start signal corresponding to the start of the frame;
The pixel is
A pixel active element having a control electrode connected to the corresponding scan line and one current electrode connected to the corresponding signal line;
A pixel electrode connected to the other current electrode of the pixel active element;
A capacitive element connected between the scanning line adjacent to the corresponding scanning line and the pixel electrode;
The scanning line driving circuit is provided for each frame.
For each of the plurality of pixels, at a predetermined timing after the active period of the pixel active element, the potential of the inactive level of the adjacent scanning line is changed based on the control signal,
Active elements constituting the scanning line driving circuit and the frequency dividing circuit are:
An image display device characterized in that all are of the same conductivity type as the pixel active element. A plurality of scanning lines arranged in parallel to each other;
A plurality of signal lines arranged orthogonal to the plurality of scanning lines;
A plurality of common electrode lines each disposed along each of the plurality of scanning lines;
A plurality of pixels disposed near each intersection of the scanning line and the signal line;
A scanning line driving circuit that sequentially scans and drives the plurality of scanning lines for each frame;
A common electrode line driving circuit for driving the plurality of common electrode lines,
A frequency dividing circuit for generating a control signal having a period obtained by dividing the start signal corresponding to the start of the frame;
The pixel is
A pixel active element having a control electrode connected to the corresponding scan line and one current electrode connected to the corresponding signal line;
A pixel electrode connected to the other current electrode of the pixel active element;
A display element connected between the corresponding common electrode line and the pixel electrode;
The common electrode line driving circuit is provided for each frame.
For each of the plurality of pixels, the potential of the corresponding common electrode line is changed based on the control signal at a predetermined timing before the active period of the pixel active element,
Active elements constituting the scanning line driving circuit, the common electrode line driving circuit, and the frequency dividing circuit are:
An image display device characterized in that all are of the same conductivity type as the pixel active element. The image display device according to any one of claims 1 to 3,
The gate line driving circuit includes:
Consists of a plurality of cascaded shift registers,
The divider circuit is
Comprising first, second and third circuits;
The first circuit includes:
Receiving the output signal of the third circuit, inverting the output signal of the third circuit in synchronization with the start signal,
The second circuit includes:
Receiving the output signal of the first circuit, inverting the output signal of the first circuit in synchronization with the output signal of a predetermined one of the plurality of shift registers,
The third circuit includes:
An image display device characterized by receiving an output signal of the second circuit and inverting the output signal of the second circuit. The image display device according to claim 4,
Each of the first, second, and third circuits is an inverter. The image display device according to claim 4 or 5,
The image display device according to claim 1, wherein the predetermined one shift register is not used for driving the pixel among the plurality of shift registers. The image display device according to any one of claims 4 to 6,
The divider circuit is
An image display device comprising first and second holding circuits for holding the output levels of the first and second circuits. The image display device according to any one of claims 4 to 7,
The divider circuit is
An image display device, further comprising: an initialization circuit that sets the output levels of the second and third circuits to a specific level at the start of operation. The image display device according to any one of claims 1 to 3,
The gate line driving circuit includes:
Consists of a plurality of cascaded shift registers,
The divider circuit is
Comprising first, second and third circuits;
The first circuit includes:
Receiving the output signal of the third circuit, inverting the output signal of the third circuit in synchronization with the output signal of the first shift register of the plurality of shift registers,
The second circuit includes:
Receiving the output signal of the first circuit, inverting the output signal of the first circuit in synchronization with the output signal of the second shift register of the plurality of shift registers,
The third circuit includes:
An image display device characterized by receiving an output signal of the second circuit and inverting the output signal of the second circuit. The image display device according to claim 9,
Each of the first, second, and third circuits is an inverter. The image display device according to claim 9 or 10,
The image display apparatus according to claim 1, wherein the first and second shift registers are not used for driving the pixels among the plurality of shift registers. The image display device according to any one of claims 9 to 11,
The divider circuit is
An image display device comprising first and second holding circuits for holding the output levels of the first and second circuits. The image display device according to any one of claims 9 to 12,
The divider circuit is
An image display device, further comprising: an initialization circuit that sets the output levels of the second and third circuits to a specific level at the start of operation. The image display device according to claim 1,
The control signal is composed of first and second control signals complementary to each other,
The capacitor line driving circuit includes:
Each of which is composed of a plurality of unit circuits for driving the corresponding capacitance lines;
Each of the unit circuits is
An output terminal connected to the corresponding capacitance line;
A first transistor for supplying a first level potential to the output terminal;
A second transistor for supplying a second level potential to the output terminal;
At the predetermined timing, one of the first and second control signals is supplied to the first node to which the control electrode of the first transistor is connected, and the first node is connected to the second node to which the control electrode of the second transistor is connected. And a polarity switching circuit for supplying the other of the second control signals;
An image display device comprising: a level holding circuit for holding levels of the first and second nodes. The image display device according to claim 14,
The level holding circuit includes:
One of the first and second nodes according to the level of the first and second control signals is repeatedly charged to maintain the level. The image display device according to claim 2,
The gate line driving circuit includes:
Consists of a plurality of cascaded shift registers,
Each of the plurality of shift registers is
An input terminal, a first output terminal, a first clock terminal and a reset terminal;
First and second power supply terminals to which first and second potentials are respectively supplied;
A first transistor for supplying a first clock signal input to the first clock terminal to the first output terminal;
A second transistor for supplying the first potential to the first output terminal;
A third transistor for supplying the second potential to the first output terminal;
A pull-up controller that drives the first transistor by controlling a level of a first node to which the control electrode of the first transistor is connected;
A first pull-down controller that drives the second transistor by controlling a level of a second node to which the control electrode of the second transistor is connected;
A second pull-down controller for driving the third transistor by controlling the level of the third node to which the control electrode of the third transistor is connected;
The pull-up control unit
Turning on the first transistor in response to activation of an input signal input to the input terminal; turning off the first transistor in response to activation of a reset signal input to the reset terminal;
The first and second pull-down controllers are
Both the second and third transistors are turned off in response to activation of the input signal, and one of the second and third transistors is selected on the basis of the control signal in response to activation of the reset signal. West,
The inactive level potential of the first clock signal is:
An image display device, wherein the image display device is set between the first potential and the second potential. The image display device according to claim 16, wherein
Each of the plurality of shift registers is
A second output terminal;
A second clock terminal to which a second clock signal having the same phase as the first clock signal is input;
A fourth transistor having a control electrode connected to the first node and supplying a second clock signal input to the second clock terminal to the second output terminal;
A fifth transistor having a control electrode connected to the second node and supplying the first potential to the second output terminal;
An image display device, further comprising: a sixth transistor having a control electrode connected to the third node and supplying the first potential to the second output terminal. The image display device according to claim 17,
The image display device according to claim 1, wherein the second clock signal has an inactive level potential that is the same as the first potential. The image display device according to claim 3,
The control signal is composed of first and second control signals complementary to each other,
The common electrode line driving circuit includes:
Each unit is composed of a plurality of unit circuits for driving the corresponding common electrode line,
Each of the unit circuits is
An output terminal connected to the corresponding common electrode line;
A first transistor for supplying a first level potential to the output terminal;
A second transistor for supplying a second level potential to the output terminal;
At the predetermined timing, one of the first and second control signals is supplied to the first node connected to the control electrode of the first transistor, and the second node connected to the control electrode of the second transistor is connected to the second node. A polarity switching circuit for supplying the other of the first and second control signals;
An image display device comprising: a level holding circuit for holding levels of the first and second nodes. The image display device according to claim 19, wherein
The level holding circuit includes:
One of the first and second nodes according to the level of the first and second control signals is repeatedly charged at a cycle shorter than the cycle of the frame to maintain those levels. An image display device. 4. The image display device according to claim 1, wherein the display element included in the pixel is a liquid crystal element. The image display device according to any one of claims 1 to 3,
A data signal output circuit for outputting a data signal to the signal line;
The data signal output circuit includes:
An image display device, wherein the polarity of the data signal supplied to each of the signal lines is determined based on the control signal.

Images