JP2009139699A - Luminous type display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively prevent a situation that an entire pixel does not shine at all while reducing the number of transistors. <P>SOLUTION: Each of a plurality of pixels includes a sampling transistor Ms, a driving transistor Md, a storage capacitor Cs, and a luminous type light emitting element (organic light emitting diode OLED). N (N≥3) or more sets of pixel circuit elements including the driving transistor Md, the storage capacitor Cs and the light emitting element are provided, and one sampling transistor Ms is connected to every set of the plurality of pixel circuit elements and shared. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a self-luminous display device in which each pixel includes a sampling transistor, a driving transistor, a holding capacitor, and a light emitting element.

An organic EL (electroluminescence) display device uses a semiconductor technology including a TFT (Thin Film Transistor) forming process on a single substrate, with a display unit in which a plurality of pixel circuits are arranged in a matrix and a driving unit thereof. A display panel formed using the same. Or the drive circuit of a display panel is provided by the flexible substrate, and performs both electrical connection.
An organic EL element is a self-luminous element that emits light by itself, and is generally called an OLED (Organic Light Emitting Diode).

  In the OLED, a plurality of organic thin films functioning as an organic hole transport layer, an organic light emitting layer, or the like are laminated between a lower electrode and an upper electrode. The film thickness varies depending on the emission wavelength and varies for reasons such as providing a light enhancement effect, but is generally thin and difficult to form because it is an organic material. An OLED is an electro-optic element that utilizes a phenomenon that emits light when an electric field is applied to an organic thin film, and obtains a gradation of color by controlling a current value flowing through the OLED. Therefore, in a display device using an OLED as an electro-optical element, a pixel circuit including a driving transistor for controlling the amount of current of the OLED is provided for each pixel.

Various pixel circuits for organic EL displays have been proposed in order to prevent deterioration in image quality due to characteristic variations of TFTs in the pixel circuit.
Mainly, 4 transistors (4T), 1 capacitor (1C) type, 4T / 2C type, 5T / 1C type, 3T / 1C type, 2T / 1C type, etc. are known.
All of these prevent image quality degradation caused by variations in the characteristics of transistors formed from TFTs (Thin Film Transistors), and the drive current is controlled to be constant inside the pixel circuit, thereby ensuring uniformity (brightness of the entire screen). The uniformity is improved. In particular, when the OLED is connected to the power source in the pixel circuit, the characteristic variation of the drive transistor that controls the amount of current according to the pixel data of the input video signal directly affects the light emission luminance of the OLED. For this reason, it is necessary to correct the characteristics of the driving transistor, that is, the threshold voltage.
Further, on the premise that the threshold voltage is corrected, if a driving capability component (generally referred to as mobility) obtained by subtracting a threshold variation component or the like from the current driving capability of the driving transistor is corrected, it is even higher. Uniformity is obtained.

When dust or the like adheres during manufacture of an electro-optical element such as an OLED, display defects such as dark spots where light emission is not normally performed are likely to occur. Such a display defect is an impediment to increasing the non-defective product ratio of the display device, and hinders cost reduction of the display device.
In particular, in an OLED, when forming a multilayer film structure in which multiple layers of organic thin films are deposited, a thin organic thin film that easily adheres to and peels off from the film forming apparatus may float in the chamber of the film forming apparatus and become dust. In many cases, when the OLED electrodes are short-circuited with a certain resistance value due to the adhesion of dust, a dark spot defect that does not always emit light tends to occur.

Patent Document 1 discloses a pixel driving method when a dark spot defect occurs.
In Patent Document 1, a light emitting element (OLED), a TFT for driving the light emitting element, a TFT for data sampling, and a holding capacitor for holding the sampled data at the gate of the driving TFT are provided in one pixel. A configuration in which a plurality of each is provided is disclosed. In the pixel driving method in Patent Document 1, when one light emitting element in one pixel does not emit light due to a defect, the driving circuit for the other light emitting elements in the pixel (two TFTs and a holding capacitor) And the other light emitting elements emit light so as to supplement the light emission amount of the non-light emitting elements.
JP 2007-41574 A

  When a non-light-emitting light-emitting element is generated as in the pixel driving method described in Patent Document 1, if control is performed so that a large amount of current flows through other light-emitting elements, a desired luminance of the pixel can be obtained. However, on the other hand, the lifetime of the other light emitting elements becomes extremely short, which is not desirable.

Patent Document 1 discloses a case where two sets of a light emitting element, a driving TFT, a sampling TFT, and a holding capacitor are provided, and there is a description that the number of sets may be two or more.
The driving TFT and the holding capacitor need to be provided for each light emitting element, but the sampling TFT can be shared. The reason is described below.

In the manufacture of an organic EL display, first, a TFT is formed on a substrate, then a holding capacitor is formed, and a light emitting element is formed on the uppermost layer. This occurs in the light emitting device manufacturing process.
Although there is a possibility that a dark spot defect may be caused by a TFT defect, for example, a disconnection of the TFT, the probability is smaller in each stage than the probability of a dark spot defect caused by a short circuit between electrodes of a light emitting element due to floating dust of organic matter.

  On the other hand, if the driving TFT and the holding capacitor are shared by a plurality of light emitting elements, the amount of light emission (display characteristics) changes for a certain amount of data depending on the presence or absence of a dark spot defect. Can not. However, even if the sampling TFT is shared, the display characteristics do not change greatly.

  Accordingly, in order to suppress the influence when a dark spot defect occurs by the same applicant as the present invention, a sampling TFT is divided into a plurality of pixel circuit components, that is, a plurality of light emitting elements, driving TFTs and holding capacitors. A common pixel configuration is proposed for each set (Japanese Patent Application No. 2007-307861).

However, in this unpublished invention, although the probability is low, there is room for improvement in this respect because a situation in which the entire pixel does not shine at all is not taken into account if a defect occurs in the sampling TFT.
The present invention relates to the improvement of this unpublished invention by the same applicant.

  A self-luminous display device according to one embodiment (first embodiment) of the present invention includes a pixel array having a plurality of pixels, and each of the plurality of pixels includes a sampling transistor, a driving transistor, and the driving transistor. A storage capacitor coupled to the light emission control node and holding a data potential input via the sampling transistor, and a drive current path are connected in series with the drive transistor together with the drive transistor, and the drive transistor is controlled according to the held data potential A light emitting element that emits light on the basis of the amount of driving current to be generated. In each of the plurality of pixels, a set of pixel circuit elements including the driving transistor, the holding capacitor, and the light emitting element is N (N ≧ 3). ) One or more sampling transitions provided for a plurality of sets of the pixel circuit elements. Data is shared is connected.

  In addition to the features of the first embodiment, a self-luminous display device according to another embodiment (second embodiment) of the present invention is shared by connecting one sampling transistor for every two sets of the pixel circuit elements. One sampling transistor is connected to one set of the pixel circuit elements remaining when N is an odd number.

  In addition to the characteristics of the second embodiment, the self-luminous display device according to another embodiment (third embodiment) of the present invention is characterized in that the sampling transistor connected to every two sets of the pixel circuit elements has its source And one of the drains is connected via a contact to a conductive layer to be one capacitor electrode of the two holding capacitors in the two sets, and the conductive layer is connected to each other capacitor electrode via a dielectric film. Two capacitor electrode portions that overlap each other, a connection portion that connects the two capacitor electrode portions, has a narrower width than the two capacitor electrode portions, and a contact portion that branches from the center of the connection portion.

  The self-luminous display device according to another embodiment (fourth embodiment) of the present invention is characterized in that, in addition to the features of the first embodiment, in the N holding capacitors, one capacitor electrode has two adjacent holding electrodes. When the N is an odd number, the one capacitor electrode that is a fraction is provided independently, and the other N capacitor electrodes are arranged separately from each other, and the N pieces of capacitor electrodes are connected to each other. In the light emitting element, N light emitting element lower electrodes, each of which is arranged for each of N regions obtained by dividing the pixel into N and respectively connected to the corresponding one of the other capacitor electrodes, and the lower part of the N light emitting elements. An organic multilayer film laminated on the electrode, one light emitting element upper layer electrode made of a common transparent electrode material formed on the organic multilayer film, and covering the light emitting element upper layer electrode, the N light emitting element upper layers Having a protective film having an opening formed for each pole.

  According to the configuration of the first to fourth embodiments, N (N ≧ 3) or more pixel circuit element groups including the drive transistor, the storage capacitor, and the light emitting element are provided. One sampling transistor is connected and shared for each of a plurality of sets of pixel circuit elements. In particular, in the second embodiment, one sampling transistor is connected to and shared by a plurality of sets of pixel circuit elements, and one sampling transistor is connected to the remaining set of pixel circuit elements when N is an odd number. Has been.

  As described above, the sampling transistor has a defect generation probability smaller than that of the light emitting element, but is not zero. Therefore, for example, the number of pixel circuit elements sharing one sampling transistor may be defined according to the difference in occurrence probability. When the sampling driving frequency is high, the sampling characteristics may be slightly different depending on the load of the sampling transistor. In such a case, if the number of sets sharing one sampling transistor is basically 2 and a fraction is obtained, if one sampling transistor is connected to one set for the set of fractions, the sampling characteristics Is desirable because it is not significantly different.

On the other hand, in the third embodiment, one capacitor electrode of two holding capacitors commonly connected to one sampling transistor has a relatively narrow connecting portion, and a contact portion connected to the sampling transistor at the center thereof. Is provided. Therefore, it is easy to perform a repair in which one or the other side of the contact portion is separated by, for example, a laser. When repair is performed, the data from the sampling transistor is not supplied to the gate of the drive transistor included in the disconnected group, so that no current flows through the defective light emitting element. Not consumed.
Note that the fourth embodiment defines a specific configuration. In this case, for each pixel region (a plurality of pixel division regions) in which the light emitting element is provided, a region for forming a transistor or a holding capacitor in each set. Are not necessarily matched, so that the degree of freedom of arrangement is high.

  According to the present invention, in addition to the benefit of providing a plurality of sets of pixel circuit elements to reduce the influence of luminance change due to a defect in a light emitting element, even when a sampling transistor has a defect and data sampling is impossible, The benefit of avoiding the worst case where one pixel does not shine at all is obtained.

  Hereinafter, an embodiment of the present invention will be described with an organic EL display as an example with reference to the drawings.

<< First Embodiment >>
<Overall configuration>
FIG. 1 shows a main configuration of an organic EL display according to an embodiment of the present invention.
The illustrated organic EL display 1 includes a pixel array 2 in which a plurality of pixel circuits 3 (i, j) are arranged in a matrix, and a drive circuit that drives the pixel array 2.
The drive circuit includes a vertical drive circuit (V scanner) 4 and a horizontal drive circuit (H scanner: H.Scan) 5.
A plurality of V scanners 4 are provided depending on the configuration of the pixel circuit 3. Here, the V scanner 4 includes a horizontal pixel line drive circuit (Drive Scan) 41 and a write signal scanning circuit (Write Scan) 42.

The code “3 (i, j)” of the pixel circuit shown in FIG. 1 indicates that the pixel circuit has an address i (i = 1, 2) in the vertical direction (vertical direction) and an address j ( j = 1,2,3). These addresses i and j take integers of 1 or more with the maximum values being “n” and “m”, respectively. Here, for simplification of the drawing, only a partial pixel array 2 of i = 1 to 2 and j = 1 to 3 is shown.
This address notation is similarly applied to the elements, signals, signal lines, voltages, and the like of the pixel circuit in the following description and drawings.

Pixel circuits 3 (1,1) and 3 (2,1) are connected to a common first signal line SIG (1) in the vertical direction. Similarly, the pixel circuits 3 (1,2) and 3 (2,2) are connected to the common second signal line SIG (2) in the vertical direction, and the pixel circuits 3 (1,3), 3 (2,3) are connected. ) Are connected to a common third signal line SIG (3) in the vertical direction.
For the pixel circuits 3 (1,1), 3 (1,2) and 3 (1,3) in the first row, the first pixel is driven from the horizontal pixel line driving circuit 41 by the common first scanning line SCAN1 (1). A scan signal (driving signal for the first display row) can be applied. Similarly, the horizontal pixel line driving circuit 41 is connected to the pixel circuits 3 (2,1), 3 (2,2) and 3 (2,3) in the second row by the common first scanning line SCAN1 (2). The first scan signal (drive signal for the second display row) can be applied.
The write signal scanning circuit 42 is connected to the pixel circuit 3 (1,1), 3 (1,2) and 3 (1,3) in the first row by the other common second scanning line SCAN2 (1). To the second scan signal (sampling signal of the first display row) can be applied. Similarly, the write signal scanning circuit is connected to the pixel circuit 3 (2,1), 3 (2,2) and 3 (2,3) in the second row by the other common second scanning line SCAN2 (2). A second scan signal (sampling signal for the second display row) can be applied from 42.

<Pixel circuit>
FIG. 2 shows one basic configuration circuit example of the pixel circuit 3 (i, j).
The pixel circuit 3 (i, j) illustrated is a circuit that controls an organic light emitting diode OLED as a light emitting element. In addition to the organic light emitting diode OLED, the pixel circuit includes a driving transistor Md and a sampling transistor Ms made of an NMOS type TFT, and one holding capacitor Cs.
Although details will be described later, the pixel circuit 3 (i, j) is provided with a plurality of, preferably three or more sets of circuit components including the organic light emitting diode OLED, the drive transistor Md, and the holding capacitor Cs, and a smaller number. A sampling transistor Ms is provided. Therefore, two or more sets are connected to at least one sampling transistor Ms.

The organic light emitting diode OLED is not particularly shown, but, for example, an anode electrode as a “lower electrode” is formed on a substrate made of transparent glass or the like, and a hole transport layer, a light emitting layer, an electron transport layer are formed thereon. Then, an electron injection layer and the like are sequentially deposited to form a laminated body constituting an organic multilayer film, and a cathode electrode as an “upper layer electrode” is formed on the laminated body. The anode electrode is connected to the positive power source, and the cathode electrode is connected to the negative power source.
FIG. 2 shows a case where the anode of the organic light emitting diode OLED is supplied with the power supply voltage VDD from the positive power supply, and the cathode of the organic light emitting diode OLED is connected to a reference voltage, for example, the ground voltage GND.

  When a bias voltage capable of obtaining a predetermined electric field is applied between the anode and cathode electrodes of the organic light emitting diode OLED, the injected electrons and holes self-emit when recombined in the light emitting layer. The organic light emitting diode OLED can emit light in each color of red (R), green (G), and blue (B) by appropriately selecting the organic material constituting the organic multilayer film. For example, color display is possible by arranging the light emission of R, G, B in the pixels of each row. Alternatively, R, G, and B may be distinguished by the color of the filter using an organic material that emits white light. A four-color configuration in which W (white) is added in addition to R, G, and B may be used.

The drive transistor Md functions as a current control unit that regulates the display gradation by controlling the amount of current flowing through the light emitting element (organic light emitting diode OLED).
The drain of the driving transistor Md is connected to a scanning line (first scanning line SCAN1 (i)) that controls the supply of the power supply voltage VDD, and the source is connected to the anode of the organic light emitting diode OLED.

  The sampling transistor Ms is connected between the supply line (signal line SIG (j)) of the data potential Vsig that determines the pixel gradation and the gate of the driving transistor Md, and is controlled by the second scanning line SCAN2 (i). One of the source and drain of the sampling transistor Ms is connected to the gate of the drive transistor Md, and the other is connected to the signal line SIG (j). A data potential Vsig is applied to the signal line SIG (j) from the H scanner 5 (see FIG. 1). The sampling transistor Ms samples data at a level to be displayed by the pixel circuit at an appropriate timing in the data potential application period. This is to eliminate the influence on the display image in the transition period where the level is unstable at the beginning or the rear of the data pulse having the desired data potential Vsig to be sampled.

  A holding capacitor Cs is connected between the gate and source of the driving transistor Md (the anode of the organic light emitting diode OLED). The role of the holding capacitor Cs will be described later in the operation.

In FIG. 2, the horizontal pixel line drive circuit 41 of FIG. 1 supplies the power supply drive pulse DSL (i) rising from the GND potential to the power supply voltage VDD to the drain of the drive transistor Md. Power is supplied when the organic light emitting diode OLED emits light.
Further, the write signal scanning circuit 42 in FIG. 1 supplies a write drive pulse WS (i) having a relatively short duration to the gate of the sampling transistor Ms, thereby performing sampling control.
The power supply control may be configured such that another transistor is inserted between the drain of the drive transistor Md and the supply line of the power supply voltage VDD, and the gate is controlled by the horizontal pixel line drive circuit 41. .

  Usually, all transistors in the pixel circuit are formed of TFTs. The thin film semiconductor layer in which the TFT channel is formed is made of a semiconductor material such as polycrystalline silicon (polysilicon) or amorphous silicon (amorphous silicon). Polysilicon TFTs can have high mobility, but their characteristic variation is large, so they are not suitable for increasing the screen size of a display device. Therefore, in a display device having a large screen, an amorphous silicon TFT is generally used. However, since it is difficult to form a P-channel TFT in an amorphous silicon TFT, it is desirable that all TFTs be an N-channel type like the pixel circuit 3 (i, j) described above.

Here, the pixel circuit 3 (i, j) described above is an example of a pixel circuit applicable in the present embodiment, that is, a basic configuration example of a two-transistor (2T) / 1-capacitor (1C) type. Therefore, the pixel circuit that can be used in the present embodiment may be a pixel circuit in which the pixel circuit 3 (i, j) is a basic configuration and a transistor and a capacitor are further added. In some basic configurations, the holding capacitor Cs is connected between the supply line of the power supply voltage VDD and the gate of the drive transistor Md.
Specifically, as a pixel circuit other than the 2T • 1C type that can be employed in the present embodiment, a detailed configuration is omitted, but for example, 4T • 1C type, 4T • 2C type, 5T • 1C type, 3T • 1C type It may be.

<Outline of light emission control operation>
A schematic light emission control operation in the pixel circuit 3 (i, j) is as follows.
A holding capacitor Cs is coupled to the control node NDc of the driving transistor Md. The signal voltage Vsig from the signal line SIG (j) is sampled by the sampling transistor Ms, and the data potential Vsig obtained thereby is applied to the control node NDc.

  When a predetermined data potential Vsig is applied to the gate of the drive transistor Md, the drain current Ids of the drive transistor Md is determined according to the gate-source voltage Vgs having a value corresponding to the data potential Vsig. Therefore, the organic light emitting diode OLED emits light with a luminance corresponding to the sampled data potential Vsig.

As is well known, the organic light emitting diode OLED changes its IV characteristic due to heat. At this time, the gate-source voltage Vgs of the drive transistor Md changes with the aging of the organic light emitting diode OLED.
As a result, the drive current Id flowing through the organic light emitting diode OLED changes, and as a result, the light emission luminance changes even at the predetermined data potential Vsig.
Further, since the threshold voltage Vth and the mobility μ of the driving transistor Md are different for each pixel circuit, the drain current Ids varies, and the light emission luminance of the pixel to which the same data potential Vsig is applied changes.

  The pixel circuit having the N-channel type driving transistor Md has an advantage of high driving capability and simplification of the manufacturing process. However, in order to suppress variations in the threshold voltage Vth and the mobility μ, the following correction operation is performed as described above. It is necessary to carry out prior to the emission control operation.

Prior to sampling, the gate potential of the drive transistor Md is held at the level of the threshold voltage Vth by the holding capacitor Cs. This preliminary operation is referred to as “threshold correction”.
After the threshold correction, since the sampled data potential Vin is applied to the gate of the drive transistor Md, the gate potential is held at “Vth + Vin”. The drive transistor Md is turned on according to the magnitude of the data potential Vin at this time. In the case of the drive transistor Md having a large threshold voltage Vth and difficult to turn on, “Vth + Vin” is large, and conversely, in the case of the drive transistor Md having a small threshold voltage Vth and easy to turn on, “Vth + Vin” is also small. Therefore, if the influence of the variation of the threshold voltage Vth is eliminated from the drive current and the data potential Vin is constant, the drain current Ids (drive current Id) is also constant.

Further, for example, “mobility (strictly, driving force correction)” is performed after threshold correction before data sampling.
In the mobility correction, the gate potential is changed according to the current drive capability of the drive transistor Md from the state where the voltage “Vth + Vsig” is held. A path is provided between the gate and the source of the driving transistor Md to charge or discharge the holding capacitor with a current through the current channel of the driving transistor Md, and it is controlled whether or not a current flows through this path. To correct the mobility.
Thereafter, the organic light emitting diode OLED emits light by being driven to the constant current value.

In the present invention, for example, a plurality of, preferably three or more sets of the organic light emitting diode OLED, the driving transistor Md, and the holding capacitor Cs in FIG. 2 are provided, and one sampling transistor is connected and shared for each of the plurality of sets. .
In the present embodiment, as a more specific example, four sets are provided, and one sampling transistor Ms is connected for every two sets. In the present embodiment, since the number of sets is an even number, the number of sets connected to one sampling transistor is always “2”.

FIG. 3 shows an equivalent circuit diagram in one pixel in the present embodiment.
In the pixel circuit 3 (i, j) shown in FIG. 3, the number of the above sets is “4”. In FIG. 3, three pixel circuit components belonging to one “set”, that is, the organic light emitting diode OLED, the driving transistor Md, and the holding capacitor Cs are indicated by broken lines. The interconnection of the three pixel circuit components is the same as in FIG.
Hereinafter, the first group, the second group, the third group, and the fourth group are sequentially referred to from the left end group to the right end group in FIG.

  The gates of the first set of drive transistors Md1 and the second set of drive transistors Md2 are both connected to the source of one sampling transistor (hereinafter referred to as the first sampling transistor) Ms1. Similarly, the gate of the third set of drive transistors Md3 and the gate of the fourth set of drive transistors Md4 are both connected to the source of one other sampling transistor (hereinafter referred to as the second sampling transistor) Ms2.

The drains of the first and second sampling transistors Ms1, Ms2 are connected to a common signal line SIG (j).
Here, the drains of the first and second sampling transistors Ms1 and Ms2 can be connected to two different signal lines. However, the same data potential needs to be applied to the two signal lines. A single signal line is sufficient.
Similarly, two scanning lines for controlling the first and second sampling transistors Ms1 and Ms2 may be provided, but one is sufficient for simultaneous control, and a second scanning line SCAN2 (i) (not shown) is sufficient. Is provided (see FIG. 2).
A cathode potential Vcath is applied to the cathode of the organic light emitting diode OLED via a common control line. The cathode potential Vcath is controlled to take a binary value of a reference voltage VSS, for example, a ground voltage GND, and a lower voltage that reversely biases the organic light emitting diode OLED. In FIG. 3, the capacitance connected in parallel to the organic light emitting diode OLED and indicated by the symbol “Coled.” Does not represent a circuit element different from the organic light emitting diode OLED, but represents the capacitance value of the reverse-biased organic light emitting diode OLED. Represents.

<Structural examples of plane and cross section>
Here, the planar pattern and cross-sectional structure of the pixel circuit will be described with reference to the drawings.
4A and 4B show a planar pattern for the pixel circuit 3 (i, j). 4B is a plan view in which the uppermost cathode electrode (entire formation) is omitted, and FIG. 4A is the uppermost cathode electrode (whole surface formation) omitted. It is a top view in the middle of manufacture which excluded the organic multilayer film. FIG. 5B is a basic cross-sectional structure diagram of the TFT portion, and FIG. 5A is a plan view thereof.

As shown in FIG. 5B, a predetermined gate metal layer (GM) such as molybdenum (directly on a substrate 9 made of glass or the like directly (or via an underlayer (a kind of insulating layer)) as shown. A gate electrode 11 made of a refractory metal layer such as Mo) is formed.
In FIG. 4A, the gate electrode 11 corresponds to the gate electrode 11A1 of the drive transistors Md1 and Md2, the gate electrode 11A2 of the drive transistors Md3 and Md4, and the common gate electrode 11B of the first and second sampling transistors Ms1 and Ms2. To do. Here, the gate electrodes 11A1 and 11A2 are arranged so as to extend in the formation regions of the holding capacitors Cs1 to Cs4 in order to function as the lower electrodes of the holding capacitors Cs1 and Cs2 and the lower electrodes of the holding capacitors Cs3 and Cs4, respectively. On the other hand, one end of the gate electrode 11B extends downward for connection to the second scanning line SCAN2 (i).

A gate insulating film 10 is formed on the substrate 9 so as to cover the surface of the gate electrode 11 in FIG. 5B, and a thin film semiconductor layer 13 made of amorphous silicon (α-Si) is formed thereon. .
Although the thin film semiconductor layer 13 is omitted in FIG. 4A, the TFT layers of the drive transistors Md1 to Md4 and the TFT layers of the first and second sampling transistors Ms1 and Ms2 are formed so as to be isolated from each other. Of layers.

  In the thin film semiconductor layer 13 in FIG. 5B, a portion facing the gate electrode 11 is a channel formation region. A channel protective film 18 made of an insulating material is formed at a position to protect the channel formation region on the thin film semiconductor layer 13. In addition, two end portions of the source / drain electrodes 14 are disposed on the channel protective film 18 so as to have a width slightly narrower than that of the thin film semiconductor layer 13 (see FIG. 5A). The source / drain electrodes 14 are separated from each other on the channel protective film 18, and one of them functions as a source (S) electrode, and the other functions as a drain (D) electrode. The two source / drain electrodes 14 are formed of, for example, a wiring layer (AL) layer mainly made of aluminum (AL).

The source / drain electrodes 14 in FIG. 5 are related to the drive transistor Md1 in FIG. 4A, the VDD line 14A that branches from the first scan line SCAN1 (i) and functions as the drain electrode of the drive transistor Md, and the drive transistor Md1. This corresponds to the connection wiring 14B1 functioning as a source electrode. In order to function as the upper electrode of the holding capacitor Cs1, the connection wiring 14B1 is disposed so as to overlap with one wide area portion of the gate electrode 11A1.
5 corresponds to the VDD line 14A and the connection wiring 14B2 functioning as the source electrode of the driving transistor Md2 with respect to the driving transistor Md2 in FIG. 4A. In order to function as the upper electrode of the holding capacitor Cs2, the connection wiring 14B2 is disposed so as to overlap the other wide area portion of the gate electrode 11A1.

The source / drain electrode 14 in FIG. 5 corresponds to the VDD line 14A and the connection wiring 14B3 functioning as the source electrode of the drive transistor Md3 with respect to the drive transistor Md3 in FIG. In order to function as the upper electrode of the holding capacitor Cs3, the connection wiring 14B3 is arranged so as to overlap with one wide area portion of the gate electrode 11A2.
5 corresponds to the VDD line 14A and the connection wiring 14B4 functioning as the source electrode of the drive transistor Md4 with respect to the drive transistor Md4 in FIG. 4A. The connection wiring 14B4 is disposed so as to overlap the other wide area portion of the gate electrode 11A2 in order to function as the upper electrode of the holding capacitor Cs4.

Further, the source / drain electrode 14 of FIG. 4 functions as the source electrode of the first sampling transistor Ms1 and the connection wiring 14C that functions as the drain electrode of the first sampling transistor Ms1 with respect to the sampling transistor Ms1 of FIG. This corresponds to the connection wiring 14D1.
Similarly, the source / drain electrodes 14 in FIG. 4 are connected to the second sampling transistor Ms2 in FIG. 4A, the connection wiring 14C functioning as the drain electrode of the second sampling transistor Ms2, and the source electrode of the second sampling transistor Ms2. This corresponds to the connection wiring 14D2 functioning as:

The connection wiring 14C is provided in common to the first and second sampling transistors Ms1 and Ms2, and also functions as a part of the signal line SIG (j).
In order to connect the control node NDc in FIG. 2, the end of the connection wiring 14D1 extends above the lower electrode (gate electrode 11A1) common to the holding capacitors Cs1 and Cs2, and is one of the 1st contact holes (1CH). A contact 12A1 is connected to the gate electrode 11A1.
Similarly, the connection wiring 14D2 has an end extending above the lower electrode (gate electrode 11A2) common to the holding capacitors Cs3 and Cs4 for connection to the control node NDc of FIG. 2, and is connected to the 1st contact hole (1CH). One contact 12A2 is connected to the gate electrode 11A2.

  As shown in FIG. 5B, the P-type thin film semiconductor layer 13 and the reverse conductivity type N-type impurity are introduced at a high concentration in the overlapping portion between the two source / drain electrodes 14 and the thin film semiconductor layer 13. A source impurity region 17S and a drain impurity region 17D are provided. A source contact in which one source / drain electrode 14 and the thin film semiconductor layer 13 are connected with low resistance is achieved by the source impurity region 17S. Similarly, the drain impurity region 17D achieves a drain contact in which the other source / drain electrodes 14 and the thin film semiconductor layer 13 are connected with low resistance.

In FIG. 4A, the first scanning line SCAN1 (i) and the second scanning line SCAN2 (i) are each formed from the (AL) layer, and are arranged in parallel to each other along opposite sides in the row direction in the cell. Has been.
On the other hand, the signal line SIG (j) is formed long in the column direction orthogonal to the first scanning line SCAN1 (i) and the second scanning line SCAN2 (i).

Most of the in-cell portions of the signal line SIG (j) are configured by the connection wiring 14C made of the (AL) layer as described above.
A bridge line 11C including a layer (GM) of the same material at the same level as the gate electrode 11 (see FIG. 5) is provided at the intersection of the signal line SIG (j) and the first scanning line SCAN1 (i). . One end of the connection wiring 14C is connected to the lower layer bridge line 11C by two contacts (1CH) 12C, and the first scanning line of the same material (AL) at the same level as the connection wiring 14C is formed on the bridge line 11C. SCAN1 (i) intersects.
Similarly, a bridge line 11 </ b> D including a layer (GM) of the same material at the same level as the gate electrode 11 is provided at the intersection of the signal line SIG (j) and the second scanning line SCAN <b> 2 (i). The other end of the connection wiring 14C is connected to the lower layer bridge line 11D by two contacts (1CH) 12D, and the second scanning line of the same material (AL) at the same level as the connection wiring 14C is formed on the bridge line 11D. SCAN2 (i) intersects.

Returning to FIG. 5B, a TFT protective film 19 covering the TFT having the above-described structure is deposited.
Although not shown in FIG. 5B, an organic light emitting diode OLED is formed on the TFT protective film 19. As shown in FIG. 3B, the organic light emitting diode OLED has lower anode electrodes AEa, AEb, AEc, and AEd formed of anode metal layers (AM) formed in regions into which pixels are divided into four. Yes.
The anode electrode AEa is connected to the lower connection wiring 14B1 by a contact 15A which is one of the 2nd contact holes (2CH). Similarly, the anode electrode AEb is connected to the connection wiring 14B2 via the contact 15B, the anode electrode AEc is connected to the connection wiring 14B3 via the contact 15C, and the anode electrode AEd is connected to the connection wiring 14B4 via the contact 15D. ing.

In this embodiment, since it is a top emission type, the anode metal layer (AM) is made of, for example, chromium (Cr), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), tantalum (Ta). , Tungsten (W), platinum (Pt), and gold (Au) can be formed by appropriately selecting a conductive material having a high work function and high reflectivity.
An EL protective film 21 is formed to cover the surfaces of the anode electrodes AEa, AEb, AEc, and AEd, and openings 21A, 21B, 21C, and 21D are provided in the EL protective film 21. The openings 21A to 21D are formed as large as possible on the anode electrode AE within a range where the contacts 15A to 15D are not exposed.
Although not particularly illustrated, an organic multilayer film is formed in a range including the inside of the opening 21A, and a cathode electrode is provided so as to be connected to the organic multilayer film and cover the entire surface. The cathode electrode is formed from a transparent electrode material.

  In the first embodiment, an even number of three or more sets of pixel circuit elements is provided. In the above example, the minimum four cases are described as an example. In the present embodiment, the number of sets is not limited to 4, but can be arbitrarily set to 6, 8,. In addition, the number of sets connected to one sampling transistor Ms is not limited to 2, and may be an arbitrary number of 3 or more.

  However, when a fraction appears as in the following embodiment, the fraction may change from the lowest 1 to a number smaller by 1 than the above arbitrary number. Therefore, if the number of pairs connected to one sampling transistor is excessively large, the sampling characteristics greatly change because the drain side load of one sampling transistor is greatly different. In order not to make this change so large, it is desirable to connect a pair to a single sampling transistor.

<< Second Embodiment >>
The second embodiment relates to a case where the number of sets is an odd number. Here, a case where the minimum number of sets is 3 will be described.

FIG. 6 shows an equivalent circuit diagram of the pixel circuit 3 (i, j) when the number of sets is three.
In the pixel circuit shown in FIG. 6, the point that the first set and the second set are connected to the common sampling transistor Ms1 is the same as that in FIG. 3 of the first embodiment, but the third set is a fraction. Three sets are independently connected to the second sampling transistor Ms2.

  4A, the driving transistor Md4 and the holding capacitor Cs4 are omitted, and therefore, there is no connection wiring 14B4, and the gate electrode 11A2 has no connection portion with the lower electrode portion of the holding capacitor Cs4. It becomes a pattern shape. The second sampling transistor Ms2 is formed directly beside the holding capacitor Cs3, and the connection wiring 14D2 is connected to the lower electrode portion thereof. Since the drive transistor Md4, the holding capacitor Cs4, and the connection wiring 14B4 related to the fourth set are omitted, the arrangement space of the other three sets is made larger than that in FIG. Good.

FIG. 7 shows an example in which three sets of anode metals are arranged almost uniformly in a pixel.
In both cases where the transistors and capacitors in the lower layer than FIG. 7 are evenly arranged and not evenly arranged, it is preferable that the anode electrodes AEa to AEc be evenly arranged as shown in FIG. 7 because the opening area of the EL protective film 21 is large. . This is because, in the organic light emitting diode OLED, each of the openings 21A to 21C corresponds to the area of the light emitting part, so that the amount of light is increased by increasing the opening area as much as possible.
The contacts 15A to 15C are contacts for connecting the anode metal and the capacitor lower electrode. Here, the position where the one contact 15C is provided is reversed from the other two, but three contacts are positioned in the same direction. Contacts 15A to 15C may be provided.

Also in the present embodiment, the number of sets is not limited to 3, and can be arbitrarily set to 5, 7,. In addition, the number of sets connected to one sampling transistor Ms is not limited to 2, and may be an arbitrary number of 3 or more. However, when there is a demand for not changing the sampling characteristics when the fraction occurs, the number of sets connected to one sampling transistor is preferably 2.
In the first and second embodiments, if the sampling characteristic does not change even if the number of sets is changed, and there is no problem even if the number of sets is changed, it is not necessary to set the number of sets connected to one sampling transistor to 2, It may be an arbitrary number.

According to the first and second embodiments described above, the following benefits can be obtained.
For example, any one (or two or more) of the pixel circuit element groups of the plurality of organic light emitting diodes OLED has a foreign matter generated during processing of the electrodes of the organic light emitting diode OLED or the organic film. Even if a short circuit occurs between the electrodes and this results in a dark spot, the anode electrodes are not electrically connected to each other, so they emit light independently, and the pixel is completely dark. It will not be a defect.
In addition, if the source and drain of the drive transistor, which is a component of a plurality of sets, are short-circuited and the opening becomes a bright spot defect, other than the set to which the defective drive transistor belongs, Therefore, the pixel does not become a complete dark spot defect. Similarly, even if the source and drain of a sampling transistor that constitutes one of the groups is short-circuited and the opening of that group becomes a half-dead point, it is connected to a sampling transistor other than the defective sampling transistor. Since the set of pixel circuit portions normally operate, the pixel does not have a complete dark spot defect.

  As described above, it is desirable that the group in which the defect is generated in various aspects is separated from the sampling transistor in the repair process.

A plan view of FIG. 8B shows a lower electrode pattern of a holding capacitor suitable for this repair. FIG. 8A is a plan view showing a pattern of a comparative example, that is, a pattern that is difficult to repair.
In the first and second embodiments of the present invention, when a pair of pixel components is connected to one sampling transistor Ms in pairs, the pattern of the holding capacitor lower electrode common to the two sets is shown in FIG. It is desirable to form as follows.
8A and 8B, the lower electrode portion that overlaps the upper electrodes of the two holding capacitors Cs is formed in a substantially rectangular shape close to a square in order to secure the capacitor area, and the two capacitor lower electrode portions. A connecting portion for connecting the two is provided. However, in FIG. 8A, since the width of the connecting portion is not much different from the width of the capacitor lower electrode portion, it is difficult to separate one holding capacitor Cs from the holding capacitor Cs at each connecting portion.
On the other hand, in FIG. 8B, since the connecting portion is formed to be sufficiently thin, it is easy to cut this portion with a laser or the like. In the first and second embodiments, the pattern shown in FIG. 8B may be adopted for this reason.

  When the repair is performed, data from the sampling transistor Ms is not supplied to the gate of the drive transistor Md in the set in which the defect has occurred, and therefore, the organic light emitting diode OLED in the set can be always non-lighted. There is no useless power consumption. For example, in the case of an electrode short-circuit defect of the organic light emitting diode OLED, when data for high brightness display close to white or white is supplied to the driving transistor Md for driving the organic light emitting diode OLED, the organic light emitting diode OLED does not emit light due to the defect. However, since the driving transistor Md is in a current driving state, a wasteful current flows between the short electrodes, but such a wasteful power does not flow when repair is performed.

As described above, according to the first and second embodiments of the present invention, it is possible to prevent a complete dark spot defect of a pixel. Utilizing the fact that the defect occurrence probability of a transistor is smaller than the defect occurrence probability of an OLED, the number of sets driven by one sampling transistor can be set according to the difference in the defect occurrence probability, thereby generating in a pixel Can optimize the effect of defects.
Further, by performing repair, it is possible to prevent wasteful power consumption accompanying the occurrence of a defect. At this time, since it has a pattern that can be easily repaired, the electrode can be reliably cut during repair.

1 is a main configuration diagram of an organic EL display according to an embodiment of the present invention. It is a figure which shows the basic structural example of the pixel circuit concerning one Embodiment of this invention. FIG. 3 is an equivalent circuit diagram of a pixel according to the first embodiment of the present invention. (A) is a lower layer plan view of the first embodiment, and (B) is an upper layer plan view thereof. (A) is a basic plan view of the TFT portion, and (B) is a basic cross-sectional structure diagram thereof. It is a figure which shows the basic structural example of the pixel circuit in connection with 2nd Embodiment of this invention. It is an upper layer top view of a 2nd embodiment. FIG. 5B is a partial plan view of a pixel including a capacitor lower electrode pattern that can be employed in the first and second embodiments. (A) is a partial top view of the pixel which shows the comparative example.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 1 ... Organic EL display, 2 ... Pixel array, 3 (i, j) ... Pixel circuit, 4 ... V scanner, 5 ... H scanner, 9 ... Substrate, 10 ... Gate insulating film, 11 ... Gate electrode, 12 ... (1st ) Contact, 13 ... thin film semiconductor layer, 14 ... source / drain electrode, 15 ... (2nd) contact, 18 ... channel protective film, 19 ... TFT protective film, 21 ... EL protective film, 21A-21D ... opening, 41 ... Horizontal pixel line driving circuit, 42... Write signal scanning circuit, Cs... Holding capacitor, OLED .organic light emitting diode, Ms .sampling transistor, Md... Driving transistor, SCAN1 (i). 2 scanning lines, SIG (j) ... signal line, AE ... anode electrode, AM ... anode metal layer, GM ... gate metal layer

Claims (4)

Having a pixel array having a plurality of pixels;
Each of the plurality of pixels is
A sampling transistor;
A driving transistor;
A holding capacitor coupled to the light emission control node of the driving transistor and holding a data potential input via the sampling transistor;
A light-emitting element that is connected in series to a drive current path together with the drive transistor, and that emits light based on a drive current amount controlled by the drive transistor according to the held data potential;
Have
In each of the plurality of pixels,
N (N ≧ 3) sets of pixel circuit elements including the driving transistor, the holding capacitor, and the light emitting element are provided,
A self-luminous display device in which one sampling transistor is connected and shared for each of a plurality of sets of the pixel circuit elements. One sampling transistor is connected and shared every two sets of the pixel circuit elements, and one sampling transistor is connected to one set of the pixel circuit elements remaining when N is an odd number. Item 2. The self-luminous display device according to Item 1. The sampling transistor connected to every two sets of the pixel circuit elements has one of its source and drain via a contact with a conductive layer that becomes one capacitor electrode of the two holding capacitors in the two sets. Connected,
The conductive layer is
Two capacitor electrode portions each overlapping with another individual capacitor electrode through a dielectric film;
Connecting the two capacitor electrode portions, a connecting portion having a width narrower than the two capacitor electrode portions;
A contact portion branched from the center of the connecting portion;
A self-luminous display device according to claim 2. In the N holding capacitors,
One capacitor electrode is connected to each of the two adjacent holding capacitors,
When the N is an odd number, the one capacitor electrode that is a fraction is provided independently,
N other capacitor electrodes are arranged separately from each other,
In the N light emitting elements,
N light emitting element lower electrodes, each of which is arranged for each of N regions obtained by dividing the pixel into N and is connected to the corresponding one of the other capacitor electrodes;
An organic multilayer film laminated on the N light emitting element lower electrodes;
One light emitting element upper layer electrode made of a common transparent electrode material formed on the organic multilayer film;
A protective film covering the light emitting element upper layer electrode and having an opening formed for each of the N light emitting element upper layer electrodes;
The self-luminous display device according to claim 1, comprising:

Images