JP2009200336A - Self-luminous type display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enlarge a capacity value per unit area, making small the occupying area of a holding capacitor. <P>SOLUTION: In a self-luminous type display (for example, an organic EL display 1), a plurality of drive transistors Md, holding capacitors Cs, and light-emitting devices (for example, an organic light-emitting diode OLED) are provided respectively in a plurality of pixels. A plurality of holding capacitors (for example, C1, C2) includes first capacitors Cs 11, Cs 21 which are constituted by laminating first conductive layers 11F1, 11F2 as lower electrodes, a first insulating layer (a gate insulating layer 10), and second conductive layers 14F1, 14F2 as upper electrodes in this sequence, and second capacitors Cs12, Cs 22 which are constituted by laminating a second insulating layer (a TFT protection film 19 and a flattening film 20) and a third conductive layer (for example, anode electrodes AEa, AEb) as an upper electrode layer in this sequence on a second electrode layer while using the second conductive layers 14F1, 14F2 as lower electrodes. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a self-luminous display device in which each pixel includes a sampling transistor, a driving transistor, a holding capacitor, and a light emitting element.

An organic EL (electroluminescence) display device uses a semiconductor technology including a TFT (Thin Film Transistor) forming process on a single substrate, with a display unit in which a plurality of pixel circuits are arranged in a matrix and a driving unit thereof. A display panel formed using the same. Or the drive circuit of a display panel is provided by the flexible substrate, and performs both electrical connection.
An organic EL element is a self-luminous element that emits light by itself, and is generally called an OLED (Organic Light Emitting Diode).

  In the OLED, a plurality of organic thin films functioning as an organic hole transport layer, an organic light emitting layer, or the like are laminated between a lower electrode and an upper electrode. The film thickness varies depending on the emission wavelength and varies for reasons such as providing a light enhancement effect, but is generally thin and difficult to form because it is an organic material. An OLED is an electro-optic element that utilizes a phenomenon that emits light when an electric field is applied to an organic thin film, and obtains a gradation of color by controlling a current value flowing through the OLED. Therefore, in a display device using an OLED as an electro-optical element, a pixel circuit including a driving transistor for controlling the amount of current of the OLED is provided for each pixel.

Various pixel circuits for organic EL displays have been proposed in order to prevent deterioration in image quality due to characteristic variations of TFTs in the pixel circuit.
Mainly, 4 transistors (4T), 1 capacitor (1C) type, 4T / 2C type, 5T / 1C type, 3T / 1C type, 2T / 1C type, etc. are known.
All of these prevent image quality degradation caused by variations in the characteristics of transistors formed from TFTs (Thin Film Transistors), and the drive current is controlled to be constant inside the pixel circuit, thereby ensuring uniformity (brightness of the entire screen). The uniformity is improved. In particular, when the OLED is connected to the power source in the pixel circuit, the characteristic variation of the drive transistor that controls the amount of current according to the pixel data of the input video signal directly affects the light emission luminance of the OLED. For this reason, it is necessary to correct the characteristics of the driving transistor, that is, the threshold voltage.
Further, on the premise that the threshold voltage is corrected, if a driving capability component (generally referred to as mobility) obtained by subtracting a threshold variation component or the like from the current driving capability of the driving transistor is corrected, it is even higher. Uniformity is obtained.

When dust or the like adheres during manufacture of an electro-optical element such as an OLED, display defects such as dark spots where light emission is not normally performed are likely to occur. Such a display defect is an impediment to increasing the non-defective product ratio of the display device, and hinders cost reduction of the display device.
In particular, in an OLED, when forming a multilayer film structure in which multiple layers of organic thin films are deposited, a thin organic thin film that easily adheres to and peels off from the film forming apparatus may float in the chamber of the film forming apparatus and become dust. In many cases, when the OLED electrodes are short-circuited with a certain resistance value due to the adhesion of dust, a dark spot defect that does not always emit light tends to occur.

Patent Document 1 discloses a pixel driving method when a dark spot defect occurs.
In Patent Document 1, a light emitting element (OLED), a TFT for driving a light emitting element (hereinafter referred to as a driving transistor), a TFT for data sampling (hereinafter referred to as a sampling transistor), and a driving transistor are included in one pixel. A case is disclosed in which two sets of holding capacitors for holding the sampled data are provided at the gates of the two, and the number of sets may be two or more. OLEDs, driving transistors, holding capacitors, and the like are referred to as “pixel circuit components”. In this configuration, since two or more sets of pixel circuit components are provided in one pixel, even if one of them does not emit light, the brightness of the entire pixel is lowered and no dark spot is generated, so that the worst situation can be avoided. Patent Document 1 relates to a driving method for suppressing the decrease in luminance.
JP 2007-41574 A

For the holding capacitor, the value should be as large as possible. The reason will be briefly described below by taking a 2T · 1C type pixel circuit as an example.
The pixel circuit adjusts the holding voltage of the holding capacitor according to the threshold voltage of the driving transistor, then turns on the sampling transistor, and sets the potential according to the input data potential at the gate of the driving transistor. A drain current flows through the driving transistor in accordance with the set potential at this time, and the holding voltage of the holding capacitor is adjusted in accordance with the amount of the current to perform mobility correction. The mobility correction is performed until the gate of the driving transistor becomes floating by turning off the sampling transistor from the on state. When the gate of the driving transistor is in a floating state, the driving transistor is held until the driving current corresponding to the data voltage which is held in the holding capacitor and whose value is adjusted by the correction according to the threshold voltage or mobility can be passed. The potentials of the gate and source of the transistor are automatically boosted (boosted).

The boost efficiency G _{bst at} this time is shown in FIG. 10A. The parasitic capacitance between the gate and the source of the driving transistor Md is “Cgs”, the parasitic capacitance between the gate and the drain is “Cgd”, and the sampling transistor Ms shown in FIG. When the parasitic capacitance between the gate and the drain is represented by “Cd”, and the device capacitance of the holding capacitor Cs is represented by the same symbol “Cs” as that of the holding capacitor, the equation shown in FIG. The device capacitance of the holding capacitor Cs is not a held capacitance value but a capacitance determined by a device structure (electrode area, capacitor dielectric film thickness, material, etc.).

Even when the sampling transistor Ms is turned off and boosting is started, the holding capacitor Cs needs to continue to hold the data voltage that has already been set and corrected, and the boost efficiency G _bst is ideally 1.
However, as can be seen from the equation of FIG. _10B , the influence of various parasitic capacitances is related to the boost efficiency G _bst . In order to eliminate the influence of these parasitic capacitances and keep the boost efficiency G _bst at approximately 1, it is necessary to increase the device capacitance (Cs) of the holding capacitor as much as possible from the equation of FIG. .

Incidentally, the pixel pitch is generally about 100 [μm] × about 300 [μm], for example, and there is a limit corresponding to the pixel area to increase the area of the holding capacitor Cs.
The storage capacitor Cs employs a so-called MIM structure in which an insulating material (dielectric film) is held between a lower electrode formed from a certain conductive film and an upper electrode formed from another conductive film. Is common. As the capacitor insulating film (dielectric film), an interlayer insulating film of wiring is used.

  If the area of the holding capacitor Cs having the MIM structure is to be increased within a limited pixel, the capacitor electrode (upper electrode or lower electrode) and another wiring or transistor electrode formed from the same conductive film as the capacitor electrode, etc. In other words, the separation distance is small between conductive layers in the same layer (hereinafter referred to as the same layer). For this reason, the probability of occurrence of a short circuit between the layers due to defective etching or foreign matter increases. Therefore, in order to prevent such a problem, it is necessary to secure a certain distance between the same layers, which limits the area expansion of the holding capacitor Cs.

  In particular, when it is necessary to provide a plurality of holding capacitors Cs in a pixel, capacitor electrodes (two upper electrodes or two lower electrodes) are arranged close to each other in the same hierarchy. Even between the capacitor electrodes, it is necessary to secure a sufficient distance to prevent the occurrence of a short circuit between the capacitor electrodes. Therefore, the area occupied by one capacitor is further reduced. As a result, the area and the number of holding capacitors arranged in one pixel are limited, and in practice, the pixel circuit configuration as disclosed in Patent Document 1 cannot be effectively implemented unless restrictions on the arrangement of the capacitors can be relaxed.

  In the present invention, when arranging a plurality of driving transistors, holding capacitors, and light emitting elements in one pixel by devising the arrangement of the holding capacitors, in particular, the area occupied by the holding capacitors is reduced, and the capacitance value per unit area is reduced. A self-luminous display device having an enlarged pixel circuit configuration is provided.

  A self-luminous display device according to one embodiment (first embodiment) of the present invention includes a pixel array having a plurality of pixels, and each of the plurality of pixels includes a sampling transistor, a driving transistor, and the driving transistor. A storage capacitor that is coupled to the light emission control node and holds a data potential input via the sampling transistor, and is connected in series to a drive current path together with the drive transistor, and the drive transistor is controlled according to the held data potential And a light emitting element that emits light based on the amount of driving current to be emitted. Further, in the self-luminous display device, in each of the plurality of pixels, a plurality of the driving transistors, the holding capacitors, and the light-emitting elements are provided, and the plurality of holding capacitors serve as a first conductive as a lower electrode. A first capacitor formed by laminating a layer, a first insulating layer, and a second conductive layer as an upper electrode in this order; a second capacitor layer as a lower electrode; and a second capacitor layer on the second electrode layer. And a second capacitor formed by laminating an insulating layer and a third conductive layer as an upper electrode layer in this order.

  In addition to the features of the first embodiment, the self-luminous display device according to another embodiment (second embodiment) of the present invention includes the driving transistor, the holding capacitor, and the light emitting element in each of the plurality of pixels. A plurality of sets of pixel circuit elements including each of them are provided, and one holding capacitor included in each set of pixel circuit elements includes the first capacitor and the second capacitor, and the first capacitor is included in the same set. The first capacitor and the second capacitor are electrically connected in parallel with each other by electrically connecting the conductive layer and the third conductive layer.

  The self-luminous display device according to another mode (third mode) of the present invention is the same as the first mode in which the first conductive layer has the same material and film thickness as the gate electrode of the driving transistor. A conductive layer separated from the gate electrode in a hierarchy, wherein the second conductive layer has the same material and film thickness as the source electrode and drain electrode of the driving transistor, and the source electrode and drain electrode in the same hierarchy The third conductive layer also serves as the lower electrode of the light emitting element.

  The self-luminous display device according to another embodiment (fourth embodiment) of the present invention is the above-described second embodiment, wherein the first capacitor and the second capacitor constituting the holding capacitor in the same set are the first capacitor and the second capacitor. One conductive layer is a conductive layer having the same material and thickness as the gate electrode of the driving transistor and separated from the gate electrode in the same layer, and the second conductive layer is a source electrode of the driving transistor. And a conductive layer having the same material and thickness as the drain electrode and separated from the source electrode and the drain electrode in the same layer, the third conductive layer also serving as a lower electrode of the light emitting element, and The third conductive layer is connected to the lower first conductive layer through a second contact formed in the second insulating layer and a first contact formed in the first insulating layer.

  According to the self-luminous display device of the present invention having the above-described configuration, a plurality of holding capacitors are included, and the plurality of holding capacitors are stacked on the first capacitor in a stacked structure of the first capacitor and the conductive layer. And a second capacitor. The upper electrode of the first capacitor also serves as the lower electrode of the second capacitor. Therefore, even if the total capacitance (device capacitance) of the first capacitor and the second capacitor is increased, the total occupied area of the first capacitor and the second capacitor is relatively small.

  In particular, in the second embodiment, the first capacitor and the second capacitor are connected in parallel with each other in terms of a circuit, and therefore, these two capacitors are equivalent to one holding capacitor. Therefore, when a plurality of pixel circuit element sets each including a driving transistor, a holding capacitor, and a light emitting element are provided for each pixel, if the holding capacitor is composed of the first capacitor and the second capacitor in each set, Despite a small occupied area, a holding capacitor having a relatively large capacity (device capacity) has been realized.

In the third and fourth embodiments, the first capacitor has a first conductive layer as a lower electrode formed of a conductive layer in the same level as the gate electrode of the drive transistor, and the source electrode and drain of the drive transistor It has the 2nd conductive layer as an upper electrode formed from the conductive layer of the same hierarchy as an electrode. The second capacitor has a lower electrode formed from the second conductive layer, and an upper electrode formed from the third conductive layer that also serves as the lower electrode of the light emitting element.
Therefore, it is not necessary to stack a new conductive layer only for the first capacitor and the second capacitor, and the holding capacitor can be formed without any additional process in the process of forming the driving transistor and the light emitting element. it can.

  According to the present invention, when a plurality of driving transistors, holding capacitors, and light emitting elements are provided in one pixel by devising the arrangement of the holding capacitor, a pixel in which the capacitance is increased while reducing the area occupied by the holding capacitor. A self-luminous display device having a circuit configuration can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings, using an organic EL display having a 2T · 1C type pixel circuit as a main example.

<Overall configuration>
FIG. 1 shows a main configuration of an organic EL display according to an embodiment of the present invention.
The illustrated organic EL display 1 includes a pixel array 2 in which a plurality of pixel circuits (PXLC) 3 (i, j) are arranged in a matrix, a vertical drive circuit (V scanner) 4 that drives the pixel array 2, and a horizontal And a drive circuit (H selector: HSEL) 5.
A plurality of V scanners 4 are provided depending on the configuration of the pixel circuit 3. Here, the V scanner 4 includes a horizontal pixel line drive circuit (DSCN) 41 and a write signal scanning circuit (WSCN) 42. The V scanner 4 and the H selector 5 are a part of the “drive circuit”. The “drive circuit” includes a circuit for supplying a clock signal to the V scanner 4 and the H selector 5, a control circuit (CPU, etc.), and the like. Also includes a circuit (not shown).

The code “3 (i, j)” of the pixel circuit shown in FIG. 1 indicates that the pixel circuit has an address i (i = 1, 2) in the vertical direction (vertical direction) and an address j ( j = 1,2,3). These addresses i and j take integers of 1 or more with the maximum values being “n” and “m”, respectively. Here, for simplification of the figure, a case where n = 2 and m = 3 is shown.
This address notation is similarly applied to the elements, signals, signal lines, voltages, and the like of the pixel circuit in the following description and drawings.

Pixel circuits 3 (1,1) and 3 (2,1) are connected to the video signal line DTL (1) in the vertical direction. Similarly, the pixel circuits 3 (1,2) and 3 (2,2) are connected to the video signal line DTL (2) in the vertical direction, and the pixel circuits 3 (1,3) and 3 (2,3) are vertical. Direction video signal line DTL (3). The video signal lines DTL (1) to DTL (3) are driven by the H selector 5.
The pixel circuits 3 (1,1), 3 (1,2) and 3 (1,3) in the first row are connected to the write scanning line WSL (1). Similarly, the pixel circuits 3 (2,1), 3 (2,2) and 3 (2,3) in the second row are connected to the write scanning line WSL (2). The write scanning lines WSL (1) and WSL (2) are driven by the write signal scanning circuit.
The pixel circuits 3 (1,1), 3 (1,2) and 3 (1,3) in the first row are connected to the power supply scanning line DSL (1). Similarly, the pixel circuits 3 (2,1), 3 (2,2) and 3 (2,3) in the second row are connected to the power supply scanning line DSL (2). The power supply scanning lines DSL (1) and DSL (2) are driven by the horizontal pixel line driving circuit 41.

Any one of the m video signal lines including the video signal lines DTL (1) to DTL (3) will be represented by the symbol “DTL (j) or DTL”. Similarly, any one of the n write scan lines including the write scan lines WSL (1) and WSL (2) is represented by the reference numeral “WSL (i) or WSL”, and the power scan line DSL (1 ), Any one of the n power supply scanning lines including DSL (2) is represented by a symbol “DSL (i) or DSL”.
For the video signal line DTL (j), line-sequential driving in which video signals are discharged all at once in units of display pixel rows (also referred to as display lines), or video is sequentially applied to video signal lines DTL (j) in the same row. Although there is dot sequential driving in which signals are discharged, any driving method may be used in this embodiment.

<Pixel circuit>
FIG. 2 shows a basic configuration example of the pixel circuit 3 (i, j). Here, a plurality of basic configurations are provided in one pixel with the basic configuration illustrated in FIG. 2 (hereinafter, also referred to as a set) as a unit. Hereinafter, the basic configuration will be described, and an example of connection between the basic configurations (sets) and an example of the pattern layout will be described later.

  The basic configuration of the pixel circuit 3 (i, j) illustrated is a circuit that controls the organic light emitting diode OLED. The basic configuration of the pixel circuit includes, in addition to the organic light emitting diode OLED, a drive transistor Md and a sampling transistor Ms made of NMOS type TFTs, and a holding capacitor Cs.

  Although the organic light emitting diode OLED is not particularly shown, for example, in the case of a top emission type, an anode electrode is first formed on a TFT structure formed on a substrate made of transparent glass or the like, and a hole transport layer, A light emitting layer, an electron transport layer, an electron injection layer, and the like are sequentially deposited to form a laminate that forms an organic multilayer film, and a cathode electrode made of a transparent electrode material is formed on the laminate. The anode electrode is connected to the positive power source, and the cathode electrode is connected to the negative power source.

  When a bias voltage for obtaining a predetermined electric field is applied between the anode and cathode electrodes of the organic light emitting diode OLED, the organic multilayer film emits light when the injected electrons and holes recombine in the light emitting layer. The organic light emitting diode OLED can emit light in each color of red (R), green (G), and blue (B) by appropriately selecting the organic material constituting the organic multilayer film. For example, color display is possible by arranging the light emission of R, G, B in the pixels of each row. Alternatively, R, G, and B may be distinguished by the color of the filter using an organic material that emits white light. A four-color configuration in which W (white) is added in addition to R, G, and B may be used.

The drive transistor Md functions as current control means for controlling the amount of current flowing through the organic light emitting diode OLED to define display gradation.
The drain of the driving transistor Md is connected to the power supply scanning line DSL (i) that controls the supply of the power supply voltage VDD, and the source is connected to the anode of the organic light emitting diode OLED.

  The sampling transistor Ms is connected between the supply line (video signal line DTL (j)) of the data potential Vsig that determines the pixel gradation and the gate (control node NDc) of the drive transistor Md. One of the source and drain of the sampling transistor Ms is connected to the gate (control node NDc) of the drive transistor Md, and the other is connected to the video signal line DTL (j). A data pulse having a data potential Vsig is supplied to the video signal line DTL (j) from the H selector 5 (see FIG. 1) at a predetermined interval. The sampling transistor Ms samples data at a level to be displayed by the pixel circuit at an appropriate timing in a data potential supply period (data pulse duration time). This is to eliminate the influence on the display image in the transition period where the level is unstable at the front or rear of the data pulse having the desired data potential Vsig to be sampled.

A holding capacitor Cs is connected between the gate (control node) and source (one electrode forming the anode of the organic light emitting diode OLED) of the drive transistor Md.
The role, arrangement, etc. (structure and pattern layout) of the storage capacitor Cs will be described later.

In FIG. 2, the horizontal pixel line drive circuit 41 supplies a power supply drive pulse DS (i) in which the peak value of the high potential Vcc_H with respect to the low potential Vcc_L becomes the power supply voltage VDD to the drain of the drive transistor Md. Power is supplied when correcting Md or when the organic light emitting diode OLED actually emits light.
Further, the write signal scanning circuit 42 supplies a write drive pulse WS (i) having a relatively short duration to the gate of the sampling transistor Ms to perform sampling control.
The power supply control may be configured such that another transistor is inserted between the drain of the drive transistor Md and the supply line of the power supply voltage VDD, and the gate is controlled by the horizontal pixel line drive circuit 41. (Refer to a modification described later).

  In FIG. 2, one electrode (anode) of the organic light emitting diode OLED is supplied with the power supply voltage VDD from the positive power supply via the drive transistor Md. The other electrode (cathode) of the organic light emitting diode OLED is supplied with a negative cathode potential Vcath from a negative power source via a cathode line.

  Usually, all transistors in the pixel circuit are formed of TFTs. The thin film semiconductor layer in which the TFT channel is formed is made of a semiconductor material such as polycrystalline silicon (polysilicon) or amorphous silicon (amorphous silicon). Polysilicon TFTs can have high mobility, but their characteristic variation is large, so they are not suitable for increasing the screen size of a display device. Therefore, in a display device having a large screen, an amorphous silicon TFT is generally used. However, since it is difficult to form a P-channel TFT in an amorphous silicon TFT, it is desirable that all TFTs be an N-channel type like the pixel circuit 3 (i, j) described above.

Here, the basic configuration of the pixel circuit 3 (i, j) is an example of a pixel circuit applicable in the present embodiment, that is, a basic configuration example of a two-transistor (2T) / 1-capacitor (1C) type. Therefore, the basic configuration of the pixel circuit that can be used in the present embodiment may be a pixel circuit to which a transistor or a capacitor is added in addition to the basic configuration of the pixel circuit 3 (i, j) (described later). (Refer to the modification). In some basic configurations, the holding capacitor Cs is connected between the supply line of the power supply voltage VDD and the gate of the drive transistor Md.
Specifically, some pixel circuits other than the 2T • 1C type that can be employed in the present embodiment will be briefly described in modification examples described later. For example, 4T • 1C type, 4T • 2C type, 5T • 1C type It may be a 3T / 1C type.

In the pixel circuit based on the configuration of FIG. 2, when the organic light emitting diode OLED is reverse-biased at the time of threshold voltage correction or mobility correction, the equivalent capacitance value at the time of reverse bias of the organic light-emitting diode OLED is sufficiently larger than the value of the holding capacitor Cs. Since it can be increased, the anode of the organic light emitting diode OLED becomes difficult to move in terms of potential, so that the correction accuracy is improved. For this reason, it is desirable to perform correction in a reverse bias state.
The cathode potential Vcath is a potential for performing reverse bias. In order to reverse bias the organic light emitting diode OLED, for example, the cathode potential Vcath is made smaller than the reference potential (low potential Vcc_L) of the power supply driving pulse DS (i). In this example, it is assumed that the cathode potential Vcath is a negative potential.

  At the time of writing data, the capacitance value seen from the anode of the organic light emitting diode OLED may be increased in order to make the anode potential of the organic light emitting diode OLED harder to move and to fix the potential. For this purpose, an auxiliary capacitor may be connected to the anode of the organic light emitting diode OLED.

<Display control>
The operation at the time of data writing in the circuit of FIG. 2 will be described together with the threshold voltage and mobility correction operation. A series of these operations is called “display control”.
First, the characteristics of the drive transistor to be corrected and the organic light emitting diode OLED will be described.

A holding capacitor Cs is coupled to the control node NDc of the drive transistor Md shown in FIG. The data potential Vsig, which is the effective potential of the data pulse transmitted through the video signal line DTL (j), is sampled by the sampling transistor Ms, and the potential thus obtained is applied to the control node NDc and held by the holding capacitor Cs. When a predetermined potential is applied to the gate of the drive transistor Md, the drain current Ids is determined according to the gate-source voltage Vgs having a value corresponding to the applied potential.
Here, it is assumed that sampling is performed after the source potential Vs of the drive transistor Md is initialized to the reference potential (data reference potential Vo) of the data pulse. The data potential Vsig after sampling, more precisely, the drain current Ids corresponding to the magnitude of the data voltage Vin defined by the potential difference between the data reference potential Vo and the data potential Vsig flows to the drive transistor Md, which is almost organic. It becomes the drive current Id of the light emitting diode OLED.
Therefore, when the source potential Vs of the driving transistor Md is initialized with the data reference potential Vo, the organic light emitting diode OLED emits light with a luminance corresponding to the data potential Vsig.

As is well known, the organic light emitting diode OLED changes its IV characteristic with time. At this time, the gate-source voltage Vgs of the drive transistor Md changes with the aging of the organic light emitting diode OLED.
As a result, the drive current Id flowing through the organic light emitting diode OLED changes, and as a result, the light emission luminance changes even at the predetermined data potential Vsig.
Further, since the threshold voltage Vth and the mobility μ of the driving transistor Md are different for each pixel circuit, the drain current Ids varies, and the light emission luminance of the pixel to which the same data potential Vsig is applied changes.

  The pixel circuit having the N-channel type driving transistor Md has an advantage of high driving capability and simplification of the manufacturing process. However, in order to suppress variations in the threshold voltage Vth and the mobility μ, the following correction operation is performed as described above. It is necessary to carry out prior to the emission control operation.

Prior to sampling, the gate potential of the drive transistor Md is held at the level of the threshold voltage Vth by the holding capacitor Cs. This preliminary operation is referred to as “threshold correction”.
After the threshold correction, since the sampled data potential Vin is applied to the gate of the drive transistor Md, the gate potential is held at “Vth + Vin”. The drive transistor Md is turned on according to the magnitude of the data potential Vin at this time. In the case of the drive transistor Md having a large threshold voltage Vth and difficult to turn on, “Vth + Vin” is large, and conversely, in the case of the drive transistor Md having a small threshold voltage Vth and easy to turn on, “Vth + Vin” is also small. Therefore, if the influence of the variation of the threshold voltage Vth is eliminated from the drive current and the data potential Vin is constant, the drain current Ids (drive current Id) is also constant.

Further, for example, “mobility (strictly, driving force correction)” is performed after threshold correction before data sampling.
In the mobility correction, the gate potential is changed according to the current drive capability of the drive transistor Md from the state where the voltage “Vth + Vsig” is held. A path is provided between the gate and the source of the driving transistor Md to charge or discharge the holding capacitor with a current through the current channel of the driving transistor Md, and it is controlled whether or not a current flows through this path. To correct the mobility.
Thereafter, the organic light emitting diode OLED emits light by being driven to the constant current value.

The light emitting operation of the organic light emitting diode OLED is started when the sampling transistor Ms changes from the on state to the off state and the gate of the drive transistor Md enters the floating state.
When the gate of the driving transistor Md is in a floating state, it is held in the holding capacitor Cs, and a driving current Id corresponding to the data voltage whose value is adjusted by correction according to the threshold voltage or mobility can be passed. Until then, the gate and source potentials of the drive transistor Md are automatically boosted.
As already described, it is necessary to eliminate the influence of the transistor parasitic capacitance at the time of boosting (by setting the boost efficiency to 1) so that the corrected holding capacitor value of the holding capacitor Cs is kept constant. . For this purpose, the capacitance value of the holding capacitor Cs (device capacitance value represented by the same symbol “Cs”) is designed to be sufficiently larger than various parasitic capacitances of the transistor.

  In the pixel circuit of the present embodiment, for example, a plurality of sets of pixel circuit components shown in FIG. 2, that is, a set of organic light emitting diodes OLED, drive transistors Md, and holding capacitors Cs are provided. Here, regarding the sampling transistor Ms, either one sampling transistor Ms per group or a plurality of sets sharing the sampling transistor Ms may be used.

  For example, as shown in FIG. 3, when the number of groups is “2”, a sampling transistor may be provided for each group. Alternatively, as shown in FIG. 4, a plurality of (here, two) sampling transistors may be shared. When sharing sampling transistors, the number of sets sharing one sampling transistor is an arbitrary number of 2 or more. The number of sets sharing one sampling transistor may not be one type in one pixel. That is, one sampling transistor may be shared by two sets and another sampling transistor may be shared by three sets within one pixel.

<Structure of plane and cross section: comparative example>
Here, for a comparative example (general structure) to which the present invention is not applied, a planar pattern and a sectional structure of a pixel circuit will be described with reference to the drawings.
FIGS. 5A and 5B show planar patterns for the pixel circuit 3 (i, j) of the comparative example. FIG. 5A corresponds to the case where two sampling transistors are provided for each set, and two sampling transistors Ms1 and Ms2 are connected to a common write scanning line WSL (i), as in FIG. To do.
FIG. 5B is a plan view in which the uppermost cathode electrode (entire formation) is omitted, and FIG. 5A is an uppermost cathode electrode (entire formation). It is a top view in the middle of manufacture which excluded the organic multilayer film. FIG. 6B is a basic cross-sectional structure diagram of the TFT portion, and FIG. 6A is a plan view thereof.

As shown in FIG. 6B, a predetermined gate metal layer (GM) such as molybdenum (directly on a substrate 9 made of glass or the like directly (or via a base layer (a kind of insulating layer)) as illustrated. A gate electrode 11 made of a refractory metal layer such as Mo) is formed.
In FIG. 5A, the gate electrode 11 corresponds to the gate electrode 11A1 of the driving transistor Md1, the gate electrode 11A2 of the driving transistor Md2, and the common gate electrode 11B of the sampling transistors Ms1 and Ms2. Here, the gate electrode 11A1 is arranged so as to extend in the formation region of the holding capacitor Cs1 in order to function as a lower electrode of the holding capacitor Cs1. Similarly, the gate electrode 11A2 extends over the formation region of the holding capacitor Cs2 so as to function as a lower electrode of the holding capacitor Cs2. On the other hand, one end of the gate electrode 11B extends downward for connection to the write scanning line WSL (i). One end of the gate electrode 11B is connected to the write scan line WSL (i) via a contact 12B which is one of the 1st contact holes (1CH).

As shown in FIG. 6B, a gate insulating film 10 is formed on the substrate 9 so as to cover the surface of the gate electrode 11 (any one of the gate electrodes 11A1, 11A2, and 11B), and amorphous silicon is formed thereon. A thin film semiconductor layer 13 made of (α-Si) is formed.
Although not shown in FIG. 5A, the thin film semiconductor layer 13 is a layer for forming the TFT layers of the drive transistors Md1 and Md2 and the TFT layers of the sampling transistors Ms1 and Ms2 so as to be isolated from each other.

  In the thin film semiconductor layer 13 in FIG. 6B, a portion facing the gate electrode 11 is a channel formation region. A channel protective film 18 made of an insulating material is formed at a position to protect the channel formation region on the thin film semiconductor layer 13. In addition, two end portions of the source / drain electrodes 14 are disposed on the channel protective film 18 so as to have a width slightly narrower than that of the thin film semiconductor layer 13 (see FIG. 6A). The source / drain electrodes 14 are separated from each other on the channel protective film 18, and one of them functions as a source (S) electrode, and the other functions as a drain (D) electrode. The two source / drain electrodes 14 are formed of, for example, a wiring layer (AL) layer mainly made of aluminum (AL).

The source / drain electrode 14 of FIG. 6 is related to the drive transistor Md1 of FIG. 5A, a VDD line 14A that branches from the power supply scanning line DSL (i) and functions as the drain electrodes of the drive transistors Md1 and Md2, and the drive transistor Md1. This corresponds to the connection wiring 14B1 functioning as the source electrode of the first electrode. The connection wiring 14B1 is disposed so as to overlap the gate electrode 11A1 in order to function as an upper electrode of the holding capacitor Cs1.
6 corresponds to the VDD line 14A and the connection wiring 14B2 functioning as the source electrode of the driving transistor Md2 with respect to the driving transistor Md2 in FIG. 4A. The connection wiring 14B2 is disposed so as to overlap the gate electrode 11A1 in order to function as an upper electrode of the holding capacitor Cs2.

Further, the source / drain electrode 14 of FIG. 6 corresponds to the connection wiring 14C functioning as the drain electrode and the connection wiring 14D1 functioning as the source electrode of the sampling transistor Ms1 of FIG.
Similarly, for the sampling transistor Ms2 in FIG. 5A, the source / drain electrode 14 in FIG. 6 corresponds to the connection wiring 14C that functions as the drain electrode and the connection wiring 14D2 that functions as the source electrode of the sampling transistor Ms2. .

The connection wiring 14C is provided in common by the two sampling transistors Ms1 and Ms2, and also functions as a part of the video signal line DTL (j).
The connection wiring 14D1 has an end extending above the lower electrode (gate electrode 11A1) of the storage capacitor Cs1 and is connected to the control node NDc of FIG. 2 by a contact 12A1 that is one of the first contact holes (1CH). Are connected to the gate electrode 11A1.
Similarly, the connection wiring 14D2 has one end extending above the lower electrode (gate electrode 11A2) of the storage capacitor Cs2 for connection to the control node NDc in FIG. 2, and is one of the first contact holes (1CH). The contact 12A2 is connected to the gate electrode 11A2.

  As shown in FIG. 6B, the P-type thin film semiconductor layer 13 and the reverse conductivity type N-type impurity are introduced at a high concentration in the overlapping portion between the two source / drain electrodes 14 and the thin film semiconductor layer 13. A source impurity region 17S and a drain impurity region 17D are provided. A source contact in which one source / drain electrode 14 and the thin film semiconductor layer 13 are connected with low resistance is achieved by the source impurity region 17S. Similarly, the drain impurity region 17D achieves a drain contact in which the other source / drain electrodes 14 and the thin film semiconductor layer 13 are connected with low resistance.

In FIG. 5A, the write scan line WSL (i) and the power supply scan line DSL (i) are each formed from the (AL) layer and arranged in parallel to each other along opposite sides in the row direction in the cell. ing.
On the other hand, the video signal line DTL (j) is formed long in the column direction orthogonal to the write scanning line WSL (i) and the like.

Most of the in-cell portions of the video signal line DTL (j) are configured by the connection wiring 14C made of the (AL) layer as described above.
At the intersection of the video signal line DTL (j) and the power supply scanning line DSL (i), a bridge line 11C including the same material layer (GM) as the gate electrode 11 (see FIG. 6) is provided. . One end of the connection wiring 14C is connected to the lower layer bridge line 11C by two contacts 12C (1CH), and the power supply scanning line DSL of the same material (AL) at the same level as the connection wiring 14C is formed on the bridge line 11C. (i) intersects.
Similarly, a bridge line 11 </ b> D including a layer (GM) of the same material at the same level as the gate electrode 11 is provided at the intersection between the video signal line DTL (j) and the write scanning line WSL (i). The other end of the connection wiring 14C is connected to the lower-layer bridge line 11D by two contacts 12D (1CH), and write scanning lines of the same material (AL) at the same level as the connection wiring 14C are formed on the bridge line 11D. WSL (i) intersects.

Returning to FIG. 6B, a TFT protective film 19 covering the TFT having the above-described structure is deposited.
Although not shown in FIG. 6B, an organic light emitting diode OLED is formed on the TFT protective film 19. In the organic light emitting diode OLED, as shown in FIG. 5B, lower-layer anode electrodes AEa and AEb each formed of an anode metal layer (AM) formed in a region where a pixel is divided into two are formed.
The anode electrode AEa is connected to the lower connection wiring 14B1 by a contact 15A which is one of the 2nd contact holes (2CH). Similarly, the anode electrode AEb is connected to the connection wiring 14B2 via the contact 15B (2CH).

In this embodiment, since it is a top emission type, the anode metal layer (AM) is made of, for example, chromium (Cr), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), tantalum (Ta). , Tungsten (W), platinum (Pt), and gold (Au) can be formed by appropriately selecting a conductive material having a high work function and high reflectivity.
An EL protective film 21 covering the surfaces of the anode electrodes AEa and AEb is formed, and openings 21A and 21B are provided in the EL protective film 21. The openings 21A and 21B are formed as large as possible on the anode electrode AE without exposing the contacts 15A and 15B.

FIG. 7 shows a schematic cross-sectional view along the line AA shown in FIG.
An insulating planarizing film 20 for planarizing the surface of the insulating TFT protective film 19 is formed, and anode electrodes AEa and AEb are formed on the planarizing film 20 apart from each other.
An EL protective film 21 is formed on the anode electrodes AEa and AEb, and the EL protective film 21 has openings 21A and 21B.
Organic multilayer films OMFa and OMFb are formed in the openings 21A and 21B, respectively. A cathode electrode 23 is provided on the organic multilayer films OMFa and OMFb so as to cover the upper surface of the organic multilayer film and the surface of the surrounding EL protective film 21. The cathode electrode 23 is made of a transparent electrode material.

  The holding capacitor Cs1 has an MIM structure in which the gate electrode 11A1 is a lower electrode, the gate insulating film 10 is a capacitor dielectric film, and the connection wiring 14B1 is an upper electrode. Similarly, the holding capacitor Cs2 has an MIM structure in which the gate electrode 11A2 is a lower electrode, the gate insulating film 10 is a capacitor dielectric film, and the connection wiring 14B2 is an upper electrode. Therefore, between the connection wirings 14B1 and 14B2 formed by processing the same level aluminum (AL) film or between the gate electrodes 11A1 and 11A2 formed by processing the same level gate metal (GM) film. It is easy for short circuit defects to occur. In order to prevent the occurrence of short-circuit failure, it is necessary to sufficiently separate the distance between the two, which leads to an increase in cell area.

In this embodiment, each of the holding capacitors Cs1 and Cs2 has a stacked structure of a first capacitor and a second capacitor, thereby eliminating this problem.
As shown in FIGS. 3 and 4, in the equivalent circuit of the pixel circuit according to the present embodiment, the holding capacitor Cs1 is connected to the first capacitor Cs11 and the second capacitor Cs12 connected in parallel to the first capacitor Cs11. It consists of and. Similarly, the holding capacitor Cs2 includes a first capacitor Cs21 and a second capacitor Cs22 connected in parallel to the first capacitor Cs21.

<Structure of plane and cross section: Examples>
Here, regarding an embodiment to which the present invention is applied, a planar pattern and a cross-sectional structure of a pixel circuit will be described with reference to the drawings.
FIGS. 8A and 8B show a planar pattern for the pixel circuit 3 (i, j) of the embodiment. FIG. 8A corresponds to the case where two sampling transistors are provided for each set and two sampling transistors Ms1 and Ms2 are connected to a common write scanning line WSL (i), as in FIG. To do.
8B is a plan view in which the uppermost cathode electrode (entire surface formation) is omitted, and FIG. 8A is an uppermost layer cathode electrode (overall surface formation) omitted. It is a top view in the middle of manufacture which excluded the organic multilayer film.

Also in this example, the basic structure of the TFT portion shown in FIGS. 6A and 6B is the same as the comparative example described above.
Hereinafter, a configuration different from the comparative example will be described.

  The TFT section (drive transistors Md1, Md2 and sampling transistors Ms1, Ms2) has the same basic structure as that shown in FIG. 6, but the embodiment and the comparative example differ in the following points.

First, in the comparative example, the gate electrodes of the drive transistors Md1 and Md2 and the lower electrodes of the holding capacitors Cs1 and Cs2 are common gate electrodes 11A1 and 11A2 formed integrally from a gate metal (GM) ( In the embodiment shown in FIGS. 5A and 8A, the gate electrode and the lower electrode are separated. More specifically, as shown in FIG. 8A, in one set, the gate electrode 11E1 of the driving transistor Md1 and the first conductive layer 11F1 that becomes the lower electrode of the first capacitor Cs11 are separately provided. Yes. Similarly, in another set, the gate electrode 11E2 of the drive transistor Md2 and the first conductive layer 11F2 that becomes the lower electrode of the first capacitor Cs21 are separately provided.
The gate electrodes 11E1 and 11E2 and the first conductive layers 11F1 and 11F2 are all formed separately on the same layer by patterning one gate metal (GM).

Second, in the comparative example, the source electrodes of the driving transistors Md1 and Md2 and the upper electrodes of the holding capacitors Cs1 and Cs2 are formed by the common connection wirings 14B1 and 14B2 (FIG. 5A), but FIG. In the embodiment shown in (A), the source electrode and the capacitor electrode are separated. More specifically, as shown in FIG. 8A, in one set, the source electrode 14E1 of the drive transistor Md1, the second electrode that serves as the upper electrode of the first capacitor Cs11, and the lower electrode of the second capacitor Cs12. The conductive layer 14F1 is provided separately. Similarly, in another set, the source electrode 14E2 of the driving transistor Md2 and the second conductive layer 14F2 that also serves as the upper electrode of the first capacitor Cs21 and the lower electrode of the second capacitor Cs22 are separately provided.
The source electrodes 14E1 and 14E2 and the second conductive layers 14F1 and 14F2 are all formed separately on the same layer by patterning one aluminum (AL) film.

  The source electrode 14E1 is connected to one end of the lower gate electrode 11E1 by a contact 12E1 (1CH). Further, the source electrode 14E1 extends to the edge of the gate electrode 11B in order to also serve as the source electrode of the sampling transistor Ms1. Similarly, the source electrode 14E2 is connected to one end of the lower gate electrode 11E2 by a contact 12E1 (1CH). The source electrode 14E2 extends to the edge of the gate electrode 11B in order to also serve as the source electrode of the sampling transistor Ms2.

On the other hand, the source electrode 14E1 of the drive transistor Md1 is connected to the lower first conductive layer 11F1 by a contact 12F1 (1CH). Similarly, the source electrode 14E2 of the drive transistor Md2 is connected to the lower first conductive layer 11F2 through the contact 12F2.
The source electrode 14E1 is connected to the upper layer anode electrode AEa by a contact 15A (2CH). Similarly, the source electrode 14E2 is connected to the upper-layer anode electrode AEb by a contact 15B (2CH).

  With the above pattern configuration and connection relationship, the holding capacitor Cs1 is formed between the first conductive layer 11F1 and the second conductive layer 14F1, the first capacitor Cs11, the second conductive layer 14F1, and the “third conductive layer”. A multilayer capacitor configuration in which a second capacitor Cs12 formed between the anode electrode AEa and the anode capacitor AEa is connected in parallel. Similarly, the holding capacitor Cs2 includes the first capacitor Cs21 formed between the first conductive layer 11F2 and the second conductive layer 14F2, the second conductive layer 14F2, and the anode electrode AEb as the “third conductive layer”. A multilayer capacitor structure in which a second capacitor Cs22 formed between the two is connected in parallel.

FIG. 9 shows a schematic cross-sectional view along the line BB shown in FIG.
From FIG. 9, in the pixel circuit according to the embodiment, the distance between the aluminum (AL) and the gate metal (GM), which are the short-risk locations in FIG. 7, is enlarged. That is, in FIG. 9, when the same capacitor capacity (device capacity) as that in FIG. 7 is secured, the occupied area of the first and second capacitors is almost halved as compared with the holding capacitor in FIG. For this reason, the distance between the second conductive layers 14F1 and 14F2 and the distance between the first conductive layers 11F1 and 11F2 can be increased. Further, the pixel area can be further reduced even if the necessary distance is secured.

  According to the embodiment of the present invention, it is possible to provide a plurality of sets of the organic light emitting diode OLED, the driving transistor Md, and the holding capacitor Cs by reducing the area of the holding capacitor portion within a limited pixel size. is there.

For this reason, foreign substances generated during processing of the electrodes of the organic light emitting diodes OLED and the organic film are placed on the openings of the EL protective film 21 in any one (or two or more) of the plurality of sets, thereby Even if a short-circuited point becomes a dark spot, the plurality of anode electrodes are not electrically connected to each other, so that light is emitted independently, and the pixel does not become a complete dark spot defect.
In addition, if the source and drain of the drive transistor, which is a component of a plurality of sets, are short-circuited and the opening becomes a bright spot defect, other than the set to which the defective drive transistor belongs, Therefore, the pixel does not become a complete dark spot defect. Similarly, even if the source and drain of a sampling transistor that constitutes one of the groups is short-circuited and the opening of that group becomes a half-dead point, it is connected to a sampling transistor other than the defective sampling transistor. Since the set of pixel circuit portions normally operate, the pixel does not have a complete dark spot defect.

In addition, since the area of the holding capacitor portion is small, the distance between capacitor electrodes belonging to different sets is long, and short-circuiting between the electrodes is prevented. In addition, the necessary distance can be secured and the pixel size can be further reduced. As a result, the overall yield can be improved.
Further, even if the storage capacitor has a two-layer structure, it is not necessary to add a new conductive layer, and a two-layer capacitor structure can be realized by using an existing conductive layer.

  A modification in this embodiment will be described.

<Modification 1>
In the above embodiment, since it is particularly effective when a plurality of sets are provided, the two-layer multilayer capacitor structure is applied to a pixel circuit having a plurality of sets. However, the organic light emitting diode OLED, the drive transistor Md, and the holding capacitor Cs are used. Even if there is only one set, it is easy to secure the distance between the capacitor electrode and the wiring adjacent to the capacitor electrode, and it is possible to obtain the same advantage that the short-circuit failure is reduced and the pixel size can be further reduced.

<Modification 2>
The pixel circuit and its basic configuration are not limited to those shown in FIGS.
2 to 4 and the basic configuration thereof, the data reference potential Vo is given by sampling the video signal Ssig, but the data reference potential Vo is given to the source and gate of the driving transistor Md via another transistor. You can also.
2 to 4 and the basic configuration thereof, the capacitor is only the holding capacitor Cs, but another holding capacitor may be provided, for example, between the gate of the driving transistor Md and the constant voltage line. . In this case, the holding capacitor and the other capacitor may have a two-layer capacitor structure as shown in FIG. The light emitting element is not limited to the organic light emitting diode OLED, and may be another self-light emitting element.

<Modification 3>
A driving method in which the pixel circuit controls light emission and non-light emission of the organic light emitting diode OLED includes a method in which the transistors in the pixel circuit are controlled by a scanning line, and a method in which a power supply voltage supply line is AC driven by a driving circuit (power supply AC Drive method).
The pixel circuit shown in FIGS. 2 to 4 and its basic configuration are an example of the latter power source AC driving method. In this method, the cathode side of the organic light emitting diode OLED is AC driven to pass a driving current. You may control.
On the other hand, in the former method of controlling the light emission control by the scanning line, another transistor is inserted between the drain side of the driving transistor Md or between the source and the organic light emitting diode OLED, and the gate thereof is scanned for power supply driving control. Drive with lines.

  Also in these modified examples, as in the embodiment of the present invention, the pixel circuit element group can be increased while reducing the capacitor area, and a plurality of pixel circuit element groups are provided to prevent dark spot defects. Effect is obtained. In addition, the overall yield can be further improved by reducing the capacitor area, or the cost can be reduced by reducing the pixel size.

It is a block diagram which shows the main structures of the organic electroluminescent display in connection with embodiment of this invention. 1 is a block diagram illustrating a basic configuration example of a pixel circuit according to an embodiment of the present invention. FIG. 5 is a pixel circuit diagram illustrating an example of connection when the number of sets is 2 according to an embodiment of the present invention. FIG. 10 is a pixel circuit diagram showing another connection example when the number of sets is 2 in the embodiment of the present invention. In a comparative example with the embodiment of the present invention, it is a figure showing a plane pattern of a pixel circuit. 2A and 2B are a plan view and a cross-sectional view showing a basic structure of a TFT used in a pixel circuit according to an embodiment of the present invention. It is a schematic sectional drawing in alignment with the AA of FIG. It is a figure which shows the plane pattern of a pixel circuit about the Example in embodiment of this invention. It is a schematic sectional drawing in alignment with the BB line of FIG. It is a figure for showing the formula of boost efficiency, and the parasitic capacitance of the pixel circuit used for the formula concerned.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Organic EL display, 2 ... Pixel array, 3 (i, j) ... Pixel circuit, 4 ... V scanner, 5 ... H selector, 9 ... Substrate, 10 ... Gate insulating film, 11 ... Gate electrode, 11F1, 11F2 ... 1st conductive layer, 12 ... (1st) contact, 13 ... thin film semiconductor layer, 14 ... source / drain electrode, 14F1, 14F2 ... 2nd conductive layer, 15 ... (2nd) contact, 18 ... channel protective film, 19 ... TFT Protective film, 21 ... EL protective film, 21A, 21B ... opening, 41 ... horizontal pixel line driving circuit, 42 ... write signal scanning circuit, Cs, Cs1, Cs2 ... holding capacitor, Cs11, Cs21 ... first capacitor, Cs12, Cs22 ... second capacitor, OLED ... organic light emitting diode, Ms ... sampling transistor, Md ... drive transistor, DSL (i) ... power supply scanning line, WSL (i) ... Write scanning lines, DTL (j) ... video signal lines, AEa, AEb ... anode electrode (third conductive layer), AM ... anode metal layer, GM ... gate metal layer, (AL) ... Aluminum

Claims (5)

Having a pixel array having a plurality of pixels;
Each of the plurality of pixels is
A sampling transistor;
A driving transistor;
A holding capacitor coupled to the light emission control node of the driving transistor and holding a data potential input via the sampling transistor;
A light-emitting element that is connected in series to a drive current path together with the drive transistor, and that emits light based on a drive current amount controlled by the drive transistor according to the held data potential;
In each of the plurality of pixels, a plurality of the driving transistors, the holding capacitors, and the light emitting elements are provided,
A plurality of said holding capacitors,
A first capacitor formed by laminating a first conductive layer as a lower electrode, a first insulating layer, and a second conductive layer as an upper electrode in this order;
A second capacitor in which the second conductive layer is used as a lower electrode and a second insulating layer and a third conductive layer as an upper electrode layer are stacked in this order on the second electrode layer;
Self-luminous display device including In each of the plurality of pixels, a plurality of sets of pixel circuit elements each including the driving transistor, the holding capacitor, and the light emitting element are provided,
One holding capacitor included in each set of pixel circuit elements includes the first capacitor and the second capacitor, and the first conductive layer and the third conductive layer are electrically connected in the same set. The self-luminous display device according to claim 1, wherein the first capacitor and the second capacitor are electrically connected in parallel with each other by being connected to the same. The first conductive layer is a conductive layer having the same material and thickness as the gate electrode of the driving transistor and separated from the gate electrode in the same layer,
The second conductive layer is a conductive layer having the same material and thickness as the source electrode and the drain electrode of the driving transistor and separated from the source electrode and the drain electrode in the same layer,
The self-luminous display device according to claim 1, wherein the third conductive layer also serves as a lower electrode of the light emitting element. In the first capacitor and the second capacitor constituting the holding capacitor in the same set,
The first conductive layer is a conductive layer having the same material and thickness as the gate electrode of the driving transistor and separated from the gate electrode in the same layer,
The second conductive layer is a conductive layer having the same material and thickness as the source electrode and the drain electrode of the driving transistor and separated from the source electrode and the drain electrode in the same layer,
The third conductive layer also serves as a lower electrode of the light emitting element, and the third conductive layer is a first contact formed on the first insulating layer and a second contact formed on the second insulating layer. The self-luminous display device according to claim 2, connected to the lower first conductive layer via a contact. The driving transistor includes a thin film semiconductor layer in which a channel of the driving transistor is formed on the gate electrode through a gate insulating film that also serves as the first insulating layer, and one end side of the thin film semiconductor layer. The self-luminous display device according to claim 4, wherein the drain electrode is connected to the thin film transistor, and the source electrode is connected to the other end.

Images