JP2009135362A - Manufacturing method of board for semiconductor package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a printed wiring board for a semiconductor package solving problems of contamination of a liquid of an electrolytic nickel/gold plating bath due to a palladium catalyst adhesion process before electroless copper plating, insulation reliability degradation between solder ball pads and the like, and having a pad subjected to electrolytic nickel/gold plating in a part of a semiconductor mounting surface without using a bus line. <P>SOLUTION: In relation to a circuit board of which the front and back sides are electrically connected through copper-plated vias, in this manufacturing method of a board for a semiconductor package, a surface roughening process of solder resist 8, a palladium removal process of a copper exposure part on a solder ball mounting surface, and a surface treatment process comprises an organic rustproofing process, electroless gold plating, electroless tin plating and a solder process. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a printed wiring board used in electronic equipment, electrical equipment, computers, communication equipment, and the like. More specifically, the present invention relates to a printed wiring board used for a pin grid array, a ball grid array, a chip size package, an MCM and the like on which a semiconductor is mounted. That is, it relates to a printed wiring board for a semiconductor package.

In a printed wiring board for a semiconductor package, electrolytic nickel / gold plating is conventionally used for a wire bond pad, which is a connection portion with a semiconductor, from the viewpoint of connection reliability with a gold wire.
However, due to the need for higher density of printed wiring boards, electrical noise problems, and the necessity of electrical inspection for short and open due to high integration of semiconductors, power supply bus lines for electrolytic nickel / gold plating have become available. They are getting in the way. In order to solve this problem, electroless nickel / gold plating has been studied and partly put into practical use. Nickel corrosion (generally called black nickel, corrosion caused by gold strike plating) and phosphorus component in nickel (during soldering) The problem of joint strength deterioration due to the formation of a high phosphorus concentration layer has been pointed out. Therefore, there is a need for a printed wiring board that is electrolytic nickel / gold plated and has no bus lines. Instead of eliminating the bus line, such a technique is that after forming the solder resist, electroless copper plating is performed on the entire surface, the electroless copper plating layer is removed only on the semiconductor mounting surface, and then the entire electroless copper plating layer on the solder ball mounting surface is removed. A current is passed through the semiconductor mounting surface through the conductive via, electrolytic nickel / gold plating is performed on the wire bond pad on the semiconductor mounting surface, and finally the electroless copper layer is removed by etching (see, for example, Patent Documents 1 and 2). .
Here, the bus line is a wiring in the work panel for supplying power necessary for electrolytic nickel / gold plating on a copper pad surface having a solder resist opened at a predetermined position of a printed wiring board. In other words, it is not necessary for the finished printed wiring board, but it is necessary to make the printed wiring board by electrolytic nickel / gold plating on the copper pad surface. It refers to the wiring in the printed wiring board work panel for electrical connection to the pad.
Further, the semiconductor mounting surface refers to a surface of a semiconductor package printed wiring board on which a semiconductor is mounted and the semiconductor is connected to the package printed wiring board. The solder ball mounting surface is a surface opposite to the semiconductor mounting surface and refers to a surface on which a solder ball connected to a printed wiring board (a main printed wiring board incorporated in an electronic / electric device called a mother board) is mounted.

JP 2001-110939 A JP 2001-110940 A

  Generally, in electroless copper plating, it is usual to put a step of attaching a palladium catalyst before the electroless copper plating step. This palladium cannot be removed in the subsequent electroless copper plating etching process, and remains on the solder resist surface and the substrate surface of the solder resist opening. The remaining palladium was dissolved in a cyan chemical solution used in the electrolytic nickel / gold plating process, and as a result, it was removed without causing a problem. However, although it can be removed in the electrolytic nickel / gold plating process, there is a problem of contaminating the plating solution of the process, and since the solder ball mounting surface is masked with an etching and plating resist during electrolytic nickel / gold plating, In the masking portion, palladium remains after the electroless copper etching, and the insulation reliability between the solder ball pads is insufficient. This invention makes it a subject to provide the manufacturing method of a printed wiring board without a bus line which solves these problems.

The inventor has found that the above problem can be improved by adding a step of removing palladium, and has completed the present invention.
That is, the present invention is conductive on the front and back by copper plated vias obtained by drilling and patterning a substrate material such as a copper clad laminate or a multilayer laminate by panel plating, pattern plating or the like. On the circuit board,
1) Solder resist pattern forming process 2) Solder resist surface roughening process 3) Palladium catalyst deposition process 4) Electroless copper plating process 5) Etching resist and plating resist process on solder ball mounting surface 6 ) Etching process of electroless copper plating of semiconductor mounting surface where etching resist / plating resist is not formed 7) Palladium removing process of semiconductor mounting surface where etching resist / plating resist is not formed 8) Etching resist / plating resist is formed Electrolytic nickel / gold plating process on copper part where solder resist is opened 9) Etching resist and plating resist removal process 10) Electroless copper plating etching process on solder ball mounting surface 11) Etching resist function Covered with plating resist It is a manufacturing method of a substrate for a semiconductor package having a pad that is electroless nickel-gold plating on a part of the semiconductor mounting surface, characterized in that performing have solder ball mounting surface of the palladium removal process.
Also,
12) A method for manufacturing a substrate for a semiconductor package, wherein a surface treatment step of a copper exposed portion is subsequently performed.
Further, the solder resist surface roughening step is a method for producing a substrate for a semiconductor package by at least one selected from permanganate solution treatment, chromate treatment, and physical treatment with fine particles.
Further, each of the palladium removal steps described above includes a nitric acid / chlorine ion / cationic polymer system, a nitrate / inorganic acid or salt thereof, a mercapto compound system, a nitrogen-containing aliphatic organic compound / iodine-containing inorganic compound system and a hydrochloric acid system removal solution. This is a method of manufacturing a semiconductor package substrate to be used.
Furthermore, the surface treatment process of the said copper exposed part is a manufacturing method of the board | substrate for semiconductor packages which is 1 type chosen from organic rust prevention processing, electroless gold plating, electroless tin plating, and solder processing.
Also,
13) In the step of 5) forming an etching resist / plating resist on the solder ball mounting surface, an opening is provided in a part of the etching resist / plating resist, and 7) mounting the semiconductor on which the etching resist / plating resist is not formed. Between the surface palladium removal step and 8) the partial electrolytic nickel / gold plating step,
7-2) A method for manufacturing a substrate for a semiconductor package, characterized by adding a step of forming a second plating resist in which the edge of the opening portion of the etching resist and plating resist covers from the side not closing the opening portion. .
Furthermore, the present invention is a semiconductor package substrate manufactured using the above manufacturing method, and a semiconductor package in which a semiconductor is mounted using the semiconductor package substrate.

  According to the present invention, it is possible to obtain a semiconductor package substrate having electrolytic nickel / gold plating without a bus line, ensuring insulation reliability and without contaminating the nickel / gold plating solution.

  The circuit board before the solder resist process used in the present invention is a substrate material such as a copper-clad laminate or a multilayer laminate, in which necessary conduction between the front and back is taken by a drilling process and then a copper pattern formation process. Yes, it is manufactured by the usual method. Examples of the drilling process include a method using a mechanical drill and a method using a laser, and copper pattern formation includes a subtractive method (panel plating / etching method), a pattern plating method (a method in which the basic copper is an ultrathin copper foil), semi An additive method (a method in which electroless copper is deposited on an insulating base material to form basic copper) is exemplified, but is not limited thereto. In these processes, processes such as cleaning, soft etching, desmear treatment, half etching, etching resist formation and plating resist formation are usually added. In the present invention, it is necessary that the pads on the semiconductor mounting surface that require electrolytic nickel / gold plating and the solder ball mounting surface be electrically connected via copper-plated vias (front and back conductive holes). The circuit board may be a double-sided board, or a multilayer board in which the front and back are electrically connected by a copper-plated through via or a copper-plated blind via and an inner via. Moreover, it is preferable to perform the adhesion provision process of a copper part as pre-processing of the process of the soldering resist after pattern formation. Usually, the process which roughens a copper surface is employ | adopted.

  1) In the present invention, the solder resist pattern forming step is carried out by applying a photocurable solder resist to a circuit board on which a copper pattern is formed, after applying and drying by a printing method, a roll coater method, etc. In the case of the shape, it is achieved by laminating or vacuum pressing, exposing the portion other than the portion where the solder resist is to be opened, developing, and then post-curing with heating or UV light. The solder resist also serves as a resist for electrolytic nickel / gold plating, plating in surface treatment, and processing. Examples of the solder resist include PSR-4000 (liquid) and PFR-800 (film) manufactured by Taiyo Ink Co., Ltd. These are composed of UV light curing and thermosetting resins.

2) The surface roughening step of the solder resist in the present invention is necessary for ensuring the adhesion of the electroless copper plating in the next step. For example, permanganese is formed on a circuit board on which a solder resist having an opening is formed. It is achieved by an acid solution treatment, a chromate treatment, a physical treatment with fine particles, or the like. As the physical treatment with fine particles, jet scrub treatment or sand blast treatment is preferable, and particles such as alumina are used.
If the roughening treatment is not performed, the electroless copper plating is peeled off, and not only the abnormality in ensuring the conductivity in the partially electrolytic nickel / gold plating but also a contaminant in the process becomes a problem.

3) The step of attaching the palladium-based catalyst in the present invention may be a treatment solution / step usually used as a pretreatment for electroless copper plating, and an ion type or colloid type chemical solution may be used. Examples include activator conch 834, activator neogant U (both manufactured by Atotech Co., Ltd.) and cataposit 44 (manufactured by Rohm and Haas Co., Ltd.), but are not particularly limited. Usually, palladium is deposited to 0.01-0.20mg / dm ² degrees. The thinner the load in the subsequent palladium removal step, the better, but such a thickness is preferred for reliable adhesion of electroless copper.

  4) The electroless copper plating in the present invention may be a commonly used chemical or process, and a Rochelle salt bath or a chelate bath can be used. Print Gantt P-DK (manufactured by Atotech Co., Ltd.) and Circvogit 4500 (manufactured by Rohm and Haas Co., Ltd.) are exemplified, but not particularly limited. Usually, electroless copper is deposited to about 0.5 to 1.5 μm. The thinner one may reduce the load in the subsequent etching process, but it is necessary to ensure electrical conduction for reliable adhesion of electrolytic nickel / gold plating, and such a thickness is preferable.

  5) The etching resist and plating resist in the present invention can be achieved by laminating a photosensitive dry film or coating a liquid photosensitive resist on a circuit board plated with electroless copper. In the present invention, the solder ball mounting surface is exposed and the semiconductor mounting surface is not exposed, thereby exposing the portion to be electrolytic nickel / gold plated. However, when a copper plating hole is used as the electric terminal portion, it is preferable to expose the copper plating hole portion so as to leave an etching resist and plating resist at both ends of the copper plating hole portion. This is not necessary when a planar electrode is used as the electrical terminal portion. Examples of the developer include an aqueous sodium carbonate solution, an aqueous potassium carbonate solution, and a tetramethylammonium hydroxide solution (EF-105A, manufactured by Mitsubishi Gas Chemical Company, Inc.).

  6) and 10) The etching of the electroless copper plating in the present invention ideally etches only the electroless copper plating layer deposited later without etching the copper pattern of the solder resist opening as much as possible. Half etching (also known as flash etching, quick etching). For this reason, hydrogen peroxide / sulfuric acid is preferably used as the etching solution. For example, SE-07 (Mitsubishi Gas Chemical Co., Ltd.), CPE-700 (Mitsubishi Gas Chemical Co., Ltd.) and CPE-810 (Mitsubishi Gas Chemical Co., Ltd.) are mentioned.

  7) and 11) In the palladium removal step of the present invention, the removal liquid is preferably a non-cyanic liquid or a non-chromic acid liquid from the viewpoint of safety / environment, nitric acid / chlorine ion / cationic polymer system, A nitrate / inorganic acid or a salt thereof, a mercapto compound, a nitrogen-containing aliphatic organic compound / iodine-containing inorganic compound, a hydrochloric acid, or the like can be used. For example, Melstrip PD-3310 (made by Meltex Co., Ltd.), Ebastrip SR-Pd (made by Sugawara Eugelite Co., Ltd.), Mekkuri Mover PJ-9710 (made by Mec Co., Ltd.), Top Lip PDJ-A (Okuno Pharmaceutical Co., Ltd.) Etc.) can be used. Examples of the treatment method include chemical solution immersion treatment and shower treatment. In order to prevent the line from being thinned by etching the patterned copper portion with the palladium removing solution, it is more preferable to use a palladium removing solution that hardly dissolves copper. By removing this palladium, insulation reliability can be ensured even with a narrow distance between conductors.

  8) The partially electrolytic nickel / gold plating in the present invention may be performed by a generally known method. For electrolytic nickel plating, a Watt bath, a sulfamic acid bath, or the like is used. In the electrolytic gold plating, soft gold is usually used because gold wire bonding is performed on the package substrate. In any case, a method of immersing and energizing is exemplified. The energization for the electrolytic nickel / gold plating is achieved by providing a terminal for electrical connection at the end of the work panel at the time of manufacture and energizing the terminal from the outside. The terminal is in a state where a solder resist or an etching resist / plating resist is opened. Copper plated through holes may be used as terminals. Conduction to the pads on the semiconductor mounting surface is achieved by connecting external electrodes to the terminals, passing through the copper part (ball pad part) where the electroless copper layer / solder resist attached to the entire solder ball surface is open, and the front and back conductive holes Done through.

  9) The removal of the etching resist and plating resist in the present invention is exemplified by immersion or showering with an alkaline solution such as caustic soda solution or tetramethylammonium hydroxide solution (R-101, manufactured by Mitsubishi Gas Chemical Co., Ltd.). The

  12) The surface treatment process in the present invention is performed on a ball pad, a flip chip pad, or an exposed copper part such as various mark parts, and no treatment (solid copper) or organic rust inhibitor treatment (for example, 0) There are electroless gold plating treatment, electroless tin plating treatment, soldering treatment, etc. (by thickness of 2 μm, immersion treatment, etc.), which are selected depending on the rust prevention effect, solder connection reliability, connection method, etc.

Also, between 7) palladium removal step and 8) partial electrolytic nickel and gold plating step,
7-2) Adding a step of forming a plating resist that covers the edge portion of the opening of the etching resist / plating resist on the solder ball mounting surface can correspond to the following cases.
If there is a portion to be plated with electrolytic nickel / gold on the solder ball mounting surface, a plating lead is required locally, but an opening is provided in the etching resist / plating resist. The size of the opening is larger than the opening of the solder resist. However, in this state, electrolytic nickel / gold plating adheres to the periphery of the opening of the etching resist and plating resist, so after removing the electroless copper plating and palladium, the second plating resist is attached to the periphery of the opening of the first plating resist. Arrange to cover. As a portion to be electrolytic nickel / gold plated, there is a mark for cutting an individual piece. This mark has a very small area, and when only this portion is later plated with electrolytic nickel / gold, it is difficult to adjust the plating thickness.

  As described above in detail, according to the present invention, insulation reliability can be ensured, and the substrate for a semiconductor package can be provided with electrolytic nickel / gold plating without a bus line without contaminating the nickel / gold plating solution. .

A double-sided copper-clad laminate (manufactured by Mitsubishi Gas Chemical Co., Ltd., CCL-HL832HS, 0.1 mmt, copper foil 12 μm) is prepared as a copper-clad laminate, and a half-etching solution SE is formed after drilling a CO ₂ laser through hole (100 μmφ). -07 (Mitsubishi Gas Chemical Co., Ltd.) etched copper foil to 5 μm, desmeared with alkali swelling treatment liquid and permanganate treatment liquid, and used activator Neogant U (Atotech Co., Ltd.) on the entire surface. The palladium catalyst was attached (0.1 mg / dm ² ), and electroless copper plating (1 μm thickness) was performed on the entire surface including the inside of the hole using a print Gantt P-DK (manufactured by Atotech Co., Ltd.). (15 μm thick) Panel plating was used. Thereafter, a dry film was laminated, exposed using a pattern mask film, developed and etched with a copper chloride solution, the dry film was peeled off with a caustic soda solution, and the steps up to patterning were completed.
After that, pattern copper is subjected to surface unevenness treatment with etch bond CZ-8100 (made by MEC Co., Ltd.), PSR-4000AUS308 (made by Taiyo Ink Co., Ltd.) is roll coated and dried (20 μt thickness after drying), and then the pattern mask is used. And then developing (sodium carbonate aqueous solution) to form a solder resist layer having an opening. Thereafter, jet scrub (Permis # 240, 60 seconds) is applied to roughen the surface of the solder resist, and a palladium catalyst is adhered to the entire surface with activator Neogant U (manufactured by Atotech Co., Ltd.) (0.1 mg / dm2). Electroless copper plating (1 μm thickness) was applied to the entire surface by P-DK (manufactured by Atotech Co., Ltd.). Thereafter, the dry film is laminated, exposed and developed to remove the dry film on the semiconductor mounting surface other than the electric terminal portion, and one solder ball surface leaves the entire surface dry film, and then CPE-810 (Mitsubishi Gas). The electroless copper plating layer on the semiconductor mounting surface was etched by Chemical Co., Ltd. Furthermore, the palladium removal process of the same part was performed by Mekku remover PJ-9710 (made by MEC Co., Ltd.). Thereafter, electrolytic nickel / gold plating was applied to the wire bond pad on the semiconductor mounting surface. This electrolytic plating power is supplied from the outside to the terminal portion provided at the end of the work panel, and from the terminal portion to the semiconductor mounting surface through the electroless copper layer on the non-semiconductor mounting surface, and further through the front and back conduction holes. Power is supplied to the pad to be electroplated through. Then, after all the dry films were peeled off with a caustic soda solution, the electroless copper layer was etched again with CPE-810, and further, a palladium removal treatment was carried out with Mekkeli Mover PJ-9710. Thereafter, electroless displacement gold plating was performed using IM-GOLD PC (manufactured by Nippon Kogyo Kagaku Co., Ltd.), which is a cyan gold potassium solution, and the ball pad surface treatment of the solder ball surface was performed. Note that a comb pattern for evaluation was placed on the solder ball surface in the work panel, and the solder resist was not covered on that portion.
The results of analyzing and evaluating the printed wiring board prepared as described above were below.
(1) Precipitation evaluation of electroless nickel plating:
The amount of remaining palladium is difficult to analyze because of the trace amount, and as a method for confirming the remaining palladium, a method of applying electroless nickel plating was adopted.
Although the electroless nickel plating process was passed, no nickel deposition other than the metal surface was observed at all locations such as the solder resist surface and the solder resist opening.
(2) Line-to-line insulation evaluation of solder resist opening part Evaluation of moisture absorption insulation under charge using a comb-shaped pattern part of line / space = 40/40 μm where the opening edge part of solder resist is in the center (evaluation process) (Condition: HAST / 110 ° C. × 85% RH × 264 hours electrical insulation resistance measurement before and after treatment), before treatment / 2 × 10 ¹² Ω, after treatment / 3 × 10 ¹¹ Ω 5 × 10 ⁸ Ω or more, good.

Comparative example

The same procedure as in Example was performed except that the palladium removal step was not passed (both twice).
As a result of analyzing and evaluating the produced printed wiring board, it was below.
(1) Precipitation evaluation of electroless nickel plating:
Through the electroless nickel plating step, nickel deposition was observed on the solder resist surfaces of the component mounting surface and the solder ball surface except for the metal surface.
(2) Line-to-line insulation evaluation of solder resist opening part Evaluation of moisture absorption insulation under charge using a comb-shaped pattern part of line / space = 40/40 μm where the opening edge part of solder resist is in the center (evaluation process) Condition: HAST / 110 ° C. × 85% RH × 264 hours electrical insulation resistance measurement before and after treatment), before treatment / 2 × 10 ¹² Ω, after treatment / 3 × 10 ⁶ Ω 5 × 10 ^{It is 8} Ω or less, which is bad.

Copper clad laminate Drilling + desmearing + half-etch Step of attaching a palladium catalyst Electroless copper plating treatment Panel plating treatment Lamination exposure and development of plating resist Etching process Process for removing plating resist Solder resist pattern formation process Surface roughening process of solder resist Step of attaching a palladium catalyst Electroless copper plating process Lamination exposure process of plating resist Etching resist and plating resist removal process (semiconductor mounting surface) Etching process for electroless copper plating on semiconductor mounting surface (Pd remains as electroless copper plating catalyst) Palladium removal process (semiconductor mounting surface) Partially electrolytic nickel and gold plating process Etching resist and plating resist removal process (solder ball mounting surface) Etching process of electroless copper plating on solder ball mounting surface (Pd as electroless copper plating catalyst remains) Palladium removal process (solder ball mounting surface) Surface treatment process (organic rust prevention treatment)

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Base material 2 Copper foil 3 Palladium 4 Electroless copper plating 5 Via hole 6 Electrical terminal hole 7 Conductor circuit 8 Solder resist 9 Jet scrub process 10 Plating resist 11 Electrolytic nickel 12 Electrolytic gold 13 Organic rust prevention film 14 Wire bond pad 15 Solder Ball pad

Claims (8)

On the circuit board that is conductive on both sides by copper plated vias,
1) Solder resist pattern forming process 2) Solder resist surface roughening process 3) Palladium catalyst deposition process 4) Electroless copper plating process 5) Etching resist and plating resist process on solder ball mounting surface 6 ) Etching process of electroless copper plating of semiconductor mounting surface where etching resist / plating resist is not formed 7) Palladium removing process of semiconductor mounting surface where etching resist / plating resist is not formed 8) Etching resist / plating resist is formed Electrolytic nickel / gold plating process on copper part where solder resist is opened 9) Etching resist and plating resist removal process 10) Electroless copper plating etching process on solder ball mounting surface 11) Etching resist function Covered with plating resist Preparation of a substrate for a semiconductor package having a pad that is electroless nickel-gold plating on a part of the semiconductor mounting surface and performs have solder ball mounting surface of the palladium removal process. Following the palladium removal step of the solder ball mounting surface that was covered with the etching resist and plating resist,
12) The method for producing a substrate for a semiconductor package according to claim 1, wherein a surface treatment step of the exposed copper portion is performed. 2. The manufacturing method of a substrate for a semiconductor package according to claim 1, wherein the surface roughening step of the solder resist is one or more selected from a permanganate solution treatment, a chromate treatment, and a physical treatment with fine particles. Law. The step of removing palladium on the semiconductor mounting surface on which the etching resist / plating resist is not formed and the step of removing palladium on the solder ball mounting surface covered with the etching resist / plating resist include nitric acid / chloride ion / cationic polymer system, nitrate 2. A semiconductor package according to claim 1, wherein at least one type of removal liquid selected from inorganic acids or salts thereof, mercapto compound systems, nitrogen-containing aliphatic organic compounds, iodine-containing inorganic compound systems and hydrochloric acid systems is used. Substrate manufacturing method 3. The method for manufacturing a substrate for a semiconductor package according to claim 2, wherein the surface treatment step of the exposed copper portion is one selected from organic rust prevention treatment, electroless gold plating, electroless tin plating, and solder treatment. In the step of forming an etching resist / plating resist on the solder ball mounting surface, an opening is provided in a part of the etching resist / plating resist, and the palladium removing step of the semiconductor mounting surface on which the etching resist / plating resist is not formed During the partial electrolytic nickel / gold plating process,
7-2) The substrate for a semiconductor package according to claim 1, wherein a step of forming a second plating resist in which the edge of the opening portion of the etching resist and plating resist covers from the side not closing the opening portion is added. Manufacturing method. A semiconductor package substrate manufactured by the manufacturing method according to claim 1. A semiconductor package in which a semiconductor is mounted on the semiconductor package substrate according to claim 7.

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