JP2009133746A - Waveform generator and semiconductor tester - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the throughput of test time for a test sample, and prevent the number of input trigger signals from being increased. <P>SOLUTION: A waveform generator 11 comprises: an output section 24 for outputting a plurality of arbitrary waveforms for testing the test sample 15; a storage section 23 having a plurality of memory areas 23A-23D for storing arbitrary waveform data, and storing the arbitrary waveforms in the memory areas in the order of outputting the arbitrary waveforms to the test sample 15; an address counter 22 for inputting the trigger signal indicating timing when the arbitrary waveform is generated, counting and outputting an address associated with the memory area every time the trigger signal is inputted; and a CPU 21 for referring to the memory address corresponding to the address output from the address counter 22, reading the arbitrary waveform data stored in the referred memory area, and outputting the arbitrary waveform from the output section 24 based on the read arbitrary waveform data. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a waveform generator and a semiconductor test apparatus.

  Conventionally, a waveform generator that generates an arbitrary waveform by a trigger signal is known.

  With reference to FIG. 9, a schematic configuration of a conventional waveform generator 101 will be described. The waveform generator 101 is provided in the semiconductor test apparatus 100.

  The waveform generator 101 generates a test waveform (arbitrary waveform) by an external trigger (trigger signal), and outputs the generated arbitrary waveform to a device under test DUT (Device Under Test) 105. The trigger signal includes a pattern synchronization signal from the digital pin module 102, an acquisition start / end signal from the digitizer 103, a status signal from the device under test 105, a signal from the handler / prober 104, a signal from other measuring device 106, and the like. It corresponds to.

  Next, the internal configuration of the waveform generator 101 will be described with reference to FIG. The waveform generation device 101 includes a CPU (Central Processing Unit) 110, a storage unit 111, and an output unit 112.

  The CPU 110 controls each part of the waveform generator 101. Specifically, when a trigger signal is input, the CPU 110 reads arbitrary waveform data assigned to the input trigger signal from the storage unit 111, and outputs based on the read arbitrary waveform data. The unit 112 is caused to output an arbitrary waveform.

  The storage unit 111 is configured by a RAM (Random Access Memory), and has a work area (memory area) that stores various programs to be executed and data related to these various programs. Specifically, the storage unit 111 stores arbitrary waveform data in each of a plurality of memory areas.

  The output unit 112 outputs an arbitrary waveform to the device under test 105 in accordance with an instruction from the CPU 110.

  Next, an operation for outputting an arbitrary waveform assigned to the trigger signal will be described with reference to FIG. FIG. 11 is a diagram showing that waveforms (arbitrary waveforms) A, B, C, and D are defined (assigned) for Triggers 1 to 4 (trigger signals 1 to 4). In this case, when the trigger signals 1 to 4 are input to the waveform generator 101, the arbitrary waveforms A to D are generated according to the allocation of the arbitrary waveform to the trigger signal. For example, when the trigger signal 1 is input, the arbitrary waveform data A is read from the storage unit 111. Based on the read arbitrary waveform data A, the output unit 112 outputs the arbitrary waveform A to the device under test 105. The same operation is performed when the trigger signals 2 to 4 are input.

There is also known a waveform generator provided with means capable of simultaneously changing frequency and phase data at high speed from the outside and both data (for example, see Patent Document 1).
JP-A-8-330914

  Since the DUT 105 described above has a complicated function, there are a wide variety of arbitrary waveforms required for the test. For example, assume that there are 100 types of waveforms (arbitrary waveforms) as shown in FIG. In this case, if each arbitrary waveform is assigned to a trigger signal, as many as 100 trigger signals need to be input. For this reason, the number of wirings and input / output terminals (IO) for inputting a large number of trigger signals is enormous. In addition, the cost increases as the number of parts (the number of wirings and IOs) increases.

  In order to prevent an increase in the number of input trigger signals, there is known a technique for rewriting the definition (assignment) of an arbitrary waveform for the trigger signal during the test. For example, as shown in FIG. 13, Trigger 1 (trigger signal 1) is assigned to waveform (arbitrary waveform) A at the start of the test. Thereafter, the arbitrary waveform A is rewritten to the arbitrary waveform E, and the trigger signal 1 is assigned to the arbitrary waveform E. Thereafter, the arbitrary waveform E is rewritten to the arbitrary waveform F, and the trigger signal 1 is assigned to the arbitrary waveform F. Thereby, since a plurality of arbitrary waveforms can be assigned to one trigger signal, the number of input trigger signals can be prevented from becoming enormous.

  However, the rewriting of the definition of the arbitrary waveform during the test has caused the throughput of the test time of the device under test 105 (device under test) to deteriorate. In other words, the rewriting time of the definition of the arbitrary waveform has become a factor of increasing the test time (deteriorating the throughput of the test time).

  An object of the present invention is to improve the test time throughput of the DUT and to prevent an increase in the number of trigger signals input.

In order to solve the above problem, the waveform generator of the invention according to claim 1 comprises
In the waveform generator having output means for outputting a plurality of test waveforms for testing the DUT,
A plurality of memory areas for storing each test waveform data; and storage means for storing each test waveform data in each memory area in order of outputting each test waveform to the DUT;
A trigger signal indicating a timing for generating the test waveform is input, and an address counter that counts and outputs an address associated with each memory area each time the trigger signal is input;
The output means refers to the memory area corresponding to the address output by the address counter, reads the test waveform data stored in the referenced memory area, and based on the read test waveform data, the output means Control means for outputting a test waveform from
Is provided.

The invention according to claim 2 is the waveform generator according to claim 1,
In the case where there are a plurality of the trigger signals, a selection means for selecting one trigger signal from the plurality of trigger signals,
The address counter
The trigger signal selected by the selection means is input.

The waveform generator of the invention described in claim 3 is:
In the waveform generator having output means for outputting a plurality of test waveforms for testing the DUT,
A plurality of memory areas for storing each test waveform data, and storage means for storing the respective test waveform data of different waveforms in the respective memory areas;
An input means for inputting a trigger signal for generating the test waveform and a count signal instructing counting of an address associated with the memory area;
When the trigger signal and the count signal are input to the input means, the address is counted and output.When the count signal is not input to the input means and only the trigger signal is input, An address counter that outputs without counting addresses,
The output means refers to the memory area corresponding to the address output by the address counter, reads the test waveform data stored in the referenced memory area, and based on the read test waveform data, the output means Control means for outputting a test waveform from
Is provided.

The invention according to claim 4 is the waveform generator according to claim 3,
In the case where there are a plurality of the trigger signals, a selection means for selecting one trigger signal from the plurality of trigger signals,
The input means includes
The trigger signal selected by the selection means is input.

A semiconductor test apparatus according to a fifth aspect of the present invention comprises:
A waveform generator according to any one of claims 1 to 4 is provided.

  According to the first aspect of the present invention, the address counter counts and outputs the address of the memory area every time the trigger signal is input. Further, the control means refers to the memory area corresponding to the address output by the address counter, reads the test waveform data stored in the referenced memory area, and based on the read test waveform data, A test waveform is output by the output means. As a result, each time a trigger signal is input, test waveforms are output in the order in which the DUT is tested, so the test waveform definition can be rewritten during the test of the DUT even when there are many test waveforms. There is no need to perform this, and the throughput of the test time of the DUT can be improved.

  According to the second and fourth aspects of the invention, one trigger signal selected by the selection means is input to the address counter. As a result, even when a plurality of test waveforms are required for the test of the device under test, the device under test can be tested with only one trigger signal selected by the selection means without inputting a plurality of trigger signals. Since this can be realized, an increase in the number of trigger signal inputs can be prevented. Therefore, it is not necessary to prepare wiring and the number of IOs for connecting a plurality of trigger signals. Moreover, since it is not necessary to increase the number of parts, it is possible to prevent an increase in cost.

  According to the invention described in claim 3, when the trigger signal and the count signal are input to the input means, the address counter counts and outputs the address of the memory area, and only the trigger signal is input to the input means. If it does, the address is output without counting. Further, the control means refers to the memory area corresponding to the address output by the address counter, reads the test waveform data stored in the referenced memory area, and based on the read test waveform data The test means outputs the test waveform. As a result, when a trigger signal and a count signal are input to the input means, a test waveform having a different waveform is output. Therefore, a memory area for storing a test waveform having a different waveform is secured in the storage means. do it. That is, consumption of the storage amount of the storage means can be prevented. Further, even if there are various test waveforms, it is not necessary to rewrite the definition of the test waveform during the test of the DUT, and the throughput of the test time of the DUT can be improved.

  According to the fifth aspect of the present invention, it is possible to provide a semiconductor test apparatus equipped with a waveform generator.

  Embodiments according to the present invention will be described below in detail with reference to the accompanying drawings. However, the scope of the invention is not limited to the illustrated examples.

(First embodiment)
A first embodiment according to the present invention will be described with reference to FIGS. First, the configuration of the waveform generator 11 of the present embodiment will be described with reference to FIG. The waveform generator 11 is provided in the semiconductor test apparatus 10.

  Specifically, the waveform generator 11 generates a test waveform (arbitrary waveform) by an external trigger (trigger signal), and outputs the generated arbitrary waveform to the device under test 15. The trigger signal is a signal indicating the timing for generating an arbitrary waveform. Specifically, the trigger signal includes a pattern synchronization signal from the digital pin module 12, a capture start / end signal from the digitizer 13, a status signal from the object 15 to be measured as a test object, and a signal from the handler prober 14. This corresponds to the signal from the other measuring device 16. In addition, generating an arbitrary waveform using a trigger signal is defined (assigned) to each trigger signal in advance and defined for the input trigger signal when the trigger signal is input. Reading arbitrary waveform data from the storage unit 23. The arbitrary waveform refers to a waveform for testing the DUT 15. The arbitrary waveform corresponds to, for example, a sine wave, a DC (direct current) wave, or the like.

  Next, the internal configuration of the waveform generator 11 will be described with reference to FIG. As shown in FIG. 2, the waveform generator 11 includes a CPU 21 as a control unit, an address counter 22, a storage unit 23 as a storage unit, and an output unit 24.

  The CPU 21 controls each part of the waveform generator 11. Specifically, the CPU 21 refers to the memory area of the storage unit 23 corresponding to the address output by the address counter 22, reads the test waveform (arbitrary waveform) data stored in the referenced memory area, Based on the read arbitrary waveform data, an arbitrary waveform is output from the output unit 24. The address refers to information for identifying each memory area, and is associated with each memory area.

The address counter 22 receives a trigger (trigger signal), counts the address associated with each memory area of the storage unit 23 and outputs it to the CPU 21 each time the trigger signal is input.
The trigger signal input to the address counter 22 is the trigger signal selected by a selection unit (not shown) as selection means. Here, the selection unit is configured by an OR circuit, for example. Specifically, the selection unit includes a plurality of trigger signals input from external devices (digital pin module 12, digitizer 13, handler / prober 104, device under test 105, and other measuring devices 106). Select one trigger signal. Then, the selected trigger signal is output to the address counter 22.

  The storage unit 23 includes a RAM, and has a work area (memory area) that stores various programs to be executed and data related to these various programs. Specifically, the storage unit 23 has a plurality of memory areas for storing the arbitrary waveform data, and stores the arbitrary waveform data in the respective memory areas in the order of outputting the arbitrary waveform data to the device under test 15.

  The output unit 24 outputs a plurality of arbitrary waveforms (eg, sine waves, DC waves, etc.) to the device under test 15 in accordance with instructions from the CPU 21. For example, when the output order of the arbitrary waveform is determined in advance in the order of the sine wave and the DC wave, the output unit 24 outputs the arbitrary waveform in the order of the sine wave and the DC wave.

  Next, the operation of the waveform generator 11 will be described with reference to FIG. FIG. 3 is a diagram showing that waveform (arbitrary waveform) data A to D are stored in the memory areas 23A to 23D of the storage unit 23, respectively. In a normal test, the order in which the DUT 15 is tested (the order in which an arbitrary waveform is output) is determined in advance. As a result, the arbitrary waveform data is stored in each memory area of the storage unit 23 in the order of outputting the arbitrary waveform. For example, when the order of outputting arbitrary waveforms is the order of arbitrary waveforms A, B, C, and D, the arbitrary waveforms A, B, C, and D are arbitrarily assigned to the memory areas 23A to 23D in the storage unit 23, respectively. Waveform data is stored.

  Hereinafter, the operation of the waveform generator 11 under the conditions of FIG. 3 will be described. Here, it is assumed that addresses “100” to “103” are associated with the memory areas 23A to 23D, respectively. The address counter 22 counts up the addresses of the memory areas 23A to 23D every time the trigger signal 1 is input. Also, assume that the test is started by assigning the first trigger signal 1 at the start of the test to the arbitrary waveform data A stored in the memory area 23A (for example, when the first trigger signal 1 at the start of the test is input, The address counter 22 outputs the address “100 address” of the memory area 23A).

  First, the trigger signal 1 is input to the address counter 22. When the trigger signal 1 is input, the address “100 address” is counted by the address counter 22, and the address “100 address” is output to the CPU 21 via the storage unit 23. Then, the CPU 21 refers to the memory area 23 </ b> A of the storage unit 23 corresponding to the address “100 address”. Then, the arbitrary waveform data A stored in the referenced memory area 23A is read out. Based on the read arbitrary waveform data A, the output unit 24 outputs the arbitrary waveform A to the device under test 15. At this time, the arbitrary waveform A is output and at the same time, the address counter 22 counts up the address from “100 address” to “101 address”.

  Then, the next trigger signal 1 is input to the address counter 22. Here, the address is counted up to “address 101” by the previous trigger signal 1. For this reason, when the next trigger signal 1 is input, the address “101” is output from the address counter 22 to the CPU 21 via the storage unit 23. Then, the CPU 21 refers to the memory area 23B corresponding to the address “address 101”. Then, the arbitrary waveform data B stored in the referenced memory area 23B is read out. Based on the read arbitrary waveform data B, the output unit 24 outputs the arbitrary waveform B to the device under test 15. At this time, the arbitrary waveform B is output, and at the same time, the address is counted up to “address 102” by the address counter 22. Thereafter, the same operation is performed.

  With the above operation, for example, as shown in FIG. 4, it is possible to output an arbitrary waveform by inputting only one trigger signal 1 even when a test is performed using various arbitrary waveforms A to X. It becomes.

  As described above, according to the present embodiment, the address counter 22 counts and outputs the address of the memory area every time the trigger signal 1 is input. Further, the CPU 21 refers to the memory area corresponding to the address output by the address counter 22, reads the arbitrary waveform data stored in the referenced memory area, and based on the read test waveform data, A test waveform is output from the output unit 24. Thus, each time a trigger signal is input, an arbitrary waveform is output in the order in which the device under test 15 is tested. Therefore, even when there are various types of arbitrary waveforms, the definition of the arbitrary waveform is determined during the test of the device under test 15. There is no need to rewrite, and the throughput of the test time of the DUT 15 can be improved.

  One trigger signal selected by the selection unit is input to the address counter 22. As a result, even when a plurality of test waveforms are required for the test of the object to be measured 15, only one trigger signal selected by the selection unit is input without inputting a plurality of trigger signals to the storage unit 23. Since the test of the measurement object 15 can be realized, an increase in the number of input trigger signals can be prevented. Therefore, it is not necessary to prepare wiring and the number of IOs for connecting a plurality of trigger signals. Moreover, since it is not necessary to increase the number of parts, it is possible to prevent an increase in cost.

  Moreover, the semiconductor test apparatus 10 provided with the waveform generator 11 can be provided.

(Second Embodiment)
A second embodiment according to the present invention will be described with reference to FIGS. FIG. 5 shows the configuration of a waveform generator 11A according to the present invention. Hereafter, the same code | symbol is attached | subjected to the part similar to the waveform generator 11, and the detailed description is used and a different part is demonstrated. In addition, the waveform generator 11 </ b> A is provided in the semiconductor test apparatus 10 similarly to the waveform generator 11.

  The waveform generator 11A includes a CPU 31 as a control unit, an address counter 32, a storage unit 33, an output unit 24 as an output unit, and an AND circuit 34 as an input unit.

  The CPU 31 refers to the memory area corresponding to the address output by the address counter 32, reads the test waveform (arbitrary waveform) data stored in the referenced memory area, and based on the read arbitrary waveform data Then, an arbitrary waveform is output from the output unit 24.

  The address counter 32 counts and outputs an address when a trigger signal and a next signal as a count signal are input to the AND circuit 34, and only the trigger signal is input to the AND circuit 34 without inputting the next signal. If it is, the address is output without counting. Here, the next signal refers to a signal instructing counting of addresses in the memory area in the storage unit 33.

  Specifically, when an instruction signal for counting up an address is input from the AND circuit 34, the address counter 32 counts up the address and outputs the counted up address to the CPU 31 via the storage unit 33. Further, when an instruction signal that does not count up the address value is input from the AND circuit 34, the address counter 32 does not count up the address, and outputs an address that has not been counted up to the CPU 31 via the storage unit 33.

  The storage unit 33 is configured by a RAM. The storage unit 33 has a plurality of memory areas for storing arbitrary waveforms, and stores arbitrary waveform data having different waveforms in each memory area.

  The AND circuit 34 receives only the trigger signal and the next signal or the trigger signal. The next signal is input to the AND circuit 34 together with the trigger signal when an arbitrary waveform having a waveform different from the arbitrary waveform output to the DUT 15 is output at the previous time of the test. For example, when a sine wave is output to the DUT 15 at the previous time of the test and a DC wave is output to the DUT 15 at the current test, the next signal and the trigger signal are input to the AND circuit 34. On the other hand, when the sine wave is output to the device under test 15 at the previous time of the test and the sine wave is output to the device under test 15 even during the current test, only the trigger signal is input to the AND circuit 34.

  Specifically, the AND circuit 34 outputs an instruction signal for counting up the address value to the address counter 32 when the trigger signal and the next signal are input. The AND circuit 34 outputs an instruction signal that does not increment the address value to the address counter 32 when only the trigger signal is input without the next signal being input.

  The trigger signal input to the AND circuit 34 is the trigger signal selected by the selection unit (not shown). Here, the selection unit is configured by an OR circuit, for example. Specifically, the selection unit includes a plurality of trigger signals input from external devices (digital pin module 12, digitizer 13, handler / prober 104, device under test 105, and other measuring devices 106). Select one trigger signal. Then, the selected trigger signal is output to the AND circuit 34.

  Next, the operation of the waveform generator 11A will be described with reference to FIGS. FIG. 6 is a diagram illustrating that arbitrary waveform data A to D are stored in the memory areas 33A to 33D of the storage unit 33, respectively. FIG. 7 is a diagram showing the relationship between the order of outputting waveforms (arbitrary waveforms) and trigger signals.

  The waveforms (arbitrary waveforms) A to D shown in FIG. 6 have different waveforms. For example, the arbitrary waveform data A is a 1 KHz sine wave, the arbitrary waveform data B is a 10 KHz sine wave, the arbitrary waveform data C is a DC wave, and the arbitrary waveform data D is a ramp wave, each having a different waveform. The arbitrary waveform data A to D are stored in the memory areas 33A to 33D in the storage unit 33, respectively.

  In a normal test, the order in which arbitrary waveforms are output is determined in advance. For example, as shown in FIG. 7, the order of outputting arbitrary waveforms is set in advance in the order of arbitrary waveform A → arbitrary waveform A → arbitrary waveform B → arbitrary waveform C → arbitrary waveform C → arbitrary waveform C → arbitrary waveform C. Yes.

  The operation of the waveform generator 11A under the conditions of FIGS. 6 and 7 (new method-2) will be described below. Here, it is assumed that addresses “100” to “103” are associated with the memory areas 33A to 33D, respectively. The address counter 32 counts up the addresses of the memory areas 33A to 33D every time the trigger signal 1 is input. Also, it is assumed that the test is started by assigning the first trigger signal 1 at the start of the test to the arbitrary waveform A stored in the memory area 33A (for example, when the first trigger signal 1 at the start of the test is input, the address The counter 32 outputs the address “100 address” of the memory area 33A).

  First, Trigger 1 (trigger signal 1) is input to the AND circuit 34 (corresponding to (1) of the new method-2 in FIG. 7). In this case, the address “100 address” is counted by the address counter 32, and the address “100 address” is output to the CPU 31 via the storage unit 33. Then, the CPU 31 refers to the memory area 33 </ b> A of the storage unit 33 corresponding to the address “100 address”. Then, the arbitrary waveform data A stored in the referenced memory area 33A is read out. Based on the read arbitrary waveform data A, the output unit 24 outputs the arbitrary waveform A to the device under test 15. Here, only the trigger signal 1 is input to the AND circuit 34. For this reason, the address counter 32 does not count up the address.

  Then, the Trigger 1 + next (trigger signal 1 and next signal) signal is input to the AND circuit 34 (corresponding to (2) of the new method-2 in FIG. 7). Here, the address is not counted up by the previous trigger signal 1 (the signal input in (1) of the new system-2 in FIG. 7). For this reason, when the trigger signal 1 and the next signal are input to the AND circuit 34, the address “100” is output to the CPU 31 by the address counter 32 via the storage unit 33. Then, the CPU 31 refers to the memory area 33 </ b> A corresponding to the address “100 address”. Then, the arbitrary waveform data A stored in the referenced memory area 33A is read out. Based on the read arbitrary waveform data A, the output unit 24 outputs the arbitrary waveform A to the device under test 15. Since the trigger signal 1 and the next signal are input to the AND circuit 34, the arbitrary waveform A is output, and at the same time, the address is counted up from "100 address" to "101 address" by the address counter 32.

  Then, the trigger signal 1 and the next signal are input to the AND circuit 34 (corresponding to (3) of the new method-2 in FIG. 7). At this time, the address is counted up by the previous trigger signal 1 and the next signal (the signal input in (2) of the new method-2 in FIG. 7). For this reason, when the trigger signal 1 and the next signal are input to the AND circuit 34, the address “address 101” is output to the CPU 31 by the address counter 32 via the storage unit 33. Then, the CPU 31 refers to the memory area 33B corresponding to the address “101 address”. Then, the arbitrary waveform data B stored in the referenced memory area 33B is read out. Based on the read arbitrary waveform data B, the arbitrary waveform A is output from the output unit 24 to the device under test 15. In addition, since the trigger signal 1 and the next signal are input to the AND circuit 34, the arbitrary waveform B is output, and at the same time, the address is counted up from “101” to “102” by the address counter 32.

  Then, the trigger signal 1 is input to the AND circuit 34 (corresponding to (4) of the new method-2 in FIG. 7). At this time, the address is counted up by the previous trigger signal 1 and the next signal (the signal input in (3) of the new method-2 in FIG. 7). Therefore, when the trigger signal 1 is input to the AND circuit 34, the address “102” is output from the address counter 32 to the CPU 31 via the storage unit 33. Then, the CPU 31 refers to the memory area 33C corresponding to the address “address 102”. Then, the arbitrary waveform data C stored in the referenced memory area 33C is read out. Based on the read arbitrary waveform data C, the arbitrary waveform C is output from the output unit 24 to the device under test 15. Here, only the trigger signal 1 is input to the AND circuit 34. For this reason, the address counter 32 does not count up the address. Thereafter, the same operation is performed in (5) to (7) of the new method-2 in FIG.

FIG. 7 shows the relationship between the output order of arbitrary waveforms in the new method-2 (this embodiment) and the trigger signal, and the output order of arbitrary waveforms in the conventional method (conventional waveform generator 101) The relation between the trigger signal and the relation between the trigger signal and the output order of the arbitrary waveform in the new method-1 (the waveform generator 11 of the first embodiment according to the present invention) is also shown.
As shown in FIG. 7, in the conventional method, if the definition of an arbitrary waveform is not rewritten, three types of arbitrary waveforms are output. For this reason, the conventional method requires three trigger signals. On the other hand, in the new method-1 and the new method-2, only one trigger signal (trigger signal 1) is required.

  FIG. 8 shows a memory area of the storage unit in each method when the arbitrary waveform in FIG. 7 is output. As shown in FIG. 8, arbitrary waveform data A, B, and C are stored in arbitrary three areas of the memory area in the conventional method. Further, the new method-1 requires a repetition of the arbitrary waveform A and a repetition of the arbitrary waveform C (total of 7 areas), and requires a larger memory area than the conventional method.

  In the new method-2, it is not necessary to store the same arbitrary waveform a plurality of times by inputting the next signal. Therefore, in the new method-2, arbitrary waveform data A, B, and C may be stored in three areas of the memory area. At this time, the arbitrary waveform data A, B, and C are packed and stored. Therefore, in the present embodiment (new method-2), the waveform can be defined without degrading the consumption amount of the memory area.

  As described above, according to the present embodiment, when the trigger signal and the count signal are input to the AND circuit 34, the address counter 32 counts and outputs the address of the memory area, and the count signal is input to the AND circuit 34. If only the trigger signal is input, the address is not counted and output. Further, the CPU 31 refers to the memory area corresponding to the address output by the address counter 32, reads the arbitrary waveform data stored in the referenced memory area, and based on the read arbitrary waveform data. The arbitrary waveform A is output from the output unit 24. Thereby, when a trigger signal and a count signal are input to the input means, an arbitrary waveform having a different waveform is output. Therefore, the storage unit 33 has a memory area for storing arbitrary waveform data having a different waveform. Should be secured. That is, consumption of the storage amount of the storage unit 33 can be prevented. Further, even when there are various arbitrary waveforms, it is not necessary to rewrite the definition of the arbitrary waveform during the test of the device under test 15, and the throughput of the test time of the device under test 15 can be improved.

  One trigger signal selected by the selection unit is input to the AND circuit 34. Thus, even when a plurality of test waveforms are required for the test of the object 15 to be measured, only one trigger signal selected by the selection unit is input without inputting a plurality of trigger signals to the storage unit 33. Since the test of the measurement object 15 can be realized, an increase in the number of input trigger signals can be prevented. Therefore, it is not necessary to prepare wiring and the number of IOs for connecting a plurality of trigger signals. Moreover, since it is not necessary to increase the number of parts, it is possible to prevent an increase in cost.

  Moreover, the semiconductor test apparatus 10 provided with the waveform generator 11A can be provided.

  The descriptions in the first embodiment and the second embodiment are examples of the signal waveform generator and the semiconductor test apparatus according to the present invention, and the present invention is not limited thereto.

  For example, in the first and second embodiments, the address counters 22 and 32 have been described as counting up addresses, but the present invention is not limited to this. For example, the address may be counted down.

In the second embodiment, the waveform generator 11A includes the AND circuit 34. However, the configuration is not limited to this. For example, it may be configured to count up (or count down) the address when the next signal is input.

In the first embodiment and the second embodiment, the selection unit (not shown) is an OR circuit, but is not limited to this. For example, any configuration may be used as long as one trigger signal is selected from a plurality of trigger signals input from each external device.

  In addition, the detailed structures and detailed operations of the waveform generators 11 and 11A and the semiconductor test apparatus 10 in the present embodiment can be appropriately changed without departing from the spirit of the present invention.

It is a block diagram which shows schematic structure of the waveform generator of 1st Embodiment which concerns on this invention. It is a block diagram which shows the internal structure of a waveform generator. It is a figure which shows that arbitrary waveform data are memorize | stored in each of the memory area of a memory | storage part. It is the figure which showed the case where a test is performed using various arbitrary waveforms. It is a block diagram which shows the internal structure of the waveform generator of 2nd Embodiment which concerns on this invention. It is a figure which shows that arbitrary waveform data are memorize | stored in each of the memory area of a memory | storage part. It is the figure which showed the relationship between the order which outputs an arbitrary waveform, and a trigger signal. FIG. 8 is a diagram showing a memory area of a storage unit in each method when outputting the arbitrary waveform of FIG. 7. It is a block diagram which shows schematic structure of the conventional waveform generator. It is a block diagram which shows the internal structure of the conventional waveform generator. It is a figure which shows that the arbitrary waveforms were each defined with respect to the trigger signal. It is a figure which shows the case where there are 100 types of arbitrary waveforms. It is a figure which shows rewriting the definition of the arbitrary waveform with respect to a trigger signal in the middle of a test.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor test apparatus 11, 11A Waveform generator 12 Digital pin module 13 Digitizer 14 Handler prober 15 Measured object 16 Other measuring instruments 21, 31 CPU
22, 32 Address counters 23, 33 Storage units 23A to 23D, 33A to 33D Memory area 24 Output unit 34 AND circuit

Claims (5)

In the waveform generator having output means for outputting a plurality of test waveforms for testing the DUT,
A plurality of memory areas for storing each test waveform data; and storage means for storing each test waveform data in each memory area in order of outputting each test waveform to the DUT;
A trigger signal indicating a timing for generating the test waveform is input, and an address counter that counts and outputs an address associated with each memory area each time the trigger signal is input;
The output means refers to the memory area corresponding to the address output by the address counter, reads the test waveform data stored in the referenced memory area, and based on the read test waveform data, the output means Control means for outputting a test waveform from
A waveform generator comprising: In the case where there are a plurality of the trigger signals, a selection means for selecting one trigger signal from the plurality of trigger signals,
The address counter
The waveform generating apparatus according to claim 1, wherein the trigger signal selected by the selection unit is input. In the waveform generator having output means for outputting a plurality of test waveforms for testing the DUT,
A plurality of memory areas for storing each test waveform data, and storage means for storing the respective test waveform data of different waveforms in the respective memory areas;
An input means for inputting a trigger signal for generating the test waveform and a count signal instructing counting of an address associated with the memory area;
When the trigger signal and the count signal are input to the input means, the address is counted and output.When the count signal is not input to the input means and only the trigger signal is input, An address counter that outputs without counting addresses,
The output means refers to the memory area corresponding to the address output by the address counter, reads the test waveform data stored in the referenced memory area, and based on the read test waveform data, the output means Control means for outputting a test waveform from
A waveform generator comprising: In the case where there are a plurality of the trigger signals, a selection means for selecting one trigger signal from the plurality of trigger signals,
The input means includes
The waveform generator according to claim 3, wherein the trigger signal selected by the selection unit is input.   A semiconductor test apparatus comprising the waveform generator according to claim 1.

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