JP2009130095A - Part built-in wiring board, and manufacturing method for part built-in wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a part built-in wiring board having a semiconductor chip buried and mounted in an insulating plate by flip-chip connection, inexpensively while securing reliability of the flip-chip connection and functionalities as the wiring board. <P>SOLUTION: The part built-in wiring board includes a first insulating layer, a second insulating layer positioned in a laminated shape over the first insulating layer, a semiconductor chip buried in the second insulating layer and having a terminal pad, a wiring pattern sandwiched between the first insulating layer and the second insulating layer, including a mounting land for the semiconductor chip, and having a roughened surface on the second insulating layer side, a conductive bump disposed between a terminal pad of the semiconductor chip and the mounting land of the wiring pattern and electrically and mechanically connecting the terminal pad and mounting land to each other, and a resin provided between the semiconductor chip and first insulating layer, and the wiring pattern. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a component built-in wiring board in which components are embedded and mounted in an insulating plate, and more particularly to a component built-in wiring board in which a semiconductor chip is embedded and mounted by flip connection.

  An example of a component built-in wiring board in which a semiconductor chip is embedded and mounted by flip connection is disclosed in Japanese Unexamined Patent Application Publication No. 2003-197849. If a semiconductor chip (bare chip) is flip-connected, the thickness generated by the mounting is saved to a minimum. Therefore, the flip connection is an effective method for incorporating a semiconductor element in a wiring board.

  In the flip connection, for example, an Au bump is further formed on a terminal pad formed on a semiconductor chip, and this is press-contacted to a wiring pattern formed on a wiring board via an adhesive (underfill resin). Can be made. The consideration here is the low resistance connection between the Au bump and the wiring pattern and the securing of the connection reliability. Therefore, a high degree of cleaning is required on the surface of the wiring pattern, and as a common method, an Au plating layer is also formed on the surface layer of the wiring pattern.

  Generally, when flip-connecting a semiconductor chip on the main surface of a wiring board, a protective layer such as a solder resist is formed, leaving only a portion of the wiring pattern to be connected, and then a portion to be connected An Au plating layer is formed on the substrate. As a result, Au plating, which is not inexpensive, can be applied with a minimum area.

In the case of embedding a semiconductor chip in a wiring board and flip-connecting it, there are some differences from the flip-connection of the semiconductor chip on the main surface as described above. First, there is an influence of the solder resist becoming a part of the inner insulating layer. Generally, the adhesion between the solder resist and the insulating plate material used in the wiring board is not so strong between the insulating plate materials. Therefore, when a configuration in which the solder resist as the inner layer is omitted is adopted, it is necessary to perform Au plating over a wide area, which affects the manufacturing cost. It cannot be said that the adhesion between the Au plating layer and the insulating plate material is strong, and a problem remains in this respect.
JP 2003-197849 A

  The present invention has been made in consideration of the above-mentioned circumstances, and in a component-embedded wiring board in which a semiconductor chip is embedded and mounted in an insulating plate by flip connection, the reliability of flip connection and functionality as a wiring board are achieved. An object of the present invention is to provide a component built-in wiring board that can be manufactured at low cost while maintaining it, and a method for manufacturing the same.

  In order to solve the above-described problem, a component built-in wiring board according to the present invention includes a first insulating layer, a second insulating layer positioned in a stacked manner with respect to the first insulating layer, and the second insulating layer. A semiconductor chip having a terminal pad embedded in an insulating layer, and provided between the first insulating layer and the second insulating layer, including a mounting land for the semiconductor chip, and the second The insulating layer side surface of the wiring pattern is sandwiched between the terminal pad of the semiconductor chip and the mounting land of the wiring pattern, and the terminal pad and the mounting land are electrically connected. And electrically conductive bumps, and a resin provided between the semiconductor chip and the first insulating layer and the wiring pattern.

  In other words, in order to satisfactorily embed and mount a semiconductor chip on a wiring board via conductive bumps on its terminal pads, the wiring pattern including the lands on the wiring board has a roughened surface. Yes. According to experiments, the electrical connection between the wiring pattern with the roughened surface and the conductive bump achieves a significantly lower resistance connection and improved connection reliability than the wiring pattern without the roughening. Is done. The adhesion between the wiring pattern with the roughened surface and the insulating layer is good, and the functionality as a wiring board is not adversely affected.

  The method of manufacturing a component built-in wiring board according to the present invention includes a step of patterning a metal foil laminated on a first insulating board and forming a wiring pattern including a land for mounting a semiconductor chip, A step of roughening the surface of the wiring pattern including lands, and a semiconductor chip having terminal pads and conductive bumps formed on the terminal pads. A step of flip-connecting the conductive bump to a position, and the second insulating plate different from the first insulating plate so as to embed the flip-connected semiconductor chip in the second insulating plate. And a step of integrating the second insulating plate in a laminated form on one insulating plate.

  This manufacturing method is one example of manufacturing the component built-in wiring board.

  According to the present invention, in a component built-in wiring board in which a semiconductor chip is embedded and mounted in an insulating plate by flip connection, the reliability of flip connection and functionality as a wiring board are maintained, and manufacturing is possible at low cost. A possible component built-in wiring board and a method of manufacturing the same can be provided.

  As an embodiment of the present invention, the second insulating layer is a laminate of at least two insulating layers, and a second wiring pattern provided between the at least two insulating layers, and the second An axis that penetrates part of the insulating layer in the stacking direction and is sandwiched between the surface of the wiring pattern and the surface of the second wiring pattern, and is made of a conductive composition and coincides with the stacking direction. And an interlayer connection body having a shape whose diameter changes in the direction of the axis.

  This interlayer connection body is an example of an interlayer connection body that penetrates a part in the stacking direction of the second insulating layer in which the semiconductor chip is embedded. For example, the interlayer connection body is derived from conductive bumps formed by screen printing of a conductive composition. It is an interlayer connection body. This interlayer connection body is sandwiched between the second wiring pattern and the wiring pattern. However, since the surface of the wiring pattern is roughened, the connection reliability between the wiring pattern and the interlayer connection body is improved. Is also preferable.

  As an embodiment, the wiring pattern may have Cu as its material, and the conductive bump may have Au as its material. Cu is the most common and low cost wiring pattern, and if the conductive bump is Au, the connection compatibility with Cu is good and preferable.

  Here, the surface of the wiring pattern may have a surface roughness exceeding 0.45 μm in the evaluation of the ten-point surface roughness Rz. According to the experiment, when the surface roughness of the wiring pattern exceeds 0.45 μm, there is no occurrence of a sample that is determined to have poor conduction with the conductive bump in the initial conduction test.

  As an embodiment as a manufacturing method, the second insulating plate is a laminate of at least two insulating layers, and is provided between the at least two insulating layers. And an axis that is in contact with the surface of the second wiring pattern, passes through a part of the second insulating plate in the stacking direction, has a head exposed, is made of a conductive composition, and coincides with the stacking direction. And the step of integrating the second insulating plate in a laminated form with the first insulating plate, the interlayer connection body having a shape whose diameter changes in the direction of the axis, The head part of the interlayer connection body of the second insulating plate may be in contact with the roughened wiring pattern.

  The interlayer connection here is an example of an interlayer connection that penetrates a part in the stacking direction of the second insulating layer in which the semiconductor chip is embedded. For example, conductive bumps formed by screen printing of a conductive composition Is an interlayer connection body derived from This interlayer connection body is sandwiched between the second wiring pattern and the wiring pattern. According to this, since the surface of the wiring pattern is roughened, this wiring pattern and the interlayer connection body It is also preferable because the connection reliability is improved.

  As an embodiment, the metal foil may have Cu as a material thereof, and the conductive bump may have Au as a material thereof. Cu is the most common and low cost wiring pattern, and if the conductive bump is Au, the connection compatibility with Cu is good and preferable.

  Here, the roughening may be performed so as to have a surface roughness exceeding 0.45 μm in the evaluation of the ten-point surface roughness Rz. According to the experiment, when the surface roughness of the wiring pattern exceeds 0.45 μm, there is no occurrence of a sample that is determined to have poor conduction with the conductive bump in the initial conduction test.

  Here, the roughening can be performed by blackening and reducing Cu. The roughening may be performed by microetching Cu. These roughening methods are examples of roughening methods that can be generally employed.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration of a component built-in wiring board according to an embodiment of the present invention. As shown in FIG. 1, this component built-in wiring board includes an insulating layer 11 (first insulating layer), 12, 12, 13, 14, and 15 (12, 13, 14, 15 second insulating layer). ), Wiring layer 21, 22 (wiring pattern), 23 (second wiring pattern), 24, 25, 26 (= 6 layers in total), interlayer connector 31, 32, 34, 35, through-hole conductor 33, semiconductor chip 41, conductive bump 42, and underfill resin 51 (resin).

  The semiconductor chip 41 is electrically and mechanically connected to the inner wiring layer 22 via conductive bumps 42 by flip connection. For this connection, conductive bumps 42 are formed in advance on terminal pads (not shown) of the semiconductor chip 41, and the built-in component mounting lands are patterned on the wiring layer 22 in alignment with the conductive bumps 42. Is formed. The conductive bump 42 is made of, for example, Au, and is previously formed in a stud shape on the terminal pad. An underfill resin 51 is filled between the semiconductor chip 41 and the wiring layer 22 and the insulating layer 11 for mechanical and chemical protection of the flip connection portion.

  The surface on the insulating layer 12 side of the wiring layer 22 including a portion provided for connection to the conductive bumps 42 is a roughened surface 22a that has been processed so that the surface roughness is appropriately increased. By providing the roughened surface 22a, the low resistance and the reliability of the connection with the conductive bump 42 are ensured. In this case, it is not necessary to consider the application of Au plating to increase the cleanliness of the surface of the wiring layer 22 on the insulating layer 12 side, or the formation of a solder resist layer so as not to increase the plating area as much as possible. . Therefore, a lower cost is realized, and it is also possible to avoid a possibility that the function as a wiring board is impaired due to insufficient adhesion between the insulating layer 12 and the Au plating layer or the solder resist layer.

  Regarding the structure other than the surface of the wiring layer 22 being the roughened surface 22a, that is, the structure itself formed by the semiconductor chip 41, the conductive bump 42, the wiring layer 22, the insulating layer 11, and the underfill resin 51 is generally used. A structure obtained by a flip connection that is frequently used may be used, and therefore a large cost increase does not occur. The roughened surface 22a further contributes to improving the adhesion between the wiring layer 22 and the insulating layer 12 and improving the reliability of the electrical connection between the wiring layer 22 and the interlayer connector 32. Also preferred.

  Here, a fine structure of a connection portion between the semiconductor chip 41 and the wiring layer 22 will be described with reference to FIG. FIG. 2 is a cross-sectional structure diagram showing the connection portion between the semiconductor chip 41 and the wiring layer 22 in the component built-in wiring board shown in FIG. In FIG. 2, the same components as those shown in FIG. As shown in FIG. 2, as a fine structure, the unevenness of the roughened surface 22a of the wiring layer 22 is crushed in a state where the conductive bumps 42 are pressed against the wiring layer 22, thereby exposing the new surface of the wiring layer 22. In contact with the conductive bump 42. Therefore, a good connection is realized.

  Returning to FIG. 1, the other structure as the component built-in wiring board will be described. The wiring layers 22, 23, 24 and 25 different from the outer wiring layers 21 and 26 are the inner wiring layers. The insulating layer 11 between the wiring layer 22 and the wiring layer 22, the insulating layer 12 between the wiring layer 22 and the wiring layer 23, the insulating layer 13 between the wiring layer 23 and the wiring layer 24, and the wiring layer 24 and the wiring layer. The insulating layer 14 is located between the wiring layers 25 and 26, and the insulating layer 15 is located between the wiring layers 25 and 26. Each of the wiring layers 21 to 26 is made of, for example, a metal (copper) foil having a thickness of 18 μm.

  Each of the insulating layers 11 to 15 is a rigid material made of, for example, a glass epoxy resin, each having a thickness of 100 μm, for example, only the insulating layer 13 has a thickness of, for example, 300 μm, excluding the insulating layer 13. In particular, the insulating layer 13 has an opening at a position corresponding to the built-in semiconductor chip 41, and provides a space for housing the semiconductor chip 41. The insulating layers 12 and 14 are deformed so as to fill the opening of the insulating layer 13 for the built-in semiconductor chip 41 and the space inside the through-hole conductor 33 of the insulating layer 13 and become voids inside. There is no space.

  The wiring layer 21 and the wiring layer 22 can be conducted by an interlayer connector 31 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 11. Similarly, the wiring layer 22 and the wiring layer 23 can be conducted by an interlayer connector 32 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 12. The wiring layer 23 and the wiring layer 24 can be conducted by a through-hole conductor 33 provided through the insulating layer 13. The wiring layer 24 and the wiring layer 25 can be conducted by an interlayer insulator 34 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 14. The wiring layer 25 and the wiring layer 26 can be conducted by an interlayer connector 25 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 15.

  The interlayer connectors 31, 32, 34, and 35 are derived from conductive bumps formed by screen printing of a conductive composition, respectively, and depend on the manufacturing process in the axial direction (shown in FIG. 1). The diameter changes in the upper and lower stacking directions). The diameter is, for example, 200 μm on the thick side.

  As described above, the component built-in wiring board according to this embodiment has an inner layer including a land for satisfactorily embedding and mounting the semiconductor chip 41 by flip connection via the conductive bumps 42 provided on the terminal pads. The wiring layer 22 is characterized in that the surface on the insulating layer 12 side is roughened. Thereby, the low resistance connection between the semiconductor chip 41 and the wiring layer 22 and the connection reliability thereof are improved. The adhesion between the wiring layer 22 having the roughened surface 22a and the insulating layer 12 is good, and the functionality as a wiring board is not adversely affected. Further, the reliability of electrical connection between the wiring layer 22 and the interlayer connector 32 is also improved.

  Next, the manufacturing process of the component built-in wiring board shown in FIG. 1 will be described with reference to FIGS. 3 to 5 are process diagrams schematically showing a part of the manufacturing process of the component built-in wiring board shown in FIG. In these figures, the same or equivalent components as those shown in FIG.

  It demonstrates from FIG. FIG. 3 shows a manufacturing process of a portion centering on the insulating layer 11 in each configuration shown in FIG. First, as shown in FIG. 3 (a), a paste-like conductive composition to be an interlayer connection 31 is formed on a metal foil (electrolytic copper foil) 22A having a thickness of 18 μm, for example, by screen printing. It is formed in a bump shape (bottom diameter, for example, 200 μm, height, for example, 160 μm). This conductive composition is obtained by dispersing fine metal particles such as silver, gold and copper or fine carbon particles in a paste-like resin. For convenience of explanation, printing is performed on the lower surface of the metal foil 22A, but it may be printed on the upper surface (the following drawings are also the same). After the interlayer connector 31 is printed, it is dried and cured.

  Next, as shown in FIG. 3B, an FR-4 prepreg 11A having a thickness of, for example, 100 μm is laminated on the metal foil 22A to penetrate the interlayer connector 31, so that the head is exposed. To do. At the time of exposure or thereafter, the tip thereof may be crushed by plastic deformation (in any case, the shape of the interlayer connection body 31 is a shape having an axis coinciding with the laminating direction and the diameter changing in the axial direction). Subsequently, as shown in FIG. 3C, a metal foil (electrolytic copper foil) 21A is laminated on the prepreg 31A, and the whole is integrated by pressing and heating. At this time, the metal foil 21A is in electrical continuity with the interlayer connector 31, and the prepreg 11A is completely cured to become the insulating layer 11.

  Next, as shown in FIG. 3D, the metal foil 22A on one side is subjected to patterning by, for example, well-known photolithography, and processed into a wiring layer 22 including mounting lands. Further, the surface of the patterned wiring layer 22 is roughened to obtain a roughened surface 22a. Specifically, for example, a blackening reduction process or a microetching process can be employed. Examples of the micro-etching process include CZ processing (MEC product name) and bond film processing (Atotech product name).

  In addition, since the process which roughens the surface of copper foil is generally performed in order to improve adhesiveness with the insulating resin laminated | stacked on copper foil, the said roughening is carried out as a process simultaneously with this process. Processing may be performed. According to this, it is not necessary to perform the roughening process as a new process, and it is possible to manufacture efficiently. However, the degree of roughening should be directed to an appropriate level in consideration of the low resistance in flip connection and its reliability (described later).

  Next, as shown in FIG. 3E, an unfilled underfill resin 51A is applied to a position on the insulating layer 11 where the semiconductor chip 41 is to be mounted using, for example, a dispenser. Subsequently, as shown in FIG. 3F, the semiconductor chip 41 with the conductive bumps 42 is positioned and pressed against the mounting land of the wiring layer 22 using, for example, a flip chip bonder. After the pressure welding, a heating step is performed to improve the connection strength and to cure the underfill resin 51A. As described above, the semiconductor chip 41 is connected to the mounting land of the wiring layer 22 via the conductive bump 42, and the underfill resin 51 is filled between the semiconductor chip 41 and the wiring layer 22 and the insulating layer 11. A wiring board material 1 in a state is obtained. The subsequent steps using this wiring board material 1 will be described later with reference to FIG.

  Next, a description will be given with reference to FIG. FIG. 4 shows a manufacturing process of a part centering on the insulating layer 13 and the same 12 in each configuration shown in FIG. First, as shown in FIG. 4A, for example, an FR-4 insulating layer 13 having a thickness of, for example, 300 μm in which metal foils (electrolytic copper foils) 23A and 24A having a thickness of 18 μm are laminated on both surfaces is prepared. A through-hole 72 for forming a through-hole conductor is formed at a predetermined position, and an opening 71 is formed in a portion corresponding to the built-in semiconductor chip 41.

  Next, electroless plating and electrolytic plating are performed, and the through-hole conductor 33 is formed on the inner wall of the through hole 72 as shown in FIG. At this time, a conductor is also formed on the inner wall of the opening 71. Further, as shown in FIG. 4C, the metal foils 23A and 24A are patterned in a predetermined manner using well-known photolithography to form wiring layers 23 and 24. By patterning the wiring layers 23 and 24, the conductor formed on the inner wall of the opening 71 is also removed.

  Next, as shown in FIG. 4D, conductive bumps (bottom diameter, for example, 200 μm, height, for example, 160 μm) to be the interlayer connector 32 are formed at predetermined positions on the wiring layer 23 of the paste-like conductive composition. It is formed by screen printing. Subsequently, as shown in FIG. 4E, an FR-4 prepreg 12A (nominal thickness, for example, 100 μm) to be the insulating layer 12 is laminated on the wiring layer 23 side using a press. In the prepreg 12A, an opening corresponding to the built-in semiconductor chip 41, which is the same as the insulating layer 13, is provided in advance.

  In this lamination process, the head of the interlayer connector 32 is passed through the prepreg 12A. In addition, the broken line of the head part of the interlayer connection body 32 in FIG. 4E indicates that there are both cases where the head part is plastically deformed and crushed at this stage, and when it is not plastically deformed. By this step, the wiring layer 23 is located by sinking to the prepreg 12A side. The wiring board material obtained as described above is referred to as a wiring board material 2.

  Note that the steps shown in FIG. 4 may be performed as follows. In the stage of FIG. 4A, only the through hole 72 is formed and the subsequent steps from FIG. 4B to FIG. 4D are performed without forming the opening 71 for the built-in component. Next, as a process corresponding to FIG. 4E, prepreg 12A (without opening) is stacked. And it is the process of forming simultaneously the opening part for components incorporation in the insulating layer 13 and the prepreg 12A.

  Next, a description will be given with reference to FIG. FIG. 5 is a diagram showing an arrangement relationship in which the wiring board materials 1 and 2 obtained as described above are stacked.

  In FIG. 5, the upper wiring board material 3 shown in FIG. 5 applies the same process as the lower wiring board material 1, and then the interlayer connection 34 and the prepreg 14 </ b> A are connected to the interlayer connection body in the intermediate wiring board material 2. 32 and the prepreg 12A. However, there is no component (semiconductor chip 41) and no part (mounting land) for connecting it, and the prepreg 14A is not provided with an opening for the semiconductor chip 41. Other than that, the metal foil (electrolytic copper foil) 26A, the insulating layer 15, the interlayer connection body 35, the wiring layer 25, the prepreg 14A, and the interlayer connection body 34 are the metal foil 21A of the wiring board material 1, the insulating layer 11, and the interlayer connection, respectively. The same as the body 31, the wiring layer 22, the prepreg 12 </ b> A of the wiring board material 2, and the interlayer connection body 32.

  The respective wiring board materials 1, 2, and 3 are laminated and arranged in the arrangement as shown in FIG. Thereby, the prepregs 12A and 14A are completely cured, and the whole is laminated and integrated. At this time, due to the fluidity of the prepregs 12 </ b> A and 14 </ b> A obtained by heating, the prepregs 12 </ b> A and 14 </ b> A are deformed into the space around the semiconductor chip 41 and the space inside the through-hole conductor 33, and no gap is generated. The wiring layers 22 and 24 are electrically connected to the interlayer connectors 32 and 34, respectively. In this laminating step, the roughened surface 22 a is provided on the surface of the wiring layer 22, thereby improving the adhesion between the insulating layer 12 and the wiring layer 22, and the electrical connection between the interlayer connector 32 and the wiring layer 22. Connection reliability is improved. This has already been described.

  After the laminating step shown in FIG. 5, the upper and lower metal foils 26A and 21A are patterned in a predetermined manner using well-known photolithography, and further, layers of solder resists 61 and 62 are formed, as shown in FIG. Such a component built-in wiring board can be obtained.

  As a modification, the through-hole conductor 33 provided in the intermediate insulating layer 13 can naturally have a configuration similar to the interlayer connector 31 or 32. In addition, the outer wiring layers 21 and 26 are formed at the stage of each wiring board material 1 and 3 (for example, at the stage of FIG. 3D) other than patterning after the last lamination step. May be.

  Further, in the laminating process shown in FIG. 5, for the wiring board materials 1 and 2, the prepreg 12 </ b> A and the interlayer connector 32 are provided not on the wiring board material 2 side but on the wiring board material 1 side. May be. That is, the formation of the interlayer connector 32 and the lamination of the prepreg 12A are performed in advance on the wiring layer 22 (on the insulating layer 11) of the wiring board material 1. In this case, the mounted semiconductor chip 41 seems to be an interference factor when the interlayer connection body 32 is formed by screen printing at first glance, but in the case of a sufficiently thin component as the semiconductor chip 41, what is actually an interference factor? Don't be. In the step of laminating the prepreg 12A, the prepreg 12A can be uniformly laminated in the in-plane direction by pressing and heating with a cushioning material capable of absorbing the thickness of the semiconductor chip 41 interposed.

  Next, the result of actually manufacturing and functionally evaluating the component built-in wiring board shown in FIG. 1 as a sample will be described with reference to FIG. FIG. 6 is a table showing the results of actually manufacturing and functionally evaluating the component built-in wiring board shown in FIG. 1 as a sample. As a premise, FIG. 6A shows the specifications of the built-in semiconductor chip 41. The used semiconductor chip 41 is a test chip for evaluation. As shown in FIG. 6A, the size is 3.0 mm × 3.0 mm, the thickness is 200 μm, the number of terminals is 30 pins, and the terminal pitch is Each specification is 300 μm, and Au stud bumps are formed as the conductive bumps 42.

  As shown in FIG. 6B, for the purpose of comparison, when the roughening process is performed on the wiring layer 22, when not performed, 100 samples are manufactured and prepared as the component built-in wiring boards, and each of these bumps is prepared. Connection resistance, initial continuity evaluation, and continuity evaluation after the thermal shock test were performed.

  As the connection resistance for each bump, a sample having a bump having a connection resistance of 10 mΩ or more per bump was determined to be conductive NG (conductivity failure). As a result, as shown in the table, in the sample in which the roughening process was performed on the wiring layer 22, the NG occurrence rate was 0% in the initial continuity evaluation, whereas in the sample in which the roughening process was not performed, 15%. % NG generation rate. Further, for the samples that were not determined to be NG in the initial continuity evaluation, the same continuity evaluation was performed after performing the thermal shock test as shown in the table. In contrast to 0%, in the sample not subjected to the roughening treatment, 15 samples out of 75 samples that were not NG before the thermal shock test became NG (NG generation rate: 20%).

  Therefore, it was confirmed in the data that the roughening treatment of the surface of the wiring layer 22 greatly contributes to the realization of the low resistance connection between the semiconductor chip 41 and the wiring layer 22 and the improvement of the connection reliability.

  Next, FIG. 7 is a table showing the results (initial continuity evaluation) of the difference in the occurrence frequency of defects due to the difference in surface roughness after roughening in the evaluation shown in FIG. Here, the surface roughness is indicated by a ten-point average roughness Rz defined by JIS. Rz = 0.2 μm in FIG. 7 corresponds to the case without the roughening process in FIG. 6, and Rz = 0.75 μm in FIG. 7 corresponds to the case with the roughening process in FIG. As shown in FIG. 7, when the surface roughness Rz after the roughening treatment of the wiring layer 22 is increased to 0.45 μm, almost no NG occurs as the initial conduction evaluation, and therefore Rz exceeding this value is set. It is considered preferable. It has also been found that there is no problem in initial conduction evaluation even when Rz increases to 2.5 μm.

Sectional drawing which shows typically the structure of the component built-in wiring board which concerns on one Embodiment of this invention. FIG. 2 is a cross-sectional structure diagram illustrating a connection portion between a semiconductor chip 41 and a wiring layer 22 in the component built-in wiring board illustrated in FIG. Process drawing which shows a part of manufacturing process of the component built-in wiring board shown in FIG. Process drawing which shows another part of manufacturing process of the component built-in wiring board shown in FIG. FIG. 9 is a process diagram schematically showing still another part of the manufacturing process of the component built-in wiring board shown in FIG. 1. The table | surface which shows the result of having actually manufactured the component built-in wiring board shown in FIG. 1 as a sample, and evaluating the function. The table | surface which shows the result of the difference in the defect occurrence frequency by the difference in the surface roughness after roughening especially in the evaluation shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Wiring board material, 2 ... Wiring board material, 3 ... Defeat board material, 11 ... Insulating layer, 11A ... Prepreg, 12 ... Insulating layer, 12A ... Prepreg, 13 ... Insulating layer, 13A ... Prepreg, 14 ... Insulating layer, 14A ... Prepreg, 15 ... Insulating layer, 21 ... Wiring layer (wiring pattern), 21A ... Metal foil (copper foil), 22 ... Wiring layer (wiring pattern), 22a ... Roughened surface, 22A ... Metal foil (copper foil) , 23 ... wiring layer (wiring pattern), 23A ... metal foil (copper foil), 24 ... wiring layer (wiring pattern), 24A ... metal foil (copper foil), 25 ... wiring layer (wiring pattern), 26 ... wiring layer (Wiring pattern), 26A... Metal foil (copper foil), 31, 32, 34, 35... Interlayer connection body (conductive bump by conductive composition printing), 33... Through-hole conductor, 41. ... Conductive bumps (Au stack Bumps), 51 ... underfill resin, 51A ... underfill resin (uncured), 61, 62 ... solder resist, 71 ... opening parts, 72 ... through hole.

Claims (10)

A first insulating layer;
A second insulating layer positioned in a stack with respect to the first insulating layer;
A semiconductor chip having a terminal pad embedded in the second insulating layer;
A wiring pattern provided between the first insulating layer and the second insulating layer, including a mounting land for the semiconductor chip and having a roughened surface on the second insulating layer side;
Conductive bumps sandwiched between the terminal pads of the semiconductor chip and the mounting lands of the wiring pattern, and electrically and mechanically connecting the terminal pads and the mounting lands;
A component built-in wiring board comprising: the semiconductor chip; and a resin provided between the first insulating layer and the wiring pattern. The second insulating layer is a stack of at least two insulating layers;
A second wiring pattern provided between the at least two insulating layers;
The second insulating layer penetrates a part in the stacking direction and is sandwiched between the surface of the wiring pattern and the surface of the second wiring pattern, and is made of a conductive composition and coincides with the stacking direction. 2. The component built-in wiring board according to claim 1, further comprising: an interlayer connection body having a shaft that has a shape that changes in diameter in a direction of the shaft.   3. The component built-in wiring board according to claim 1, wherein the wiring pattern has Cu as a material thereof, and the conductive bump has Au as a material thereof.   4. The component built-in wiring board according to claim 3, wherein the surface of the wiring pattern has a surface roughness exceeding 0.45 [mu] m in evaluation of a ten-point surface roughness Rz. Patterning a metal foil laminated on the first insulating plate, forming a wiring pattern including lands for mounting a semiconductor chip; and
Roughening the surface of the wiring pattern including the lands;
Flip-connecting a semiconductor chip having a terminal pad and a conductive bump formed on the terminal pad by aligning the position of the conductive bump with the position of the land of the roughened wiring pattern; ,
The second insulating plate is integrated with the first insulating plate in a stacked manner so that the flip-connected semiconductor chip is embedded in a second insulating plate different from the first insulating plate. A process for producing a component built-in wiring board. The second insulating plate is a laminate of at least two insulating layers, and a second wiring pattern sandwiched between the at least two insulating layers, and a surface of the second wiring pattern The head is exposed through a part of the second insulating plate in the laminating direction and is made of a conductive composition and has an axis that coincides with the laminating direction and has a diameter in the direction of the axis. An interlayer connection body having a changing shape,
The wiring pattern in which the step of integrating the second insulating plate in a laminated form with the first insulating plate includes the roughening of the head portion of the interlayer connection body of the second insulating plate. The method of manufacturing a component built-in wiring board according to claim 5, wherein the component built-in wiring board is brought into contact with the wiring board.   The method of manufacturing a component built-in wiring board according to claim 5 or 6, wherein the metal foil has Cu as a material thereof, and the conductive bump has Au as a material thereof.   8. The method of manufacturing a component built-in wiring board according to claim 7, wherein the roughening is performed so as to have a surface roughness exceeding 0.45 [mu] m by evaluation of a ten-point surface roughness Rz.   8. The method of manufacturing a component built-in wiring board according to claim 7, wherein the roughening is performed by blackening and reducing Cu.   8. The method of manufacturing a component built-in wiring board according to claim 7, wherein the roughening is performed by microetching Cu.

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