JPH07201917A - Circuit formation board and manufacture thereof - Google Patents
Circuit formation board and manufacture thereofInfo
- Publication number
- JPH07201917A JPH07201917A JP5336351A JP33635193A JPH07201917A JP H07201917 A JPH07201917 A JP H07201917A JP 5336351 A JP5336351 A JP 5336351A JP 33635193 A JP33635193 A JP 33635193A JP H07201917 A JPH07201917 A JP H07201917A
- Authority
- JP
- Japan
- Prior art keywords
- metal electrode
- film metal
- thin film
- insulating substrate
- electrically insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子やＩＣなど
の電子部品をフェースダウン実装して搭載するための回
路形成基板とその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit-forming board for mounting electronic parts such as semiconductor elements and ICs by face-down mounting and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】近年、電子部品の高密度実装により、電
子部品を搭載する回路形成基板と電子部品との電気的接
続の信頼性向上や回路形成基板に設ける配線パターンの
高密度化が要望されている。2. Description of the Related Art In recent years, due to high-density mounting of electronic components, it has been demanded to improve reliability of electrical connection between a circuit-forming substrate on which electronic components are mounted and electronic components, and to increase the density of wiring patterns provided on the circuit-forming substrate. ing.
【０００３】以下、従来の回路形成基板について図面を
参照しながら説明する。図４は従来の回路形成基板を示
す断面図である。図４に示すように、回路形成基板は、
ガラスからなる電気絶縁性基板１１と、その表面に設け
た薄膜金属電極１４と、Ａｕからなるバンプ１６を介し
て薄膜金属電極１４と電気的に接合する半導体ＩＣ１５
と、この半導体ＩＣ１５と電気絶縁性基板１１とを接着
する接着樹脂１７とを有した構成である。A conventional circuit board will be described below with reference to the drawings. FIG. 4 is a sectional view showing a conventional circuit board. As shown in FIG. 4, the circuit board is
An electrically insulating substrate 11 made of glass, a thin film metal electrode 14 provided on the surface thereof, and a semiconductor IC 15 electrically joined to the thin film metal electrode 14 via bumps 16 made of Au.
And a bonding resin 17 for bonding the semiconductor IC 15 and the electrically insulating substrate 11 together.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら上記従来
の構成では、次のような問題点を有していた。However, the above conventional structure has the following problems.
【０００５】一般に、配線幅を小さくして配線数を増や
し、配線パターンの高密度化をする場合、配線の形成方
法としては、薄膜電極金属１４を電気絶縁性基板１１
に、蒸着やスパッタリングやフォトエッチング法によっ
て形成する方法がある。この方法によると、電気絶縁性
基板１１の表面には極力凹凸層がないものが望ましく、
ガラスからなる電気絶縁性基板１１が用いられる。Generally, when the wiring width is reduced to increase the number of wirings to increase the density of the wiring pattern, the method for forming the wiring is to use the thin film electrode metal 14 as the electrically insulating substrate 11.
There is a method of forming it by vapor deposition, sputtering or photo etching. According to this method, it is desirable that the surface of the electrically insulating substrate 11 has no uneven layer as much as possible,
An electrically insulating substrate 11 made of glass is used.
【０００６】第一の問題点は、ガラスのような凹凸層の
非常に少ない電気絶縁性基板１１に薄膜金属電極１４を
形成すると、薄膜金属電極１４と電気絶縁性基板１１と
を強固に密着接合する手段がなく、電気絶縁性基板１１
への薄膜金属電極１４の密着強度が非常に小さくなり、
薄膜金属電極１４が剥離しやすいというものである。The first problem is that when the thin film metal electrode 14 is formed on the electrically insulating substrate 11 having very few uneven layers such as glass, the thin film metal electrode 14 and the electrically insulating substrate 11 are firmly adhered and joined. Electrical insulating substrate 11
The adhesion strength of the thin film metal electrode 14 to the
The thin film metal electrode 14 is easily peeled off.
【０００７】第二の問題点は、一般に、薄膜金属電極１
４の表面は電気絶縁基板１１の表面に影響を受けるため
に、従来のガラスを用いた電気絶縁性基板１１の場合、
電気絶縁性基板１１の表面を投影した形状が薄膜金属電
極１４の表面に形成され、薄膜金属電極１４の表面は凹
凸が非常に少なくなり鏡面のようになる。このため、電
子部分を回路形成基板に加圧接着する際、バンプ１６と
薄膜金属電極１４の表面間において、薄膜金属電極１４
の摩擦係数が小さくなり、バンプ１６と薄膜金属電極１
４とにズレが生じて、接着樹脂１７が、バンプ１６と薄
膜金属電極１４との間に流入したり、バンプ１６と薄膜
金属電極１４との接合力を弱め、接触抵抗が大きくなっ
たりして、信頼性を悪くするというものである。The second problem is generally the thin film metal electrode 1
Since the surface of 4 is affected by the surface of the electrically insulating substrate 11, in the case of the electrically insulating substrate 11 using conventional glass,
A shape obtained by projecting the surface of the electrically insulating substrate 11 is formed on the surface of the thin film metal electrode 14, and the surface of the thin film metal electrode 14 has very few irregularities and becomes a mirror surface. Therefore, when the electronic portion is pressure-bonded to the circuit forming substrate, the thin film metal electrode 14 is provided between the bump 16 and the surface of the thin film metal electrode 14.
Has a smaller friction coefficient, and bump 16 and thin-film metal electrode 1
4 and the adhesive resin 17 flows between the bump 16 and the thin film metal electrode 14 or weakens the bonding force between the bump 16 and the thin film metal electrode 14 to increase the contact resistance. , It makes the credibility worse.
【０００８】本願発明は上記問題点を解決するものであ
り、第一の目的としては、薄膜金属電極と電気絶縁性基
板との密着強度を大きくして、薄膜金属電極の剥離防止
を図ること、第二の目的としては、バンプと薄膜金属電
極の間への接着樹脂の流入防止およびバンプと薄膜金属
電極との接合力を強めて、接触抵抗が大きくなることの
防止をした信頼性の高い回路形成基板を提供することに
ある。The present invention is intended to solve the above problems, and a first object thereof is to increase the adhesion strength between a thin film metal electrode and an electrically insulating substrate to prevent the thin film metal electrode from peeling off. The second purpose is a highly reliable circuit that prevents the adhesive resin from flowing between the bump and the thin film metal electrode and strengthens the bonding force between the bump and the thin film metal electrode to prevent the contact resistance from increasing. It is to provide a formation substrate.
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するため
に本発明の回路形成基板では、前記薄膜金属電極の表面
に凹凸層を有した構成とするものである。In order to achieve the above object, the circuit forming substrate of the present invention has a structure having an uneven layer on the surface of the thin film metal electrode.
【００１０】[0010]
【作用】上記構成によって本発明は、次のような作用を
示す回路形成基板を提供することができるものである。With the above-described structure, the present invention can provide a circuit-forming substrate that exhibits the following effects.
【００１１】第一の作用は次の通りである。すなわち、
薄膜金属電極の表面に凹凸を有するので、バンプと薄膜
金属電極の表面間において、薄膜金属電極の摩擦係数が
大きくなり、電子部品を回路形成基板に加圧接着する
際、バンプが潰れて薄膜金属電極の表面の凹凸層に食い
込み、バンプと薄膜金属電極とが密着接合する。その結
果、電子部品と回路形成基板を接着する接着樹脂が、バ
ンプと薄膜金属電極との間に流入せず、またバンプと薄
膜金属電極との接合力を強め、接触抵抗を小さくするこ
とができる。The first action is as follows. That is,
Since the surface of the thin-film metal electrode has irregularities, the friction coefficient of the thin-film metal electrode between the bump and the surface of the thin-film metal electrode increases, and when the electronic component is pressure-bonded to the circuit forming substrate, the bump is crushed and the thin-film metal electrode is crushed. The bumps and the thin-film metal electrode are intimately bonded to each other by digging into the uneven layer on the surface of the electrode. As a result, the adhesive resin for adhering the electronic component and the circuit forming substrate does not flow between the bump and the thin film metal electrode, and the bonding force between the bump and the thin film metal electrode can be strengthened to reduce the contact resistance. .
【００１２】第二の作用は次の通りである。すなわち、
薄膜金属電極と接触する電気絶縁性基板の表面に凹凸層
を有するので、薄膜金属電極と電気絶縁性基板の表面間
において、電気絶縁基板の表面積が大きくなり、薄膜金
属電極を電気絶縁性基板に形成する際、薄膜金属電極と
電気絶縁性基板との接触面積が大きくなる。その結果、
薄膜金属電極と電気絶縁基板とが強固に密着接合して、
薄膜金属電極の電気絶縁性基板への密着強度が非常に大
きくなり、薄膜金属電極の剥離を防止することができ
る。The second action is as follows. That is,
Since the uneven surface is provided on the surface of the electrically insulating substrate that is in contact with the thin film metal electrode, the surface area of the electrically insulating substrate is large between the surface of the thin film metal electrode and the surface of the electrically insulating substrate, and the thin film metal electrode is used as the electrically insulating substrate. When formed, the contact area between the thin film metal electrode and the electrically insulating substrate increases. as a result,
The thin-film metal electrode and the electrically insulating substrate are firmly and closely joined,
The adhesion strength of the thin film metal electrode to the electrically insulating substrate becomes very large, and peeling of the thin film metal electrode can be prevented.
【００１３】[0013]
（実施例１）以下、本発明の第１の実施例について図面
を参照しながら説明する。(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
【００１４】図１は本発明の第１の実施例における回路
形成基板を示す断面図である。図１に示すように、回路
形成基板は、ガラスからなる電気絶縁性基板１と、厚さ
０．０５μｍ程度のＣｒやＮｉからなる密着強化層９を
介して電気絶縁基板１の上面に形成した厚さ０．０５〜
３μｍ程度のＣｕからなる薄膜金属電極４とこの薄膜金
属電極４の上面に形成した厚さ０．１μｍ程度のＡｕか
らなるメッキ層１０と、薄膜金属電極４にメッキ層とＡ
ｕからなるバンプ６を介して電気的に接合する半導体Ｉ
Ｃ５と、半導体ＩＣ５と電気絶縁性基板１とを接着する
紫外線硬化樹脂である接着樹脂７とを備えている。さら
に、電気絶縁性基板１の表面は表面粗さ０．０５〜１μ
ｍ程度の微細な凹凸層の粗面２を有し、かつこの粗面２
を含んだ電気絶縁基板１の上層部に電気絶縁性基板１の
構成元素であるナトリウムをカリウムで化学的に置換す
る科学処理を施した表面強化処理層３を有するととも
に、薄膜金属電極４の表面に表面粗さ０．０５〜１μｍ
程度の微細な凹凸層の粗面８を有した構成である。FIG. 1 is a sectional view showing a circuit-forming board in the first embodiment of the present invention. As shown in FIG. 1, the circuit forming substrate was formed on the upper surface of the electrically insulating substrate 1 via the electrically insulating substrate 1 made of glass and the adhesion strengthening layer 9 made of Cr or Ni having a thickness of about 0.05 μm. Thickness 0.05 ~
A thin film metal electrode 4 made of Cu having a thickness of about 3 μm, a plating layer 10 made of Au having a thickness of about 0.1 μm formed on the upper surface of the thin film metal electrode 4, a plating layer formed on the thin film metal electrode 4 and
A semiconductor I that is electrically joined via a bump 6 made of u
C5 and an adhesive resin 7 which is an ultraviolet curable resin for adhering the semiconductor IC 5 and the electrically insulating substrate 1 are provided. Furthermore, the surface of the electrically insulating substrate 1 has a surface roughness of 0.05 to 1 μm.
It has a rough surface 2 of a fine uneven layer of about m, and this rough surface 2
The surface of the thin-film metal electrode 4 is provided with the surface-strengthening treatment layer 3 that has been subjected to the chemical treatment of chemically replacing sodium, which is a constituent element of the electrically-insulating substrate 1, with potassium in the upper layer portion of the electrically-insulating substrate 1 containing Surface roughness of 0.05-1 μm
This is a structure having a rough surface 8 of a fine uneven layer.
【００１５】上記構成による回路形成基板について、以
下その特性を説明する。薄膜金属電極４の表面に表面粗
さ０．０５〜１μｍ程度の微細な凹凸層の粗面８を有す
るので、この粗面８上に形成した厚さ０．１μｍ程度の
Ａｕからなるメッキ層１０を介して、Ａｕからなるバン
プ６と薄膜金属電極４の表面間において、薄膜金属電極
４の摩擦係数が大きくなる。すると、電子部品として半
導体ＩＣ５を電気絶縁性基板１に加圧接着する際、バン
プ６が潰れてメッキ層１０とともに薄膜金属電極４の表
面に形成した微細な凹凸層の粗面８に食い込み、バンプ
６と薄膜金属電極４とが密着接合する。その結果、半導
体ＩＣ５と電気絶縁性基板１を接着する紫外線硬化樹脂
である接着樹脂７が、バンプ６と薄膜金属電極４との間
に流入せず、またバンプ６と薄膜金属電極４との接合力
を強め、接触抵抗を小さくすることができる。The characteristics of the circuit-formed board having the above structure will be described below. Since the surface of the thin-film metal electrode 4 has a rough surface 8 of a fine uneven layer having a surface roughness of about 0.05 to 1 μm, the plating layer 10 made of Au and having a thickness of about 0.1 μm is formed on the rough surface 8. Thus, the friction coefficient of the thin film metal electrode 4 becomes large between the bump 6 made of Au and the surface of the thin film metal electrode 4. Then, when the semiconductor IC 5 as an electronic component is pressure-bonded to the electrically insulating substrate 1, the bumps 6 are crushed and bite into the rough surface 8 of the fine concavo-convex layer formed on the surface of the thin film metal electrode 4 together with the plating layer 10, and the bumps 6 and the thin film metal electrode 4 are in close contact with each other. As a result, the adhesive resin 7, which is an ultraviolet curable resin for bonding the semiconductor IC 5 and the electrically insulating substrate 1, does not flow between the bump 6 and the thin film metal electrode 4, and the bump 6 and the thin film metal electrode 4 are bonded together. Strength can be increased and contact resistance can be reduced.
【００１６】また、薄膜金属電極４と接触する電気絶縁
性基板１の表面に表面粗さ０．０５〜１μｍ程度の微細
な凹凸層の粗面２を有するので、この粗面２上に形成し
た厚さ０．０５μｍ程度のＣｒやＮｉからなる密着強化
層９を介して、薄膜金属電極４と電気絶縁性基板１の表
面間において、電気絶縁性基板１の表面積が大きくな
る。すると、ＣｒやＮｉからなる密着強化層９を介し
て、薄膜金属電極４を電気絶縁性基板１に形成する際、
薄膜金属電極４と電気絶縁性基板１との接触面積が大き
くなる。その結果、薄膜金属電極４と電気絶縁性基板１
とが強固に密着接合して、薄膜金属電極４の電気絶縁性
基板１への密着強度が非常に大きくなり、薄膜金属電極
４の剥離を防止することができる。Further, since the surface of the electrically insulating substrate 1 contacting the thin film metal electrode 4 has a rough surface 2 of a fine uneven layer having a surface roughness of about 0.05 to 1 μm, it is formed on this rough surface 2. The surface area of the electrically insulating substrate 1 is increased between the thin film metal electrode 4 and the surface of the electrically insulating substrate 1 through the adhesion strengthening layer 9 made of Cr or Ni having a thickness of about 0.05 μm. Then, when the thin film metal electrode 4 is formed on the electrically insulating substrate 1 via the adhesion strengthening layer 9 made of Cr or Ni,
The contact area between the thin film metal electrode 4 and the electrically insulating substrate 1 increases. As a result, the thin film metal electrode 4 and the electrically insulating substrate 1
Are firmly adhered to each other, the adhesion strength of the thin film metal electrode 4 to the electrically insulating substrate 1 becomes very large, and peeling of the thin film metal electrode 4 can be prevented.
【００１７】さらに、電気絶縁性基板１の微細な凹凸層
の粗面２を含んだ上層部に化学処理を施した表面強化処
理層３を有するので、電気絶縁性基板１の上層部におけ
る対破壊強度が大きくなる。その結果、半導体ＩＣ５を
電気絶縁性基板１に紫外線硬化樹脂である接着樹脂７に
よって加圧接着する際、加圧による薄膜金属電極４への
歪み強度が大きくなっても、その歪みによって薄膜金属
電極４と密着接合する電気絶縁性基板１の粗面２の破壊
や剥がれの発生を防止することができる。Furthermore, since the upper layer portion including the rough surface 2 of the fine uneven layer of the electrically insulating substrate 1 has the chemically strengthened surface-strengthening layer 3, the upper layer portion of the electrically insulating substrate 1 is resistant to damage. Strength increases. As a result, when the semiconductor IC 5 is pressure-bonded to the electrically insulating substrate 1 by the adhesive resin 7 which is an ultraviolet curable resin, even if the strain strength on the thin-film metal electrode 4 increases due to the pressure, the strain causes the thin-film metal electrode 4 to distort. It is possible to prevent the rough surface 2 of the electrically insulating substrate 1 that is in close contact with the substrate 4 from breaking or peeling.
【００１８】このように本実施例によれば、半導体ＩＣ
５と電気絶縁性基板１を接着する紫外線硬化樹脂である
接着樹脂７が、バンプ６と薄膜金属電極４との間に流入
せず、またバンプ６と薄膜金属電極４との接合力を強
め、接触抵抗を小さくすることができる。As described above, according to this embodiment, the semiconductor IC
The adhesive resin 7, which is an ultraviolet curable resin for adhering 5 and the electrically insulating substrate 1, does not flow between the bump 6 and the thin film metal electrode 4, and strengthens the bonding force between the bump 6 and the thin film metal electrode 4, The contact resistance can be reduced.
【００１９】また、薄膜金属電極４と電気絶縁性基板１
とが強固に密着接合して、薄膜金属電極４の電気絶縁性
基板１への密着強度が非常に大きくなり、薄膜金属電極
４の剥離も防止することができる。The thin film metal electrode 4 and the electrically insulating substrate 1 are also provided.
Firmly adhere to each other, the adhesion strength of the thin film metal electrode 4 to the electrically insulating substrate 1 becomes very large, and peeling of the thin film metal electrode 4 can be prevented.
【００２０】さらに、半導体ＩＣ５を電気絶縁性基板１
に紫外線硬化樹脂である接着樹脂７によって加圧接着す
る際、加圧による薄膜金属電極４への歪み強度が大きく
なっても、その歪みによって薄膜金属電極４と密着接合
する電気絶縁性基板１の粗面２の破壊や剥がれの発生ま
でも防止することができる。Further, the semiconductor IC 5 is connected to the electrically insulating substrate 1
In the case of pressure bonding with an adhesive resin 7 which is an ultraviolet curable resin, even if the strain strength to the thin film metal electrode 4 due to the pressure increases, the strain causes the electrical insulating substrate 1 to be in close contact with the thin film metal electrode 4. It is possible to prevent the rough surface 2 from being broken or peeled.
【００２１】なお、本実施例では電気絶縁性基板１の表
面強化処理層３は化学処理によって形成するが、熱処理
によって形成しても同様の効果を得ることができる。In the present embodiment, the surface-strengthening treatment layer 3 of the electrically insulating substrate 1 is formed by chemical treatment, but the same effect can be obtained by forming it by heat treatment.
【００２２】また、本実施例ではフェースダウン実装に
おけるマイクロバンプ実装の構成について説明したが、
その他のフェースダウン実装の構成においても同様の効
果を得ることができる。In this embodiment, the structure of the micro bump mounting in the face down mounting has been described.
Similar effects can be obtained in other face-down mounting configurations.
【００２３】（実施例２）以下、本発明の第２の実施例
について図面を参照しながら説明する。(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings.
【００２４】図２は回路形成基板の製造方法を示す工程
図である。図２（Ａ）、（Ｂ）、（Ｃ）、（Ｄ）に示す
ように、回路形成基板の製造方法は、高圧ガスによって
ガラスやＳｉＣなどの微粒子を吹きつけるサンドブラス
ト法や粒径１μｍ程度のアルミナ微粒子などによる研磨
によって、ガラスからなる電気絶縁性基板１の表面に表
面粗さ０．０５〜１μｍ程度の微細な凹凸層の粗面２を
形成する第１工程と、電気絶縁性基板１の構成元素であ
るナトリウムをカリウムで化学的に置換する化学処理を
施した表面強化処理層３上に粗面２を含んだ電気絶縁性
基板１の上層部に形成する第２工程と、薄膜金属電極４
と電気絶縁性基板１との密着性を高めるために、電気絶
縁性基板１上に厚さ０．０５μｍ程度のＣｒやＮｉから
なる密着層９を形成する第３工程と、このＣｒやＮｉか
らなる密着層９上に厚さ０．３〜２μｍ程度のＡｌやＣ
ｕからなる薄膜金属電極４を形成し、フォトエッチング
によって所望の配線パターンに加工する第４工程と、こ
の薄膜金属電極４上に腐食防止のために厚さ０．１μｍ
程度のＡｕからなるメッキ層１０を形成する第５工程と
を有した構成である。この工程後に、図１（Ｅ）に示す
ように、メッキ層１０とＡｕからなるバンプ６を介して
薄膜金属電極４に電気的に接合する半導体ＩＣ５を電気
絶縁性基板１に紫外線硬化樹脂である接着樹脂７によっ
て加圧接着する工程を有して、回路形成基板に半導体Ｉ
Ｃ５を形成する。FIG. 2 is a process diagram showing a method for manufacturing a circuit-forming board. As shown in FIGS. 2 (A), 2 (B), 2 (C), and 2 (D), a method for manufacturing a circuit-forming substrate is a sandblasting method in which fine particles such as glass or SiC are blown by a high pressure gas, or a particle diameter of about 1 μm. The first step of forming a rough surface 2 of a fine uneven layer having a surface roughness of about 0.05 to 1 μm on the surface of the electrically insulating substrate 1 made of glass by polishing with alumina fine particles and the like. Second step of forming on the upper layer portion of the electrically insulating substrate 1 including the roughened surface 2 on the surface-strengthening treatment layer 3 which has been chemically treated to chemically replace sodium which is a constituent element with potassium, and a thin film metal electrode Four
A third step of forming an adhesion layer 9 of Cr or Ni having a thickness of about 0.05 μm on the electrically insulating substrate 1 in order to improve the adhesion between the electrically insulating substrate 1 and Al or C having a thickness of about 0.3 to 2 μm on the adhesion layer 9
A fourth step of forming a thin film metal electrode 4 made of u and processing it into a desired wiring pattern by photoetching, and a thickness of 0.1 μm on the thin film metal electrode 4 to prevent corrosion.
And a fifth step of forming the plated layer 10 made of Au. After this step, as shown in FIG. 1E, a semiconductor IC 5 that is electrically bonded to the thin film metal electrode 4 via the bump 6 made of the plated layer 10 and Au is formed on the electrically insulating substrate 1 by using an ultraviolet curable resin. There is a step of pressure bonding with the adhesive resin 7, and the semiconductor I is attached to the circuit forming substrate.
Form C5.
【００２５】上記構成による回路形成基板について、以
下その特性を説明する。電気絶縁性基板１の微細な凹凸
層の粗面２を形成することにより、その上に形成する薄
膜金属電極４は電気絶縁性基板１の表面に影響を受け
て、薄膜金属電極４の表面にも微細な凹凸層の粗面８を
形成する。この結果、実施例１における回路形成基板を
容易に製造することができる。The characteristics of the circuit-formed board having the above structure will be described below. By forming the rough surface 2 of the fine concavo-convex layer of the electrically insulating substrate 1, the thin film metal electrode 4 formed thereon is affected by the surface of the electrically insulating substrate 1 and is formed on the surface of the thin film metal electrode 4. Also forms the rough surface 8 of the fine uneven layer. As a result, the circuit-formed board in the first embodiment can be easily manufactured.
【００２６】このように本実施例では、サンドブラスト
法や研磨によって電気絶縁性基板１の表面に微細な凹凸
層を形成することにより、電気絶縁性基板１と薄膜金属
電極４との表面に微細な凹凸層の粗面２、粗面８を形成
するので、実施例１における回路形成基板を容易に製造
できる。As described above, in this embodiment, a fine uneven layer is formed on the surface of the electrically insulating substrate 1 by the sand blast method or polishing, so that the fine surface is formed on the surface of the electrically insulating substrate 1 and the thin film metal electrode 4. Since the rough surface 2 and the rough surface 8 of the concavo-convex layer are formed, the circuit-formed board in the first embodiment can be easily manufactured.
【００２７】（実施例３）以下、本発明の第３の実施例
について図面を参照しながら説明する。(Embodiment 3) A third embodiment of the present invention will be described below with reference to the drawings.
【００２８】第３の実施例は第２の実施例における回路
形成基板の製造方法を改良したものである。第３の実施
例における回路形成基板の製造方法は、第２の実施例に
おける回路形成基板の製造方法と略同等であるが、電気
絶縁性基板１の表面に微細な凹凸層の粗面２を形成せず
に、薄膜金属電極４の表面に微細な凹凸層の粗面８を形
成するものである。The third embodiment is an improvement of the method for manufacturing the circuit-forming board in the second embodiment. The method for manufacturing the circuit-forming board in the third embodiment is substantially the same as the method for manufacturing the circuit-forming board in the second embodiment, except that the rough surface 2 of the fine uneven layer is formed on the surface of the electrically insulating substrate 1. The rough surface 8 of the fine concavo-convex layer is formed on the surface of the thin film metal electrode 4 without forming it.
【００２９】図３は回路形成基板の製造方法を示す工程
図である。図３（Ａ）、（Ｂ）に示すように、回路形成
基板の製造方法は、薄膜金属電極４と電気絶縁性基板１
との密着性を高めるために、電気絶縁性基板１上に厚さ
０．０５μｍ程度のＣｒやＮｉからなる密着層９を形成
する第１工程と、このＣｒやＮｉからなる密着層９上に
厚さ０．３〜２μｍ程度のＡｌやＣｕからなる薄膜金属
電極４を形成し、フォトエッチングによって所望の配線
パターンに加工する第２工程と、この薄膜金属電極４の
表面に厚さ１μｍのＮｉからなるメッキ層１０を形成す
る第３工程と、高圧ガスによってガラスやＳｉＣなどの
微粒子を吹きつけるサンドブラスト法や粒径１μｍ程度
のアルミナ微粒子などによる研磨によってＮｉからなる
メッキ層の表面に０．０５〜１μｍ程度の微細な凹凸層
の粗面２を形成する第４工程と、この粗面８上に腐食防
止のために厚さ０．１μｍ程度のＡｕからなるメッキ層
１０を形成する第５工程とを有した構成である。この工
程後に、図３（Ｃ）に示すように、メッキ層とＡｕから
なるバンプ６を介して薄膜金属電極４に電気的に接合す
る半導体ＩＣ５を電気絶縁性基板１に紫外線硬化樹脂で
ある接着樹脂７によって加圧接着する工程を有して、回
路形成基板に半導体ＩＣ５を実装する。FIG. 3 is a process diagram showing a method of manufacturing a circuit board. As shown in FIGS. 3 (A) and 3 (B), a method for manufacturing a circuit-formed substrate includes a thin-film metal electrode 4 and an electrically insulating substrate 1.
In order to enhance the adhesion with the first step of forming an adhesion layer 9 made of Cr or Ni with a thickness of about 0.05 μm on the electrically insulating substrate 1, and on the adhesion layer 9 made of Cr or Ni. The second step of forming a thin film metal electrode 4 made of Al or Cu having a thickness of about 0.3 to 2 μm and processing it into a desired wiring pattern by photoetching, and a Ni film having a thickness of 1 μm on the surface of the thin film metal electrode 4. The third step of forming the plating layer 10 made of Ni, the sand blasting method in which fine particles of glass, SiC, or the like are blown by high-pressure gas, or the polishing with alumina fine particles having a particle size of about 1 μm A fourth step of forming a rough surface 2 of a fine uneven layer having a thickness of about 1 μm, and a fifth step of forming a plating layer 10 of Au having a thickness of about 0.1 μm on the rough surface 8 for preventing corrosion. It is configured to have a door. After this step, as shown in FIG. 3C, a semiconductor IC 5 that is electrically bonded to the thin film metal electrode 4 through the plating layer and the bump 6 made of Au is bonded to the electrically insulating substrate 1 by an ultraviolet curable resin. The semiconductor IC 5 is mounted on the circuit forming substrate by a step of pressure bonding with the resin 7.
【００３０】上記構成による回路形成基板について、以
下その特性を説明する。実施例２における回路形成基板
の製造方法において、薄膜金属電極４と電気絶縁性基板
１との間で、薄膜金属電極４の剥離の恐れがない場合
は、本実施例のように薄膜金属電極４上に直接微細な凹
凸層の粗面８を形成することにより、回路形成基板の製
造方法をより容易にすることができる。The characteristics of the circuit-formed board having the above structure will be described below. In the method for manufacturing a circuit-formed substrate according to the second embodiment, when there is no risk of peeling of the thin-film metal electrode 4 between the thin-film metal electrode 4 and the electrically insulating substrate 1, the thin-film metal electrode 4 is used as in the present embodiment. By directly forming the rough surface 8 of the fine concavo-convex layer on the top, the manufacturing method of the circuit forming substrate can be made easier.
【００３１】このように本実施例によれば、薄膜金属電
極４と電気絶縁性基板１との間で、薄膜金属電極４の剥
離の恐れがない場合は、薄膜金属電極４上に直接微細な
凹凸層の粗面８を形成することにより、回路形成基板の
製造方法をより容易にすることができる。As described above, according to the present embodiment, when there is no fear of peeling of the thin film metal electrode 4 between the thin film metal electrode 4 and the electrically insulating substrate 1, the fine metal film 4 can be directly finely laid on the thin film metal electrode 4. By forming the rough surface 8 of the concavo-convex layer, the manufacturing method of the circuit forming substrate can be made easier.
【００３２】[0032]
【発明の効果】以上のように本発明によれば、電気絶縁
性基板上に薄膜金属電極を形成することにより回路形成
基板の小型化を図りつつ、薄膜金属電極と電気絶縁性基
板との密着強度を大きくして、薄膜金属電極の剥離防止
と、バンプと薄膜金属電極の間への接着樹脂の流入防止
およびバンプと薄膜金属電極との接合力を強めて、接触
抵抗が大きくなることの防止をした信頼性の高い回路形
成基板を提供することができるものである。As described above, according to the present invention, by forming a thin film metal electrode on an electrically insulating substrate, it is possible to reduce the size of the circuit-forming substrate, and at the same time, to adhere the thin film metal electrode to the electrically insulating substrate. Increase strength to prevent peeling of thin-film metal electrodes, prevent inflow of adhesive resin between bumps and thin-film metal electrodes, and strengthen bonding force between bumps and thin-film metal electrodes to prevent contact resistance from increasing. Thus, it is possible to provide a highly reliable circuit forming substrate.
【図１】本発明の第１の実施例における電子部品を搭載
した回路形成基板を示す断面図FIG. 1 is a cross-sectional view showing a circuit-forming board on which an electronic component according to a first embodiment of the present invention is mounted.
【図２】本発明の第２の実施例における電子部品を搭載
した回路形成基板の製造方法を示す工程図FIG. 2 is a process diagram showing a method for manufacturing a circuit-formed board on which electronic components are mounted according to a second embodiment of the present invention.
【図３】本発明の第３の実施例における電子部品を搭載
した回路形成基板の製造方法を示す工程図FIG. 3 is a process chart showing a method for manufacturing a circuit-formed board on which an electronic component is mounted according to a third embodiment of the present invention.
【図４】従来の電子部品を搭載した回路形成基板を示す
断面図FIG. 4 is a cross-sectional view showing a circuit-forming board on which a conventional electronic component is mounted.
１ 電気絶縁性基板 ２ 粗面 ３ 表面強化処理層 ４ 薄膜金属電極 ５ 半導体ＩＣ ６ バンプ ７ 接着樹脂 ８ 粗面 ９ 密着層 １０ メッキ層 1 Electrical Insulating Substrate 2 Rough Surface 3 Surface Reinforcement Treatment Layer 4 Thin Film Metal Electrode 5 Semiconductor IC 6 Bump 7 Adhesive Resin 8 Rough Surface 9 Adhesion Layer 10 Plating Layer
Claims (5)
の表面に設けた薄膜金属電極と、前記薄膜金属電極にバ
ンプを介して電気的に接合した電子部品とを備え、前記
薄膜金属電極の表面に凹凸層を形成した回路形成基板。1. An electrically insulating substrate, a thin film metal electrode provided on a surface of the electrically insulating substrate, and an electronic component electrically bonded to the thin film metal electrode via a bump, wherein the thin film metal electrode is provided. A circuit-formed substrate with a concavo-convex layer formed on its surface.
の表面に凹凸層を形成した請求項１記載の回路形成基
板。2. The circuit forming substrate according to claim 1, wherein an uneven layer is formed on the surface of the electrically insulating substrate which is in contact with the thin film metal electrode.
に表面強化処理層を有した請求項２記載の回路形成基
板。3. The circuit-forming board according to claim 2, further comprising a surface-strengthening treatment layer on an upper layer portion of the electrically insulating substrate including the uneven layer.
形成し、前記薄膜金属電極にバンプを介して電子部品を
接合する工程において、前記電気絶縁性基板の表面に前
記薄膜金属電極を形成する前に、前記電気絶縁性基板の
表面に微細な凹凸層を形成する凹凸層形成工程を有した
回路形成基板の製造方法。4. A thin-film metal electrode is formed on the surface of an electrically insulating substrate, and the thin-film metal electrode is formed on the surface of the electrically insulating substrate in the step of joining an electronic component to the thin-film metal electrode via a bump. The method for producing a circuit-formed board, comprising a step of forming a fine uneven layer on the surface of the electrically insulating substrate before the step.
凹凸層を含んだ上層部に表面強化処理層を形成する表面
強化処理工程を設ける請求項４記載の回路形成基板の製
造方法。5. The method for producing a circuit-formed substrate according to claim 4, further comprising a surface-strengthening treatment step of forming a surface-strengthening treatment layer on an upper layer portion of the electrically insulating substrate including the unevenness layer, after the unevenness layer formation step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5336351A JPH07201917A (en) | 1993-12-28 | 1993-12-28 | Circuit formation board and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5336351A JPH07201917A (en) | 1993-12-28 | 1993-12-28 | Circuit formation board and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07201917A true JPH07201917A (en) | 1995-08-04 |
Family
ID=18298232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5336351A Pending JPH07201917A (en) | 1993-12-28 | 1993-12-28 | Circuit formation board and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07201917A (en) |
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| US7705315B2 (en) | 1998-06-18 | 2010-04-27 | Hamamatsu Photonics K.K. | Scintillator panel and radiation image sensor |
| US7994636B2 (en) | 2000-03-10 | 2011-08-09 | Stats Chippac, Ltd. | Flip chip interconnection structure |
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| JP4903966B2 (en) * | 2000-03-10 | 2012-03-28 | スタッツ・チップパック・インコーポレイテッド | Flip chip bonding structure and method for forming flip chip bonding structure |
| US10388626B2 (en) | 2000-03-10 | 2019-08-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming flipchip interconnect structure |
| US6538335B2 (en) | 2001-01-29 | 2003-03-25 | Nec Corporation | Semiconductor apparatus and a semiconductor device mounting method |
| KR100688755B1 (en) * | 2005-03-21 | 2007-03-02 | 삼성전기주식회사 | Method for forming solder ball pad in BGA printed circuit board and BGA printed circuit board manufactured therefrom |
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| US8987901B2 (en) | 2007-11-01 | 2015-03-24 | Dai Nippon Printing Co., Ltd. | Component built-in wiring board and manufacturing method of component built-in wiring board |
| JP2009130095A (en) * | 2007-11-22 | 2009-06-11 | Dainippon Printing Co Ltd | Part built-in wiring board, and manufacturing method for part built-in wiring board |
| JP2011159725A (en) * | 2010-01-29 | 2011-08-18 | Toppan Printing Co Ltd | Base for solar cell module, method of manufacturing the same, and solar cell module |
| JP2012023528A (en) * | 2010-07-14 | 2012-02-02 | Daishinku Corp | Piezoelectric vibrating piece and piezoelectric transducer |
| US8773844B2 (en) | 2010-12-28 | 2014-07-08 | Industrial Technology Research Institute | Solid electrolytic capacitor |
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