JP2009123762A - Semiconductor memory and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable nonvolatile semiconductor memory wherein the variation between devices and the malfunction scarcely occur and the power consumption is suppressed. <P>SOLUTION: This nonvolatile semiconductor memory comprises a semiconductor layer 100 of a first conductivity type formed on an insulator, a charge storage film 103 having a charge storage function formed on the semiconductor layer 100 and a gate electrode 105a formed on the charge storage film 103, a channel region 108 formed in the semiconductor layer 100 under the gate electrode 105a, diffusion regions 106 and 107 of a second conductivity type formed within the semiconductor layer 100 and on both sides of the channel region 108, a body contact region 109 of the first conductivity type formed by extending the semiconductor layer 100, and a gate electrode leader 105b which extends the gate electrode 105a onto the extended semiconductor layer 100 and separates the body contact region 109 and the diffusion regions 106, 107 on both sides of the channel region 108. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device formed on an insulator such as a glass substrate and a manufacturing method thereof.

A conventional semiconductor memory device formed on an insulator will be described. FIG. 11 is a cross-sectional view of one form thereof. A semiconductor layer 901 is provided over the insulating substrate 900, and a memory film and a gate electrode 905 are formed thereover. The memory film is, for example, a two-layer structure of a first insulating film 902 such as a silicon oxide film, a charge storage film 903 such as a silicon nitride film, or a second insulating film such as a silicon oxide film as shown in FIG. A three-layer structure including a film 904 is taken. In the semiconductor layer 901 on both sides of the gate electrode 905, an n-type doped source region 906 and drain region 907 are formed. If necessary, a selection transistor made of a TFT is appropriately provided adjacent to the memory cell (not shown).
In the writing to the semiconductor memory device, a positive high voltage is applied to the gate electrode 905 and the drain electrode 907, current is passed between the source region 906 and the drain region 907, hot electrons are generated, and this is stored in the charge storage film. This is done by injecting into 903.
When a read voltage is applied to the gate electrode 905 and the drain region 907 in a state where electrons are stored in the charge storage film 903, a read current flowing between the source region 906 and the drain region 907 causes the stored electrons in the charge storage film 903 to be stored. Due to the influence of the potential, it becomes smaller than when there is no stored electron. Therefore, the accumulated charge state of the charge accumulation film 903 is reflected as the magnitude of the read current, so that information can be written and read.
In the erase operation, a high negative erase voltage is applied to the gate electrode 905, holes are injected into the charge storage film 903 by FN tunneling, and stored electrons are erased (Patent Document 1).

However, in the semiconductor memory device described above, the semiconductor layer 901 (body) is in a floating state and the controllability of the potential is poor, which may cause variation in operation and malfunction. Therefore, in order to improve this, Patent Document 2 proposes a semiconductor memory device having a body contact. This is shown in FIG.
In this semiconductor memory device, the semiconductor layer 901 is thick in one or both of the source region 906 and the drain region 907, and another region of the semiconductor layer 901 is highly doped with an impurity having the same conductivity type as that of the semiconductor layer. The body contact region 909 is provided. The source region 906 or the drain region 907 and the body contact region 909 are separated by a field oxide film 917 for element isolation. The semiconductor layer 901 is formed from the body contact 909 via the semiconductor layer 901 under the field oxide film 917. The potential is controlled.
JP-A-4-313274 JP-A-8-172199

As described above, since the body potential of the semiconductor memory device of Patent Document 1 is unstable and there is a risk of characteristic variation or malfunction, the semiconductor memory device of Patent Document 2 is provided with a body contact as shown in FIG.
However, the semiconductor memory device of Patent Document 2 has a complicated structure in which the film thickness of the semiconductor layer 901 is changed in the channel portion 908, and the structure itself is likely to vary between devices during manufacturing. The resulting characteristic variation becomes a problem. That is, since the inclined portion is provided on the surface of the semiconductor layer 901 by photolithography and etching, and then the gate electrode 905 is formed by deposition of the material film, photolithography and etching, the positional relationship between the inclined portion and the gate electrode 905 is , And changes due to misalignment of photolithography. For example, in the case of the structure as shown in FIG. 12, when the gate electrode 905 is formed relatively leftward in the drawing, the thick portion of the semiconductor layer 901 in the channel 908 increases. In the case where it is formed on the right side, a thin portion of the semiconductor layer 901 in the channel 908 increases. As described above, the lithography misalignment affects the distribution of the film thickness of the semiconductor layer in the channel 908 portion, which also affects the characteristics of the device. In other words, there is a problem that the misalignment of lithography causes the device characteristics to vary.
Further, in the technique of Patent Document 2 using an etching technique to obtain a structure in which the thickness of the semiconductor layer 901 is changed in the channel part 908, the surface of the channel part 908 is exposed to etching during processing. Since the device is damaged, the device characteristics are deteriorated, which also causes variation in the characteristics. Furthermore, variation in the shape of the inclined portion also causes variation in characteristics.

  The present invention solves the above-described problems, and provides a semiconductor memory device that is highly reliable and that suppresses power consumption, in which device-to-device variations and malfunctions do not easily occur. The present invention also provides a semiconductor memory device that can be manufactured easily without using a special process while reducing costs. Furthermore, the present invention provides a semiconductor memory device with high reliability and low power consumption.

  In order to solve the above problems, a semiconductor memory device according to a first invention includes a first conductivity type semiconductor layer formed on an insulator and a charge storage film having a charge storage function formed on the semiconductor layer. And a gate electrode formed on the charge storage film, a channel region formed in the semiconductor layer below the gate electrode, and a second conductivity type formed in the semiconductor layer on both sides of the channel region. A diffusion region, a body contact region of a first conductivity type formed by extending the semiconductor layer, the gate electrode extending on the extended semiconductor layer, the body contact region, and both sides of the channel region A gate electrode lead portion for separating the diffusion region.

According to the above invention, the body potential is controlled from the body contact region, and excess carriers generated during operation are quickly discharged, thereby stabilizing the body potential and preventing variation in operation and malfunction. In addition, since the body potential can be controlled, at the time of erasing, high-speed erasing can be performed in which hot carriers are generated by applying a reverse bias to the body (storage layer) and the diffusion region.
In addition, since the body contact region and the diffusion region are separated by the gate electrode lead portion, a voltage corresponding to a reverse bias is applied between the body contact and the diffusion region during writing or erasing. However, the reverse leakage current of the junction is suppressed and the increase in power consumption is prevented. This leakage current also prevents the body potential from becoming unstable and malfunctioning.

The semiconductor layer of the first conductivity type is a p-type semiconductor, and the Fermi level is such that the gate electrode is higher than the Fermi level of the p-type semiconductor and lower than the lower end of the conduction band of the p-type semiconductor layer. It consists of the material which has.
In another embodiment, the semiconductor layer of the first conductivity type is an n-type semiconductor, and the gate electrode is lower than the Fermi level of the n-type semiconductor. It is made of a material having a Fermi level that is higher than the upper end of the charged electron band.
By using such a gate electrode material, when the gate of the memory cell of the non-selected cell is at an off potential, the semiconductor layer under the gate electrode is almost in a carrier depletion state due to the potential of the gate electrode. As a result, the body contact region and the diffusion region are separated by the depleted semiconductor layer, so that a leakage current can be suppressed even when a voltage corresponding to a reverse bias is applied between them. The above effect can be obtained without applying a special voltage to the gate electrode in the standby state, and the above effect can be obtained only by turning the gate to a normal OFF state. Therefore, the above effect can be obtained without using a special circuit.

The semiconductor memory device according to one embodiment of the present invention is characterized in that the insulator is a glass substrate.
Thereby, it can be manufactured at a lower cost than using a single crystal substrate or an SOI substrate. Particularly in this case, since only a relatively low-temperature process is used for manufacturing the device, the semiconductor layer contains many crystal defects. However, in the semiconductor memory device of this embodiment, this crystal is also written and erased. Leakage current due to defects is small, preventing an increase in power consumption as much as possible.

The semiconductor memory device according to an embodiment of the present invention is characterized in that the semiconductor layer is formed in an island shape, and an end portion of the gate electrode lead-out portion is formed to coincide with an end portion of the island-shaped semiconductor layer. To do.
Thus, since the gate electrode lead portion is disposed without straddling the semiconductor layer end, the memory film destruction due to the electric field concentration at the semiconductor layer end and the memory film destruction due to the structural defect are prevented. For this reason, the memory film can be thinned and can be operated at a lower voltage, so that power consumption can be reduced and peripheral circuits can be simplified. Therefore, it can be used as a semiconductor memory device of a display device.

The semiconductor memory device according to an embodiment of the present invention is characterized in that the gate electrode lead portion has a portion disposed so as to surround the body contact region.
Also in this structure, since the gate electrode lead portion is arranged without straddling the semiconductor layer end, the memory film destruction due to the electric field concentration at the semiconductor layer end and the memory film destruction due to the structural defect are prevented. For this reason, the memory film can be thinned and can be operated at a lower voltage, so that power consumption can be reduced and peripheral circuits can be simplified. In addition to this, the body contact portion is surrounded by the gate electrode lead-out portion and is partitioned from the diffusion region. Therefore, even when a voltage corresponding to a reverse bias is applied between the body contact and the diffusion region at the time of writing or erasing, a junction reverse leakage current is suppressed and an increase in power consumption is prevented. This leakage current also prevents the body potential from becoming unstable and malfunctioning. Since the semiconductor memory device of this embodiment has a simple structure and can be easily manufactured without using a special process or the like, the variation in characteristics due to the variation in structure at the time of manufacture and the decrease in yield are prevented as much as possible. be able to. Moreover, since it can manufacture simply, the increase in manufacturing cost is also prevented.

The semiconductor memory device according to one embodiment of the present invention is characterized in that the charge storage film includes, in order from the semiconductor layer side, a first insulating film, an insulator having a charge storage function, and a second insulating film. To do.
With this structure, the accumulated charge is prevented from flowing out to the outside by the first insulating film and the second insulating film, which is suitable for long-term holding. In addition, since charges are held in the insulator, even if a part of the first insulating film or the second insulating film is damaged, the accumulated charge does not flow out from the damaged portion at once. High reliability.

In one embodiment of the present invention, the body contact region has a portion that is close to the semiconductor layer region below the gate electrode lead portion or overlaps the gate electrode lead portion. Features.
As a result, when performing an erase operation, carriers flow from the body contact region to the semiconductor layer under the gate electrode to form a storage layer, and a low-resistance current from the position where carriers are generated during erase to the body contact region Since a route is formed, stable and high-speed erasure is possible.

The semiconductor memory device according to an embodiment of the present invention is characterized in that a thin film transistor further including a gate insulating film, a gate electrode, a second conductivity type diffusion region, a channel region, and a body contact region is formed on the insulator. To do.
With the above configuration, by providing body contact regions in both the circuit thin film transistor and the memory cell, it is possible to control the body potential in both of them and suppress variation in characteristics. Whether the memory cell is in a written state or an erased state is determined by a sensing operation using a thin film transistor in the peripheral circuit. If the variation in the thin film transistor for the peripheral circuit is large, erroneous reading may be caused. In this embodiment, the body contact region is also provided in the peripheral circuit thin film transistor to control the body potential, thereby suppressing variation between devices and reducing the reading window (read current difference between the write state and the erase state) relatively small. It can be judged correctly. Therefore, a highly reliable semiconductor memory device can be obtained even when held for a long time. In the semiconductor memory device of this embodiment, the gate electrode lead-out portion does not protrude from the semiconductor layer in both the thin film transistor portion and the memory portion easily without using a special process or the like, and is diffused with the body contact region. The region can be separated from the region by the gate electrode lead portion.

In one embodiment, the gate electrode lead portion extended from the gate electrode has a ring-shaped portion surrounding the body contact region.
With this structure, the gate electrode lead-out portion of the thin film transistor is disposed without straddling the semiconductor layer end, so that the memory film destruction due to the electric field concentration at the semiconductor layer end and the memory film destruction due to the structural defect are prevented.

One embodiment of a method for manufacturing a semiconductor memory device according to the present invention is a method for manufacturing the semiconductor memory device, wherein a semiconductor layer, a film having a charge storage function, and a gate electrode material are deposited on an insulator. A gate electrode for separating a source / drain region and a gate electrode leading portion for separating a source / drain region and a body contact region by patterning the film having the charge storage function and the gate electrode material with the same mask pattern It has the process of processing.
By the above manufacturing method, the gate electrode end of the memory cell and the semiconductor layer end can be matched without being affected by misalignment in the photo process, and the semiconductor memory device of the present invention can be easily manufactured. For this reason, manufacturing cost can be suppressed low.

As described above, according to the present invention, a memory cell having a body contact region is formed on an insulator such as a glass substrate, and in the memory cell, while suppressing a reverse junction leakage current, the memory film Therefore, it is possible to obtain a semiconductor memory device with high reliability and low power consumption, in which device-to-device variations and malfunctions are unlikely to occur. Further, since the semiconductor memory device of the present invention is formed over an insulator such as a glass substrate, the cost can be reduced as compared with a semiconductor device using a single crystal substrate or the like. Further, the structure of the present invention can be easily manufactured without using a special process, so that it can be obtained without significantly increasing the manufacturing cost.
Further, a thin film transistor used for the peripheral circuit is also provided with a body contact region by applying a similar structure, whereby a semiconductor memory device with higher reliability and lower power consumption can be obtained.

Hereinafter, the present invention will be described in detail with reference to the drawings. In the following description, a p-type device will be mainly described, but an n-type device may be used. In the case of an n-type device, in the following description, the conductivity type of the impurity may be a reverse conductivity type, and the applied voltage may be a reverse bias. However, as described below, when a substrate having low heat resistance such as a glass substrate is used, a low-temperature process is used in the manufacture. It is preferable to form a memory cell as a type device because writing and erasing can be repeatedly and stably performed and reliability is higher.
In the case of a p-type device mainly described below, a state in which holes are accumulated in a charge storage film, and a state in which electrons are accumulated in an n-type device is defined as a writing state. An erased state is a state in which almost no electrons or holes are accumulated, a state in which electrons and holes are accumulated to the same extent and are electrically neutralized, or a carrier of the opposite type to the written state (of a p-type device). In the case of an n-type device, a hole is mainly accumulated.

(First embodiment)
The configuration of the semiconductor memory device according to the first embodiment will be described with reference to FIGS. FIG. 1A is a schematic bird's-eye view of a memory cell portion in the present embodiment, and FIG. 1B is a schematic plan view thereof. FIG. 2 is a schematic cross-sectional view, and FIG. 2A shows a cross section taken along a dotted line AA ′ in FIG. 1 and FIG. 2B shows a cross section taken along BB ′.

In the semiconductor memory device of the first embodiment, an n-type semiconductor layer 101 such as silicon having a thickness of about 50 nm is provided in an island shape on an insulating substrate 100 made of large area flat glass. For example, when the insulating substrate 100 is a substrate for a liquid crystal display device, the place where the semiconductor layer 101 is arranged in an island shape is below or near each liquid crystal display pixel electrode. The insulating substrate 100 can be a resin substrate or a substrate in which an insulating film is provided on the surface of a semiconductor substrate, that is, the substrate surface only needs to be an insulator. For example, the insulating substrate 100 and the semiconductor layer 101 can be obtained by processing the silicon layer on the surface into an island shape using an SOI (silicon-on-insulator) substrate. On the semiconductor layer 101, a memory film composed of three layers, a first insulating film 102, a charge storage insulating film 103, and a second insulating film 104, and a gate electrode 105 are sequentially deposited. As the memory film, the second insulating film 104 can be omitted as a two-layer structure of the first insulating film 102 and the charge storage insulating film 103, but from the viewpoint of charge retention performance, a three-layer structure is desirable as described above.
These three layers of the first insulating film 102, the charge storage insulating film 103, and the second insulating film 104 are patterned in substantially the same planar shape, for example, like a T shape, and the end portion protrudes from the island-shaped semiconductor layer 101. And formed so as to coincide with the end portions of the island-shaped semiconductor layer 101, and these divide the semiconductor layer 101 into three regions. That is, there are three regions: a region including the diffusion region 106, a region including the diffusion region 107, and a region including the body contact region 109. The diffusion regions 106 and 107 are highly doped to be p-type, and these become the source region and the drain region of the memory cell. A channel region 108 is formed in the semiconductor layer 101 between them, and has a MOS transistor-like structure together with the gate electrode 105 thereon (see FIG. 2A).

  Further, another region of the semiconductor layer 101 separated by the gate electrode lead-out portion 105b is n-type heavily doped to form a body contact region 109. The gate electrode 105a and the gate electrode lead-out portion 105b are continuously integrated to form the gate electrode 105, and there is no clear boundary. However, the portion where the channel region is formed between the source and drain regions is the gate electrode 105a, and the channel A portion outside the region is the gate electrode lead portion 105b. The width of the gate electrode 105a is several tens of nanometers to several tens of micrometers, and determines the gate length. The width of the gate electrode lead-out portion 105b is about 100 nm to 100 μm, more preferably 1 μm to 20 μm, and separates the body contact region and the semiconductor memory device region. Contact plugs 110, 111, 112, and 113 are provided in the diffusion regions 106 and 107, which serve as source / drain regions, the gate electrode lead-out portion 105 b, and the body contact region 109, respectively. And only the bottom position is shown).

  In the above, as the first insulating film 102, the charge storage insulating film 103, and the second insulating film 104 constituting the memory film, a silicon oxide film, a silicon nitride film, a hafnium oxide film, a zirconium oxide film, an aluminum oxide film, or the like is used. Can be used. For the first insulating film 102 and the second insulating film 104, a combination in which the charge storage insulating film 103 has a higher charge trap density and a smaller or similar band gap may be selected. For example, a silicon oxide film may be used as the first insulating film 102 and the second insulating film 104, and a silicon nitride film may be used as the charge storage insulating film 103. This configuration is also a film material used in a general semiconductor device production line, and is advantageous in reducing production costs.

Although these films can be formed by a well-known CVD method, in this embodiment, an inexpensive glass substrate or the like is used as a substrate without using an expensive single crystal semiconductor substrate. Although the use of a glass substrate enables low-cost production, it is preferable to use a plasma CVD method, which is a relatively low-temperature process, because the substrate has low heat resistance.
The first insulating film 102 can be formed by oxidizing the semiconductor layer 101 and can be formed by a wet oxidation method using an oxidizing aqueous solution such as hydrogen peroxide. As the charge storage insulating film 103, in addition to the above, a film in which fine dots of silicon or metal are contained inside an insulating film such as a silicon oxide film can also be used.
As the gate electrode 105, polysilicon doped with impurities of the same type as the diffusion regions 106 and 107, or a metal such as tungsten or molybdenum can be used. The gate electrode 105 is preferably made of a material having such a property that its Fermi level is lower than the Fermi level of the n-type semiconductor layer 101 and higher than the upper end of the valence band of the n-type semiconductor layer 101. In the case where the semiconductor layer 101 is n-type, a material having a Fermi level that is higher than the Fermi level of the semiconductor layer 101 and lower than the lower end of the conduction band is preferable. As a result, the semiconductor layer 101 under the gate electrode 105 is in a carrier depletion state when the potential of the gate electrode 105 is in an off state, and the merit of this embodiment described later is effectively exhibited.

The film thickness of the memory film may be appropriately determined according to the specifications of the semiconductor memory device. Generally speaking, the film thickness of the first insulating film 102 is about 3 nm to 20 nm, and the film thickness of the charge storage film insulating film 103 is 5 nm. The film thickness of the second insulating film 104 is set in a range of about 3 nm to 50 nm. If these films are set thin, writing or erasing can be performed at a low voltage, and power consumption can be reduced. In particular, the first insulating film 102 is preferably set thinner than the second insulating film 104. The thinner the first insulating film 102, the higher the carrier injection efficiency and the higher the writing or erasing speed. On the other hand, the second insulating film 104 is thicker than the first insulating film 102 to prevent carriers from being exchanged between the charge storage insulating film 103 and the gate electrode 105. This is advantageous. On the other hand, if these films are too thin, accumulated charges may flow out, or there may be a disturb problem that causes erroneous writing or erasing in a read operation.
Therefore, in this embodiment, the first insulating film thickness is 6 nm, the second insulating film thickness is 10 nm, the silicon nitride film is used as the charge storage insulating film 103, and the film thickness is 10 nm. With this stacked structure, the charges accumulated in the charge storage insulating film 103 are prevented from leaking to the outside as much as possible, and can be held for a long time. That is, it is preferable from the viewpoint of low power consumption to make the memory film as thin as possible within a range that does not impair the stability of the memory function. The semiconductor memory device according to the present embodiment maintains high reliability such that the memory film is not easily broken even if the memory film is thinned, and prevents junction leakage current and does not hinder low power consumption. This advantage will be described in detail later.

Reading of stored information in the semiconductor memory device of the present embodiment utilizes the fact that the amount of charge in the charge storage insulating film 103 affects the amount of drive current between the diffusion regions 106 and 107. That is, for example, when the diffusion region 106 is used as a source and the diffusion region 107 is used as a drain, a ground potential is applied to the diffusion region 106 serving as a source, and a read drain voltage (for example, −4 V) is applied to the diffusion region 107 serving as a drain. A read gate voltage (for example, −4 V) is applied to the electrode 105. As a result, a current flows through the channel region 108 between the diffusion region 106 serving as the source and the diffusion region 107 serving as the drain. At this time, if holes are accumulated in the charge accumulation insulating film 103 in this writing state, the accumulated electrons cancel the influence of the electric field exerted on the channel region 108 by the gate electrode 105. Therefore, the current flowing between the diffusion region 106 serving as the source and the diffusion region 107 serving as the drain is smaller than that in the erased state (the state in which the accumulated electrons are substantially absent). That is, information storage can be stored and read by combining information storage with the amount of trapped charges in the charge storage insulating film 103 and reflecting this in the amount of drive current.
During the above read operation, the body potential control from the body contact region 109 may be in a floating state where no potential is applied, but by setting an appropriate potential such as a ground potential, hot holes generated during writing are discharged. Thus, the potential distribution inside the device is stabilized, and a stable read operation with little variation is possible.

A write operation to the semiconductor memory device is performed by injecting high energy carriers generated by operating a transistor at a higher voltage than the read operation. For example, this time, contrary to the above, the ground potential is applied using the diffusion region 107 as a source, and a write drain voltage (for example, −6 to −15 V) is applied using the diffusion region 106 as a drain. A write gate voltage (for example, −6 to −18 V) is applied to the gate electrode 105. At this time, a large current flows through the channel region 108 between the diffusion region 107 serving as the source and the diffusion region 106 serving as the drain, and heat is generated due to Joule heat and the temperature rises. Due to this temperature rise, a large amount of high energy carriers are generated. Some of the generated high-energy carriers run upward in the drawing due to the influence of the electric field of the gate electrode 105, jump into the charge storage insulating film 103, and are trapped. Thereby, a write state in which electrons are trapped in the charge storage insulating film 103 can be realized.
Note that an appropriate potential such as a ground potential may be applied to the body contact region 109 in the write operation. By applying the body voltage, carriers generated at the time of writing can be discharged from the body contact region to suppress fluctuations in the body potential, and stable writing with little variation can be performed. By the above writing operation, writing can be performed at higher speed than charge injection using an FN tunnel.

  In the erasing operation of the semiconductor memory device, a high potential (for example, +25 to 30 V) is applied to the gate electrode with respect to the body contact potential, so that the FN tunnel through the first insulating film causes the charge storage insulating film 103 to be erased. Although it can also be performed by injecting electrons, the following method can be used as a more preferable mode of erasing operation. That is, a ground potential or the like is applied to the body contact region 109, a negative erase voltage (for example, −8 to −15 V) is applied to the diffusion regions 106 and 107, and a positive erase voltage (for example, 5 to 5) is applied to the gate electrode 105. 20V) is applied. At this time, an electron storage layer is formed under the semiconductor layer 101 under the gate electrode 105, and a junction to which a strong reverse bias is applied is formed between the electron storage layer and the diffusion regions 106 and 107. At this time, a reverse leakage current is generated at the junction, and high-energy carriers are generated due to this current. Some electrons jump into the charge storage insulating film 103 due to the electric field of the gate electrode 105 and trap. Erases the charge of the electrons. Although the erasing operation is performed as described above, the erasing operation can be performed at a higher speed than the charge injection using the FN tunnel.

Note that the diffusion regions 106 and 107 serving as the source and drain partially overlap the gate electrode 105a on the side in contact with the channel region 108 (the side on which the source and drain are opposed) as shown in FIG. It is preferable. This prevents current reduction and malfunction due to parasitic resistance. The diffusion region 106 and the diffusion region 107 are preferably provided at a distance T of 0.3 μm or more from the gate electrode lead portion 105b as shown in FIG. For example, as a preferable form, the distance of about 0.5 μm to 5 μm can be provided. If the diffusion region 106 and the diffusion region 107 overlap with the gate electrode lead portion 105b, a current will also be generated through the semiconductor layer 101 below the gate electrode lead portion 105b during the read operation. In the operation, charge is injected into the charge storage insulating film 103 and the read current is affected by the charge mainly in the diffusion region 106 and the channel region 108 inserted in the diffusion region 107, via the semiconductor layer 101. All currents are a kind of leakage current that is not easily affected by electric charge. When the diffusion region 106 and the diffusion region 107 are separated from the gate electrode lead portion 105b by 0.3 μm or more, the leakage current under the gate electrode lead portion 105b can be suppressed, and the amount of accumulated charge is reduced to the read current. Since it is strongly reflected, stable reading is possible.
Further, it is preferable that at least a part of the body contact region 109 overlaps or is close to the gate electrode lead-out portion 105b as shown in FIG. As a result, when performing an erase operation, carriers flow from the body contact region to the semiconductor layer under the gate electrode to form a storage layer, and a low resistance from the position where carriers are generated during erase to the body contact region. Since a current path is formed, stable and high-speed erasure is possible.

  In the above description, the case where the memory cell is formed as a p-type device has been described. However, when glass is used as the insulating substrate 100 as in the present embodiment, the memory cell is thus used as the p-type device. Is preferably formed. When a glass substrate is used, there is a merit that it can be manufactured at a low cost, but the heat resistance of the substrate is low, and a high-temperature process cannot be used in manufacturing. In such a case, writing and erasing can be performed at high speed and stably when the memory cell is formed as a p-type device rather than when the memory cell is formed as an n-type device. When a memory cell is manufactured by a process at a relatively low temperature, there is a risk of damage to the insulating film of the memory cell or the interface between the insulating film and the semiconductor layer due to high energy carriers generated during writing or erasing. In the p-type device, this damage is less likely to occur and the memory cell is highly reliable. On the other hand, when manufacturing using a high-temperature process is possible, such as when using an SOI substrate, a highly reliable memory cell can be obtained even if an n-type device is used.

  Here, in this embodiment, the gate electrode lead portion 105b is installed without protruding from the island-shaped semiconductor layer 101, and the diffusion regions 106 and 107 and the body contact region 109 are separated by the gate electrode lead portion 105b. It is characterized by being. The advantages of this feature are described below.

FIG. 3 is a diagram in the case where the gate electrode lead-out end portion 117 is disposed so as to straddle the end portion of the island-shaped semiconductor layer 101 and to protrude from the semiconductor layer 101 unlike the present embodiment. FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along a dotted line CC ′ in FIG.
In such a structure, when a high voltage difference is applied between the semiconductor layer 101 and the gate electrode 105 particularly during an erase operation, an electric field tends to concentrate on the edge of the semiconductor layer 101. This is because the edge upper end 114a and the edge lower end 114b of the semiconductor layer 101 have corners as shown in the cross-sectional view of FIG. In the edge upper end 114a, the corner portion faces the gate electrode lead-out end portion 117, and the electric field is easily concentrated. On the other hand, the edge lower end 114b does not directly face the gate electrode lead-out end portion 117, but if the side surface is tapered during lithography processing of the semiconductor layer 101, the edge lower end 114b becomes an acute angle, and the electric field concentration is likely to occur. For this reason, the memory film may cause dielectric breakdown at these points. In order to prevent this, it is necessary to increase the thickness of the memory film, and accordingly, it is necessary to increase the operating voltage, resulting in an increase in power consumption.

  In addition, in the edge portion lower end 114b portion, there are cases where the glass substrate 100 in the vicinity is etched and the edge portion lower end 114b is bent due to various dry etching in the manufacturing process or wet etching with a hydrofluoric acid aqueous solution. . The CVD film is difficult to be deposited only on this portion, and the memory film may be specifically thinned. As a result, gate breakdown is caused and yield is lowered. In particular, in the process of forming a memory cell and a normal TFT on the same substrate, it is necessary to create a memory film for the memory cell portion and a gate insulating film for the TFT portion separately, so that etching is performed as compared with the case where only the TFT is formed. The number of processes is also large, and device breakdown is likely to occur due to shape defects in the edge portion of the semiconductor layer 101 as described above.

4 is a semiconductor memory device in which the gate electrode lead-out portion 105b is installed so as not to protrude from the semiconductor layer 101, unlike the semiconductor memory device in FIG. 3 described above. Unlike the semiconductor memory device of this embodiment, this semiconductor memory device has a structure in which the diffusion regions 106 and 107 and the body contact region 109 are not completely partitioned by the gate electrode lead portion 105b. That is, the body contact region 109 that is heavily n-type doped is continuous by the region of the n-type semiconductor layer 101 that is not covered by the gate electrode lead-out portion 105b, and further through this region, the p-type doped diffusion is performed. The regions 106 and 107 form a pn junction.
When the same write / erase operation as that of the semiconductor memory device of the present embodiment described above is applied to the semiconductor memory device of FIG. 4, one of the diffusion regions 106 and 107 is interposed via the n-type semiconductor layer 101 at the time of write / erase. A high reverse bias is applied between the body contact region 109 and both.

Here, when the semiconductor layer 101 is formed on the glass insulating substrate 100 as in the present embodiment, the crystallinity of the semiconductor layer is not high compared to the case of a semiconductor device using a single crystal substrate, and the crystal It contains many irregular crystal structures such as defects and crystal grain boundaries. In particular, when the insulating substrate 100 is made of a glass substrate, there is a merit that it can be produced at low cost, but only a relatively low temperature process can be used, so that the crystal defect density of the semiconductor layer 101 becomes larger. For this reason, even when a reverse bias is applied, a current easily flows through these defects, and a reverse junction leakage current 115 is generated. When a voltage is applied at the time of erasing, this leakage current 115 is a useless current that does not contribute to the actual erasing operation itself, and causes an increase in power consumption. In addition, when a body voltage is applied during writing, this reverse leakage current flows from the drain to the body, which is not only a useless current that does not contribute to the writing operation itself, but also deteriorates the controllability of the body potential and causes abnormal operation. There is also a possibility of causing.
Such a problem may also occur when a structure such as that of Patent Document 2 is formed on a glass substrate. This is because also in the structure of Patent Document 2, a junction is always formed between the diffusion region and the body. Since the body is made of a thin film semiconductor, the resistance of the body is high, and if a reverse leakage current is generated between the diffusion region and the body, the body potential becomes unstable and may cause malfunction. .

On the other hand, the semiconductor memory device of this embodiment has a planar structure shown in FIG. 2B, and this structure solves both of the problems in the cases of FIGS.
First, unlike the case of FIG. 3, in this embodiment, the gate electrode lead-out portion 105 b does not straddle the end of the semiconductor layer 101. For this reason, the memory film destruction at the end of the semiconductor layer 101 does not become a problem, and a high yield can be realized even if the memory film is thinned. If the memory film can be thinned, an electric field is efficiently applied to the memory film, so that the operating voltage can be lowered and the semiconductor memory device operates with low power consumption. In addition, since operation is possible at a low voltage, the peripheral circuit can be simplified and the circuit area can be reduced.

Further, unlike the case of FIG. 4, the semiconductor layer arrangement of the embodiment having the structure shown in FIG. 2 is a planar structure in which the diffusion regions 106 and 107 and the body contact region 109 are completely partitioned by the gate electrode lead portion 105b. It has become. For example, in a non-selected memory cell, when the gate electrode 105 is in a so-called off state such as the same potential as the source, the semiconductor layer 101 under the gate electrode 105 is depleted by the potential of the gate electrode 105. Therefore, the diffusion regions 106 and 107 and the body contact region 109 are separated by the depleted semiconductor layer.
This prevents a large reverse junction leak from occurring between the drain of the non-selected cell and the body contact region even when a write drain voltage is applied to the drain of the non-selected cell when writing to another cell. . As a material of the gate electrode 105, a material whose Fermi level is lower than the Fermi level of the n-type semiconductor layer 101 and higher than the upper end of the valence band is used, and thus a special voltage is applied to the gate electrode. (No special circuit is required), and such an effect can be obtained only by setting the normal OFF state.

  Also in the selected cell where data is written, the semiconductor layer between the body contact region and the diffusion region is depleted except for the upper part where the inversion layer is formed, so that reverse leakage in the vicinity of the channel region is suppressed, and the body potential is reduced. Stabilize and prevent variation.

In erasing, a negative erasing voltage is applied to the gate electrode 105 to use a reverse current flowing between the accumulation region generated in the semiconductor layer 101 under the gate electrode 105 and the diffusion regions 106 and 107. . Also in this case, by adopting the structure of the present embodiment, it is possible to reduce leaks that do not contribute to the erase operation as much as possible, so that power consumption can be reduced.
As described above, even when a reverse bias is applied between the diffusion regions 106 and 107 and the body contact region 109 at the time of writing or erasing, the leakage current is suppressed, and the semiconductor memory device that operates stably with low power consumption. It has become. This effect is also exhibited when a semiconductor memory device is formed on a glass substrate for the purpose of inexpensive manufacturing. In other words, the structure of this embodiment has an advantage that it can be widely applied in addition to the case where an expensive substrate such as SOI is used. Further, the body contact provided in the present embodiment can play a sufficient role for the stable operation of the memory.

  Next, a manufacturing method of the semiconductor memory device of this embodiment, particularly, a case where both memory cells and TFTs used for peripheral circuits and the like are formed on the same insulating substrate will be described. Here, only the PMOS is mentioned as the TFT to be formed, but the formation of the NMOS can also be easily realized by a combination with a known method. In the NMOS portion, the semiconductor layer is a p-type semiconductor, and the diffusion region is an n-type heavily doped layer. Further, in the figure, for convenience of explanation, the memory cell and the TFT are arranged adjacent to each other. However, in an actual semiconductor memory device, the layout may be freely made according to the necessity of circuit connection.

First, a semiconductor layer 101 made of n-type silicon or the like having a thickness of about 50 nm is formed on an insulating substrate 100 such as a glass substrate by a known method such as CVD. Further, as a memory film, the first insulating film 102 made of, for example, a silicon oxide film has a thickness of 6 nm and the charge storage insulating film 103 made of a silicon nitride film has a thickness of 10 nm by a well-known method such as CVD. A second insulating film 104 made of is deposited to a thickness of 10 nm. Further, a gate electrode 105 material film made of a metal such as tungsten is deposited. Thereafter, each layer from the gate electrode 105 material film to the semiconductor layer 101 is patterned into a desired shape by lithography and etching techniques.
The patterning here is processed into an island shape along the shape of the finally formed memory cell and the semiconductor layer of the TFT. This is shown in FIG. FIG. 5B is a cross-sectional view taken along the dotted line in FIG. The size of the semiconductor layer 101 processed into an island shape is set according to the performance and specifications of the memory cell and TFT, such as a square with a side of 1 μm to 100 μm and a rectangle with a size of 1 μm to 100 μm. . For example, when the insulating substrate 100 is a substrate for a liquid crystal display device, the island-shaped semiconductor layer 101 is disposed below or in the vicinity of each liquid crystal display pixel electrode.

Next, as shown in FIG. 6, the gate electrode 105 and the three-layer memory film (103 to 105) in the memory cell portion are processed by lithography using, for example, etching using a substantially T-shaped photoresist 116 as a mask. . At this time, as shown in FIG. 6A, the photoresist 116 is formed so as to protrude from the island-shaped semiconductor layer 101 with a margin corresponding to misalignment of the exposure machine. That is, both ends in the horizontal direction of the upper side of the T shape and the lower end in the vertical direction protrude from the semiconductor layer 101. Since the gate electrode 105 is formed in the overlap portion between the photoresist 116 and the semiconductor layer 101, the gate electrode 105 does not protrude from the semiconductor layer 101, and conversely, from the semiconductor layer 101 end to the gate electrode 105 end. Can be formed almost online without retreating.
On the other hand, at this time, in the TFT forming portion, the gate electrode 105 and the memory films 102 to 104 are completely removed, and the surface of the semiconductor layer 101 is exposed.

  Next, after depositing a silicon oxide film as a gate insulating film material for TFT and a metal such as tungsten as a gate electrode material for TFT on the entire surface, these are processed using lithography and etching techniques. For example, as shown in FIG. 7A, the TFT gate insulating film 202 and the TFT gate electrode 205 form a channel portion 205a that separates into a source region and a drain region, and a gate electrode lead portion 205b. The width of the gate electrode forming the channel portion 205a is several tens of nanometers to several tens of micrometers, and determines the channel length. The gate electrode lead portion 205b is not necessarily formed on the semiconductor layer 101, and may be formed on the insulating substrate 100 as shown in FIG. The gate electrode lead-out portion 205b may have a size that allows a contact plug to be installed.

  In this processing, the TFT gate electrode 205 is preferably etched by combining dry etching with strong directionality and isotropic dry etching with low directionality, and the side surface of the gate electrode 105 for the memory cell that has already been processed. In addition, the TFT gate electrode 205 is prevented from remaining in a sidewall shape as much as possible. Regarding the processing of the TFT gate insulating film 202, only directional dry etching is performed in order to improve the processing shape of the TFT gate insulating film 202. In this case, an insulating film remains in the shape of a sidewall on the side surface of the gate electrode of the memory cell (not shown). However, since this sidewall is a sufficiently thin film at the TFT gate insulating film level (several tens of nm), there is no problem. Although the deposited TFT gate electrode 205 material and TFT gate insulating film 202 material are both processed by etching here, only the TFT gate electrode 205 may be processed and the gate insulating film 202 may be left on the entire surface. In this case, the gate insulating film 202 remaining on the entire surface can serve as an implantation protective film in the subsequent implantation process.

Subsequently, the body contact region portion of the memory cell is masked by a masking using an photoresist and an ion implantation technique, and a p-type impurity is implanted into the diffusion region portion of the TFT and the memory cell. Next, n-type impurities are implanted into the body contact region of the memory cell by masking the diffusion region of the memory cell. Thereafter, annealing is performed to form p-type diffusion regions 106 and 107 of the memory cell, p-type diffusion regions 206 and 207 of the TFT, and n-type body contact region 109 of the memory cell, respectively. Due to diffusion during annealing, each region slightly penetrates under the gate electrode and overlaps with a part of the gate electrode.
Further, after forming an interlayer insulating film on the entire surface, contact holes are opened by lithography and etching, and metal plugs are embedded, so that contact plugs 110 and 111 in the source / drain region of the memory cell, contact plugs 112 in the gate electrode, body Contact plug 113 in the contact region, contact plugs 210 and 211 in the source / drain region of the TFT, and contact plug 212 in the gate electrode are formed, respectively. These contact plugs are connected to each other by metal wiring on the interlayer insulating film to form a memory circuit (both FIGS. 8A and 8B, the interlayer insulating film and the upper metal wiring are not shown).

As described above, the gate electrode end of the memory cell and the semiconductor layer end can be easily matched without requiring a complicated process and without being affected by misalignment of the exposure apparatus. The structure of the semiconductor memory device of this embodiment in which the diffusion region and the body contact region are separated without protruding can be obtained.
In the above description, after the memory films 102 to 104 and the gate electrode 105 of the memory cell are formed, the gate insulating film 202 and the gate electrode 205 of the TFT portion are formed. Conversely, the gate insulating film 202 and the gate of the TFT portion are formed. After forming the electrode 205, the memory films 102 to 104 and the gate electrode 105 of the memory cell may be formed. Although omitted in the above embodiment, a p-type (thin n-type thin in NMOS) region, a so-called LDD region, which is thinner than the diffusion region, is provided at the gate electrode side end of the TFT diffusion region by a known method. The breakdown voltage of the TFT can be improved.

(Second Embodiment)
FIG. 9A is a plan view of the semiconductor memory device of the second embodiment, and FIG. 9B shows a cross-sectional view taken along the dotted line in the figure. In the second embodiment, p-type heavily doped diffusion regions 136 and 137 are provided in the semiconductor layer 101 on both sides of the gate electrode 135a to form a source region and a drain region. The gate electrode 135a is extended on the semiconductor layer 101 to form a gate electrode lead portion, and a ring-shaped portion 135b is formed at the tip portion thereof. The outer side of the ring-shaped portion 135b is disposed on the inner side with a margin from the end of the n-type semiconductor layer 101. An n-type heavily doped body contact portion 139 is formed in the portion where the semiconductor layer 101 is exposed from the window inside the ring-shaped portion 135b. In addition, the configuration of the memory films 102 to 104 in portions other than the ring-shaped portion 135b conforms to the first embodiment.

Also in the semiconductor device of the present embodiment, the ring-shaped portion 135b formed by pulling out the gate electrode from the gate electrode 135a is disposed without straddling the end of the semiconductor layer 101, so that the end of the semiconductor layer 101 is the same as in the first embodiment. The memory film is not broken by the gate electric field in the portion. For this reason, the memory film can be thinned, and power consumption can be reduced.
In particular, the memory cell of FIG. 9 is different from the first embodiment in that the body contact region 139 is surrounded by the ring-shaped portion 135b. With this structure, it is possible to obtain a structure in which the body contact portion 139 and the diffusion regions 136 and 137 are partitioned by the ring-shaped portion 135b without matching the end portion of the semiconductor layer 101 and the end portion of the ring-shaped portion 135b. Can do. For this reason, the leak current 115 passing through the blank portion between the gate electrode leading end and the semiconductor layer end described in FIG. 4 does not flow.

Particularly in this embodiment, a body contact can also be provided for a TFT used for a peripheral circuit or the like in accordance with the structure of the memory cell. That is, as shown in FIGS. 10A and 10B, the memory cell portion and the TFT portion are shown side by side, and the island-shaped semiconductor layer 201 forming the TFT portion is formed large so as to form the TFT body contact region 239. Then, the ring-shaped portion 235b is formed on the semiconductor layer 101 by being drawn out from the gate electrode 235a. The ring-shaped portion 235b surrounds the body contact region 239.
The body potential can be applied from the body contact region 239 at the time of TFT operation by the ring-shaped portion 235b formed by pulling out from the gate electrode 235a, and the body potential can be controlled to stabilize the TFT operation and reduce the operation variation. be able to.
Whether the memory cell is in the written state or the erased state is determined by sensing using the peripheral circuit TFT. Therefore, the memory cell window for determining whether the memory cell is in the written state or the erased state has a peripheral circuit. A margin for TFT variation is required. In this embodiment, the body contact is provided in the peripheral circuit TFT and the body potential is controlled, so that the variation in the TFT is suppressed. Therefore, the margin can be reduced, and the write / erase determination of the smaller memory cell window can be performed. Become. As a result, a highly reliable semiconductor memory device can be obtained even when held for a long time.

  As described above, the gate electrode lead-out portion of the circuit TFT is installed so as not to protrude from the semiconductor layer, and the body contact region 239 is surrounded by the ring-shaped portion 235b, so that the gate electrode lead-out portion covers the end of the semiconductor layer. Not. For this reason, breakdown due to an electric field does not occur at this portion, and a high yield can be realized. In particular, when the gate insulating film is thinned to reduce the voltage, it is effective to prevent destruction at the edge of the semiconductor layer by the structure of this embodiment. Both the memory film of the memory cell and the gate insulating film of the TFT Since both can be thinned, the voltage of the entire memory device can be reduced. At the same time, the body contact region 139 and diffusion regions 136 and 137 in the memory cell portion and the body contact region 239 and diffusion regions 236 and 237 in the TFT portion are surrounded by the ring-shaped portions 135b and 235b, respectively. As described in the embodiment, even when a reverse bias is applied between the body contact region and the diffusion region, the leakage current can be suppressed as much as possible, and a semiconductor memory device with low power consumption can be obtained.

10A and 10B are schematic views in the case where a memory cell portion and a circuit TFT (only PMOS) are mounted on the same substrate, where FIG. 10A is a plan view and FIG. 10B is a cross-sectional view at a dotted line portion. Here, for convenience of explanation, only the PMOS is shown in the TFT portion. However, NMOS can also be formed by a combination of lithography and ion implantation. In addition, although the memory cell portion and the TFT portion are separated from each other and are adjacent to the semiconductor layers 101 and 201, in practice, the memory cell portion and the TFT portion may be freely laid out as required for circuit connection. Further, the semiconductor layers 101 and 201 may be integrated without being separated. In this figure, the interlayer insulating film and the upper wiring are not shown.
In manufacturing the semiconductor memory device of the present embodiment, first, an n-type semiconductor layer having a thickness of about 50 nm is deposited on an insulating substrate 100 such as glass by a method such as CVD, and this is appropriately formed into an island shape by lithography and etching. Processing (101 and 201 in the figure). Next, for example, a silicon oxide film (for example, a thickness of about 30 nm to 100 nm) corresponding to the gate insulating film of the TFT portion and a gate electrode material film made of metal such as tungsten are deposited and processed by lithography and etching. Thus, a gate electrode 235a having a ring-shaped portion 235b from which the gate insulating film 202 of the TFT portion and the gate electrode of the TFT portion are drawn is formed.
At this time, since the ring-shaped portion 235b is installed without protruding from the semiconductor layer 201, the ring-shaped portion 235b is designed to recede from the end of the semiconductor layer 201 by at least the misalignment of the exposure machine. Further, the ring-shaped portion 235b from which the gate electrode is drawn out has a ring shape, and the inside of this ring later becomes the body contact region 239.

Next, as a memory film, the first insulating film 102 made of, for example, a silicon oxide film is formed with a thickness of 6 nm and the charge storage insulating film 103 made of a silicon nitride film is formed with a thickness of 10 nm using a known method such as CVD. A second insulating film 104 is deposited to a thickness of 10 nm to form a memory film. Further, after depositing a gate electrode material film made of a metal such as tungsten, the gate electrode 135a having the memory film (102 to 104) of the memory cell portion and the ring-shaped gate electrode lead portion 135b is processed by lithography and etching techniques. .
Since the gate electrode 135a for the memory cell is also installed without protruding from the semiconductor layer 101, the memory cell gate electrode 135a is designed to recede from the end of the semiconductor layer 101 by at least a misalignment of the exposure machine. The ring-shaped portion 135b from which the gate electrode is drawn out has a ring shape, and the inside of this ring later becomes the body contact region 139.
When processing the gate electrode 135a and the ring-shaped portion 135b, a combination of anisotropic etching and isotropic etching is used so that no etching residue of the gate electrode 135 occurs on the side wall of the gate electrode of the TFT portion. It is desirable to process. Further, a memory film is formed in a sidewall shape (not shown) on the gate electrode side wall portion of the TFT portion, but the TFT is sufficiently thin and does not cause a problem in terms of function.

Thereafter, by lithography, impurity ion implantation, and annealing techniques, p-type diffusion regions 136 and 137 in the memory cell portion, p-type diffusion regions 236 and 237 in the TFT portion, n-type body contact region 139 in the memory cell portion, and TFT portion Body contact region 239 is formed. Here, in the previous step, the memory films 102 to 104 are processed into the shape of the gate electrode 135A and the ring-shaped portion 135b. However, only the gate electrode 135 and the ring-shaped portion 135b are processed into a predetermined shape, and the memory films 102 to 104 are processed. 104 may be left on the entire surface. In this case, this memory film functions as an implantation protective film at the time of impurity ion implantation.
Next, an interlayer insulating film (not shown) is deposited on the entire surface, contact holes are formed by lithography and etching, and contact plugs 110 on the diffusion regions (source / drain) of the memory cell portion and TFT portion are buried by metal filling. , 111, 210, 211, contact plugs 113, 213 on the gate electrode, and contact plugs 112, 212 on the body contact region. These plugs are connected by metal wiring on the interlayer insulating film (not shown) to form a memory circuit.

In the above description, after the gate insulating film 202 and the gate electrode 235 of the TFT portion are formed, the memory films 102 to 104 and the gate electrode 135 of the memory cell are formed. After forming the gate electrode 135, the gate insulating film 202 and the gate electrode 235 in the TFT portion may be formed. In this case, the gate insulating film material for TFT remains in a sidewall shape on the side wall of the gate electrode 135 of the memory cell portion, but it is sufficiently thin and does not cause a problem in terms of function. Although omitted in the above embodiment, a p-type (thin n-type thin in NMOS) region, a so-called LDD region, which is thinner than the diffusion region, is provided at the gate electrode side end of the TFT diffusion region by a known method. The breakdown voltage of the TFT can be improved.
As described above, a low power consumption semiconductor memory device can be easily manufactured without using a special process. Also in this embodiment, a p-type (thin n-type in NMOS) region, a so-called LDD region, which is thinner than the diffusion region, may be provided at the end of the TFT diffusion region on the gate electrode side. Can be improved.
It is also possible to combine the first embodiment and the second embodiment to form one of the memory cell portion and the TFT portion along the first embodiment and the other along the second embodiment.
As in the first embodiment, in particular, when a semiconductor device is formed by a low temperature process using a substrate having low heat resistance such as a glass substrate, it is more preferable to form the memory cell as a p-type device. Thereby, it is possible to obtain a semiconductor device with higher reliability than when a memory cell is formed as an n-type device.

BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic of the memory cell of the semiconductor memory device of 1st Embodiment of this invention, (a) is a bird's-eye view, (b) is a top view. 2 is a schematic cross-sectional view of a memory cell of the semiconductor memory device according to the first embodiment of the present invention, where (a) is a cross-sectional view taken along a dotted line AA ′ in FIG. 1 and (b) is a cross-sectional view taken along a dotted line BB ′. is there. 2A and 2B are schematic views of a semiconductor memory device in a case where a gate electrode is installed so as to straddle a semiconductor layer end, where FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along a dotted line C-C ′. 1 is a schematic plan view of a semiconductor memory device having a structure in which a gate electrode is installed without protruding from a semiconductor layer and the gate electrode does not divide a diffusion region and a body contact region. BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic showing the manufacturing method of the semiconductor memory device of 1st Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the dotted-line part of (a). BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic showing the manufacturing method of the semiconductor memory device of 1st Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the dotted-line part of (a). BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic showing the manufacturing method of the semiconductor memory device of 1st Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the dotted-line part of (a). BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic showing the manufacturing method of the semiconductor memory device of 1st Embodiment of this invention, (a) is a top view, (b) is sectional drawing in the dotted-line part of (a). It is the schematic of the memory cell of the semiconductor memory device of 2nd Embodiment of this invention, (a) is a top view, (b) is sectional drawing in a dotted line. It is the schematic of the memory cell and TFT of the semiconductor memory device of 2nd Embodiment of this invention, (a) is a top view, (b) is sectional drawing in a dotted line. It is a schematic sectional drawing of the semiconductor memory device on the conventional insulating substrate. It is a schematic sectional drawing of the semiconductor memory device on the conventional insulating substrate which has a body contact.

Explanation of symbols

100 Insulating substrate 101 Silicon layer 102 First insulating film 103 Charge storage film 104 Second insulating film 105 135 Gate electrode 106 107 136 137 Diffusion region (source / drain region)
108 channel region 109 139 body contact region 110 111 source / drain contact 112 gate contact 113 body contact 114 edge portion of semiconductor layer and overlap portion 114a of gate electrode 114b upper end 114b of semiconductor layer edge portion overlapped with gate electrode gate electrode Bottom edge 115 of overlapping semiconductor layer edge portion 115 Reverse leakage current 116 flowing between diffusion region and body contact region Photoresist 202 Gate insulating film 205 of circuit TFT Gate electrode 206 207 236 237 Circuit TFT Diffusion region (source / drain region)
209 239 Circuit TFT body contact region 210 211 Source / drain contact 212 of circuit TFT Gate contact of circuit TFT

Claims (11)

A first conductivity type semiconductor layer formed on an insulator;
A charge storage film having a charge storage function formed on the semiconductor layer and a gate electrode formed on the charge storage film;
A channel region formed in the semiconductor layer below the gate electrode;
A diffusion region of a second conductivity type formed in the semiconductor layer on both sides of the channel region;
A body contact region of a first conductivity type formed by extending the semiconductor layer;
A semiconductor memory device comprising: the gate electrode extended on the extended semiconductor layer; and the body contact region and a gate electrode lead portion for separating diffusion regions on both sides of the channel region.   The first conductivity type semiconductor layer is an n-type semiconductor, and the gate electrode has a Fermi level that is lower than the Fermi level of the n-type semiconductor and higher than the upper end of the valence band of the n-type semiconductor layer. The semiconductor memory device according to claim 1, comprising:   The first conductivity type semiconductor layer is a p-type semiconductor, and the gate electrode is made of a material having a Fermi level that is higher than the Fermi level of the p-type semiconductor and lower than the lower end of the conduction band of the p-type semiconductor layer. The semiconductor memory device according to claim 1.   The semiconductor memory device according to claim 1, wherein the insulator is a glass substrate.   5. The semiconductor memory according to claim 1, wherein the semiconductor layer is formed in an island shape, and an end portion of the gate electrode lead-out portion is formed to coincide with an end portion of the island-shaped semiconductor layer. apparatus.   5. The semiconductor memory device according to claim 1, wherein the gate electrode lead portion has a ring-shaped portion disposed so as to surround the body contact region. 6. The semiconductor according to any one of claims 1 to 6, wherein the charge storage film includes, in order from the semiconductor layer side, a first insulating film, an insulator having a charge storage function, and a second insulating film. Storage device. 8. The device according to claim 1, wherein the body contact region has a portion that is close to a semiconductor layer region below the gate electrode lead portion or overlaps with the gate electrode lead portion. 9. Semiconductor memory device.   9. The semiconductor memory according to claim 1, wherein a thin film transistor further having a gate insulating film, a gate electrode, a second conductivity type diffusion region, a channel region, and a body contact region is formed on the insulator. apparatus.   The semiconductor memory device according to claim 9, wherein the gate electrode lead portion extended from the gate electrode has a ring-shaped portion surrounding the body contact region. Depositing a semiconductor layer, a film having a charge storage function, and a gate electrode material on the insulator;
Patterning the semiconductor layer, the film having a charge storage function, and the gate electrode material to form a gate electrode disposed between the source region and the drain region, and a gate electrode lead portion for separating the source / drain region and the body contact region A method of manufacturing a semiconductor memory device.

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