JP2009101585A - Thermal head driver, thermal head, electronic equipment, printing system, and layout method of thermal head driver and thermal head - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thermal head driver which can reduce a surge voltage without increasing a chip size and be manufactured by the high-density process. <P>SOLUTION: The thermal head driver (30) for actuating a heating element is equipped with a first output driver (OD1) which actuates a first heating element from first pixel data in synchronization with the variation timing of a strobe signal, a delay inversion circuit (DL2) for delaying the strobe signal and outputting a delay inversion strobe signal reversed, and a second output driver (OD2) which actuates a second heating element from second pixel data in synchronization with the variation timing of the delay inversion strobe signal. The delay inversion circuit (DL2) is composed of one inverter. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a thermal head driver, a thermal head, an electronic apparatus, a printing system, and a thermal head driver and a thermal head layout method.

  A thermal printer is a printer that prints on a medium using thermal energy obtained by a heating element. For example, this thermal printer may be employed as a printer for printing a receipt delivered when purchasing an article or a printer for printing an image taken with a digital camera or the like.

  FIG. 1 is a diagram illustrating an example of the principle of a thermal printer.

The thermal printer includes a thermal head 12. A plurality of heating elements are arranged in the thermal head 12, and a heating element that generates heat by a thermal head driver mounted on the thermal head 12 is selected. When the thermal energy of the heating element of the thermal head 12 is transmitted to the sheet (heat sensitive sheet) 14, for example, the ink on the sheet 14 is melted (molten type) or the ink is vaporized (sublimation type) to print an image on the paper 16. To do.
When the paper 16 is thermal paper, the sheet 14 is not necessary, and the thermal head 12 directly prints an image on the thermal paper 16.

  For example, the thermal head driver selects a heating element that generates heat for each line, prints an image for one line, and then repeatedly feeds the paper 16. In this way, one image can be printed on the paper 16.

  The heating element of the thermal head 12 is constituted by a heating resistor, and the thermal head driver selects the heating resistor and controls the current to flow through the selected heating resistor. However, the number of heating elements increases to increase the definition of the printed image, and the amount of current flowing through the heating elements tends to increase for each line. As a result, it appears as a surge voltage of the power supply voltage and generates noise. This noise causes a malfunction of the thermal head driver.

For example, Patent Document 1 discloses a technique for suppressing such a surge voltage. In Patent Document 1, when a current is passed through a heating resistor of a thermal head with a plurality of driver ICs (Integrated Circuits), a strobe signal that defines the timing of current flow is shifted and supplied to each driver IC. A control device is disclosed. Further, there is disclosed a control device that prevents a sudden voltage drop by preventing a latch signal for taking in data of the next row from being input while delaying a strobe signal.
JP 2001-301111 A

  However, in Patent Document 1, the types of strobe signals delayed in advance by a strobe delay circuit mounted in the driver IC are limited. Since the surge voltage can be reduced by reducing the amount of current flowing through the heating resistor at the same time, the surge voltage may not be sufficiently reduced with the type of strobe signal generated in advance by the strobe delay circuit in the driver IC. .

  Further, the surge voltage depends exclusively on the configuration of the thermal head, and the surge voltage may not be reduced only on the driver IC side. For example, when the number of outputs of the driver IC (the number of heating resistors) increases, the surge voltage may not be reduced with the strobe signal generated in advance by the strobe delay circuit of the driver IC. Therefore, it is desirable that the number of strobe signals delayed by the thermal head driver can be determined depending on the thermal head on which the thermal head driver is mounted.

  Further, in recent years, there has been a demand for higher definition of printed images, while there is a high demand for downsizing and cost reduction of thermal printers. Therefore, in order to reduce the size of the thermal head, it is necessary to reduce the chip size of the thermal head driver that has been made into an IC. However, if the manufacturing process of the thermal head driver is a high-density process, the withstand voltage margin decreases, and a surge voltage that has no problem in the conventional manufacturing process may exceed this withstand voltage.

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to reduce a surge voltage without increasing the chip size and to produce a thermal head by a high-density process. To provide a driver, a thermal head, an electronic device, and a printing system.

In order to solve the above problems, the present invention
A thermal head driver (30) for driving the heating element,
A first output driver (OD ₁ ) that drives the first heating element based on the first pixel data in synchronization with the change timing of the strobe signal (STB ₁ );
Delaying the strobe signal (STB _1), and the delay inverting circuit for outputting an inverted delay inverted strobe signal were _{(STB 2) (DL 2)} ,
A second output driver (OD ₂ ) for driving the second heating element based on the second pixel data in synchronization with the change timing of the delayed inversion strobe signal (STB ₂ );
With
The delay inversion circuit (DL ₂ ) is related to the thermal head driver (30) configured by one inverter (DL ₂ ).

The present invention also provides
A thermal head driver (30) composed of a plurality of driver blocks (DB1, DB2) for driving a plurality of heating elements,
Each driver block (DB _J ) includes an output driver (OD _J ) that drives the heating element,
The first driver block (DB1) among the plurality of driver blocks (DB1, DB2)
The heating element corresponding to the first driver block is driven based on the strobe signal (STB _J-1 ) and the first pixel data,
The second driver block (DB2) among the plurality of driver blocks (DB1, DB2)
The heating element corresponding to the second driver block, the strobe signal delayed by the delay inverting circuit (DL _J), and driven on the basis of the inverted thereby delay the inverted strobe signal (STB _J) and the second pixel data ,
In the second driver block (DB2), the delay inversion circuit (DL _J ) is related to the thermal head driver (30) configured by one inverter.

The present invention also provides
A thermal head driver (30) composed of a plurality of driver blocks (DB1, DB2) for driving a plurality of heating elements,
Each driver block (DB _J ) includes an output driver (OD _J ) that drives the heating element,
Each driver block (DB _J )
Output strobe signal from the adjacent driver block _{(DB J-1)} to _{(STB J-1)} as it is, or the strobe signal _{(STB J-1)} delayed by the delay inverting circuit (DL _J), and is inverted And
The first driver block (DB1) among the plurality of driver blocks (DB1, DB2)
The heating element corresponding to the first driver block is driven based on the strobe signal (STB _J-1 ) and the first pixel data from the adjacent driver block (DB _J-1 ),
The second driver block (DB2) among the plurality of driver blocks (DB1, DB2)
The heating element corresponding to the second driver block, delayed by the adjacent driver block strobe signal from _{(DB J-1) (STB} J-1) the delay inverting circuit (DL _J), and the inverted delayed inverted Drive based on the strobe signal (STB _J ) and the second pixel data,
In the second driver block (DB2), the delay inversion circuit (DL _J ) is related to the thermal head driver (30) configured by one inverter.

  According to any one of the above inventions, the heating elements can be driven at different timings according to the characteristics of the thermal head on which the thermal head driver is mounted. In addition, the circuit scale of the delay inversion circuit is very small, and a significant increase in the chip size of the thermal head driver can be suppressed. Since the surge voltage can be reduced without increasing the chip size, a thermal head driver that can be manufactured by a high-density process can be provided.

In the thermal head driver according to the present invention,
Each driver block (DB _J )
A flip-flop (DFF _J ) constituting a shift register in which pixel data is shifted in a given shift direction;
A latch (LT _J ) for latching the pixel data held in the flip-flop,
The output driver (OD _J )
The heating element can be driven based on the output of the latch and the strobe signal (STB _J-1 ) or the delayed inversion strobe signal (STB _J ).

In the thermal head driver according to the present invention,
When the strobe signal (STB _J-1 ) is positive logic in the first driver block (DB1), the output of the latch (LT _J ) is positive logic (FIG. 7), and the strobe signal (STB _J-1 ). ) Is negative logic, the output of the latch (LT _J ) is negative logic (FIG. 8),
In the second driver block (DB2), when the delay inversion strobe signal (STB _J ) is negative logic, the output of the latch (LT _J ) is negative logic (FIG. 9), and the delay inversion strobe signal (STB _J) ) Is positive logic, the output of the latch (LT _J ) can be positive logic (FIG. 10).

When the output of the latch (LT _J ) is positive logic in each driver block (DB _J ), the output driver (OD _J ) is controlled by the AND circuit (OC _J ) (FIGS. 7 and 10). When the output of the latch (LT _J ) is negative logic, the output driver (OD _J ) can be controlled by an OR circuit (OC _J ) (FIGS. 8 and 9).

In the thermal head driver according to the present invention,
One inverter (DL _J ) includes transistors of first and second conductivity types,
The capability of the first conductivity type transistor is at least one transistor constituting a flip-flop (DFF _J ) and / or a latch (LT _J ), and having at least one transistor of the same conductivity type as the first conductivity type Lower than the ability of
The capability of the second conductivity type transistor is at least one transistor constituting a flip-flop (DFF _J ) and / or a latch (LT _J ), and having at least one transistor of the same conductivity type as the second conductivity type Can be lower than the ability.

The present invention also provides
A thermal head driver (30) composed of a plurality of driver blocks (DB _{1 to} DB _N ) for driving a plurality of heating elements,
Each driver block (DB _J ) includes an output driver (OD _J ) that drives the heating element,
All of the plurality of driver blocks (DB _{1 to} DB _N )
The heating element corresponding to each driver block (DB _J ) is obtained by delaying the strobe signal (STB _J-1 ) by the delay inversion circuit (DL _J ) and inverting the inverted inversion strobe signal (STB _J ), pixel data, Drive based on
In each driver block (DB _J ), the delay inversion circuit (DL _J ) is related to the thermal head driver (30) configured by one inverter.

The present invention also provides
A plurality of heating resistance elements to which a given power supply voltage is supplied at one end;
The present invention relates to a thermal head including any one of the above thermal head drivers in which the output of each output driver is electrically connected to the other end of each of the plurality of heating resistance elements.

The present invention also provides
The present invention relates to a thermal head including the thermal head driver described above.

  According to any one of the above inventions, it is possible to provide a thermal head to which a thermal head driver that can reduce a surge voltage and can be manufactured by a high-density process is applied.

The present invention also provides
Any one of the above thermal head drivers;
The present invention relates to an electronic device including a paper feed means for printing a portion of a printing paper.

The present invention also provides
The thermal head described above;
The present invention relates to an electronic device including a paper feed means for printing a portion of a printing paper.

  According to any one of the above inventions, it is possible to provide an electronic device that can reduce surge voltage and prevent malfunction due to noise.

The present invention also provides
An electronic device as described above;
The present invention relates to a printing system including a control unit that supplies print data to an electronic device.

  According to the present invention, it is possible to provide a printing system that can reduce surge voltage and prevent malfunction due to noise.

The present invention also provides
A layout method of a thermal head driver (30) composed of _N driver blocks (DB _{1 to} DB _N ) for driving N heating elements,
Preparing a total delay time of one line of strobe signals (STB _{0 to} STB _N ) flowing in the thermal head driver (30);
Preparing a first delay amount capable of delaying the strobe signal (STB _J-1 ) by one inverter (DL _J ) in one driver block (DB _J );
If the total delay time of one line / (N-1) <the first delay amount, the number of driver blocks that does not exceed the quotient obtained by dividing the total delay time of the one line by the first delay amount (DB2) is selected from the _N driver blocks (DB _{1 to} DB _N );
One inverter (DL _J ) that delays the strobe signal (STB _J-1 ) and outputs an inverted delayed inverted strobe signal (STB _J ) to each of the selected driver blocks (DB2); An output driver (OD _J ) controlled based on a delayed inversion strobe signal (STB _J ),
An output driver (OD _J ) controlled based on a strobe signal (STB _J-1 ) is disposed in each of the remaining driver blocks (DB1) that are not selected.
This relates to the layout method of the thermal head driver (30) including

The present invention also relates to a layout method of a thermal head (20) including M thermal head drivers (30).
Each of the M thermal head drivers (30) is laid out by the above-described layout method of the thermal head driver (30).

  According to any one of the above inventions, it is possible to provide a thermal head to which a thermal head driver that can reduce a surge voltage and can be manufactured by a high-density process is applied.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Thermal Head FIG. 2 shows a configuration example of the thermal head in this embodiment.

In the thermal head 20 in the present embodiment, a plurality of thermal resistance elements (a heating element and a heating resistor in a broad sense) are formed on a ceramic plate 22. In FIG. 2, a plurality of thermal resistance elements are arranged at one edge of the long side of the ceramic plate 22 according to the interval of the pixels. A power supply voltage VH is supplied to one end of the plurality of thermal resistance elements. This power supply voltage is a high voltage such as 24 V or 18 V supplied from the outside of the thermal head 20 (ceramic plate 22). The thermal head 20 is (the M 2 or more integer) first to M including a thermal head driver ₃₀ 1 to 30 _M of. The outputs of the _first to _Mth thermal head drivers 30 ₁ to 30 _M are electrically connected to the other ends of the plurality of thermal resistance elements.

Each of the _first to _M-th thermal head drivers 30 ₁ to 30 _M thermal head drivers sets the output of the output driver connected to the thermal resistance element to, for example, a ground power supply voltage, thereby supplying current to the thermal resistance element. It can flow (drive).

2. Thermal Head Driver Next, the first to Mth thermal head drivers 30 ₁ to 30 _M in FIG. 2 will be described. In the following, since the configuration of each of the _first to _Mth thermal head drivers 30 ₁ to 30 _M is substantially the same, the thermal head driver in the present embodiment applied to the _first thermal head driver 301. Will be described as an example.

  The thermal head driver in the present embodiment has a plurality of output drivers, and the timing for driving the heating elements can be shifted for each output driver. That is, the thermal head driver according to the present embodiment includes a first driver block having a first output driver for driving the first heat generating element and a second driver for driving the second heat generating element among the plurality of driver blocks. And a second driver block having a plurality of output drivers. The first output driver drives the first heating element based on the first pixel data in synchronization with the change timing of the strobe signal. Furthermore, the thermal head driver includes a delay inversion circuit that delays and inverts the strobe signal and outputs a delayed inversion strobe signal. The second output driver synchronizes with the change timing of the delay inversion strobe signal. The second heating element is driven based on the pixel data. As a result, the surge voltage can be reduced according to the characteristics of the thermal head on which the thermal head driver is mounted.

  FIG. 3 shows a configuration example of the thermal head driver in the present embodiment.

The thermal head driver 30 in the present embodiment includes a plurality of driver blocks DB _{1 to} DB _N (N is an integer of 2 or more). The driver block DB _j (1 ≦ j ≦ N, j is an integer) may include an output driver OD _j , a delay inversion circuit DL _j , a latch LT _j, and a flip-flop DFF _j .
In FIG. 3, the driver block DB ₁ does not include a delay inversion circuit, but may include a delay inversion circuit DL ₁ not shown. In FIG. 3, it is assumed that the plurality of driver blocks DB _{2 to} DB _N include corresponding delay inversion circuits DL _{2 to} DL _N , but each of the plurality of driver blocks DB _{2 to} DB _N is not necessarily The delay inverting circuit DL may not be included. In other words, the plurality of driver blocks DB ₁ to DB _N, and the first driver block that does not include a delay inverting circuit DL, in the second driver block including a delay inverting circuit DL, may be configured.

The thermal head driver 30 receives a clock signal CLK, serial data SI, a latch signal LAT, and an inverted strobe signal XSTROBE. Pixel data is serially input as serial data SI in synchronization with the clock signal CLK. The latch signal LAT is a signal for taking pixel data for one line into the latches LT _{1 to} LT _N. Inverted strobe signal XSTROBE is a negative logic signal, for example, positive logic strobe signal is supplied to the driver block DB _1.

Flip-flop _DFF 1 _{~DFF N} driver blocks _DB 1 to DB _N constitutes a shift register in which the pixel data to be input as serial data SI is shifted in the shift direction SDR. Each flip-flop constituting the shift register captures the output of the preceding flip-flop and outputs the data captured by the flip-flop in synchronization with the change timing of the clock signal CLK.

The latch LT _j latches (holds) the data fetched into the flip-flop DFF _j when the latch signal LAT is at H level, for example. The data latched in the latch LT _j is input to the output control circuit OC _j . The output control circuit OC _j generates an output control signal cnt ₁ that performs output control of the output driver OD ₁ .

The delay inversion circuit DL _j is configured by one inverter. The strobe signal STB _j−1 from the adjacent driver block DB _j−1 is input to the input of this inverter. Then, the delay inversion circuit DL _j delays the strobe signal STB _j−1 and generates a delayed inversion strobe signal DSTB _j . The output control circuit OC _j, the strobe signal _{STB j-1} or delay inverting strobe signal DSTB _j is output as a strobe signal STB _j.

FIG. 4 is an explanatory diagram of the delay inverting circuit DL _j shown in FIG.

As shown in FIG. 4, the input of the delay inverting circuit DL _j driver block DB _j, the strobe signal _{STB j-1} from the driver block _{DB j-1} adjacent is input. Then, the delay inversion circuit DL _j delays the strobe signal STB _j−1 and outputs the inverted delay inversion strobe signal DSTB _j . The delayed inverted strobe signal DSTB _j is output as the strobe signal STB _{j to the} adjacent driver block DB _{j + 1} .

Delay inversion circuit DL _j is formed of one inverter, and this inverter is formed of, for example, P and N type transistors (CMOS transistors). The capability (current driving capability) of the P-type transistor constituting the delay inverting circuit DL _j is lower than the capability of at least one P-type transistor constituting the flip-flop DFF and / or the latch LT. Further, the capability of the N-type transistor constituting the delay inverting circuit DL _j is lower than the capability of the at least one N-type transistor constituting the flip-flop DFF and / or the latch LT.
Note that the delay inversion circuit DL _j can further delay the strobe signal STB _j−1 as the capability of the delay inversion circuit DL _j is set lower.

Hereinafter, an example in which the delay amount of the delay inverting circuit DL _j configured by one inverter is set to, for example, 0.1 [ns] will be described. For example, the channel length and the channel width of the P-type transistor of the delay inverting circuit DL _j are Lp1 (= 0.8 [μm]) and Wp1 (= 12 [μm]), respectively, and the channel length of the N-type transistor and The channel widths are Ln1 (= 0.8 [μm]) and Wn1 (= 6 [μm]), respectively.

By the way, the delay inverting circuit DL _j may be replaced with a delay circuit composed of an even number of inverters. This delay circuit is described in Japanese Patent Application No. 2006-347012, an unpublished Japanese application. In an undisclosed delay circuit, at least two inverters are required.
Hereinafter, an example in which the delay amount of an undisclosed delay circuit including two inverters is set to, for example, 0.1 [ns] will be described. For example, the channel length and channel width of each P-type transistor of the undisclosed delay circuit are Lp2 (= 0.8 [μm]) and Wp2 (= 24 [μm]), respectively, and the channel length of the N-type transistor The channel widths are Ln2 (= 0.8 [μm]) and Wn2 (= 12 [μm]), respectively.
Therefore, when setting the same delay amount, the delay inverting circuit DL _j has a smaller size than the undisclosed delay circuit. In addition, since one inverter of the delay inverting circuit DL _j has a small size as compared with one inverter of the undisclosed delay circuit, the effect of reducing the size of the delay inverting circuit DL _j is large.

When the delay amount of the delay inversion circuit DL _j composed of one inverter is set to, for example, 1 [ns], for example, the channel widths of the P-type and N-type transistors of the delay inversion circuit DL _j are designed. In some cases, the minimum value of the rule (for example, 1 [μm]) is fixed (Wp1 (= 1 [μm], Wn1 (= 1 [μm]). In this example, the P type and N of the delay inversion circuit DL _j The channel length of the type transistor is, for example, Lp1 (= 4 [μm], Ln1 (= 8 [μm]). The delay amount of an undisclosed delay circuit composed of two inverters is, for example, 1 [ ns], for example, the channel length and channel width of each P-type transistor of the undisclosed delay circuit are Lp2 (= 2 [μm]) and Wp2 (= 1 [μm]), respectively, and N-type of The channel length and the channel width of the transistor are Ln2 (= 4 [μm]) and Wn2 (= 1 [μm]), respectively, so that when the channel width of the transistor is fixed to the minimum value of the design rule, the delay The gate area of the inverting circuit DL _j is almost the same as the gate area of the undisclosed delay circuit, but when the gate area is smaller than that in the above example in which the delay amount is 0.1 [ns], the other areas ( connection contacts, wires, is more space, etc.) of the transistor is larger than the gate area. Therefore, the delay inverting circuit DL _j consists of one inverter, for example, the delay unpublished composed of two inverters It is about 60% of the size of the circuit and has a small size.

  Returning to FIG. 3, the description will be continued.

The output driver OD _j is configured by an N-type metal oxide semiconductor (MOS) transistor (hereinafter simply referred to as a MOS transistor). The drain of this MOS transistor becomes the driver output DOj. The source of the MOS transistors constituting the output driver _OD 1 _{~OD N} driver blocks _DB 1 to DB _N, the ground power supply voltage GND is supplied. The gates of the MOS transistors constituting the output driver OD _j, the output control signal cnt _j from the output control circuit OC _j is supplied. In Figure 3, the output control signal cnt _j, between the source and the drain of the MOS transistors constituting the output driver OD _j is by electrically conductive, the driver output DOj is set to the ground power supply voltage GND.

Driver block DB _j is directly a strobe signal from the driver block DB _j-1, or driver block DB delays the strobe signal from the _j-1, and the delayed inverted strobe signal obtained by inverting the adjacent driver block DB j _{+ 1} To supply.

The output control circuit OC _j is the strobe signal _{STB j-1} from the driver block _{DB j-1} adjacent, or delaying the strobe signal, and the delayed strobe signal DSTB _j obtained by inverting, corresponding to the driver block DB _j An output control signal cnt _j is generated based on the pixel data (pixel data latched in the latch LT _j ).

  FIG. 5 and FIG. 6 are timing charts of an operation example of the thermal head driver 30 of FIG.

FIG. 5 shows the timing at which image data input as serial data SI is stored in the flip-flops DFF _{1 to} DFF _N constituting the shift register. Image data P1, P2, P3,..., PN are serially input as serial data SI in synchronization with the clock signal CLK. For example, the image data P1 corresponds to the driver output DO1 of the driver blocks DB _1, the image data P2 corresponds to the driver output DO2 driver block DB _2, ···, the image data PN is the driver output DON of the driver block DB _N It corresponds. The flip-flop DFF ₁ takes in the image data P1 of the serial data SI in synchronization with the changing point of the clock signal CLK. Flip-flop DFF ₂ captures the image data P2 of the serial data SI synchronously with the change point of the clock signal CLK. The flip-flop DFF _N takes in the image data PN of the serial data SI in synchronization with the changing point of the clock signal CLK.

FIG. 6 shows driver output timings using image data held in the latches LT _{1 to} LT _N. FIG. 6 shows the driver outputs DO1 and DO2, but the other driver outputs are the same.

When the latch signal LAT is at the H level, image data P1 that is held in the flip-flop DFF ₁ is taken into the latch LT _1. At this time, similarly the image data P2~PN held by the flip-flop _DFF 2 _{~DFF N} is taken into the latch _LT 2 to LT _N. Accordingly, the latch signal LAT, can capture image data P1~PN of one line to latch _LT 1 to LT _N.

In FIG. 3, the strobe signal STB ₀ is output as it is as the strobe signal STB ₁ . The delay inversion circuit DL ₂ delays the strobe signal STB ₁ and outputs a delayed inversion strobe signal DSTB ₂ that is inverted. The delayed inversion strobe signal DSTB ₂ is output as the strobe signal STB ₂ to the adjacent driver block DB ₃ .

Here, as shown in FIG. 3, the output driver OD ₁ of driver block DB ₁ is thermal resistance on the basis of the image data P1 held in the strobe signal STB ₁ and the latch LT _1, is connected to the driver output DO1 The element can be driven. More specifically, the image data P1 stored in the latch LT ₁ is "1", and the strobe signal STB ₁ are at H level, the output control signal cnt ₁ becomes H level, the output driver OD ₁ of the MOS transistor The drain is set to the ground power supply voltage GND. Accordingly, current flows through the thermal resistance element connected to the output driver OD _1.

On the other hand, when the image data P1 is “0” or the strobe signal STB ₁ is at L level, the output control signal cnt ₁ remains at L level and the drain and source of the MOS transistor of the output driver OD ₁ are electrically cut off. Is done. As a result, current does not flow through the thermal resistance element connected to the output driver OD _1.

As shown in FIG. 3, the output driver OD ₂ of the driver block DB ₂ is a thermal resistance element connected to the driver output DO ₂ based on the strobe signal STB ₂ and the image data P ₂ held in the latch LT _2. Can be driven. As described below, the output of the latch LT ₂ is a negative logic, data image data P2 held is inverted is supplied to the driver output DO _2.
More specifically, the image data P2 held in the latch LT ₂ is "1" (therefore, the output of the latch LT ₂ is "0"), and the strobe signal STB ₂ is L-level (i.e., the strobe signal STB ₁ Output control signal cnt ₂ becomes H level, and the drain of the MOS transistor of the output driver OD ₂ is set to the ground power supply voltage GND. Accordingly, current flows through the thermal resistance element connected to the output driver OD _2.

On the other hand, when the image data P2 is “0” (therefore, the output of the latch LT ₂ is “1”) or the strobe signal STB ₂ is at the H level (that is, the strobe signal STB ₁ is at the L level), the output control signal cnt ₂ There remains L-level, between the drain and source of the MOS transistor of the output driver OD ₂ is cut off electrically. As a result, current does not flow through the thermal resistance element connected to the output driver OD _2.

Due to the delay difference between the strobe signals STB ₁ and STB ₂ , the driver outputs DO 1 and DO ₂ also have a delay difference. As a result, there is a time difference between the current I1 flowing through the thermal resistance element connected to the driver output DO1 and the current I2 flowing through the thermal resistance element connected to the driver output DO2. Although the driver outputs DO1 and DO2 have been described with reference to FIG. 6, it is possible to suppress fluctuations in the level of the power supply voltage VH and generated noise by suppressing the generated surge voltage by providing a time difference for the other driver outputs. Become.

  Preferably, the surge voltage can be minimized by flowing or interrupting the current through the thermal resistance element at different timings of the driver outputs DO1 to DON. However, when there is a restriction on the delay time for one line, the current flowing through or shutting off the current flowing through the thermal resistance elements connected to the driver outputs DO1 to DON is shifted at any one of a plurality of timings. Also good. Even in this case, the surge voltage can be reduced.

2.1 Configuration Example of Driver Block DB Each driver block of the thermal head driver 30 is not limited to the configuration shown in FIG.

FIG. 7 shows a first example configuring the output control circuit OC and the latch LT in the driver block DB.
As described above, the plurality of driver blocks DB _{1 to} DB _N can be configured by the first driver block DB 1 that does not include the delay inverting circuit DL and the second driver block DB 2 that includes the delay inverting circuit DL. .
The driver block DB _J shown in FIG. 7 belongs to the first driver block DB1. That is, the driver block DB _J shown in FIG. 7 outputs the strobe signal STB _J-1 from the adjacent driver block DB _J-1 as it is as the strobe signal STB _J. When the driver block DB _J shown in FIG. 7 is the first-stage driver block DB ₁ , the driver block DB ₁ outputs the strobe signal STB _{0 as it} is as the strobe signal STB ₁ .
In the driver block DB _J shown in FIG. 7, when the strobe signal STB _J is positive logic, the output of the latch LT _J is positive logic, and the output driver OC _J is composed of an AND circuit (logical product circuit). The The AND circuit OC _J can be composed of a NAND circuit and an inverter.

FIG. 8 shows a second example configuring the output control circuit OC and the latch LT in the driver block DB.
The driver block DB _J shown in FIG. 8 also belongs to the first driver block DB1. That is, the driver block DB _J shown in FIG. 8 outputs the strobe signal STB _J-1 from the adjacent driver block DB _J-1 as it is as the strobe signal STB _J. Note that the driver block DB _J shown in FIG. 8 may be the first-stage driver block DB ₁ . The driver block DB _J shown in FIG. 8, may be any of a plurality of driver blocks _DB 2 to DB _N.
In the driver block DB _J shown in FIG. 8, when the strobe signal STB _J is negative logic, the output of the latch LT _J is negative logic, and the output driver OC _J is composed of a NOR circuit (OR circuit). The

FIG. 9 shows a third example configuring the output control circuit OC and the latch LT in the driver block DB.
The driver block DB _J shown in FIG. 9 belongs to the second driver block DB2. That is, the driver block DB _J shown in FIG. 9, a strobe signal _{STB J-1} from the driver block _{DB J-1} adjacent delayed by the delay inverting circuit DL _J, and inverts, the output as a strobe signal STB _J To do. When the driver block DB _J shown in FIG. 7 is the first stage driver block DB ₁ and the driver block DB _J shown in FIG. 9 is the next stage driver block DB ₂ , strobe signal _{STB J-1} from the driver block _{DB J-1} to are positive logic, therefore, the strobe signal STB _J from driver block DB _J, is a negative logic.
In the driver block DB _J shown in FIG. 9, when the strobe signal STB _J is negative logic, the output of the latch LT _J is negative logic, and the output driver OC _J is configured by a NOR circuit (OR circuit). The

FIG. 10 shows a fourth example configuring the output control circuit OC and the latch LT in the driver block DB.
The driver block DB _J shown in FIG. 10 also belongs to the second driver block DB2. That is, the driver block DB _J shown in FIG. 10, a strobe signal _{STB J-1} from the driver block _{DB J-1} adjacent delayed by the delay inverting circuit DL _J, and inverts, the output as a strobe signal STB _J To do. The driver block DB _J shown in FIG. 7 is the first-stage driver block DB ₁ , the driver block DB _J shown in FIG. 9 is the next-stage driver block DB ₂ , and the driver shown in FIG. If block DB _J is its next driver block DB _3, 10, the strobe signal _{STB J-1} from the driver block _{DB J-1} adjacent is a negative logic, therefore, the driver block DB _J The strobe signal STB _{J from} is positive logic.
In the driver block DB _J shown in FIG. 10, when the strobe signal STB _J is positive logic, the output of the latch LT _J is positive logic, and the output driver OC _J is composed of an AND circuit (logical product circuit). The

By the way, as described above, preferably, the surge voltages can be minimized by flowing currents through the thermal resistance elements at different timings of the driver outputs DO1 to DON. That is, it is preferable that the stove signals STB _{1 to} STB _N are sequentially delayed in each of the driver blocks DB _{1 to} DB _N. However, if there are restrictions on 1 total delay time of the line the strobe signals flowing through the thermal head driver 30 (the delay amount between the strobe signal STB _N and the strobe signal STB ₀₎ is one of a plurality of timing Thus, the timing of flowing the current flowing through the thermal resistance elements connected to the driver outputs DO1 to DON may be shifted. That may be selected driver block including a delay inverting circuit DL from the driver blocks _DB 1 to DB _N.
Referring to the thermal head 20 in FIG. 2, the thermal head 20 includes first to Mth thermal head drivers 30 ₁ to 30 _M. Therefore, in each of the _first to _M-th thermal head drivers 30 ₁ to 30 _M , a driver block including the delay inversion circuit DL may be selected from the driver blocks DB _{1 to} DB _N.

Specifically, the total delay time (DT) of one line of the strobe signal that flows in one thermal head driver 30 shown in FIG. 3 is set to be shorter than the period for fetching pixel data for one line. When the delay amount that can delay the strobe signal by one delay inverting circuit DL (that is, one inverter) is D1, when DT / (N−1) ≧ D1, the driver block DB ₁ is excluded. each driver block _DB 2 to DB _N can be provided with a delay inverting circuit DL.
In other words, if a DT / (N-1) < D1, all of the driver block _DB 2 to DB _N, can not be provided with the delay inverting circuit DL, a part of the driver block _DB 2 to DB _N, A delay inversion circuit DL can be provided.

When DT / (N−1) <D1, among the driver blocks DB _{1 to} DB _N , preferably, among the driver blocks DB _{2 to} DB _N , the driver block that can include the delay inverting circuit DL The maximum number is a number equal to the quotient when DT is divided by D1. Therefore, a number of driver blocks that do not exceed the quotient obtained by dividing DT by D1 are selected, and each of the selected driver blocks includes a delay inversion circuit DL, and the remaining driver blocks include a delay inversion circuit DL. Absent.

For example, in FIG. 3, when only the even-numbered driver block includes the delay inversion circuit DL, the first driver block DB ₁ is configured by the driver block DB of FIG. 7, and the second driver block DB ₂ is The third driver block DB ₃ is composed of the driver block DB of FIG. 8, the fourth driver block DB ₄ is composed of the driver block DB of FIG. 10, and the fifth driver block DB ₃ is composed of the driver block DB of FIG. The driver block DB ₅ includes the driver block DB shown in FIG.
Thus, the J-th driver block DB _J is configured according to the logical code of the strobe signal STB _J-1 from the adjacent driver block DB _J-1 .

FIG. 11 shows a specific example of the latch LT _j shown in FIG.
As shown in FIG. 11, the latch LT _j is composed of, for example, five N-type transistors N11 to N15 and five P-type transistors P11 to P15. The gates of the transistors P12 and N12 receive data held in the flip-flop DFF _j . The drains of the transistors P13 and N13 output the data held in the latch LT _j to the output control circuit OC _j in synchronization with the change timing of the latch signal (LAT) or the inverted latch signal (XLAT). The drains of the transistors P13 and N13 are positive logic outputs. Further, as shown in FIG. 11, the latch LT _j can output in accordance with negative logic at the drains of the transistors P12 and N12.
Therefore, the output control circuit OC _j is connected to the drains of the transistors P13 and N13 or the drains of the transistors P12 and N12 according to the logic sign of the output of the latch LT _j shown in FIGS.

3. Next, a printer apparatus (thermal printer) as an electronic apparatus to which the thermal head according to the present embodiment is applied, and a printing system to which the printer apparatus is applied will be described.

  FIG. 12 is an explanatory diagram of the printer apparatus according to this embodiment.

  FIG. 12 is a longitudinal sectional view showing only the main part of the longitudinal section of the printer apparatus 120 in the present embodiment. The printer apparatus 120 is configured such that thermal paper is set as the roll paper 122. The print target portion of the roll paper 122 is sent out in the paper feed direction 123 line by line by a given paper feed mechanism (paper feed means). The print target portion is guided toward the print head 125 in the housing 124. The print head 125 carries the thermal head 20 of FIG. When the print target portion of the roll paper 122 passes between the print head 125 and the platen 126, the print head 125 performs predetermined printing on the print target portion.

  The paper feed mechanism further feeds the print target portion in the paper feed direction 123, the roll paper 122 is cut by the cutter 127, and the cut paper can be taken out as a receipt 128.

  In the housing 124, a paper end sensor 129 is provided in front of the print head 125, so that the end of the roll paper 122 can be detected when the roll paper 122 is fed in the paper feed direction 123.

  According to the printer device in the present embodiment, surge voltage can be reduced and malfunction due to noise can be prevented.

  FIG. 13 shows a configuration example of a printing system to which the printer device 120 of FIG. 12 is applied.

  The printing system 130 in the present embodiment includes a host computer 132 (a control unit in a broad sense) and a printer device 120 that issues a receipt 128 and the like. The host computer 132 includes a main body 134, a display device 136, a keyboard 137, and a mouse 138 as a pointing device.

  FIG. 14 is a block diagram showing a configuration example of the host computer 132 shown in FIG.

  In the host computer 132, a ROM (Read Only Memory) 143 storing program data and the like is stored in a CPU (Central Processing Unit) 141 via a bus line 142, and a RAM for buffering a data processing work area and print data. (Random Access Memory) 144, a communication interface 145 for transmitting print data, a print command, and the like to the printer device 120, a display controller 146 for driving the display device 136 to display characters corresponding to the display data, and the keyboard 137 A keyboard controller 147 that captures key signals corresponding to keys and a mouse controller 148 that controls data exchange with the mouse 138 are connected. The printer device 120 also includes a communication interface 149 that receives print data and the like from the communication interface 145.

  The CPU 141 executes predetermined print processing in accordance with a program stored in the ROM 143 or the RAM 144, expands the print data in the RAM 144, and transfers the print data in the RAM 144 to the printer device 120 via the communication interface 145. Can do.

  According to the printing system of the present embodiment, surge voltage can be reduced and malfunction due to noise can be prevented.

The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the delay inverting circuit DL _j may not be in the driver block DB _j .

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

The figure explaining an example of the principle of a thermal printer. The figure which shows the structural example of the thermal head in this embodiment. FIG. 3 is a diagram illustrating a configuration example of a thermal head driver in the present embodiment. FIG. 4 is an explanatory diagram of the delay inverting circuit DL _j of FIG. FIG. 4 is a timing diagram of an operation example of the thermal head driver of FIG. 3. FIG. 4 is a timing diagram of an operation example of the thermal head driver of FIG. 3. A first example configuring an output control circuit OC and a latch LT in a driver block. A second example configuring the output control circuit OC and the latch LT in the driver block. A third example configuring the output control circuit OC and the latch LT in the driver block. A fourth example configuring the output control circuit OC and the latch LT in the driver block. A specific example of the latch LT _j shown in FIG. FIG. 3 is an explanatory diagram of a printer apparatus according to the present embodiment. The figure which shows the structural example of the printing system with which the printer apparatus of FIG. 12 is applied. FIG. 14 is a block diagram of a configuration example of a host computer in FIG. 13.

Explanation of symbols

20 thermal head, 22 ceramic plate,
30 ₁ to 30 _{M first} to _M- th thermal head drivers,
30 thermal head driver, 120 printer device, 122 roll paper,
123 paper feed direction, 124 housing, 125 print head,
126 platen, 127 cutter, 128 receipt, 130 printing system,
132 host computer, 134 main body, 136 display device,
137 keyboard, 138 mouse, CLK clock signal,
DB _{1 to} DB _N driver block, DFF _{1 to} DFF _N flip-flop,
DL ₁ through DL _N delay inverting circuit, DO1～DON driver output,
DSTB _{1 to} DSTB _N delay strobe signal, LT _{1 to} LT _N latch,
LAT latch signal, _OC 1 ~OC _N output control circuit,
OD ₁ ~OD _N output driver, _STB 0 ~STB _N strobe signals,
SI serial data

Claims (15)

A thermal head driver for driving a heating element,
A first output driver for driving the first heating element based on the first pixel data in synchronization with the change timing of the strobe signal;
A delay inversion circuit that delays and inverts the strobe signal and outputs a delayed inversion strobe signal;
A second output driver for driving the second heating element based on the second pixel data in synchronization with the change timing of the delayed inversion strobe signal;
With
The delay inversion circuit is a thermal head driver composed of one inverter. A thermal head driver composed of a plurality of driver blocks for driving a plurality of heating elements,
Each driver block includes an output driver that drives the heating element,
A first driver block of the plurality of driver blocks is
Driving the heating element corresponding to the first driver block based on the strobe signal and the first pixel data;
A second driver block of the plurality of driver blocks is
The heating element corresponding to the second driver block is driven based on the delayed inversion strobe signal and the second pixel data obtained by delaying the strobe signal by the delay inversion circuit and inverting the strobe signal.
In the second driver block, the delay inversion circuit is a thermal head driver including one inverter. A thermal head driver composed of a plurality of driver blocks for driving a plurality of heating elements,
Each driver block includes an output driver that drives the heating element,
Each driver block
Output the strobe signal from the adjacent driver block as it is, or delay and invert the strobe signal by the delay inversion circuit,
A first driver block of the plurality of driver blocks is
Driving the heating element corresponding to the first driver block based on the strobe signal and the first pixel data from the adjacent driver block;
A second driver block of the plurality of driver blocks is
The heating element corresponding to the second driver block is driven based on the delayed inversion strobe signal and the second pixel data obtained by delaying the strobe signal from the adjacent driver block by the delay inversion circuit and inverting the strobe signal.
In the second driver block, the delay inversion circuit is a thermal head driver including one inverter. In claim 2 or 3,
Each driver block
A flip-flop constituting a shift register in which pixel data is shifted in a given shift direction;
A latch for latching pixel data held in the flip-flop,
The output driver is
A thermal head driver that drives a heating element based on the output of the latch and the strobe signal or the delayed inversion strobe signal. In claim 4,
In the first driver block, when the strobe signal is positive logic, the output of the latch is positive logic; when the strobe signal is negative logic, the output of the latch is negative logic;
In the second driver block, when the delayed inverted strobe signal) is positive logic, the output of the latch is positive logic, and when the delayed inverted strobe signal is negative logic, the output of the latch is Thermal head driver that is negative logic. In claim 5,
In each driver block, when the output of the latch is positive logic, the output driver is controlled by an AND circuit, and when the output of the latch is negative logic, the output driver is controlled by an OR circuit.
Thermal head driver. In any one of Claims 4 thru | or 6.
The one inverter includes transistors of first and second conductivity types,
The capability of the transistor of the first conductivity type is the capability of at least one transistor constituting the flip-flop and / or the latch, and the capability of at least one transistor of the same conductivity type as the first conductivity type. Low,
The capability of the transistor of the second conductivity type is at least one transistor constituting the flip-flop and / or the latch, and is greater than the capability of at least one transistor of the same conductivity type as the second conductivity type. Low thermal head driver. A thermal head driver composed of a plurality of driver blocks for driving a plurality of heating elements,
Each driver block includes an output driver that drives the heating element,
All of the plurality of driver blocks are
The heat generating element corresponding to each driver block is driven based on the delayed inverted strobe signal and pixel data obtained by delaying and inverting the strobe signal by the delay inverting circuit,
In each driver block, the delay inversion circuit is a thermal head driver composed of one inverter. A plurality of heating resistance elements to which a given power supply voltage is supplied at one end;
The thermal head driver according to any one of claims 1 to 8, wherein an output of each output driver is electrically connected to the other end of each of the plurality of heating resistors.
Thermal head equipped with.   A thermal head comprising the thermal head driver according to claim 1. The thermal head driver according to any one of claims 1 to 8,
An electronic apparatus comprising: a printing target portion of printing paper; and paper feeding means. The thermal head according to claim 9 or 10,
An electronic apparatus comprising: a printing target portion of printing paper; and paper feeding means. The electronic device according to claim 11 or 12,
A control unit for supplying print data to the electronic device;
A printing system comprising: A thermal head driver layout method composed of N driver blocks for driving N heat generating elements,
Preparing a total delay time for one line of a strobe signal flowing through the thermal head driver;
Preparing a first delay amount capable of delaying the strobe signal by one inverter in one driver block;
If the total delay time of one line / (N-1) <the first delay amount, the number of driver blocks that does not exceed the quotient obtained by dividing the total delay time of the one line by the first delay amount Selecting from among the N driver blocks;
In each of the selected driver blocks, one inverter that delays and inverts the strobe signal and outputs a delayed inversion strobe signal and an output driver that is controlled based on the delayed inversion strobe signal are arranged. thing,
Placing an output driver controlled based on a strobe signal in each of the remaining driver blocks not selected;
Layout method of thermal head driver including A thermal head layout method including M thermal head drivers,
Laying out each of the M thermal head drivers by the method of claim 14;
Layout method of thermal head including

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