JP2000185423A - Integrated circuit for driving thermal head - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrict an increase in circuit size even when printing with a plurality of gradations or in a plurality of colors is carried out by one heating resistor. SOLUTION: Two latch circuits 5r and 5b for red and black are used for two-color printing data. One shift register 4 is used in common for inputs of a red data r and a black data b to supply data to the latch circuits 5r and 5b. Since the shift register 4 is shared, one shift register 4 will do for two-color printing and a chip can be made small. In using the integrated circuit for driving a thermal head, inputs of the read data r and black data b are alternately input from a control terminal SI and a corresponding latch signal is input after 64 bits of each color data are completely input, thereby enabling two-color printing (setting).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit for driving a thermal head, and more particularly to an integrated circuit for driving a thermal head capable of performing multicolor printing by setting a plurality of energizing times for each heating resistor.

[0002]

2. Description of the Related Art A printer using a thermal head is widely used as a printer for printing documents and images created with the spread of various OA supplies such as personal computers and word processors. This thermal head is used, for example, when printing on A4 paper in a line-sequential manner.
There are 1728 heating resistors arranged in a line. Then, the heating resistors are divided into blocks of 64 pieces, and ON (energization) and OFF (stop of electricity) of each heating resistor are controlled by a thermal head driving IC for each block.

FIG. 4 shows such a thermal head driving I.
The basic configuration in C is represented by blocks. As shown in FIG.
0 is a shift register 101, a latch circuit 102,
And a driver 103. The shift register 101 is connected in series with 64 D-FFs (data flip-flop circuits) corresponding to the heating resistors connected to the driver 103, and controls print data supplied serially to a control terminal. The shift is performed according to a clock signal input from CLK. The latch circuit 102 also has 64 latch elements, and the print data of each DFF of the corresponding shift register 101 is printed on the corresponding latch element by the latch signal input from the control terminal LCH as indicated by an arrow B in FIG. The print data is held at the same time, and the held print data is supplied to the driver 103. The driver 103 includes 64 transistors for driving the connected heating resistor, and while the strobe signal is being supplied from the control terminal STB, the print data is changed according to the print data supplied from the latch circuit 102. A current is supplied to each heating resistor from the transistor corresponding to 1 ".

By the way, printing by a thermal head is 1
Normally, the color is used, and the thermal head driver IC for that is also configured for one color as shown in FIG.
On the other hand, it is conceivable to print a plurality of gradations or print a plurality of colors using one heating resistor that prints one dot. That is, the color density may be changed by changing the energizing time to one heating resistor, or a plurality of colors may be printed by using a recording paper that develops a different color in accordance with the amount of heat energy by the energizing time. Conceivable. FIG. 5 shows a configuration of a thermal head driving IC for two-color printing, which can be considered by using a conventional one-color thermal head driving IC. As shown in this figure, two colors (for example, red and black)
When configuring the thermal head driving IC 100 for
There are two types of input print data: print data r for red and print data b for black. Therefore, a shift register 101r for red print data and a latch circuit 102r,
And a shift register 101b for black print data and a latch circuit 102b. With respect to the driver 103, by forming a logic circuit for selecting one of the print data supplied from the latch circuit 102r and the latch circuit 102b, the transistors for energizing the heating resistor are switched between red and black. However, since strobe signals for controlling the driving of the transistors also need to be used for red and black, the control terminals STBr and STB
b is provided.

In such a configuration of the driving section, the output time of the strobe signal STBr and the strobe signal STB
By making the output time of b different, the time when the transistor of the driver 103 is turned on changes according to the printing color,
Multi-tone printing and multi-color printing are performed by changing the heating time of the heating resistor. For example, when using recording paper in which red color is generated by short-time energization and black color is generated by long-time energization, a strobe signal STBr having a short pulse width is supplied while supplying red print data r. By 1
It becomes possible to print red in the line. On the other hand, by supplying the strobe signal STBb having a long pulse width while supplying the print data DATb for black, it becomes possible to print black on the same line.

[0006]

However, as shown in FIG. 5, when a two-color thermal head driver IC is formed using a conventional one-color thermal head driver IC, the type of print data (FIG. In the case of 5, it is necessary to arrange the shift registers and the latch circuits as many as the number of colors to be used in accordance with the increase of the two types of red and black. That is, in the case of performing n-color printing using print data for n colors, n sets of shift registers and latch circuits are required, and there is a problem that the chip becomes large.

Accordingly, the present invention provides an integrated circuit for driving a thermal head capable of suppressing an increase in circuit size even when performing multiple gradation printing or multiple color printing with one heating resistor. Aim.

[0008]

SUMMARY OF THE INVENTION According to the present invention, there is provided an integrated circuit for driving a thermal head for controlling the energization of a plurality of heating resistors in accordance with print data, the serially supplied print data being sequentially transferred. N sets of shift registers for storing the print data stored in the shift registers, m (m> n) sets of holding means for collectively holding the print data stored in the shift registers, and data held in the m sets of holding means. A set of driving means for reading out at a time and controlling the energization of the plurality of heating resistors, and an output of at least one set of the shift registers is connected to an input of a plurality of sets of the holding means. According to the present invention, there is provided an integrated circuit for driving a thermal head for controlling energization of a plurality of heating resistors in accordance with print data, wherein the n sets of shift registers for sequentially transferring and storing serially supplied print data And m (m <n) for collectively holding the print data stored in the shift register.
A set of holding means, and a set of driving means for sequentially reading out data held in the m sets of holding means and controlling the energization of the plurality of heating resistors, and at least one set of the holding means Are connected to the outputs of a plurality of sets of the shift registers. As described above, in the present invention, one of the shift register and the holding means is made smaller than the other, and at least one set on the smaller side is commonly used. Thereby, the circuit size of the integrated circuit for driving the thermal head can be reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the integrated circuit for driving a thermal head according to the present invention will be described below in detail with reference to the drawings. (1) Overview of First Embodiment In this embodiment, two latch circuits are used for print data of two colors, one for red and one for black. One shift register for supplying data to this latch circuit is used. The red data r and the black data b are commonly used. By commonly using the shift register in this way,
With only one shift register, the size of the chip can be reduced. When such a thermal head driving integrated circuit is used, the input of red data r and the input of black data b are alternately input from the control terminal SI, and the corresponding latch signal is input after 64 bits of each color data have been input. Is input, two-color printing (printing) becomes possible. By using a common shift register, red data r and black data b
Is latched and printed in the corresponding latch circuit is slower than when inputting data in parallel by two shift registers. In this regard, printing at the same speed can be performed by doubling the operating frequency of the clock signal CLK supplied to the shift register.

(2) Details of First Embodiment FIG. 1 is a block diagram showing a circuit configuration of a thermal head driving integrated circuit (IC) of the present embodiment. The integrated circuit for driving a thermal head 0 is integrated on a semiconductor chip, and is used to control the energization of a plurality of heating resistors 1 constituting the thermal head in accordance with print data. In the present embodiment, two-color printing is possible. For example, red is generated during the energization time t1 and the energization time t2
A description will be given of a thermal head driving IC in the case of performing two-color printing of red and black using a recording paper that emits black at (t2> t1).

As shown in FIG. 1, a thermal head driving IC0 has a driver output terminal DO as an external terminal.
1 to DO64, power supply terminal VDD, ground terminal VSS, print data input terminal SI, print data output terminal SO, various control terminals STBr, STBb, LCHr, LCHb, C
LK. And a thermal head driving IC
Numeral 0 denotes a drive unit 11 as a driver for driving a thermal head, and a shift register unit 4 for sequentially transferring and storing serially supplied print data as its internal circuits.
And a latch unit 5r for latching red data r for red printing among the print data stored in the shift register unit 4.
And a latch section 5b for latching black data b for black printing.

The drive section 11 has driver output terminals DO1 to DO1.
The drive transistor 2, the inverter 12, the NOR circuit 13, the two 2-input AND circuits 3r,
3b and 64 inverters 7r and 7b
have. As each drive transistor 2, an enhancement type FET is used. Each drive transistor 2
Are connected to the corresponding driver output terminals DO1 to DO64 by open drain, and a total of 64 heating resistors 1 are connected to the driver output terminals DO1 to DO64. All sources are at ground potential VS
Connected to S. The gate of each drive transistor 2 is connected to an output terminal of an inverter 12 as a delay unit configured to increase the L length, and an input terminal of the inverter 12 is connected to a two-input NOR circuit 13. ing. Both input terminals of the NOR circuit 13 have an output terminal of an AND circuit 3r for red printing and an AND terminal for black printing.
The D circuit 3b is connected. The first input terminals of the 64 AND circuits 3r are commonly connected to a control terminal STBr via an inverter 7r. Similarly, the first input terminals of the 64 AND circuits 3b are commonly connected to a control terminal STBb via an inverter 7b. The control terminals STBr and STBb are pulled up to the power supply VDD via pull-up resistors. Further, the second input terminals of the respective AND circuits 3r are all connected to corresponding stages of the latch circuit 5r. The second input terminals of each AND circuit 3b are all connected to corresponding stages of the latch circuit 5b.

The shift register unit 4 has 64 D-FFs.
(Data-flip-flop) in series, and stores 64 bits of red data r and black data b in one line of print data while sequentially shifting them to the output terminal side. I have. Shift register 4
Are connected via a buffer 8 to a print data input terminal SI. The last stage of the shift register 4 is
The output terminal SO of the print data via the buffer 8
It is connected to the. Each stage of the shift register 4
Commonly connected to a control terminal CLK via a buffer 8, and a clock signal is supplied to each of them. The shift register 4 sequentially reads the print data signal input to the data input terminal SI at the rise of the clock signal applied to the control terminal CLK, and reads the print data already read (stored in the D-FF). The stage shifts to the stage on the output terminal SO side.

The latch section 5 includes a latch circuit 5r for taking in red data r and a latch circuit 5b for taking in black data b. The latch circuits 5r and 5b are composed of 64 latch elements LA, and the output of each stage is connected to the corresponding AN.
It is connected to the second input terminals of the D circuits 3r, 3b.
The inputs of each stage of the latch circuits 5r and 5b are both connected to the output of the D-FF of the corresponding stage in the shift register 4. A control terminal LCHr is commonly connected to each latch element LA of the latch circuit 5r via a buffer 8, and a latch signal LCHr is supplied. Latch circuit 5b
Similarly, the control terminals LCHbr are commonly connected via the buffer 8 to each of the latch elements LA, and are supplied with the latch signal LCHb. Latch circuit 5r, 5b
When the latch signals LCHr and LCHb rise, the print data stored in the corresponding stage of the shift register 4 is fetched collectively. The latch circuits 5r and 5b hold the print data fetched immediately before until the next latch signals LCHr and LCHb are supplied (at the time of rising), and hold the second input of the corresponding AND circuits 3r and 3b. Supply to the terminal.

The latch circuits 5 r and 5 b have their inputs connected to the shift register 4, so that red data r and black data b are fetched from the same shift register 4. That is, when the red data r is input to the shift register 4, the red data r is taken into the latch circuit 5 r by supplying the latch signal LCHr, and when the black data b is input to the shift register 4. Is the latch signal L
CHb is supplied, and the black data b is taken into the latch circuit 5b. As described above, according to the integrated circuit for driving a thermal head of the first embodiment, by sharing one shift register 4 for the red data r and one for the black data b, one chip is used for one shift register. The size can be reduced.

Next, a description will be given of an operation when two-color printing of red and black is performed by the thermal head driving IC configured as described above. Now, a case where printing is performed for the mth and subsequent lines will be described as an example. When printing the red color included in the m-th line and one line, the common use control terminal SI
And 64 bits of red data r are supplied serially. Each time a clock signal is supplied from the control terminal CLK, 64-bit red data r is stored in the shift register 4 while sequentially shifting the D-FF in the direction of the output terminal SO. Red data r stored in the shift register 4
Is supplied to both the latch circuits 5r and 5b, but since the red data r, the black latch signal LCHb is not supplied, and only the latch signal LCHr is supplied to the control terminal LCHr.
Supplied from Therefore, the 64-bit red data r stored in the shift register 4 is simultaneously captured only by the latch circuit 5r when the latch signal LCHr rises. The red data r captured by the latch circuit 5r is used for the red data r in the driving unit 11 until the next latch signal LCHr is supplied and the red data r of the next line (the (m + 1) th line) is latched. It is continuously supplied to the AND circuit 3r.

At a predetermined timing, the L-level strobe signal STBr is supplied for a time T1 (T1 = t1 + α (α
Is supplied by the inverter 7r, the H level signal is supplied to the AND circuit 3r, and the red data r supplied from the corresponding stage of the latch circuit 5r is supplied to the AND circuit 3r. 3r.
During this time, the strobe signal STBb for the black data b
Is not output, and therefore, the black data b is not output from the AND circuit 3b. When the red data r is output from the AND circuit 3r, the red data r is inverted by the NOR circuit 13 and then inverted again by the inverter 12 and output to the gate of the drive transistor 2. That is, when the signal level of the red data r supplied from the latch circuit 5r of each stage is at the H level, an H-level signal is output from the inverter 12 by the strobe signal STBr. As a result, the drive transistor 2 is turned on, and the corresponding heating resistor 1 of the thermal head is energized for the time t1 to print red. On the other hand, the drive transistor 2 of the bit whose signal level of the red data r is L level is OFF.
become.

The 64-bit red data r input to the shift register 4 is held in the latch circuit 5r by supplying the latch signal LCHr, and the driving unit 11 drives the thermal head by the output of the strobe signal STBr to drive the red data r. Is printed, the process for performing black printing on the same line is performed. That is, the red data r
Is held in the latch circuit 5r, black data b for the m-th line is serially supplied from the control terminal SI, and each time the clock signal CLK is supplied from the control terminal CLK, the black data b sequentially outputs the D-FF. The data is stored in the shift register 4 while being shifted in the direction of the output terminal SO. The black data b stored in the shift register 4 is also transmitted to the latch circuits 5r and 5r.
b, but since the black data b, the latch signal LCHr for red is not supplied.
Only CHb is supplied from the control terminal LCHb. Therefore, the 64-bit black data b stored in the shift register 4 is simultaneously captured only by the latch circuit 5b when the latch signal LCHb rises. The black data b captured by the latch circuit 5b is used for the black data b in the driving unit 11 until the next latch signal LCHb is supplied and the black data b of the next line (the (m + 1) th line) is latched. It continues to be supplied to the AND circuit 3b.

When the L-level strobe signal STBb is supplied for a time T2 (T2 = t2 + α) at a predetermined timing, the black data b AND circuit 3b outputs the black data b as in the case of printing the red data r. b is output.
Then, when the H-level black data b is output, it is inverted and output by the NOR circuit 13, then inverted again by the inverter 12, rises with a delay, and turns on the drive transistor 2. Driving transistor 2 energizes heating resistor 1 for a time t2 corresponding to strobe signal STBb = T2. Thereby, black is printed on the recording paper.

With the above-described printing operation of the red data r and the black data b, printing of 64 bits per line is completed, and the recording paper or the thermal head is moved by one line by a driving unit (not shown). Is similarly performed.

As described above, the latch signal LCH
r, LCHb supply timing and strobe signal ST
By controlling the supply timing of Br and STBb, 1
Two shift registers 4 can be shared for inputting red data r and inputting black data b, thereby performing two-color printing.
Note that a shift register dedicated to red data r and black data b
Compared to the configuration of FIG. 5 using a dedicated shift register,
When supplying clock signals CLK of the same frequency,
In the case of the integrated circuit for driving a thermal head according to the present embodiment, the printing speed is reduced. However, by doubling the operating frequency of the clock signal CLK, printing can be performed at the same speed as when two shift registers are used.

Further, by further increasing the operating frequency of the clock signal CLK to three times, four times, or five times or more, using the integrated circuit for driving a thermal head of the present embodiment,
It is possible to perform two-color printing at the same speed as one-color printing. Regarding this, a second embodiment described later, a third
This is common to the embodiments. However, the clock signal CLK
When the operating frequency of the shift register 4 is increased, for example,
When the red data r of the m + 1 line is stored in the shift register 4, the red data r of the m line is still being printed (while the strobe signal STBr for the m line is being supplied).
Could be As described above, when the red data r of the (m + 1) th line is held by the latch circuit 5r by the latch signal LCHr, if the printing of the red data r of the mth line is not completed, the red data r of the mth line is transmitted from the latch circuit 5r to the AND circuit 3r. It is necessary to keep supplying r. Therefore,
Even if the red data r of the (m + 1) th line has been stored in the shift register 4, the latch signal LCHr is not supplied immediately. In this case, the latch circuit 5r holds m lines of red data r, the latch circuit 5b holds m lines of black data b, and the shift register 4 stores m + 1 lines of red data r. is there. Then, when the supply of the strobe signal STBr ends (time T1 elapses) and the printing of the m-line red data r ends, the strobe signal STBb is output, and the printing of the m-line black data b starts. The latch signal LCHr is supplied, and the red data r of the (m + 1) th line stored in the shift register 4 is simultaneously held in the latch circuit 5r. Similarly, when the latch circuit 5b holds the black data b of the m + 1 line by the latch signal, the black data b of the m line
If printing is being performed, the latch signal L
CHb is supplied to simultaneously hold the m + 1-line black data b in the latch circuit 5r, and the strobe signal S
TBr is supplied, and printing of the red data r of the (m + 1) th line is started.

In the present embodiment, an inverter 12 having a large L length is connected to each gate of each drive transistor 2 for controlling energization to each heating resistor, and an output terminal of a NOR circuit 13 is connected to the inverter 12. And red data r and black data b are input to two input terminals of the NOR circuit 13 by the strobe signals STBr and STBb, respectively. Thus, in the present embodiment,
The inverter 12 is used as an element for adjusting the delay time by increasing the L length to mitigate the overshoot, and both the red data r and the black data b use the inverter 1
2 to drive the driving transistor 2, the switching speed of the driving transistor 2 for the same dot becomes the same for the red data r and the black data b, and the gradation control and color control (PWM = pulse width) for the same dot ), The gradation of each dot (bit) is prevented from becoming non-uniform, and print quality can be improved. According to the present embodiment, print quality can be maintained even when high-speed printing is performed by increasing the operating frequency of the clock signal CLK.

Next, a second embodiment will be described. (3) Overview of Second Embodiment In the integrated circuit for driving a thermal head according to the second embodiment, as in the first embodiment, two latch circuits are provided, and one shift register is provided with red data r. Although they are common in that they are shared with the black data b, the latch circuits 5r, 5b
In the way data is imported into That is, in the first embodiment, the red data r and the black data b alternately stored in the shift register are held in the corresponding latch circuits 5r and 5b by the latch signals LCHr and LCHb supplied alternately and independently. You. Thus, the red data r in the first embodiment is held only in the latch circuit 5r, and the black data b is held only in the latch circuit 5b. On the other hand, in the second embodiment, the latch circuit 5r
Does not hold the red data r directly from the shift register 4,
The red data r temporarily output via the latch circuit 5b is held. As described above, in the second embodiment, the red data r and the black data b are held in both the latch circuits 5r and 5b. The printing timing of the red data r and the black data b is determined by the strobe signals STBr and STBb supplied alternately and independently.

(4) Details of Second Embodiment FIG. 2 is a block diagram showing a circuit configuration of a thermal head driving integrated circuit (IC) according to the second embodiment.
The same portions as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate. As shown in FIG. 2, in the latch circuit 5r of the second embodiment, a D-FF is used as a latch element, and the latch circuit 5b
And the latch signal LCH common to the latch circuit 5b is input. Then, the output from each latch element constituted by the D-FF is supplied to the AND circuit 3r of the drive unit 11.

As the D-FF in the latch circuit 5r, the same element as the D-FF used in each stage of the shift register 4 is used. This D-FF element has 2
It is designed to store different types of data. The D-FF element includes two data storage units in the front and rear stages so that two data are stored therein, and the data stored in the rear stage (the data input earlier) is output from the output terminal. Has become. When new data is input, data stored in the previous stage is first shifted to the next stage, and then new data is stored in the previous stage. For example, when data is input in the order of data D1 and data D2, the data D1 is placed before the D-FF element.
However, the data D2 is stored in the subsequent stage, and the previously input data D1 is output from the output terminal. When the next data D3 is input by the clock signal CLK (the latch signal LCH in the latch circuit 5r), the clock signal C
At the rise of LK (LCH), the data D2 stored in the previous stage is stored in the subsequent stage and output from the output terminal (at this point, the data D2 is stored in both the previous stage and the subsequent stage). Then, at the fall of the clock signal CLK (LCH), the latest input data D3 is stored in the preceding stage, and the state of the preceding stage data D3 and the succeeding stage data D2 is established. Such D-
By using the FF element as the latch element of the latch circuit 5r, data can be stored from the latch circuit 5b using the common latch signal LCH.

Next, a printing operation based on the red data r and the black data b according to the second embodiment will be described. When the red data r is stored in the shift register 4, the latch signal LCH is supplied to both the latch circuits 5r and 5b, and at the time of the rise, the red data r is stored in each of the latch elements LA of the latch circuit 5b. The stored red data r is output and supplied to the AND circuit 3b and the D-FF of the latch circuit 5r. In the latch circuit 5r, the red data r output from the latch circuit 5b is output.
Is stored before the respective D-FFs when the latch signal LCH falls. In this state, since the corresponding red data r and black data b are not yet stored (output) in the latch circuits 5r and 5b, both strobe signals STB and STB are output.
Both r and STBb are not output.

Next, when the black data b is stored in the shift register 4 and the latch signal LCH is supplied to both the latch circuits 5r and 5b, the latch circuit 5b stores the black data b in each latch element LA at the time of the rise. At the same time, the stored black data b is supplied to the D-FF of the AND circuit 3b and the latch circuit 5r. On the other hand, each D-FF of the latch circuit 5r
Then, the red data r already stored in the previous stage is stored in the subsequent stage when the latch signal LCH rises, and the red data r stored in the subsequent stage is output from the D-FF and supplied to the AND circuit 3r of the drive unit 11. You. And the latch signal LC
At the fall of H, the black data b supplied from each latch element LA of the latch circuit 5b is stored in the preceding stage.

As described above, the rising edge of the second latch signal LCH causes the latch circuit 5b to output the black data b,
Red data r is output from the latch circuit 5r, and printing is enabled by the output of both strobe signals STBr and STBb. That is, when the L-level strobe signal STBr is first supplied for the time T1, the latch circuit 5
r, the red data r supplied from the corresponding stage
Driving the driving transistor 2 output from the circuit 3r,
Printing of the red data r is performed by the thermal head 1.
After the printing of the red data r is completed (the strobe signal STB
After the time T1 has been output and the time T1 has elapsed), the strobe signal STBb for the black data b is supplied for the time T2, and the black data b supplied from the corresponding stage of the latch circuit 5b is supplied from each AND circuit 3b. The output is used to drive the drive transistor 2, and the thermal head 1 prints black data b.

While the red data r and the black data b are being printed, the red data r for the next line is stored in the shift register 4. Then, after the printing of the black data b is completed, the latch signal LCH is supplied, and the red data r of the next line is supplied to the latch circuit 5 in the same manner as described above.
b, and each D-FF of the latch circuit 5r.
Is stored in the preceding stage. Similarly, the black data b of the next line is stored in the latch circuit 5b, the red data r is stored in the subsequent stage of the latch circuit 5r, the black data b is stored in the previous stage, and the strobe signals STBr and STBb are stored. With the output, the red data r and the black data b of the next line are printed.

As described above, in this embodiment, black data b and red data r are alternately output from the latch circuit 5r, and red data r and black data b are output from the latch circuit 5b.
Are alternately output (red data r is not output at the same time, and black data b is not output at the same time).
The red data r is output from the AND circuit 3r by the supply timing of the strobe signals STBr and STBb (the timing during which the red data r is output from the latch circuit 5r and the black data b is output from the latch circuit 5b). T1 is output, and black data b is output from the AND circuit 3b for a time T2, so that printing of red data r and printing of black data b are appropriately performed. As described above, according to the second embodiment, the shift register 4 is shared by the red data r and the black data b to be one, thereby reducing the size of the chip and appropriately setting the red data r and the black data b. Printing can be performed at an appropriate timing.

In the second embodiment, as shown in FIG. 2, the data input terminal of each D-FF of the latch circuit 5r is connected to the output terminal of the corresponding latch element LA of the latch circuit 5b. However, the following may be performed. That is, at the timing when data is stored in the preceding stage of the latch circuit 5r (when the latch signal LCH falls),
The print data output from each latch element LA of the latch circuit 5b is the same as the print data output from each D-FF of the shift register 4. Therefore, the data input terminal of each D-FF of the latch circuit 5r may be connected to the output terminal of the D-FF of the corresponding stage in the shift register 4. In this case, each D-
The data input terminal of the FF is commonly connected to the input terminal of the latch element LA of the corresponding stage of the latch circuit 5b. Even in the case of such a configuration, the red data r and the black data b can be appropriately printed by operating the thermal head driving integrated circuit as in the second embodiment.

As described above, in the thermal head driving IC0 of the first and second embodiments, the shift register 4 and the latch circuit 5 for holding the print data supplied serially are provided with the red data r and the black data. b strobe signal ST having different output times (pulse widths)
The signals are output from the AND circuits 3r and 3b by Br and STBb. Then, the red data r output from the AND circuit 3r and the black data b output from the AND circuit 3b are
Output from a common output terminal by a two-input NOR circuit 13;
Further, by outputting the same delay element, that is, the output from the one-input inverter 12, the driving transistor 2 is turned on,
OFF is controlled. As described above, according to the present embodiment, since the print data of two colors is output from the same delay element to drive the drive transistor 2, the energization delay time in each heating resistor 1 is the same for each color. Can be Further, in the thermal head driving IC0 of this embodiment, only one inverter 12 is used as a delay element. And this inverter 12
Is one input, and the L length for that input is configured to be large. As described above, in the present embodiment, since the portion having the large L length is one location, an increase in the chip size is prevented.

Next, a third embodiment will be described. (5) Overview of Third Embodiment In the integrated circuit for driving a thermal head according to the third embodiment, two shift registers are provided in correspondence with red data r and black data b, while one latch circuit is used as the red data. r
In this case, the number of latch circuits is reduced by one and the chip size is reduced by sharing the data for the black data b.

(6) Details of Third Embodiment FIG. 3 is a block diagram showing a circuit configuration of a thermal head driving integrated circuit (IC) of this embodiment. In addition,
The same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate. As shown in FIG.
The shift register 4 includes a shift register 4r for red data r and a shift register 4b for black data b configured in the same manner as the shift register 4 described in the embodiment. As shown in FIG. 3, the integrated circuit for driving a thermal head according to the third embodiment includes a shift register 4r and a shift register 4b having the same configuration as the shift register 4 described in the first embodiment. Red data r is serially input from the control terminal SIr to the shift register 4r, and the shift register 4b
, Black data b is serially input from the control terminal SIb.

In this embodiment, there is provided one latch circuit 5 which is shared for holding the red data r and the black data b. This latch circuit 5 includes a shift register 4r,
4b, 64 latch elements LA are provided corresponding to each stage, and the output of each stage is connected to the second input terminal of the corresponding AND circuit 3 respectively. A data input terminal of each stage of the latch circuit 5 includes an AND circuit 53r and an AND circuit 5
3b are connected to each other, and the control terminal is connected to an OR circuit 5
The 3L output terminal is connected. A first input terminal (left side in the drawing) of each OR circuit 53L and each AND circuit 53r
Has a control terminal L via a buffer 8
CHr are commonly connected, and a latch signal LCHr is supplied. A control terminal LCHb is commonly connected via a buffer 8 to a second input terminal (on the right side in the drawing) of each OR circuit 53L and a first input terminal of each AND circuit 53b. It is being supplied. The second input terminal of each AND circuit 53r is
D-FF of the corresponding stage in each shift register 4r
Output terminal. The second input terminal of each AND circuit 53b is connected to the output terminal of the corresponding stage D-FF in the shift register 4b.

Thus, the latch circuit 5 is supplied with the red data r from the shift register 4r via the AND circuit 53r, and collectively collects the red data r when the latch signal LCHr supplied via the OR circuit 53L rises. And supplies it to the AND circuit 3 of the drive unit 11. Also, AN
Black data b is supplied from the shift register 4b via the D circuit 53b, and the black data b is fetched collectively at the rise of the latch signal LCHb supplied via the OR circuit 53L and supplied to the AND circuit 3 of the drive unit 11. I do.

On the other hand, the driving unit 11 in the present embodiment
The output terminal of the AND circuit 3 is connected to the gate of each drive transistor 2. The output terminal of the latch element LA of the corresponding stage of the latch circuit 5 is connected to the second input terminal of the AND circuit 3 and the first input terminal is pulled up to the power supply VDD via the inverter 7. Connected to the connected control terminal STB. In the first and second embodiments, the overshoot is prevented by the inverter 12 having a long L length. However, in the present embodiment, the inverter 12 is not used, and instead, the AND circuit connected to the control terminal STB is used. 3 first input terminal (left side in the drawing)
The overshoot is prevented by increasing the length L on the side.

As described above, according to the third embodiment, the number of latch circuits can be reduced by one, and the chip size can be reduced by sharing one latch circuit for red data r and black data b. The size can be reduced. The latch circuit 5 includes an OR circuit 53L,
Although it is necessary to use the AND circuits 53r and 53b, since the number of logic elements of the driving unit 11 can be reduced, the number of elements including the latch circuit 5 and the driving unit 11 increases only slightly. By reducing the number of chips, it is possible to reduce the size of the chip in the entire thermal head driving integrated circuit.

Next, a printing operation based on red data r and black data b according to the third embodiment will be described. First, when red data r is sequentially input serially from the control terminal SIr and stored in the shift register 4r, the red data r is supplied from the D-FF of each stage to the corresponding AND circuit 53r. In this state, the latch circuit 5 outputs the latch signal L for red.
CHr is supplied to each OR circuit 53L and AND circuit 53r. Then, the latch signal LCHr is supplied to the latch element LA via the OR circuit 53L, the red data r is supplied from the AND circuit 53r, the red data r is stored in each latch element LA, and the driving unit 11 AND
It is supplied to the circuit 3. Thereafter, the strobe signal STB is supplied for the time T1, and the red data r is output from each AND circuit 3.
The corresponding drive transistor 2 is driven according to the contents of the above, and printing based on the red data r is performed. During the period from the input of the red data r to the shift register 4r to the end of the printing,
The black data b is serially input from the control terminal SIb and stored in the shift register 4b. And red data r
Is completed (after the time T1 has elapsed after the strobe signal STBr is supplied), the black latch signal LCH
b is supplied to each OR circuit 53L and AND circuit 53b. Then, the latch signal LCHb is supplied to the latch element LA via the OR circuit 53L, and the AND circuit 5L
3b, black data b is supplied. Each latch element LA stores new black data b instead of red data r, and black data b is supplied to the AND circuit 3 of the drive unit 11. Thereafter, the strobe signal STB is supplied only for the time T2, and the corresponding drive transistor 2 is driven from each AND circuit 3 in accordance with the content of the black data b, and the black data b
Is performed based on the.

Although the red data r and the black data b are input to the control terminal SIr and the control terminal b at different timings, the red data r and the black data b are input at the same timing. Latch signal LCHr for
And the supply timing of the black latch signal LCHb may be shifted (after the printing of one is completed, the latch signal of the other is supplied). As described above, when the red data r and the black data b are sequentially input to the respective shift registers 4r and 4b at the same timing, the control terminal CLK
r and the control terminal CLKb can be made common. That is, each D-FF of the shift register 4r and each D-FF of the shift register 4b can all be commonly connected to the common control terminal CLK via the buffer 8.

The configuration and operation of the thermal head driving IC 0 of the present embodiment have been described above. However, the present invention is not limited to these configurations and operations, and the scope of the invention described in each claim is not limited thereto. Various modifications are possible.

For example, in the above-described embodiment, the case of two-color printing of red and black has been described. However, the same can be applied to the case of n-color printing and n-gradation printing. Also in this case, as described in the first to third embodiments, by using a common shift register or latch circuit for each specific number of colors, even in the case of n colors and n gradation printing. , At least one or more shift registers or latch circuits can be reduced. As a result, the chip size of the integrated circuit for driving the thermal head can be reduced.

[0044]

According to the present invention, one of the shift register and the holding means is made smaller than the other, and at least one of the shift registers and the holding means is made smaller.
Since the set is commonly used, it is possible to suppress an increase in the circuit size of the integrated circuit for driving a thermal head even when performing multiple gradation printing or multiple color printing with one heating resistor.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a circuit configuration of a thermal head driving integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a circuit configuration of a thermal head driving integrated circuit according to a second embodiment.

FIG. 3 is a block diagram illustrating a circuit configuration of a thermal head driving integrated circuit according to the second embodiment.

FIG. 4 is a block diagram showing a basic configuration of a conventional thermal head driving IC.

FIG. 5 is a block diagram illustrating a configuration of a thermal head driving IC for two-color printing, which can be considered by using a conventional one-color thermal head driving IC.

[Explanation of symbols]

 0 Integrated circuit for driving a thermal head 1 Heating resistor 2 Drive transistor 3, 3r, 3b AND circuit 35L OR circuit 35r, 35b AND circuit 4, 4r, 4b Shift register 5, 5r, 5b Latch circuit 7r, 7b Inverter 8 Buffer 11 Drive unit 12 Inverter 13 NOR circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tatsuya Tachibana 1-8-1 Nakase, Mihama-ku, Chiba-shi, Chiba Inside Seiko Instruments Inc. Within Seiko Instruments Inc. (72) Inventor Sumitaka Goshima 1-8 Nakase, Mihama-ku, Chiba-shi, Chiba F-term within Saiko Instruments Inc. DB18 EA01 EA02

Claims (2)

[Claims] 1. An integrated circuit for driving a thermal head for controlling energization of a plurality of heating resistors in accordance with print data, wherein n sets of shift registers sequentially transfer and store print data supplied serially. M (m> n) sets of holding means for collectively holding the print data stored in the shift register; and sequentially reading out the data held in the m sets of holding means to collectively generate the plurality of heats. A set of driving means for controlling the energization of a resistor; and an output of at least one set of the shift register is connected to an input of a plurality of sets of the holding means. circuit. 2. An integrated circuit for driving a thermal head for controlling energization of a plurality of heating resistors in accordance with print data, wherein n sets of shift registers sequentially transfer and store print data supplied serially. And m (m <n) sets of holding means for collectively holding the print data stored in the shift register; and sequentially reading out the data held in the m sets of holding means to collectively generate the plurality of heats. A pair of driving means for controlling energization of a resistor, wherein at least one input of the holding means is connected to outputs of a plurality of sets of the shift registers. circuit.