JP3625389B2 - Integrated circuit for driving thermal head - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit for driving a thermal head, for example, to an integrated circuit for driving a thermal head capable of performing multicolor printing by setting a plurality of energizing times for each heating resistor.
[0002]
[Prior art]
Printers using thermal heads are widely used as printers for printing documents and images created with the widespread use of various OA supplies such as personal computers and word processors.
For example, this thermal head includes 1728 heating resistors arranged in a line when printing line-sequentially on A4 paper. The heating resistors are divided into 64 blocks, and each block is controlled to be turned on (energized) and off (energized) by a thermal head driving IC for each block.
[0003]
FIG. 4 is a block diagram showing the basic configuration of such a thermal head driving IC.
As shown in this figure, the thermal head driving IC 100 includes a shift register 101, a latch circuit 102, and a driver 103.
The shift register 101 is connected in series with 64 D-FFs (data-flip flop circuits) corresponding to the heating resistors connected to the driver 103, and print data supplied serially is controlled by a control terminal. The shift is performed according to a clock signal input from CLK.
The latch circuit 102 also includes 64 latch elements, and print data of each DFF of the corresponding shift register 101 is indicated by an arrow B in each corresponding latch element by a latch signal input from the control terminal LCH. The print data is held at the same time, and the held print data is supplied to the driver 103.
The driver 103 includes 64 transistors for driving the connected heating resistors, and the print data is supplied according to the print data supplied from the latch circuit 102 while the strobe signal is supplied from the control terminal STB. Each heating resistor is energized from the transistor corresponding to 1 ″.
[0004]
Incidentally, printing by the thermal head is usually one color, and the thermal head driver IC for that purpose is also configured for one color as shown in FIG.
On the other hand, a case where a plurality of gradations are printed or a plurality of colors is printed by one heating resistor that prints one dot is conceivable. That is, there are cases where the color density is changed by changing the energizing time for one heating resistor, or multiple colors are printed by using recording paper that develops different colors according to the amount of heat energy by the energizing time. Conceivable.
FIG. 5 shows a configuration of a thermal head driving IC for two-color printing, which can be considered by using a conventional one-color thermal head driving IC.
As shown in this figure, when the thermal head driving IC 100 for two colors (for example, red and black) is configured, the print data to be input includes the print data r for red and the print data b for black. There are two types. For this reason, the shift register 101r and latch circuit 102r for red print data, and the shift register 101b and latch circuit 102b for black print data are used.
For the driver 103, a logic circuit for selecting one of the print data supplied from the latch circuit 102r and the latch circuit 102b is assembled, so that the transistors for energizing the heating resistor are used for red and black. However, since the strobe signal for controlling the driving of the transistors needs to be red and black, control terminals STBr and STBb are provided.
[0005]
In such a configuration of the drive unit, by changing the output time of the strobe signal STBr and the output time of the strobe signal STBb, the time for which the transistor of the driver 103 is turned on changes according to the print color, and the heating resistor Multi-tone printing and multi-color printing are performed by changing the heat generation time by the body.
For example, when using a recording paper in which red is developed by short-time energization and black is developed by long-time energization, strobe signal STBr having a short pulse width is supplied while supplying red print data r. This makes it possible to print red in one line. On the other hand, black of the same line can be printed by supplying strobe signal STBb having a long pulse width while supplying black print data DATb.
[0006]
[Problems to be solved by the invention]
However, as shown in FIG. 5, when a two-color thermal head driver IC is configured using a conventional one-color thermal head driver IC, the type of print data (in the case of FIG. In accordance with the increase in the number of two types, it is necessary to arrange the number of colors using shift registers and latch circuits.
That is, when n-color printing is performed using print data for n colors, n sets of shift registers and latch circuits are required, which increases the size of the chip.
[0007]
Accordingly, an object of the present invention is to provide an integrated circuit for driving a thermal head that can suppress an increase in circuit size even when performing multiple gradation printing or multiple color printing with a single heating resistor. .
[0008]
[Means for Solving the Problems]
In the present invention, an integrated circuit for driving a thermal head that controls energization of a plurality of heating resistors in response to print data, and n sets of shift registers that sequentially transfer and store print data supplied serially; , M (m> n) sets of holding means for collectively holding the print data stored in the shift register, and the plurality of heating resistors by sequentially reading the data held in the m sets of holding means. A set of driving means for controlling energization of the body, and outputs of at least one set of the shift registers are connected to inputs of a plurality of sets of the holding means.
According to the present invention, there is provided a thermal head driving integrated circuit for controlling energization of a plurality of heating resistors corresponding to print data, and n sets of shift registers for sequentially transferring and storing print data supplied serially And m (m <n) sets of holding means for collectively holding the print data stored in the shift register, and sequentially reading the data held in the m sets of holding means in batches to generate the plurality of heat generations. And a set of driving means for controlling energization of the resistor, and the inputs of at least one set of the holding means are connected to the outputs of a plurality of sets of the shift registers.
As described above, in the present invention, one of the shift register and the holding means is smaller than the other, and at least one set on the smaller side is commonly used. As a result, the circuit size of the integrated circuit for driving the thermal head can be reduced.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Preferred embodiments of the thermal head driving integrated circuit according to the present invention will be described in detail below with reference to the drawings.
(1) Overview of the first embodiment
In this embodiment, two latch circuits for red and black are used for print data of two colors, but one shift register for supplying data to this latch circuit is used, and the input of red data r and black The data b is commonly used for input. Thus, by using the shift register in common, only one shift register is required, and the chip can be reduced in size.
When such a thermal head driving integrated circuit is used, the input of the red data r and the black data b are alternately input from the control terminal SI, and the corresponding latch signal is output after the 64 bits of each color data have been input. Two-color printing (printing) becomes possible by inputting.
By commonly using the shift register, the time for latching and printing the red data r and the black data b in the corresponding latch circuit is delayed as compared with the case where the two shift registers input in parallel. In this regard, printing at the same speed can be performed by doubling the operating frequency of the clock signal CLK supplied to the shift register.
[0010]
(2) Details of the first embodiment
FIG. 1 is a block diagram showing a circuit configuration of a thermal head driving integrated circuit (IC) of this embodiment.
The integrated circuit 0 for driving the thermal head is integrated on a semiconductor chip, and is used for controlling energization to the plurality of heating resistors 1 constituting the thermal head in accordance with print data. In this embodiment, two-color printing is possible. As an example, red and black 2 are printed using recording paper that develops red at energization time t1 and develops black at energization time t2 (t2> t1). A thermal head driving IC for color printing will be described.
[0011]
As shown in FIG. 1, the thermal head driving IC 0 includes driver output terminals DO1 to DO64, a power supply terminal VDD, a ground terminal VSS, a print data input terminal SI, a print data output terminal SO, and various control terminals as external terminals. STBr, STBb, LCHr, LCHb, and CLK are provided.
The thermal head driving IC 0 includes, as internal circuits, a driving unit 11 as a driver for driving the thermal head, a shift register unit 4 for sequentially transferring and storing print data supplied serially, and a shift register unit. 4 includes a latch unit 5r that latches red data r for red printing, and a latch unit 5b that latches black data b for black printing.
[0012]
The drive unit 11 has 64 sets of drive transistors 2, an inverter 12, a NOR circuit 13, two 2-input AND circuits 3r and 3b, and two inverters 7r and 7b corresponding to the driver output terminals DO1 to DO64. doing.
Each drive transistor 2 is an enhancement type FET. Each drive transistor 2 is open drain connected to the corresponding driver output terminals DO1 to DO64, and a total of 64 heating resistors 1 are connected to the driver output terminals DO1 to DO64. All sources are connected to the ground potential VSS.
The gate of each drive transistor 2 is connected to an output terminal of an inverter 12 as a delay means configured to increase the L length, and a 2-input NOR circuit 13 is connected to the input terminal of the inverter 12. ing. The input terminal of the NOR circuit 13 is connected to the output terminal of the AND circuit 3r for red printing and the AND circuit 3b for black printing.
The first input terminals of the 64 AND circuits 3r are commonly connected to the control terminal STBr via the inverter 7r. Similarly, the first input terminals of the 64 AND circuits 3b are commonly connected to the control terminal STBb via the inverter 7b. The control terminals STBr and STBb are pulled up to the power supply VDD via a pull-up resistor.
The second input terminals of each AND circuit 3r are all connected to the corresponding stages of the latch circuit 5r. The second input terminals of each AND circuit 3b are all connected to the corresponding stages of the latch circuit 5b.
[0013]
The shift register unit 4 is configured by serial connection of 64 D-FFs (data-flip flops), and sequentially outputs red data r and black data b for 64 bits of print data for one line. The data is stored while shifting to the terminal side.
The shift register 4 is connected to an input terminal SI for print data via a buffer 8. The last stage of the shift register 4 is connected to the print data output terminal SO via the buffer 8.
Each stage of the shift register 4 is commonly connected to the control terminal CLK via the buffer 8 so that a clock signal is supplied to each stage.
The shift register 4 sequentially reads the print data signal input to the data input terminal SI at the rising edge of the clock signal applied to the control terminal CLK, and also reads the print data already read (stored in the D-FF). The stage shifts to the stage on the output terminal SO side.
[0014]
The latch unit 5 includes a latch circuit 5r that captures red data r and a latch circuit 5b that captures black data b. The latch circuits 5r and 5b are composed of 64 latch elements LA, and the outputs of the respective stages are connected to the second input terminals of the corresponding AND circuits 3r and 3b, respectively. The inputs of each stage of the latch circuits 5 r and 5 b are both connected to the output of the D-FF of the corresponding stage in the shift register 4.
The latch elements LA of the latch circuit 5r are commonly connected to the control terminal LCHr via the buffer 8, and are supplied with a latch signal LCHr. Similarly, the latch elements LA of the latch circuit 5b are connected in common to the control terminal LCHbr via the buffer 8 and supplied with the latch signal LCHb.
The latch circuits 5r and 5b collectively fetch the print data stored in the corresponding stage of the shift register 4 when the latch signals LCHr and LCHb rise. The latch circuits 5r and 5b hold the print data fetched immediately before the next latch signals LCHr and LCHb are supplied (until the rise time), and the second inputs of the corresponding AND circuits 3r and 3b, respectively. It is designed to be supplied to the terminal.
[0015]
The latch circuits 5r and 5b are both connected to the shift register 4 so that the red data r and the black data b are taken in from the same shift register 4, respectively. That is, when the red data r is input to the shift register 4, the red data r is captured by the latch circuit 5 r by supplying the latch signal LCHr, and the black data b is input to the shift register 4. Is supplied with the latch signal LCHb and the black data b is taken into the latch circuit 5b.
As described above, according to the integrated circuit for driving the thermal head of the first embodiment, the shift register 4 is shared by one for the red data r and the black data b, so that one chip corresponds to one shift register. It can be downsized.
[0016]
Next, the operation when two-color printing of red and black is performed by the thus configured thermal head driving IC will be described.
Now, the case of printing after the mth line will be described as an example.
When red printing included in the m-th line is performed, 64-bit red data r is serially supplied from the commonly used control terminal SI. Each time a clock signal is supplied from the control terminal CLK, 64-bit red data r is stored in the shift register 4 while sequentially shifting the D-FF in the direction of the output terminal SO.
The red data r stored in the shift register 4 is supplied to both the latch circuits 5r and 5b. However, since the red data is r, the black latch signal LCHb is not supplied and only the latch signal LCHr is controlled. Supplied from terminal LCHr. For this reason, the 64-bit red data r stored in the shift register 4 is taken into only the latch circuit 5r at the same time when the latch signal LCHr rises.
The red data r fetched into the latch circuit 5r is used for the red data r in the drive unit 11 until the next latch signal LCHr is supplied and the red data r of the next line (m + 1th line) is latched. It continues to be supplied to the AND circuit 3r.
[0017]
Then, when the L level strobe signal STBr is supplied for a time T1 (T1 = t1 + α (α is the time due to the rise delay)) at a predetermined timing, the inverter 7r inverts the H level signal to the AND circuit 3r. The supplied red data r supplied from the corresponding stage of the latch circuit 5r is output from the AND circuit 3r. During this time, the strobe signal STBb for the black data b is not output, and therefore the black data b is not output from the AND circuit 3b.
When the red data r is output from the AND circuit 3r, the red data r is inverted by the NOR circuit 13, then inverted again by the inverter 12, and output to the gate of the driving transistor 2.
That is, when the signal level of the red data r supplied from the latch circuit 5r at each stage is H level, a signal of H level is output from the inverter 12 by the strobe signal STBr. As a result, the drive transistor 2 is turned on, and the corresponding heating resistor 1 of the thermal head is energized for a time t1, and red is printed.
On the other hand, the drive transistor 2 of the bit whose red data r signal level is L level is turned OFF.
[0018]
The 64-bit red data r input to the shift register 4 is held in the latch circuit 5r by the supply of the latch signal LCHr, and the drive unit 11 drives the thermal head by the output of the strobe signal STBr to print the red data r. In the meantime, a process for performing black printing on the same line is performed.
That is, after the red data r is held in the latch circuit 5r, the black data b for the m-th line is serially supplied from the control terminal SI, and the black data b is supplied every time the clock signal CLK is supplied from the control terminal CLK. The D-FFs are sequentially stored in the shift register 4 while being shifted toward the output terminal SO.
The black data b stored in the shift register 4 is also supplied to both the latch circuits 5r and 5b. However, since the black data is b, the red latch signal LCHr is not supplied and only the latch signal LCHb is controlled. Supplied from terminal LCHb. For this reason, the 64-bit black data b stored in the shift register 4 is taken into only the latch circuit 5b at the same time when the latch signal LCHb rises.
The black data b fetched by the latch circuit 5b is used for the black data b in the driving unit 11 until the next latch signal LCHb is supplied and the black data b of the next line (m + 1th line) is latched. It continues to be supplied to the AND circuit 3b.
[0019]
Then, when the L-level strobe signal STBb is supplied for a time T2 (T2 = t2 + α) at a predetermined timing, the black data b is output from the AND circuit 3b for the black data b as in the printing of the red data r. Is done. When the H level black data b is output, it is inverted by the NOR circuit 13 and then inverted again by the inverter 12 and rises with a delay to turn on the driving transistor 2. The driving transistor 2 energizes the heating resistor 1 for a time t2 corresponding to the strobe signal STBb = T2. Thereby, black is printed on the recording paper.
[0020]
With the above printing operation of red data r and black data b, printing for 64 bits per line is completed, the recording paper or the thermal head is moved by one line by a driving unit (not shown), and printing for the next m + 1 line is performed. The same is done.
[0021]
As described above, by controlling the supply timing of the latch signals LCHr and LCHb and the supply timing of the strobe signals STBr and STBb, one shift register 4 can be used for inputting red data r and black data b. Two colors can be printed in common.
In the case where the clock signal CLK having the same frequency is supplied as compared with the configuration of FIG. 5 using the shift register dedicated to the red data r and the shift register dedicated to the black data b, the thermal head drive for this embodiment is used. In the case of an integrated circuit, the printing speed is slow, but it is possible to print at the same speed as in the case of two shift registers by doubling the operating frequency of the clock signal CLK.
[0022]
Further, the operating frequency of the clock signal CLK is further increased to 3 times, 4 times, 5 times or more, so that the thermal head driving integrated circuit of this embodiment is used and the speed is equivalent to that of one-color printing. Two-color printing can be performed. This is common to the second and third embodiments described later.
However, when the operating frequency of the clock signal CLK is increased, for example, when m + 1 lines of red data r are completely stored in the shift register 4, m lines of red data r are still being printed (m lines). During the supply of the strobe signal STBr to the In this way, when the m + 1 line red data r is held by the latch signal LCHr, if the m line red data r has not been printed, the latch circuit 5r sends the m line red data to the AND circuit 3r. It is necessary to continue supplying r. Therefore, even if the m + 1 line red data r is stored in the shift register 4, the latch signal LCHr is not immediately supplied. In this case, the latch circuit 5r holds m lines of red data r, the latch circuit 5b holds m lines of black data b, and the shift register 4 stores m + 1 lines of red data r. is there.
When the supply of the strobe signal STBr ends (time T1 elapses) and the printing of the m-line red data r ends, the strobe signal STBb is output and the printing of the m-line black data b starts. The latch signal LCHr is supplied and the m + 1 line red data r stored in the shift register 4 is simultaneously held in the latch circuit 5r.
Similarly, when the black data b of m + 1 line is held in the latch circuit 5b by the latch signal, if the black data b of m line is being printed, the latch signal LCHb is supplied to the latch circuit 5r after the printing is finished. The m + 1 line black data b is held at the same time, and the strobe signal STBr is supplied to start printing the m + 1 line red data r.
[0023]
In this embodiment, an inverter 12 having a large L length is connected to each gate of each drive transistor 2 that controls energization to each heating resistor, and an output terminal of the NOR circuit 13 is connected to this inverter 12. The red data r and the black data b are input to the two input terminals of the NOR circuit 13 by the strobe signals STBr and STBb, respectively. Thus, in this embodiment, the inverter 12 is used as an element for reducing the overshoot by adjusting the delay time by increasing the L length, and the inverter 12 is used for both the red data r and the black data b. Since the drive transistor 2 is driven through, the switching speed of the drive transistor 2 for the same dot is the same for the red data r and the black data b, and gradation control and color control (PWM = pulse width control) for the same dot. ), It is possible to prevent the gradation of each dot (bit) from becoming non-uniform and improve the printing quality. According to the present embodiment, the print quality can be maintained even when the operating frequency of the clock signal CLK is increased to perform high-speed printing.
[0024]
Next, a second embodiment will be described.
(3) Outline of the second embodiment
In the thermal head driving integrated circuit according to the second embodiment, as in the first embodiment, two latch circuits are provided, and one shift register is shared by the red data r and the black data b. Although common, the method for fetching data into the latch circuits 5r and 5b is different.
That is, in the first embodiment, the red data r and the black data b that are alternately stored in the shift register are held in the corresponding latch circuits 5r and 5b by the latch signals LCHr and LCHb that are alternately supplied independently of each other. The Thus, the red data r in the first embodiment is held only in the latch circuit 5r, and the black data b is held only in the latch circuit 5b.
On the other hand, in the second embodiment, the latch circuit 5r does not directly hold the red data r from the shift register 4, but temporarily holds the red data r output via the latch circuit 5b. As described above, in the second embodiment, the red data r and the black data b are held in both the latch circuits 5r and 5b. The print timing of red data r and black data b is determined by strobe signals STBr and STBb supplied alternately and independently of each other.
[0025]
(4) Details of the second embodiment
FIG. 2 is a block diagram showing a circuit configuration of a thermal head driving integrated circuit (IC) in the second embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.
As shown in FIG. 2, in the latch circuit 5r of the second embodiment, a D-FF is used as a latch element, and the output of the corresponding latch element in the latch circuit 5b is input to the latch circuit 5r. A latch signal LCH common to the circuit 5b is input. An output from each latch element constituted by the D-FF is supplied to the AND circuit 3r of the drive unit 11.
[0026]
The D-FF in the latch circuit 5r uses the same element as the D-FF used in each stage of the shift register 4. This D-FF element is configured to store two types of data therein.
The D-FF element is provided with a data storage unit in the former stage and the latter stage so that two data are stored therein, so that the data stored in the latter stage (data input earlier) is output from the output terminal. It has become. When new data is input, the data stored in the previous stage is first shifted to the subsequent stage, and then the new data is stored in the previous stage. For example, when data is input in the order of data D1 and data D2, data D1 is stored in the preceding stage of the D-FF element, data D2 is stored in the subsequent stage, and the previously input data D1 is output from the output terminal. .
When the next data D3 is input by the clock signal CLK (the latch signal LCH in the latch circuit 5r), the data D2 stored in the previous stage is stored and output in the subsequent stage at the rising edge of the clock signal CLK (LCH). The data is output from the terminal (at this time, the data D2 is stored in both the preceding stage and the subsequent stage). Then, at the falling edge of the clock signal CLK (LCH), the latest input data D3 is stored in the preceding stage, and the state of the preceding stage data D3 and the following stage data D2 is obtained.
By using such a D-FF element as a latch element of the latch circuit 5r, data can be stored from the latch circuit 5b using the common latch signal LCH.
[0027]
Next, a printing operation based on the red data r and the black data b according to the second embodiment configured as described above will be described.
When the red data r is stored in the shift register 4, the latch signal LCH is supplied to both the latch circuits 5r and 5b. At the rising edge, the red data r is stored in each latch element LA of the latch circuit 5b, and from the latch circuit 5b. The stored red data r is output and supplied to the AND circuit 3b and the D-FF of the latch circuit 5r.
In the latch circuit 5r, the red data r output from the latch circuit 5b is stored in the previous stage of each D-FF when the latch signal LCH falls. In this state, since the corresponding red data r and black data b are not yet stored (not output) in the latch circuits 5r and 5b, both the strobe signals STBr and STBb are not output.
[0028]
Next, when the black data b is stored in the shift register 4 and the latch signal LCH is supplied to both the latch circuits 5r and 5b, the latch circuit 5b stores the black data b in each latch element LA at the rising edge. The stored black data b is supplied to the AND circuit 3b and the D-FF of the latch circuit 5r.
On the other hand, in each D-FF of the latch circuit 5r, the red data r already stored in the previous stage is stored in the subsequent stage when the latch signal LCH rises, and the red data r stored in the subsequent stage is output from the D-FF and driven. This is supplied to the AND circuit 3r of the unit 11. Then, the black data b supplied from each latch element LA of the latch circuit 5b is stored in the previous stage when the latch signal LCH falls.
[0029]
As described above, the black data b is output from the latch circuit 5b and the red data r is output from the latch circuit 5r by the rising of the second latch signal LCH, and printing is possible by the output of both strobe signals STBr and STBb. become.
That is, when the L level strobe signal STBr is first supplied for a time T1, the red data r supplied from the corresponding stage of the latch circuit 5r is output from each AND circuit 3r to drive the drive transistor 2, The red data r is printed by the thermal head 1.
After the printing of the red data r is completed (after the strobe signal STBr is output and the time T1 has elapsed), the strobe signal STBb for the black data b is then supplied for the time T2 and supplied from the corresponding stage of the latch circuit 5b. The black data b thus output is output from each AND circuit 3 b to drive the drive transistor 2, and the black data b is printed by the thermal head 1.
[0030]
While the above red data r and black data b are being printed, the red data r for the next line is stored in the shift register 4. Then, after the printing of the black data b is completed, the latch signal LCH is supplied, and the red data r of the next line is converted into each latch element LA of the latch circuit 5b and each D of the latch circuit 5r in the same manner as above. -Stored in front of FF. Similarly, the black data b of the next line is stored in the latch circuit 5b, the red data r is stored in the subsequent stage of the latch circuit 5r, the black data b is stored in the previous stage, and the strobe signals STBr and STBb The red data r and black data b of the next line are printed by the output.
[0031]
As described above, in the present embodiment, the black data b and the red data r are alternately output from the latch circuit 5r, and the red data r and the black data b are alternately output from the latch circuit 5b (note that The red data r is output at the same time, and the black data b is not output at the same time. However, the supply timing of the strobe signals STBr and STBb (the red data r is output from the latch circuit 5r and the black data b is the latch circuit). 5b), the red data r is output from the AND circuit 3r for the time T1, the black data b is output from the AND circuit 3b for the time T2, the red data r is printed, and the black data b is output. Is properly printed.
As described above, according to the second embodiment, the shift register 4 is shared by one for the red data r and the black data b, thereby reducing the size of the chip, and appropriately using the red data r and the black data b. Can be printed at any time.
[0032]
In the second embodiment, as shown in FIG. 2, the data input terminal of each D-FF of the latch circuit 5r is connected to the output terminal of the corresponding latch element LA of the latch circuit 5b. It may be as follows.
That is, at the timing when data is stored in the previous stage of the latch circuit 5r (at the falling edge of the latch signal LCH), the print data output from each latch element LA of the latch circuit 5b and each D-FF of the shift register 4 The print data output from is the same. Therefore, the data input terminal of each D-FF of the latch circuit 5 r may be connected to the output terminal of the corresponding stage D-FF in the shift register 4. In this case, the data input terminal of each D-FF of the latch circuit 5r is commonly connected to the input terminal of the latch element LA of the corresponding stage of the latch circuit 5b.
Even in such a configuration, the red data r and the black data b can be appropriately printed by operating the integrated circuit for driving the thermal head as in the second embodiment.
[0033]
As described above, in the thermal head driving IC 0 of the first and second embodiments, the shift register 4 and the latch circuit 5 that hold serially supplied print data are used for the red data r and the black data b. Divided into two systems, the strobe signals STBr and STBb having different output times (pulse widths) are outputted from the AND circuits 3r and 3b.
Then, the red data r output from the AND circuit 3r and the black data b output from the AND circuit 3b are output from a common output terminal in the 2-input NOR circuit 13, and further, the same delay element, that is, 1 The drive transistor 2 is controlled to be turned on and off by being output from the input inverter 12.
As described above, according to the present embodiment, the printing data of two colors are output from the same delay element to drive the drive transistor 2, so that the energization delay time in each heating resistor 1 is the same for each color. Can be.
Further, in the thermal head driving IC 0 of this embodiment, only one inverter 12 is used as a delay element. The inverter 12 has one input and is configured to have a large L length with respect to the input. Thus, in this embodiment, since the portion with a large L length is one place, an increase in the chip size is prevented.
[0034]
Next, a third embodiment will be described.
(5) Overview of the third embodiment
In the integrated circuit for driving the thermal head of the third embodiment, two shift registers are provided corresponding to the red data r and the black data b, while the latch circuit is provided as one for the red data r and the black data b. Thus, the number of latch circuits is reduced by one to reduce the chip size.
[0035]
(6) Details of the third embodiment
FIG. 3 is a block diagram showing a circuit configuration of the thermal head driving integrated circuit (IC) of the present embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.
As shown in FIG. 3, a shift register 4r for red data r and a shift register 4b for black data b, which are configured in the same way as the shift register 4 described in the first embodiment, are provided.
As shown in FIG. 3, the thermal head driving integrated circuit according to the third embodiment includes a shift register 4r and a shift register 4b having the same configuration as the shift register 4 described in the first embodiment. Red data r is serially input from the control terminal SIr to the shift register 4r, and black data b is serially input from the control terminal SIb to the shift register 4b.
[0036]
In the present embodiment, a single latch circuit 5 is provided which is commonly used for holding red data r and black data b. The latch circuit 5 includes 64 latch elements LA corresponding to the stages of the shift registers 4r and 4b, and the output of each stage is connected to the second input terminal of the corresponding AND circuit 3. Yes. The output terminals of the AND circuit 53r and the AND circuit 53b are connected to the data input terminals of each stage of the latch circuit 5, and the output terminal of the OR circuit 53L is connected to the control terminal.
A control terminal LCHr is commonly connected to the first input terminal (left side of the drawing) of each OR circuit 53L and the first input terminal of each AND circuit 53r via a buffer 8, and a latch signal LCHr is supplied. The The control terminal LCHb is commonly connected to the second input terminal (right side of the drawing) of each OR circuit 53L and the first input terminal of each AND circuit 53b via the buffer 8, and the latch signal LCHb is It comes to be supplied.
The second input terminal of each AND circuit 53r is connected to the output terminal of the corresponding D-FF in the shift register 4r. The second input terminal of each AND circuit 53b is connected to the output terminal of the corresponding D-FF in the shift register 4b.
[0037]
As described above, the latch circuit 5 is supplied with the red data r from the shift register 4r via the AND circuit 53r, and takes in the red data r at the rising edge of the latch signal LCHr supplied via the OR circuit 53L. This is supplied to the AND circuit 3 of the drive unit 11. Further, black data b is supplied from the shift register 4b via the AND circuit 53b, and the black data b is fetched at a time when the latch signal LCHb supplied via the OR circuit 53L rises, and the AND circuit 3 of the drive unit 11 is read. To supply.
[0038]
On the other hand, in the drive unit 11 in this embodiment, the output terminal of the AND circuit 3 is connected to the gate of each drive transistor 2. The output terminal of the latch element LA of the corresponding stage of the latch circuit 5 is connected to the second input terminal of the AND circuit 3, and the first input terminal is pulled up to the power supply VDD via the inverter 7. Connected to the control terminal STB.
In the first and second embodiments, an overshoot is prevented by the inverter 12 having a long L length, but in this embodiment, an AND circuit connected to the control terminal STB is used instead of using the inverter 12. The overshoot is prevented by increasing the L length on the first input terminal 3 (left side of the drawing).
[0039]
As described above, according to the third embodiment, the number of latch circuits can be reduced by one by reducing the chip size by sharing one latch circuit for red data r and black data b. be able to.
The latch circuit 5 needs to use an OR circuit 53L and AND circuits 53r and 53b in addition to the latch element LA. However, since the number of logic elements of the drive unit 11 can be reduced, the latch circuit 5 and the drive unit The total number of elements including 11 is small, and the chip can be reduced in size in the entire integrated circuit for driving the thermal head by reducing it by one latch circuit.
[0040]
Next, a printing operation based on the red data r and the black data b according to the third embodiment will be described.
First, when red data r is serially input serially from the control terminal SIr and stored in the shift register 4r, the red data r is supplied from the D-FF in each stage to the corresponding AND circuit 53r.
In this state, the latch circuit 5 supplies the red latch signal LCHr to each of the OR circuits 53L and the AND circuit 53r. Then, the latch signal LCHr is supplied to the latch element LA via the OR circuit 53L, the red data r is supplied from the AND circuit 53r, the red data r is stored in each latch element LA, and the drive unit 11 To the AND circuit 3.
Thereafter, the strobe signal STB is supplied for the time T1, and the corresponding driving transistor 2 is driven from each AND circuit 3 in accordance with the contents of the red data r, and printing based on the red data r is performed.
Between the input of the red data r to the shift register 4r and the end of printing, the black data b is sequentially input serially from the control terminal SIb and stored in the shift register 4b. Then, after the printing of the red data r is completed (after the time T1 has elapsed since the strobe signal STBr is supplied), the black latch signal LCHb is supplied to each of the OR circuits 53L and the AND circuit 53b. Then, the latch signal LCHb is supplied to the latch element LA via the OR circuit 53L, and the black data b is supplied from the AND circuit 53b, and the black data b is changed to the red data r in each latch element LA. Are stored, and black data b is supplied to the AND circuit 3 of the drive unit 11.
Thereafter, the strobe signal STB is supplied for a time T2, and the corresponding driving transistor 2 is driven from each AND circuit 3 in accordance with the contents of the black data b, and printing based on the black data b is performed.
[0041]
Although the red data r and the black data b are input to the control terminal SIr and the control terminal b at different timings, respectively, the red data r and the black data b are input at the same timing, and the red latch The supply timing of the signal LCHr and the black latch signal LCHb may be shifted (the other latch signal is supplied after one print is completed). As described above, when the red data r and the black data b are sequentially input to the shift registers 4r and 4b at the same timing, the control terminal CLKr and the control terminal CLKb can be made common. That is, all the D-FFs of the shift register 4r and all the D-FFs of the shift register 4b can be commonly connected to the common control terminal CLK via the buffer 8.
[0042]
The configuration and operation of the thermal head driving IC 0 of the present embodiment have been described above. However, the present invention is not limited to these configuration and operation, and various modifications can be made within the scope of the invention described in each claim. Is possible.
[0043]
For example, in the embodiment described above, the case of two-color printing of red and black has been described. However, the present invention can be similarly applied to the case of n-color printing or n-tone printing.
Even in this case, as described in the first to third embodiments, by using a shift register or a latch circuit for each specific number of colors in common, even in the case of printing with n colors and n gradations. At least one shift register or latch circuit can be reduced. As a result, the chip size of the thermal head driving integrated circuit can be reduced.
[0044]
【The invention's effect】
In the present invention, one of the shift register and the holding means is made smaller than the other, and at least one set on the smaller side is used in common, so when performing multi-tone printing or multi-color printing with one heating resistor. However, an increase in the circuit size of the thermal head driving integrated circuit can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a circuit configuration of an integrated circuit for driving a thermal head according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a circuit configuration of an integrated circuit for driving a thermal head according to the second embodiment.
FIG. 3 is a block diagram showing a circuit configuration of an integrated circuit for driving a thermal head according to the second embodiment;
FIG. 4 is a block diagram showing a basic configuration of a conventional thermal head driving IC.
FIG. 5 is a block diagram showing the configuration of a thermal head driving IC for two-color printing, which can be considered by using a conventional one-color thermal head driving IC.
[Explanation of symbols]
0 Integrated circuit for thermal head drive
1 Heating resistor
2 Drive transistor
3, 3r, 3b AND circuit
35L OR circuit
35r, 35b AND circuit
4, 4r, 4b shift register
5, 5r, 5b Latch circuit
7r, 7b inverter
8 buffers
11 Drive unit
12 Inverter
13 NOR circuit

Claims (2)

An integrated circuit for driving a thermal head that controls energization of a plurality of heating resistors in response to print data,
A shift register for sequentially transferring and storing print data supplied serially; first holding means for collectively holding the first print data stored in the shift register;
Second holding means for collectively holding the second print data stored in the shift register;
A first control terminal to which a signal for energizing the heating resistor during energization time t1 is input;
A second control terminal to which a signal for energizing the heating resistor during energization time t2 (t2> t1) is input;
Drive means for controlling the energization of the plurality of heating resistors by sequentially reading the data held in the first and second holding means in batches;
The driving means energizes the heating resistor during an energization time t1 based on a signal input to the first control terminal and a signal output from the first holding means, and the second control terminal An integrated circuit for driving a thermal head, wherein the heating resistor is energized for an energization time t2 based on a signal input to the second holding means and a signal output from the second holding means. An integrated circuit for driving a thermal head that controls energization of a plurality of heating resistors in response to print data,
A first shift register for sequentially transferring and storing first print data supplied serially;
A second shift register for sequentially transferring and storing the second print data supplied serially;
Holding means for collectively holding the first or second print data stored in the shift register;
A control terminal to which a first signal for energizing the heating resistor during energization time t1 and a second signal for energizing the heating resistor during energization time t2 (t2>t1); ,
Driving means for controlling the energization of the plurality of heating resistors by sequentially reading data held in the holding means in batches;
The driving means energizes the heating resistor based on a signal based on the first signal input to the control terminal and a signal based on the first print data output from the holding means. The heating resistor is energized for an energization time t2 based on a signal based on the second signal input to the control terminal and a signal based on the second print data output from the holding means. An integrated circuit for driving a thermal head.

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