JP2000198188A - Ink jet recording apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ink jet recording apparatus in which power consumption not only at an intermediate voltage driving circuit, but also at least at a part of a low voltage driving circuit is reduced, thereby restricting heating at a circuit part and preventing record images from being deteriorated or nozzles from clogging. SOLUTION: A regulator 10 executes ON/OFF control to an intermediate voltage MVDD to be supplied to predrivers 4 in accordance with an inverting signal of an NRST signal which becomes 'L' when a driving operation is not carried out. A low voltage LVDD is supplied to most of a low voltage driving circuit via a switching circuit 5. The intermediate voltage MVDD is input to a gate electrode of the switching circuit 5, whereby the low voltage LVDD is controlled to be ON/OFF in accordance with the intermediate voltage MVDD. A consumption power at the low voltage driving circuit is reduced accordingly. Since the intermediate voltage MVDD is supplied to the gate, a decrease in output voltage at the switching circuit 5 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ink jet apparatus which applies energy to a heating element provided in a nozzle to generate heat in ink held in the nozzle to generate bubbles in the ink to eject the ink. It relates to a recording device.

[0002]

2. Description of the Related Art At present, an ink jet recording system has been attracting much attention. The inkjet recording method enables recording on plain paper,
It is characterized by easy colorization, excellent quietness, and excellent balance between recording speed and price.
Furthermore, it has the advantage that the structure is simple.

On the other hand, even though the structure is simple, there still remains a problem in the handling of recording heads and inks. In particular, securing reliability and durability by handling ink has become an issue. Factors that impair reliability and durability include clogging with ink, mixing of air bubbles into the ink flow path, and deterioration of the recording head material due to ink.

[0004] In recent years, the number of ink jet recording apparatuses capable of recording high-quality images close to photographic quality even at low cost has increased. Use multicolor inks of 6 colors or more,
The tone expression was enriched by ingenuity, such as overprinting ink in one place, and the image was less grainy. Such an ink jet recording apparatus has been commonly used not only in a professional business such as a company and an advertisement but also in a general household with the spread of personal computers. For example,
Postcards with family photos have become routine. In such an application, the face of a person may be quite small, and must be represented by a group of small dots. In such a case, if the performance is low, the expression of the eyes changes, or the dots are noticeably rough on the skin. However, the image quality has been improved by the recent enhancement of functions, and it has become sufficiently usable for such uses.

[0005] In the ink jet method, a thermal (bubble) method in which ink is rapidly heated by a heating element and ink is ejected by bubbles generated in the ink, and an ink is ejected by using a ceramic which is deformed when a voltage is applied. There is a piezo method. In particular, in the thermal method, since a heating element for applying ejection energy to ink can be created by a relatively simple thin film process, the configuration in which an electronic circuit created by the same thin film process is mounted on the same substrate as the heating element has increased. I have. In addition to the heating element, a driver, a low-voltage logic function element, and the like are also integrated on a substrate on which the heating element is mounted. As a result, the wiring can be simplified, the load on the drive IC can be reduced, and the number of pads for electrical connection can be reduced to reduce the chip size. It is effective in terms of cost. The configuration in which the driving circuit and the like are formed on the same substrate as the heating element as described above is described in, for example, Japanese Patent Application Laid-Open No. 9-254368.

[0006] The ink used for recording in the ink jet recording system has a lower viscosity as the temperature increases, and the amount of ejected droplets increases. Therefore, if there is a change in the temperature, the amount of the ejected droplet changes and the recorded image deteriorates. Also, it is known that when a certain temperature is reached, bubbles are easily generated in the ink, and normal printing cannot be performed. Therefore, on the board on which the heating element is mounted,
It is desirable to avoid unnecessary heat generation as much as possible. From this viewpoint, when the driving circuit is mounted on the substrate on which the heating element is mounted, it is preferable that the power consumption be small in order to reduce the amount of heat generated in the driving circuit.

[0007] In addition, the ink evaporates and becomes thicker during standby, and the amount of ejected droplets may be reduced to deteriorate the image quality or cause clogging. In particular, when heated during standby, the evaporation of water is accelerated, and the viscosity of the ink is also accelerated. Therefore, it is desirable to reduce the amount of heat generated during standby, and it is required to reduce power consumption even during standby. For example, for a long standby time,
It is considered that a standby mode is provided as described in 328681 or the like, and in the standby mode, for example, the power supply of a pre-driver that operates at an intermediate potential level is cut off.

When these drive circuits are mounted on the substrate on which the heating elements are mounted, for example, it is conceivable to configure the drive circuits by CMOS to reduce power consumption. However, when the driving circuit is formed of CMOS, there is a problem that the process cost is increased due to, for example, a process of forming a heating element or the like. When the drive circuit is formed by the NMOS process, although the process cost is lower than that of the CMOS, the power consumption increases because the through current always flows, and the ink increases in viscosity during standby to cause clogging. There is a problem that the danger increases.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and reduces power consumption not only in an intermediate voltage driving circuit but also in at least a part of a low voltage driving circuit, thereby reducing the power consumption in a circuit portion. It is an object of the present invention to provide an ink jet recording apparatus that suppresses heat generation to prevent deterioration of a recorded image and clogging of nozzles.

[0010]

According to the present invention, in an ink jet recording apparatus, a plurality of heating elements, a driver for driving the heating elements, and a low voltage drive for controlling the driver in accordance with image data are provided. Circuit and an intermediate voltage driving circuit, and the low voltage driving circuit is supplied with a low voltage via switching means. In the intermediate voltage driving circuit, the supplied intermediate voltage is ON / OFF controlled, and the low voltage driving circuit is ON / OFF controlled by the switching means in conjunction with the intermediate voltage. by this,
The power consumption in the low-voltage drive circuit can be reduced, and the amount of heat generated can be reduced to reduce image quality deterioration due to thickening of the ink, and image quality deterioration due to a decrease in viscosity of the ink during recording and generation of bubbles.

The switching means is, for example, an N-channel M
It can be composed of an OS transistor. At this time,
If the gate voltage of the N-channel MOS transistor that constitutes the switching means is low, the output voltage will decrease when it is turned on. N-channel MO constituting switching means
By supplying an intermediate voltage to the gate of the S transistor, a decrease in the output voltage at the time of ON can be prevented, and a voltage at substantially the same level as that of the low-voltage power supply can be supplied. Further, there is no adverse effect on the timing, the voltage level, and the like due to the voltage drop. Furthermore, on the substrate on which the heating elements are mounted, the intermediate voltage driving circuit and the low voltage driving circuit are laid out in parallel in the arrangement direction of the heating elements, so that the intermediate voltage is arranged in close proximity to the entire low voltage driving circuit. Therefore, the modification of the layout by inserting the switching means using the intermediate voltage is slight.

[0012]

FIG. 1 is a block diagram showing an example of a circuit provided on a substrate on which a heating element is mounted in a first embodiment of an ink jet recording apparatus according to the present invention.
In the figure, 1 is a common electrode, 2 is a heating element, 3 is a driver element, 4 is a pre-driver, 5 is a switching circuit, 6 is a data holding circuit, 7 is a 4-bit ring counter, and 8 is 8b
An it ring counter, 9 is a clock generation circuit, 10 is a regulator, 11 is a D latch, 12 is a pre-driver power supply voltage monitor terminal, and 13 and 14 are test signal output terminals. Note that this drawing and the following drawings are all conceptual circuit diagrams, ignoring fan-out and wiring capacitance, and omitting detailed parts such as buffers.

FIG. 1 shows, as an example, a configuration having 256 heating elements 2. Strictly speaking, it has 256 heating element areas, and there is only a heating element area and there is no actual heating element, or an element having different characteristics that is not used for normal recording. Or a so-called dummy element. For example, when printing is performed by ejecting inks of different colors using one substrate, a number of dummy elements are often provided at boundaries of different colors. In the following description, the number of heat generating elements that can be arranged will be referred to as the number of heat generating elements based on the above. Of course, the number of heating elements is arbitrary, and 2
The number is not limited to 56.

These heating elements 2 are divided into 32 groups of eight, and are driven in a time-division manner. The heating elements 2 in each group are constituted by heating elements 2 which are discretely arranged every three elements. For example, 1, 5, 9, 13, 1
The first, second, seventh, twenty-fifth, and twenty-ninth heating elements 2
The second group is composed. The heating element 2 is, for example,
It can be arranged to have a resolution of 600 dots / 25.4 mm.

The overall configuration includes 256 heating elements 2, a driver 3 (high breakdown voltage transistor) that causes current to flow through each heating element 2 to generate heat, and a drive circuit that controls the drivers. The heating element 2 includes, for example, a sheet resistor 5.
It can be formed by a polysilicon layer of about 0 to 80Ω. The HVDD voltage applied to the common electrode 1 is, for example, about 36 to 40V. One end of the heating element 2
All are connected to the high voltage HVDD via the common electrode 1. The other ends of the heating elements 2 are respectively connected to the driver elements 3. The driver element 3 drives the corresponding heating element 2 according to a drive signal from the pre-driver 4.

The driving circuit has a function of controlling a printing current for each heating element 2 by printing data serially input from the outside. It has a preheat function as a typical function. This is a function in which a heating element for performing printing is heated in advance as a pre-pulse by applying a current for a short time as described above. Here, this function is called a prepulse function. Also, a signal given to the heat generating element to actually fly the ink after the pre-pulse is called a main pulse.

The driving circuit for controlling the driver 3 is composed of a low voltage driving circuit and a pre-driver 4 which is an interface to the driver. In the example shown in FIG. 1, the driver 3 is configured by a MOS transistor. To sufficiently turn on the MOS transistor, the pre-driver power supply is set to 10 to 15 V, and the pre-driver 4 drives the driver 3 by synthesizing and boosting the output of the low-voltage drive circuit. The power supply for the pre-driver is configured to be supplied from the regulator 10. FIG. 2 is a circuit configuration diagram illustrating an example of the regulator. The regulator circuit shown in FIG. 2 is a general circuit, in which two resistors are connected in series between a power supply and a ground, and a divided voltage is connected to the gate of the FET, and the FE is connected.
The output of T is used as a pre-driver power supply. An FET is connected in parallel to the resistor connected to the ground, and a signal obtained by inverting the NRST signal is input to the gate of the FET. Thus, the pre-driver power supply can be controlled based on the NRST signal, and the pre-driver 4
A standby mode in which power is not supplied to the power supply. The intermediate voltage output from the regulator 10 is also supplied to the switching circuit 5.

FIG. 3 is a circuit diagram showing an example of the pre-driver. In the figure, 21, 25 and 29 are load D-MOS transistors, and 22 to 24 and 26 to 28 are driving E-MOS transistors. The first stage gate includes a load D-MOS transistor 21 and driving E-MOS transistors 22 to 24.
Is a three-input NAND gate having an ED-MOS transistor configuration by series connection. Output lines from output terminals RE1 to RE4 of the 4-bit ring counter 7 shown in FIG.
Drive E-MOS according to the contact position of the cross wiring structure
The signal is input to the gate electrode of the transistor 22. Also, 8
The output lines from the output terminals B1 to B8 of the bit ring counter 8 are driven according to the contact position of the cross wiring structure.
-Input to the gate electrode of the MOS transistor 23.
Further, output lines from the output terminals D1 to D4 of the data holding circuit 6 are input to the gate electrode of the driving E-MOS transistor 24 according to the contact position of the cross wiring structure.

The gate of the second stage is an inverter having an ED-MOS transistor configuration in which a load D-MOS transistor 25 and a drive E-MOS transistor 26 are connected in series. The connection point of the MOS transistor 22 is the drive EM
Connected to the gate electrode of OS transistor 26.

The gate of the third stage is a push-pull drive in which the drive E-MOS transistors 27 and 28 are connected in series. Load D of the second stage gate
The connection point between the MOS transistor 25 and the drive E-MOS transistor 26 is connected to the gate electrode of the drive E-MOS transistor 27, and the drive E-MOS
The gate electrode of transistor 26 is connected to the gate electrode of drive E-MOS transistor 28.

A connection point between the driving E-MOS transistor 27 and the driving E-MOS transistor 28 at the gate of the third stage is connected to a pull-down resistor by a load D-MOS transistor 29 and becomes an output terminal of the pre-driver 4. Connected to the gate electrode of driver 3.

As described above, the pre-driver 4 is supplied with the intermediate voltage MVDD from the regulator 10. For example, only when the signals from the 4-bit ring counter 7, the 8-bit ring counter 8, and the data holding circuit 6 are all “H”, the pre-driver 4 sets the signal to the gate of the driver 3 to “H” and the heating element 2 Driven.
All of the MOS transistors constituting the pre-driver 4 are of the N-channel type. Even if the heating element 2 is not driven, if the intermediate voltage is supplied, the load D-MO
A through current flows through the S transistor 25 and the driving E-MOS transistor 26. For example, when the intermediate voltage supplied from the regulator 10 is about 13 V, a through current of about 50 μA flows. Therefore, by realizing the standby mode in which power is not supplied to the pre-driver 4 in the regulator 10, power consumption in the standby load D-MOS transistor 25 and driving E-MOS transistor 26 can be eliminated. As a result, the amount of heat generated can be reduced, and image quality defects due to a decrease in ink viscosity and an increase in ink viscosity due to drying can be reduced.

The switching circuit 5 controls ON / OFF of the low voltage LVDD supplied to the low voltage driving circuit. In this example, it is composed of an N-channel MOS transistor, and is inserted in series with a low-voltage power supply line.
The intermediate voltage MVDD output from the regulator 10 is supplied to the gate electrode.

FIG. 4 is a conceptual diagram of power supply to the low-voltage drive circuit. FIG. 4A shows a configuration when a low voltage is supplied according to the present invention, and FIG. 4B shows a configuration when a conventional low voltage is supplied. As shown in FIG. 4B, conventionally, the low-voltage power supply to the low-voltage drive circuit is always supplied, so that heat is generated by power consumption in the low-voltage drive circuit,
The substrate temperature was raised by several degrees. In the present invention, FIG.
As shown in (A), the low voltage LVDD supplied to the low voltage drive circuit by the switching circuit 5 is turned on / off.
Since control is performed, power consumption during standby in the low-voltage drive circuit can be reduced, and the amount of heat generated can be reduced, thereby suppressing an increase in substrate temperature. Also, this switching circuit 5 is only formed on the low voltage line on the substrate,
Further, the intermediate voltage MVD output from the regulator 10
Since the D line also extends in the arrangement direction of the heating elements 2,
Changes in circuit layout can be minimized.
Of course, for the part that must be operated even during standby, the low voltage LVD
D may be supplied.

When an N-channel MOS transistor is provided as the switching circuit 5 on the low voltage LVDD line, the output voltage is changed from the gate voltage to the threshold voltage Vth.
(Vth ≒ 1.3 V due to the substrate effect). For example, when the low voltage LVDD is 5 V, when the output of the low voltage circuit is input to the gate electrode and a voltage of about 5 V is input, the output voltage becomes about 3.7 V. When the power supply voltage of the low-voltage drive circuit reaches such a level, the timing deteriorates to an unacceptable level, and the pre-driver 4 cannot be driven sufficiently.

In the present invention, by supplying the intermediate voltage MVDD to the gate electrode, power can be supplied to the low-voltage drive circuit without lowering the low voltage LVDD so much. In addition, when the gate voltage is high, the ON resistance of the transistor is reduced accordingly, and the output voltage can be set to substantially the same level as LVDD. For example, when a voltage of about 13 V is supplied as the intermediate voltage MVDD, when the input low voltage LVDD is 5 V, an output voltage of about 4.8 to 4.9 V can be secured. Thus, the low-voltage drive circuit can be operated stably.

Further, as described above, the intermediate voltage MVDD supplied from the regulator 10 is ON / OFF controlled based on the NRST signal.
VDD can be ON / OFF controlled. That is, the driving operation of the heating element is performed when the NRST signal is “H”, but when the NRST signal is “L”, the intermediate voltage MVDD from the regulator 10 is cut off, and the switching circuit 5 is also cut off. As a result, power consumption of the low-voltage drive circuit can be cut off, thereby reducing power consumption.
For example, even if a current of about 30 mA flows during energization in the low-voltage drive circuit, only about 2 mA flows in the standby mode in which the NRST signal is "L", and is reduced to several tenths. can do.

Further, on the substrate on which the heating element 2 is mounted, due to its nature, the intermediate voltage MVDD is wired so as to cross the substrate as shown in FIG. Therefore, the Tr. Is installed to easily shut off the low voltage LVDD. In the configuration of the regulator 10 shown in FIG. 2, the connection node between the two resistors is connected to the intermediate voltage MV.
The signal may be input to the gate of the transistor of the switching circuit 5 instead of the DD.

Another important advantage of this configuration is that it is not necessary to generate another signal for cutting off the low voltage LVDD. In other words, a power supply line where the low voltage LVDD is cut off and a power supply line which is not cut off are provided, the switching circuit 5 is provided therebetween, and the intermediate voltage MVDD is simply input to the gate of the transistor of the switching circuit 5 to provide a standby state. Power consumption can be reduced.

The low-voltage driving circuit includes data holding circuits 6, 4
bit ring counter 7, 8 bit ring counter 8,
It has a clock generation circuit 9, a D latch 11, and the like. FIG.
FIG. 3 is a schematic configuration diagram illustrating an example of a low-voltage drive circuit. The data holding circuit 6 outputs print data according to a signal generated by the clock generation circuit 9. In addition, the 4-bit ring counter 7 and the 8-bit ring counter 8 function as a time-division driving circuit, and respectively select a block to be driven (a set of heating elements 2 that are driven simultaneously) according to a signal generated by the clock generation circuit 9. Outputs a block division drive signal.

The data holding circuit 6 holds print data used for the pre-pulse and the main pulse for one block each, that is, print data for a total of two blocks, and outputs the print data by switching between the pre-pulse and the main pulse. I do. The circuit scale is reduced as compared with a configuration in which print data for all heating elements is held. The print data is DTDI
It is supplied as an R signal and takes in the DCLK signal as a clock. Switching of print data is performed by an ENABLE signal composed of a pre-pulse and a main pulse.
The transfer from the clock generation circuit 9 is performed to transfer the print data used at the time of the pre-pulse to use the print data at the time of the main pulse.

The 4-bit ring counter 7 basically performs a shift operation using the ENABLE signal as a clock.
The 8-bit ring counter 8 performs a shift operation using the carry-out signal of the 4-bit ring counter 7 as a clock. An 8-bit link counter 8 selects any 4 blocks out of 32 blocks, and
One of the four blocks selected by the bit ring counter is selected. However, when a pulse of another block is inserted between a pre-pulse and a main pulse of a certain block, the block driven by the pre-pulse and the block driven by the main pulse following the pre-pulse are different. At the same time, a signal for switching between the pre-pulse and the main pulse is received. The order of selecting blocks is given by the DTDIR signal, and the order of selection is obtained based on the NRST signal that is a reset signal. Also, N
RST signal is 4 bit ring counter 7 and 8 bit
It is also used to reset the ring counter. As the 4-bit ring counter and the 8-bit ring counter, a binary counter which is a field counter can be used in order to reduce the circuit scale as much as possible.

The clock generation circuit 9 generates a switching signal for a pre-pulse and a main pulse, a pre-pulse, a clock signal for one set of a main pulse, and the like based on the ENABLE signal, and outputs the signal together with the ENABLE signal. Also, NRS
Whether a single pulse drive or a double pulse drive is determined from the T signal and the DTDIR signal, and a signal to be generated is made to correspond to the determined drive method. The D latch 11 latches the DTDIR signal based on the NRST signal, and outputs a DIR signal that is a switching signal of a block driving order.

Each signal will be described. The input signal line is
NRST signal, ENABLE signal, DTDIR signal, D
There are only four CLK signals. The NRST signal is a clear signal for resetting, and the “L” clears the 4-bit ring counter 7 and the 8-bit ring counter 8. When the level is “L”, the regulator 10 enters a low power consumption mode in which the intermediate voltage MVDD is not supplied,
No power is supplied to the pre-driver 4. At the same time, the switching circuit 5 is also turned off, the supply of the low voltage LVDD to the low voltage drive circuit is cut off, and the power consumption in the low voltage drive circuit is reduced. Further, it is used to set the block selection order at the rising edge and select and set single pulse driving or double pulse driving at the falling edge.

The ENABLE signal is "H" and the driver 3
To ON. When performing the double pulse driving, the waveform has a waveform in which the pre-pulse and the main pulse alternately appear. At the rise of the pre-pulse, the data holding circuit 6 latches the print data. 4 bits at the fall of the main pulse
Shift the ring counter.

The DTDIR signal is sent together with the serial print data, as well as a selection signal for the drive order of the blocks and a signal for selecting between single pulse drive and double pulse drive. FIG. 6 is an explanatory diagram of an example of the selection of the pre-pulse function and the driving order by the DTDIR signal. Single pulse drive or double pulse drive is set by the DTDIR signal at the time of the falling of the NRST signal. As shown in FIG. 6A, if the DTDIR signal is “L” when the NRST signal falls, double pulse driving is set,
As shown in (B), in the case of “H”, single pulse driving is set. This setting is performed in the clock generation circuit 9.

DT at the time of rising of the NRST signal
The driving order of the blocks is set by the DIR signal. As shown in FIG. 6 (C), when the NDT signal rises, the forward direction is set when the DTDIR signal is “L”, and when the DTDIR signal is “H” as shown in FIG. 6 (D). Is set in the opposite direction. This setting is performed by the D latch 11. That is, the D latch 11
Latches the DTDIR signal at the falling edge of the inverted signal of the NRST signal. This is used as a DIR signal indicating the drive order of the block, and the 4-bit ring counter 7
It is input to an 8-bit ring counter 8. As described above, since the D latch 11 must operate even when the NRST signal is “L”, it is necessary to supply the low voltage LVDD without passing through the switching circuit 5.

The DCLK signal is a clock signal for serial print data. At the fall of this signal, the data holding circuit 6 takes in the print data.

The pre-driver power supply voltage monitor terminal 12 outputs an MVDD signal. This MVDD signal is an output for monitoring the voltage of the pre-driver power supply for the pre-driver 4. Also, test signal output terminal 1
DOUT1 and DOUT2 signals are output from 3,14. The DOUT1 and DOUT2 signals are output of internal logic test signals. In the example shown in FIG.
The signal is one of the output lines of the 4-bit ring counter 7 and 8
The logical sum of one of the output lines of the bit ring counter 8 is output. As the DOUT2 signal, the logical sum of one output line of the 8-bit ring counter 8 and one output line of the data holding circuit 6 is output. The pre-driver power supply voltage monitor terminal 12 and the test signal output terminals 13 and 14 may be omitted.

FIG. 7 is a circuit diagram showing an example of the clock generation circuit. In the figure, 31 to 33 are D flip-flops,
34 is an AND circuit, 35 is an OR circuit, 36 is a selector,
37 is a delay circuit. The D flip-flop 31 latches the DTDIR signal at the rising edge of the inverted signal of the NRST signal and supplies it as a select signal for the AND circuit 34 and the selector 36. As described above, whether to perform single-pulse drive or double-pulse drive at the falling edge of the NRST signal is set. Pulse drive, 'H' indicates single pulse drive. Here, the inverted output is used to output a PPOUT signal that is “H” when performing double pulse driving and “L” when performing single pulse driving.

D flip-flop 32 is ENABLE
The output logic is inverted at the falling edge of the signal, and the A signal is output. That is, it becomes 'H' at the first fall,
It becomes 'L' at the second fall. AND circuit 34
Outputs the output of the D flip-flop 32 as an M signal only when the output of the D flip-flop 31 is 'H'.

The D flip-flop 33 has a function of ENA
The logic of the output is inverted at the rise of the BLE signal to output the B signal. That is, it becomes 'H' at the first rising and 'L' at the second rising. OR circuit 3
5 is a D flip-flop 32 and a D flip-flop 3
The output of No. 3, ie, the logical sum of the A signal and the B signal, is output as the C signal. The C signal is 1 even in the case of double pulse drive.
The signal has a width including a set of pre-pulses and a main pulse.

The selector 36 outputs the C signal and the ENABLE signal output from the OR circuit 35 to the D flip-flop 3
1 and output as an E signal. When double pulse driving is performed, “H” is input to the SEL terminal. At this time, the C signal output from the OR circuit 35 is selected, and when single pulse driving is performed, ENABL is input.
Select the E signal. The timing of the ENABLE signal is adjusted by the delay circuit 37 and output as an ENA signal.

The M signal, E signal,
The ENA signal is supplied to the data holding circuit 6, the 4-bit ring counter 7, and the like.

FIG. 8 is an explanatory diagram of an example of a signal generated at the time of double pulse driving. During double pulse drive, D
The output (PPOUT) of the flip-flop 31 becomes “H”, and a signal including a pre-pulse and a main pulse is input as an ENABLE signal. D flip-flop 3
The signal A output from 2 becomes "H" at the fall of the pre-pulse and becomes "L" at the fall of the main pulse. The B signal output from the D flip-flop 33 becomes “H” at the rise of the pre-pulse and becomes “L” at the rise of the main pulse. The OR circuit 35 performs a logical OR operation of the A signal and the B signal, and outputs a C signal that becomes “H” at the rise of the pre-pulse and becomes “L” at the fall of the main pulse. Also, the AND circuit 3
4 outputs the A signal as it is as the M signal. Since “H” is input to the SEL terminal, the selector 36 selects the C signal and outputs it as an E signal.

FIG. 9 is an explanatory diagram of an example of a signal generated during single pulse driving. In this case, a single drive pulse is input as an ENABLE signal. At the time of single pulse driving, the output of the D flip-flop 31 (PPOU
T) becomes 'L', and the M signal output from the AND circuit 34 remains 'L'. In the selector 36, EN
The ABLE signal is selected and output as the E signal.

FIG. 10 is a circuit diagram showing an example of the data holding circuit. In the figure, 41 is a shift register, 42 is a latch, 43 is a D flip-flop, and 44 is a selector. The shift register 41 is configured to be able to hold 8-bit print data, and sequentially performs a shift operation in accordance with the DCLK signal. The shift register 41 reads the print data for the pre-pulse every 8 bits. When the E signal is “H”, the latch 42 reads the 8
Latch bit print data. The output from the latch 42 becomes print data for pre-pulse.

Thereafter, the D flip-flop 43 latches the output of the latch 42 at the fall of the E signal. As a result, the D flip-flop 43 holds the print data for the main pulse. The D flip-flop 43
The output is reset to “L” by the RST signal.

The selector 44 selects the output of the latch 42 or the output of the D flip-flop 43 by using a signal obtained by inverting the M signal. At the time of the pre-pulse, the latch 42 is selected and output, and subsequently, the D flip-flop 43 is selected and output. After that, the E signal falls, so the latch 4
2 is the D flip-flop 43
Is forwarded to Next, when the E signal rises and becomes “H”, the latch 42 stores new print data in the shift register 41.
, And latched, and output from the selector 44. Subsequently, the print data of the D flip-flop 43 latched earlier is output.

Next, the 4-bit ring counters 7 and 8bi
An example of the t-ring counter 8 will be described. 4 bits
The ring counter 7 shifts based on the E signal output from the clock generation circuit 9. The 8-bit ring counter 8 operates using the carry-out signal of the 4-bit ring counter 7 as a clock.

FIG. 11 is an explanatory diagram of an example of a binary counter not synchronized with a clock. In the figure, 51 to 55 are D
Flip-flops 56 to 59 are AND circuits. The configuration shown in FIG. 11 is a configuration in which the delay is suppressed as much as possible while being an asynchronous binary counter. Each D
The flip-flops 51 to 55 invert the output at the falling edge of the clock input, and
To 54 are output to AND circuits 56 to 59, respectively. The clock input from the outside is a D flip-flop 5
1, input to the AND circuits 56 and 57. AND circuit 5
6 outputs the logical product of the output of the D flip-flop 51 and the clock to the D flip-flop 52 and the AND circuit 57. The AND circuit 57 outputs the logical product of the output of the D flip-flop 52, the output of the AND circuit 56, and the clock to the D flip-flop 53 and the AND circuits 58 and 59. AND circuit 58 outputs the logical product of the output of D flip-flop 53 and AND circuit 57 to D flip-flop 54 and AND circuit 59. AND circuit 59 outputs D
The logical product of the output of the flip-flop 54 and the outputs of the AND circuits 57 and 58 is output to the D flip-flop 55.

FIG. 12 is a timing chart showing an operation example of one example of the binary counter shown in FIG. In the initial state, the Q outputs of the D flip-flops 51 to 55 are “L”, and the * Q output, which is the inverted output of the Q output, is “H” and is connected to the D input. At the falling edge of the first clock, the D flip-flop 51 latches and outputs the D input, and the U signal becomes 'H'. As a result, one input of the AND circuit 56 becomes “H”. At the next falling edge of the clock, the output of the D flip-flop 51 is inverted to “L”. In this manner, the output of the D flip-flop 51 is inverted every time the falling edge of the clock is input, and has a waveform like the U signal in FIG.

At the time of the second clock, the U signal is "H".
Therefore, the second clock pulse is input to the D flip-flop 52 as it is, and the output is inverted at the fall. Therefore, the W signal becomes “H”. In the next third clock, since the output of the D flip-flop 51 is “L”, no clock pulse is input from the AND circuit 56. Since the output of the D flip-flop 51 is "H" at the third clock, the fourth clock pulse is input to the D flip-flop 52, and the output is inverted at the falling edge to "L". Becomes

When the output of the D flip-flop 52 becomes "H" and the fourth clock pulse is output from the AND circuit 56, the AND circuit 57 outputs the fourth clock pulse directly input. At this time, the AND circuit 56
Is delayed by the AND circuit 56, the rising of the clock pulse output from the AND circuit 57 is delayed. However, since the fall follows the fall of the directly input clock pulse,
The delay of the falling edge of the clock pulse output from the AND circuit 57 is only the delay amount caused by the AND circuit 57 alone.

The clock pulse output from the AND circuit 57 is input to the D flip-flop 53 and inverts the output. D flip-flops 53 and 54 are connected to AND circuit 5
7 operates in the same manner as the D flip-flops 51 and 52 using the clock pulse output from 7 as a clock. Thus, the X and Y signals shown in FIG. 12 are obtained.

Further, D flip-flop 55 is connected to AND
D flip-flop 5 using the output of circuit 59 as a clock
1 and 53, and a Z signal inverted at the falling edge of the Y signal is obtained as shown in FIG. Again,
Since the operation can be performed at the falling edge of the clock pulse output from the AND circuit 57, the delay amount is equivalent to the two AND circuits 57 and 59. As described above, in the circuit shown in FIG. 11, the clock delay per one is much shorter than the delay time of one flip-flop, and the output of the Z signal which is the most delayed is slightly, although it is an asynchronous binary counter. It is only delayed by two gates.

The U, W, X, Y,
The Z signal is a signal obtained by counting clocks.
By decoding this, a selection signal for the corresponding block can be obtained.

Using the binary counter shown in FIG.
When configuring the bit ring counters 7 and 8, the D flip-flops 51 and 52, AND
The circuits 56 and 57 are added to the 4-bit ring counter 7, the D flip-flops 53, 54 and 55, and the AND circuits 58 and 59.
May be provided in the 8-bit ring counter 8 and the output of the AND circuit 57 may be passed from the 4-bit ring counter 7 to the 8-bit ring counter 8 as a carry signal.

FIG. 13 is a block diagram showing an example of a 4-bit ring counter and an 8-bit ring counter using the binary counter shown in FIG. In the figure, the same parts as those in FIG. 11 are denoted by the same reference numerals, and description thereof will be omitted. 61-
70 is a selector, 71 to 74 are OR circuits, 75 and 76 are decoding units, and 77 is an AND circuit unit. The configuration of the 4-bit ring counter 7 is shown above the broken line, and the configuration of the 8-bit ring counter 8 is shown below the broken line. Basically, it has the same configuration as the binary counter shown in FIG. The outputs of the D flip-flops 51 to 55 are respectively connected to selectors 61 to 65,
The selectors 66 to 70 are connected, and the decoding unit 7
5, 76 are connected. Further, an AND circuit unit 77 is connected to the 4-bit ring counter. When the selection signal SEL is 'H', Q = I1,
When * Q = I2 and 'L', Q = I2 and * Q = I1.

Although the circuit shown in FIG. 11 can perform only the count-up operation, it can be configured so that the count-down operation can be easily performed. That is, the outputs of the D flip-flops 51 to 55 may be inverted in the forward / reverse direction. Therefore, in the 4-bit ring counter 7 and the 8-bit ring counter 8 shown in FIG. 13, selectors 61 to 65 are provided, and the DIR indicating the driving order of the blocks is provided.
The output is switched between the normal output and the inverted output by a signal. As described above, the DIR signal is "L" when indicating the forward direction and "H" when indicating the reverse direction. Therefore, in each of the selectors 61 to 65, when the inverted signal of the DIR signal is "H", the D flip-flop is used. The Q outputs of the steps 51 to 55 are selected, and when it is "L", the * Q output which is an inverted signal is selected.

However, the problem here is that the blocks selected by the pre-pulse and the main pulse are different. That is, at the time of driving in the forward direction, the block driven by the main pulse is the block immediately before the block driven by the prepulse. To solve this problem, selectors 66 to 70 for the main pulse are provided. The select signal is D based on the pre-pulse.
The outputs of the flip-flops 51 to 55 are selected and output, and the state that must be inverted to change the selected block by the main pulse is obtained by the Quinma class key method, and only the selector to be inverted outputs the inverted output. select.

The selectors to be inverted are OR circuits 71 to 7
4 is selected. Here, when all the lower digits of the binary number of the count value are 0, the count value is inverted including the place where 1 appears first. The OR circuits 71 to 74 determine whether or not all the places below that place are 0. For example, if the count value is “00100” in binary, the OR circuits 71 and 72 become “L” during main pulse driving, and the selectors 66 to 68 are inverted. As a result, "00011" is set, and the immediately preceding block is selected. The same applies to the case of the reverse order. When the count value is “00100”, the count value is inverted by the selectors 61 to 65 to become “11011”. The selectors 66 to 68 are inverted to “11100”, and the immediately preceding block is selected in the reverse order.

In this way, the numbers of the blocks to be driven during the pre-pulse driving and the main pulse driving are determined. This is decoded by the decoding units 75 and 76, and a driving signal is output to the corresponding signal line.

In the 4-bit ring counter 7, A
In the ND circuit unit 77, the output of the decoding unit 75 and EN
AND with the A signal. This eliminates the need to input the ENABLE signal to the pre-driver 4 and simplifies the wiring.

In the above-described configuration example, the configuration for realizing both the double pulse drive and the single pulse drive has been described.
However, the present invention is not limited to this, and the circuit scale can be reduced by using only double pulse driving. In addition, both the forward driving and the backward driving can be performed. However, the driving can be limited to one of the driving directions and the circuit size can be reduced.

The operation of the ink jet recording apparatus according to the first embodiment of the present invention will be described below. Generally, the driver 3 is selectively turned on, a current is supplied to the heating element 2 to generate bubbles in the ink, and the ink is ejected by the expansion and contraction of the generated bubbles to perform printing. In this example, up to eight heating elements 2 can be selected at the same time, and pre-heating (pre-pulse) is possible before printing. The printing direction and the presence or absence of the pre-pulse function can be switched by an input signal. Regarding the direction of block drive, normally, only the forward direction is used for one-way printing, and in the case of bidirectional printing, when the head scans in the same direction as one-way printing and prints, When scanning and printing, the reverse direction is selected.

After the input of the clear signal (NRST signal), the print data is read serially by the data holding circuit 6,
It is memorized. Printing of the first eight heating elements 2 is performed according to the stored print data. The eight heating elements 2 selected at the same time are, for example, 1, 5, 9, 13, 17, 21, and 2.
5th and 29th heating elements (the numbers described at the top of FIG. 1 are 1 at the left end and 256 at the right end.
o. ).
The selected eight heating elements are one block. The print data to be provided also needs to be rearranged and provided so as to have such three skipped pixels. The printing data of the next eight heating elements 2 are read into the data holding circuit 6 during printing (preheating if there is a prepulse and printing during the main pulse).

4 bit ring counter 7 and 8 bit
The ring counter 8 sequentially selects eight heating elements (one block). The 4-bit ring counter 7 has the ENA
When the BLE signal is “H”, one of the four output lines is set to “H”, and the 8-bit ring counter 8 sets one of the eight output lines to “H”. One of the 32 blocks is selected by the combination of the four output lines and the eight output lines. The eight pre-drivers 4 to which “H” has been output from both the 4-bit ring counter 7 and the 8-bit ring counter 8 are connected to the data holding circuit 6.
The driver 3 is driven in accordance with the print data latched in step (1), and the heating element 2 is energized. At the time of single pulse driving, printing is performed by this. In the case of the double pulse drive, when the pre-pulse is performed, the heating element 2 only generates heat and printing is not performed, and when the main pulse is generated, printing is performed. ENAB
At the fall of the LE signal, the output of the 4-bit ring counter 7 becomes “L”, and the heating of the heating element 2 ends. The control of the pulse width of the pre-pulse and the interval between the pre-pulse and the main pulse during the double-pulse drive are controlled by ENAB.
This is performed at the source of the LE signal. Thereafter, the 4-bit ring counter 7 shifts to select the next heating element.

In the case of single-pulse driving without using a pre-pulse, such a block is driven by changing the block 32 times for each printing. In the case of double-pulse driving using a pre-pulse, the block is driven for each preheating or printing. This is done 66 times. Thus, the driving of the 256 heating elements 2 is completed. Further, in the low power consumption mode, the regulator 10 does not supply the intermediate voltage MVDD to the pre-driver 4, so that the power consumption during non-printing can be reduced. In the low power consumption mode, the switching circuit 5 also turns off most of the low voltage LVDD supplied to the low voltage driving circuit. As a result, the power consumption can be further reduced, the amount of heat generated can be suppressed, and a decrease in image quality due to a decrease or increase in ink viscosity can be prevented.

The above printing operation will be described in detail. First, clearing of the whole, selection of a pre-pulse function, and selection of a printing direction are performed. The NRST signal is changed from “H” to “L” and is changed to “H” again. This signal is inverted by the NOT circuit, and the D flip-flop 31 of the clock generation circuit 9 shown in FIG. 7 latches the DTDIR signal at the rise of the inverted signal. According to the logic of the latched DTDIR signal, selection is made between double pulse drive using a pre-heating function (pre-pulse function) and single pulse drive. As shown in FIGS. 6A and 6B, double pulse driving is selected when the DTDIR signal is “L”, and single pulse driving is selected when the DTDIR signal is “H”.

The D latch 11 latches the DTDIR signal at the falling edge of the inverted signal of the NRST signal, and sets the driving direction of the block. FIG. 6 (C),
As shown in (D), the forward direction is set when the DTDIR signal is "L", and the reverse direction is set when it is "H".

It should be noted that such a clearing and driving method,
The selection of the driving direction is always performed after one printing cycle for selecting all the blocks. At this time, NRST
The driving method and the driving direction are selected by the logic of the DTDIR signal when the signal rises and falls.

When the NRST signal becomes "L",
The 4-bit ring counter 7 and the 8-bit ring counter 8 are cleared. During this time, the regulator 10
Does not supply power to the pre-driver 4 and enters a low power consumption mode. Further, when the intermediate voltage MVDD from the regulator 10 is cut off, the switching circuit 5 also cuts off the low voltage LVDD, and power supply to most of the low voltage driving circuit is not performed.

Since the D flip-flop 31 of the clock generation circuit 9 latches the DTDIR signal when the NRST signal is "L" as described above, the low voltage LVDD is supplied without passing through the switching circuit 5. There is a need. The same applies to the D latch 11.

After the completion of the initialization, the 4-bit ring counter 7 and the 8-bit ring counter 8 are either a block including the first heating element 2 or a block including the 256th heating element 2 according to the set driving direction. Select Hereinafter, the operation during the double pulse driving using the pre-pulse function and the operation during the single pulse driving without using the pre-pulse function will be described separately.

When performing double pulse driving using the pre-pulse function, the pulse of the ENABLE signal is input 66 times during one printing cycle. A pre-pulse for performing pre-heating and a main pulse for performing injection are alternately input. Among them, the injection is not performed in the first main pulse, and the pre-heat is not performed in the last pre-pulse. The clock generation circuit 7, as shown in FIG.
An M signal, an E signal, and an ENA signal are created from the ENABLE signal. 33 pulses of the E signal are generated. N
The pre-pulse during the period when the E-th signal becomes 'H';
The main pulse during the period in which the + 1st E signal is “H” selects the same heating element. No injection is performed in the first main pulse, and no pre-heat is performed in the last (in the 33rd E signal) prepulse.

First, the print data of the first block is read. FIG. 14 is a timing chart at the time of reading print data for the first block at the time of double pulse driving, and FIG. FIG. After the NRST signal becomes “H” and before the ENABLE signal is input (becomes “H”), DCLK is output as shown in FIG.
The signal is input eight times. When the DCLK signal falls,
The DTDIR signal is used as the print data as shown in FIG. Are skipped in the order of the youngest number.
When the DTDIR signal is fetched at “H”, the heating element 2 corresponding to this print data is pre-pressed by a subsequent pre-pulse.
Heat is applied and ink is ejected by the main pulse. When the reading of the printing data of the first block is completed, the printing operation based on the printing data and the reading of the printing data of the next block are performed.

FIG. 16 is a timing chart for reading the print data for the N-th block during the double pulse driving, and FIG. Illustration of FIG. 18
Is a heating element No. corresponding to the print data read in the reverse direction. FIG. As shown in FIG. 16, during the (N-1) -th (N = 2 to 32) E signals, the print data of the N-th block is read serially for eight heating elements for preheating. The print data read at this time is the heating element No. shown in FIG. In the case of the heating element No. shown in FIG. , And are read correspondingly.
At this time, the driving order of the heating elements is set so that the adjacent heating elements are not driven as much as possible. For example, when the heating element No. = 1 group (N = 1)
Next to the heating element No. = 3 group (N = 2)
It is.

FIG. 19 is an explanatory diagram of the timing of driving the same block by the pre-pulse and driving by the main pulse in the double pulse driving. As indicated by hatching in FIG. 19, the heating element 2 of the N-th block is preheated by the pre-pulse of the N-th signal of the E signal by the print data read during the (N-1) -th signal of the E signal. Then, printing is performed with the (N + 1) th main pulse of the E signal. That is, during the period when the pre-pulse is “H”,
The preheating of the heating elements of the Nth block is performed, and printing is performed not by the subsequent main pulse but by the heat generated by the next hatched main pulse.

For example, when the data holding circuit 6 having the circuit configuration shown in FIG. 10 is used, the print data is read into the shift register 41 during the (N-1) -th E signal, and the shift register is activated by the rise of the N-th E signal. The print data read by 41 is latched by the latch 42. The latched print data is selected by the selector 44 and is used at the time of prepulse driving of the Nth E signal. At the same time, this print data is also transmitted to the D flip-flop 43, and is latched at the falling edge of the Nth E signal. During this time, driving by the N-th main pulse is performed. At this time, the D flip-flop 43
Since the print data in 2 is not latched, the selector 4
4 outputs the print data of the (N-1) th block latched in the D flip-flop 43. The print data of the N-th block latched by the D flip-flop 43 at the falling of the E signal is held while the (N + 1) -th E signal is at "H", and is selected by the selector 44 at the time of driving the (N + 1) -th main pulse. , Used for printing.

FIG. 20 is a timing chart at the time of reading print data during the 32nd E signal during double pulse driving. The print data of the last block is 3
It will be read during the first E signal. In the 32nd E signal, as shown in FIG. 18, the DTDIR signal is always set to “L”, and the DCLK signal is input eight times. As a result, the print data driven by the 33rd last pre-pulse is cleared, and the heating element is not driven. The DTDIR signal and DCLK signal in the 33rd E signal do not affect printing.

FIG. 21 is an explanatory diagram of an example of the operation of the 4-bit ring counter in the forward direction at the time of double pulse driving, and FIG. 22 is an explanatory diagram of an example of the operation of the 8-bit ring counter. In the figure, E at the left end indicates the number of the E signal. Pre / Main on the right side thereof indicates the state of “H” of the pre-pulse or main pulse in the E signal. RE1 to RE4 and B1 to B8 are the output signal line names shown in FIG. Note that a blank indicates “L” and only “H” is entered. For example, during the pre-pulse driving of N = 2, the 4-bit ring counter sets RE2 to “H” and the 8-bit ring counter sets B1 to “H” to perform preheating of the second block. At the time of the subsequent main pulse drive, the 4-bit ring counter sets RE1 to "H" and the 8-bit ring counter sets B1 to "H" to perform printing by the main pulse drive of the first block. Also, at the time of N = 5 pre-pulse driving, the 4-bit ring counter and the 8-bit ring counter pre-heat the fifth block by setting RE1 and B2 to “H”, respectively.
The bit ring counter sets RE4 to "H", and the 8-bit ring counter also changes the output signal line to "H" to B1, and performs the main pulse driving of the fourth block.

FIG. 23 is an explanatory diagram of an example of the operation of the 4-bit ring counter in the reverse direction during double pulse driving, and FIG. 24 is an explanatory diagram of an example of the operation of the 8-bit ring counter. The case of the reverse direction is almost the same as that of the forward direction. However, if the order of the blocks driven during the forward drive is the block number, the block number driven by the main pulse in the reverse drive is It is larger than the number of the block driven by the prepulse. For example,
During the pre-pulse driving of N = 2, the 4-bit ring counter sets RE3 to “H” and the 8-bit ring counter sets B8 to “H” to perform preheating of the 31st block. In the following main pulse drive, 4 bits
The ring counter sets RE4 to "H" and the 8-bit ring counter sets B8 to "H", thereby performing printing by the main pulse driving of the 32nd block. Also, during the pre-pulse driving of N = 5, the 4-bit ring counter and the 8-bit ring counter are RE4 and B7, respectively.
Is set to “H”, and the 28th block is preheated. During the subsequent main pulse driving, the 4-bit ring counter changes RE1 to “H” and the 8-bit ring counter changes to “H” to change the output signal line to B8. 29
The main pulse driving of the block is performed.

FIG. 25 is a signal sequence diagram showing an example of one printing cycle at the time of double pulse driving. The above operation is summarized as shown in FIG. That is,
DTDI at rising and falling of NRST signal
The driving method and the driving direction are set by latching the R signal. Before the rising of the first ENABLE signal, the print data corresponding to the first block is read. Thereafter, at the N-th drive, the print data corresponding to the (N + 1) -th block is read, and at the 32nd and 33rd drives, the DTDIR is read.
The signal is set to "L" and the print data is reset. on the other hand,
At the time of the first driving, only the prepulse of the ENABLE signal is used, and the preheating is performed in accordance with the print data of the first block. No printing is performed with the first main pulse. Thereafter, at the time of the N-th drive, pre-heating is performed by a pre-pulse corresponding to the print data of the N-th block, and further, printing is performed by the main pulse corresponding to the print data of the (N-1) -th block.
At the time of the last 33rd drive, the drive by the pre-pulse is not performed, and the drive of the 32nd block is performed by the main pulse.

Next, an example of a printing operation at the time of single pulse driving without the pre-pulse function will be described. Without the pre-pulse function, a pulse in which the ENABLE signal becomes “H” in one cycle is input 32 times. As shown in FIG. 9, the E signal is the same as the ENABLE signal,
The signal is always 'L'. Each time the pulse of the ENABLE signal is input, the selected block is shifted.

First, the print data of the first block is read. FIG. 26 is a timing chart at the time of reading print data for the first block at the time of single pulse driving. FIG. FIG. After the NRST signal becomes “H” and before the ENABLE signal is input (becomes “H”), as shown in FIG.
The signal is input eight times. When the DCLK signal falls,
The heating element No. shown in FIG. Are skipped in the order of the youngest number.
When the DTDIR signal is fetched at “H”, the heating element 2 corresponding to this print data is pre-pressed by a subsequent pre-pulse.
Heat is applied and ink is ejected by the main pulse. When the reading of the printing data of the first block is completed, the printing operation based on the printing data and the reading of the printing data of the next block are performed.

FIG. 28 is a timing chart for reading print data for the N-th block during single pulse driving, and FIG. 29 is a diagram showing a heating element No. corresponding to print data read in the forward direction. FIG. 30
Is a heating element No. corresponding to the print data read in the reverse direction. FIG. As shown in FIG. 28, printing is performed during a period when the ENABLE signal is “H”. The printing time is determined by the period when the ENABLE signal is 'H'. The print data is captured while the ENABLE signal immediately before printing is "H". That is, in FIG.
Assuming that the NABLE signal is the period of the (H) of the (N-1) th, the print data to be read is the print data of the Nth block. Heating element No. shown in FIG. , And are read correspondingly.

FIG. 31 shows ENABL during single pulse driving.
It is a timing chart at the time of reading of print data in the 31st and 32nd of the E signal. The print data of the 32nd block is read in the 31st ENABLE signal. Therefore, the DCLK signal and the DTDIR signal in the 32nd ENABLE signal have no effect on printing.

FIG. 32 shows the state of 4b during single pulse driving.
FIG. 33 is an explanatory diagram of an example of the operation of the it ring counter,
It is explanatory drawing of an example of operation | movement of an 8-bit ring counter similarly. The 4-bit ring counter 7 outputs 4 bits (R
One of E1 to RE4) is “H” and the remaining three bits are “L”. As shown in FIG. 32A, during forward driving, the pulse of the ENABLE signal causes the falling edge of RE1 → RE2 → RE3 → RE4 → RE1 → RE2.
The signal lines that become “H” shift in the order of →. At the time of reverse drive, as shown in FIG. 32B, the pulse of the ENABLE signal causes RE4 → RE3 → RE2 → RE1 → R
The signal lines that become “H” shift in the order of E4 → RE3 →.

In the 8-bit ring counter 8, one of the output eight bits (B1 to B8) is "H" and the remaining seven bits are "L". As shown in FIG. 33A, in the forward driving, the falling edge of the pulse of the ENABLE signal is 4 times.
'H' shifts in the order of B1 → B2 → ... → B8 every time. At the time of reverse drive, as shown in FIG.
B8 → B7 → ... → every four pulses of the NABLE signal
'H' shifts in the order of B1.

FIG. 34 is a signal sequence diagram showing an example of one printing cycle at the time of single pulse driving. To summarize the above operation, as shown in FIG. 34, the DTDIR signal is latched at the rise and fall of the NRST signal to set the driving method and the driving direction, and the first ENABL is set.
Before the rising of the E signal, the print data corresponding to the first block is read. Thereafter, at the Nth drive, the print data corresponding to the (N + 1) th block is read, and at the 32nd drive, the print data read at the 31st drive is printed, and the operation ends.

As can be seen from the above detailed description of the operation, the low voltage LVDD is supplied to the NRS in the low voltage driving circuit.
There is a part that must be energized even when the T signal is "L". For example, as shown in FIG. 6, when the NRST signal falls or rises, the state of the DTDIR signal is recognized, and the presence / absence of a pre-pulse and the driving direction are set. Therefore, a circuit for performing such recognition must be energized even when the NRST signal is “L”. Specifically, the D latch 11 and the three D flip-flops 31 to 33 and the 4-bit ring counter 7 and the 8-bit ring counter 8 shown in FIG. It must be energized. The 4-bit ring counter 7 and the 8-bit ring counter 8 are not shown in FIG. 13, but two D flip-flops 51 and 52 in the 4-bit ring counter 7 and three D flip-flops 53 in the 8-bit ring counter 8. To clear ~ 55, the NRST signal is used. Further, as described above, the state of the DTDlR signal at the time of rising or falling of the NRST signal is represented by
Since recognition is performed by flip-flops or the like, it is necessary to keep energizing some circuits on the way to these D flip-flops.

When the NRST signal is “L”, the low-voltage driving circuit that does not need to be energized is a portion other than the above-described circuit. 4b other than the part related to the input of
Except for the portion related to the inputs of the two D flip-flops 51 and 52 in the it ring counter 7, the three D flip-flops 53 to 55 in the 8-bit ring counter 8
And the low voltage operation output circuit of DOUT1 and DOUT2.

Such a low voltage driving circuit is an N channel M
The following specifically shows how much power consumption can be reduced as a configuration including OS transistors. Here, as a specific example, regarding the E-MOS transistor in the low-voltage drive circuit, Vthe = 1V and the process coefficient = 16 ×
For 10 ^-6 A / V ² , D-MOS transistor,
Vthd = -4V, process coefficient = 19 × 10 ^-6 A / V
^The gate oxide film thickness is about 90 nm for both E-MOS and D-MOS transistors. Further, the capacitance relationship with the spice parameter is Cg = 3.8 ×
10 ⁻⁴ pF / μm ² , Cjad, as = 1.6 × 10 ⁻⁴
pF / μm ² , Cjpd, ps = 12 × 10 ⁻⁴ pF / μ
m ² .

If the period of the DCLK signal is 40 ns,
Standard E, D- that constitutes an inverter in a 5 μm process
The width (W) and length (L) of the MOS transistor are determined by the load-side D-MOS transistor (W / L): (5 μm / 1
0 μm), drive side E-MOS transistor (W / L):
(10 μm / 5 μm). In FIG. 1, in order to drive signals D1 and D2 having a large wiring capacitance, a buffer having a size about five times larger than that of a standard inverter is used in a Super Buffer configuration.

In this case, about 3
A current of about 0 mA flows. Here, as shown in FIG. 4A, the switching circuit 5 cuts off the power supplied to most of the low-voltage drive circuit at the time of standby,
Power consumption can be reduced. That is, when the NRST signal is “H”, the driving operation of the heating element 2 is performed in synchronization with the ENABLE signal. However, when the NRST signal is “L”, the power supply of the low-voltage driving circuit that does not need to operate is cut off.
Power consumption can be reduced. When the power consumption is reduced in this manner, about 2 mA is used in the low power consumption mode.
Only about current flows, and power consumption can be reduced to several tenths.

The NRST signal becomes 'L' and the pre-driver and the low-voltage drive circuit enter the low power consumption mode, as shown in FIG. 25 and FIG. Occurs every cycle. When the head reciprocates and prints both ways,
When the NRST signal becomes “L” when the scanning direction of the head changes, and printing is performed only when the head moves in one direction, after scanning once, and while returning to the original position (usually 0). .3 seconds to 0.5 seconds) is NRS
The T signal becomes 'L'. These NRST signals are 'L'
During the period, most of the low-voltage driving circuit together with the pre-driver is in the low power consumption mode. Incidentally, in general, printing in only one direction can provide higher image quality than printing in both directions.

FIG. 35 is a block diagram showing an example of a circuit provided on a substrate on which a heating element is mounted in the second embodiment of the ink jet recording apparatus of the present invention. In the figure,
The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. 81 is a 16-bit counter, 82 is a 64-bit latch, and 83 is a 64-bit shift register. In this example, 64 heating elements 2 are mounted. As in the above-described example, a dummy element may be included. Of course, the number of heating elements is arbitrary and is not limited to 64.

The pre-driver 4 generates a drive signal for the corresponding heating element 2, boosts the voltage, and inputs the drive signal to a control electrode of the driver 3, for example, a gate electrode in a MOS-FET. One of the block division drive signals from the 16-bit counter 81, the print enable signal ENABLE, and the data signal from the 64-bit latch 82 are input to the pre-driver 4, and the drive signal is obtained by ANDing these signals. Can be generated. That is, a block including the corresponding heating element 2 is selected, data to be recorded exists, and a print enable signal E
When NABLE is input, a drive signal is output to the driver element 2.

The 16-bit counter 81 counts the block transfer clock BCLK, generates a block division drive signal, and inputs it to the pre-driver 4 corresponding to each block. In addition, by the block transfer direction signal BDIR,
The direction in which the block division drive signal is generated, that is, in this example, the direction from block 1 to block 16 or the direction from block 16 to block 1 can be switched. It is reset by a block reset signal BRST.

The 64-bit latch 82 has 64 bits corresponding to each heating element 2 according to the data latch clock LCLK.
The bit print data is latched and held, and output to the corresponding pre-driver 4. It is reset by the data reset signal DRST.

The 64-bit shift register 83 sequentially holds the recording data serially input as the data signal DATA together with the data transfer clock DCLK. Further, the held 64-bit recording data is transferred to the 64-bit latch 6 in parallel.

The regulator 10 may have the same configuration as that of the first embodiment, for example, as shown in FIG. Here, the MVOFF signal is input in FIG. 35 as the input signal in FIG. By this MVOFF signal, the intermediate voltage MV output from the regulator 10
DD ON / OFF control can be performed.

Also in this example, the regulator 10
Is supplied to the gate of the switching circuit 5 and the low voltage LVDD
To reduce the power consumption of the low-voltage drive circuit.

FIG. 36 is a timing chart showing an example of the operation of the ink jet recording apparatus according to the second embodiment of the present invention. Prior to the first recording, 64 print data corresponding to each heating element 2 are serially input to the 64-bit shift register 83 in advance. Thereafter, the 64-bit latch 82 is reset by the data reset signal DRST, and 6 bits are reset by the data latch clock signal LCLK.
All the recording data in the 4-bit shift register 83 is
The data is transferred to the 4-bit latch 82 and latched. 64bi
The t-latch outputs the recording data to each pre-driver 4.

The 16-bit counter 81 is reset by the block reset signal BRST, and after the driving order is selected by the block transfer direction signal BDIR, counts the block transfer clock signal BCLK and selectively sends out the block division drive signal. . In FIG. 36, when the block transfer direction signal BDIR is "L", forward recording is selected, and when "H", reverse recording is selected. Here, first, the block transfer direction signal BD
'L' is input as IR, and forward recording is performed.

The 16-bit counter 81 outputs a block division drive signal for the block 1 to the first to fourth pre-drivers 4 based on the first block transfer clock signal BCLK. When a print enable signal ENABLE having a pre-pulse and a main pulse is input from the outside, 64 out of the first to fourth pre-drivers 4
Only the output of the recording data from the bit latch 82 outputs a drive signal in accordance with the print enable signal ENABLE. As a result, the driver 3 is driven via the pre-driver 4, and a current flows through one of the first to fourth heating elements 2 where print data exists, and the heating elements 2 generate heat. At this time, the ink is not ejected by the pre-pulse, but only the temperature is increased by the heat generated by the heating element 2, and bubbles are generated in the ink by the heat generated by the heating element 2 in the next main pulse, and the ink is ejected to perform recording. Done.

Subsequently, the 16-bit counter 81 counts the next block transfer clock signal BCLK, outputs a block division drive signal for the block 2 to the fifth to eighth pre-drivers 4, and generates the fifth to eighth heat generation signals. Element 2
Among them, the recording data exists and the recording is performed by generating heat. Hereinafter, printing is performed by sequentially driving up to the block 16.

During the driving of the blocks 1 to 16, the next 64 pieces of print data are serially transmitted in 64 bits.
Input to the shift register 83. That is, the data signal DATA is synchronized with the data transfer clock signal DCLK.
Are input to the 64-bit shift register 83, and 64 pieces of print data are stored in the 64-bit shift register 83. Note that the transfer of the recording data to the 64-bit shift register 83 does not have to be synchronized with the recording operation.
What is necessary is just to carry out within one period which drives four heating elements 2.

When the driving of the 16 blocks is completed, the 16-bit counter 81 is reset by the block reset signal BRST, and the driving direction is set by the block transfer direction signal BDIR. In the latter half of FIG. 36, 'H' is input as the block transfer direction signal BDIR, and reverse recording is set. Also, the data reset signal D
The RST resets the 64-bit latch 82,
64bi by the data latch clock signal LCLK
The recording data in the t shift register 83 is latched by the 64-bit latch 82. Further, in this case, reverse recording is performed, and the recording is driven sequentially from the block 16.

The recording is performed by repeating such a series of operations. Here, the forward recording and the reverse recording are performed continuously, but of course, the forward recording or the reverse recording may be actually performed continuously.

Although the timing chart in the case of the double pulse drive is shown here, the print enable signal E
By inputting a single drive pulse as NABLE, single pulse drive can be performed.

As described above, when the heating element 2 is not driven, the regulator 10 can stop supplying power to the pre-driver 4 by inputting the control signal MVOFF. Thereby, the power consumption in the pre-driver 4 can be reduced. Further, since the intermediate voltage MVDD output from the regulator 10 is applied to the gate electrode of the switching circuit 5, power supply to the pre-driver 4 and power supply to the low-voltage drive circuit can be stopped.

As the control signal MVOFF, for example, FIG.
LCLK shown in the timing chart shown in FIG.
An inverted signal of the signal can be used. That is, LC
While the LK signal is at "H", the intermediate voltage MVDD is output from the regulator 10, the pre-driver 4 operates, and the switching circuit 5 is turned on to supply the low voltage LVDD to the low voltage driving circuit. . The LCLK signal becomes 'L' during the driving of a series of blocks. During this time, the 64-bit shift register 83 to 64b
while the recording data is being transferred to the it latch 82,
No recording operation is performed. During this time, the intermediate voltage MVDD from the regulator 10 is cut off and the operation of the pre-driver 4 is stopped, and the low voltage LVDD is also cut off by the switching circuit 5 so that part of the operation of the low voltage drive circuit is stopped. This makes it possible to reduce power consumption while the recording operation is not being performed, and to suppress the temperature rise of the substrate.

However, in the second embodiment, the portion where the low voltage LVDD can be cut off is limited to some extent. In this example, it is necessary to read data of the next cycle during a certain cycle operation (driving operation of all bits) and latch the data before moving to the next cycle. Therefore, the 64-bit latches 82 and 64b in FIG.
The it shift register 83 cannot shut off the low voltage LVDD between cycles. In addition, the flip-flop of the 16-bit counter 81 that requires reset cannot cut off the low voltage LVDD between cycles. Otherwise, the low voltage LVDD can be cut off between cycles. Also, when the head reciprocates and performs printing, most of the low-voltage driving circuit together with the pre-driver is in the low power consumption mode when the scanning direction of the head changes or the head returns to the original position. obtain. For example, the low voltage LVDD can be cut off also for the 64-bit latch 82 and the 64-bit shift register 83 in FIG.

In each of the above examples, the heating element 2
And the number of heating elements 2 to be driven simultaneously (the number of blocks associated therewith) are arbitrary. Further, which heating element 2 is selected as the heating element 2 to be driven at the same time is arbitrary, and the driving order is also arbitrary. As shown in FIG. 1, the output line of the data holding circuit 6, the output line of the 4-bit ring counter,
Depending on the configuration, each output line and the input line of the pre-driver 4 are arranged vertically and horizontally so that the output line of the 8-bit ring counter can be easily input to any of the pre-drivers 4. It is possible to change the block configuration and the driving order of the heating elements only by changing the contact position. FIG.
In the example shown in FIG. 5, the block division drive signal from the 16-bit counter 81 may be all wired in the direction in which the heating element 2 extends. Then, it is possible to change the block configuration and the driving order of the heating elements only by changing the contact position. In the example shown in FIG. 1, it is necessary to change the arrangement order of the print data input to the data holding circuit 6 in accordance with the block configuration and the drive order.

FIG. 37 is a schematic structural perspective view showing an application example of the ink jet recording apparatus of the present invention. In the figure, 91 is a recording medium, 92 is a recording head, 93 is a carriage, 9
4 is an ink cartridge, 95 is a guide shaft, 96 is a guide rail, and 97 is a flexible cable. The recording medium 91 is composed of any recordable medium such as paper, postcard, cloth, and the like. The recording medium 91 is transported to a position facing the recording head 92 by the transport mechanism.

The recording head 92 realizes the configuration of the present invention shown in, for example, FIG. 1 or FIG. 35 described above, and performs recording by ejecting ink to the opposing recording medium 91 by a heating element. An ink cartridge 94 is mounted on the recording head 92, and the ink to be ejected is supplied from the ink cartridge 94.

The recording head 92 and the ink cartridge 94 are mounted on a carriage 93. In this example,
Two sets of recording heads 92 and ink cartridges 94 are mounted on the carriage 93. The carriage 93 is
The recording medium 91 is configured to be slidable along a guide shaft 95 and a guide rail 96 extending in a direction orthogonal to the transport direction of the recording medium 91.

A recording medium 91 is conveyed from the direction of arrow A. The recording head 92 is moved by the carriage 93 sliding along the guide shaft 95 and the guide rail 96.
It moves in a direction substantially orthogonal to the direction of arrow A. At this time, print data, control signals, and power are supplied via the flexible cable 97, and printing is performed on the print head 92 in a band-like area having a width in which the heating elements are arranged. An image is formed on the recording medium 91 by repeatedly performing such a recording operation for each band-shaped area.

The present invention is not limited to the apparatus having such a configuration. For example, the present invention includes a recording head having a width larger than the width of the recording medium, and performs recording by moving the recording medium without moving the recording head. The present invention can be applied to various configurations, such as a configuration in which the recording medium is stopped and a configuration in which only the recording head moves while the recording medium is stopped.

[0122]

As is apparent from the above description, according to the present invention, the power consumption of the low-voltage drive circuit during standby can be greatly reduced. As a result, it is possible to reduce the temperature rise of the substrate on which the heating element is mounted, to prevent clogging due to the temperature rise, to reduce the viscosity of the ink, and to reduce the poor image quality due to bubbles generated during high-temperature printing. . Normally, when the temperature rises during printing, the operation is performed so that the printing speed is reduced to lower the temperature. Therefore,
The fact that it is difficult to raise the temperature leads to an increase in the speed of the printing operation. That is, there is an effect that it is possible to provide an inkjet recording apparatus which has high reliability and enables high-speed printing.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating an example of a circuit provided on a substrate on which a heating element is mounted in a first embodiment of an inkjet recording apparatus of the present invention.

FIG. 2 is a circuit configuration diagram illustrating an example of a regulator.

FIG. 3 is a circuit diagram illustrating an example of a pre-driver.

FIG. 4 is a conceptual diagram of power supply to a low-voltage drive circuit.

FIG. 5 is a schematic configuration diagram illustrating an example of a low-voltage drive circuit.

FIG. 6 is an explanatory diagram of an example of selection of a prepulse function and a driving order by a DTDIR signal.

FIG. 7 is a circuit diagram illustrating an example of a clock generation circuit.

FIG. 8 is an explanatory diagram of an example of a signal generated during double pulse driving.

FIG. 9 is an explanatory diagram of an example of a signal generated during single pulse driving.

FIG. 10 is a circuit diagram illustrating an example of a data holding circuit.

FIG. 11 is an explanatory diagram of an example of a binary counter not synchronized with a clock.

FIG. 12 is a timing chart illustrating an operation example of an example of the binary counter illustrated in FIG. 11;

FIG. 13 shows an example of 4 using the binary counter shown in FIG. 11;
It is a block diagram showing an example of a bit ring counter and an 8-bit ring counter.

FIG. 14 is a timing chart when reading print data for the first block during double pulse driving.

FIG. 15 shows a heating element No. corresponding to print data read at the beginning of double pulse driving. FIG.

FIG. 16 is a timing chart at the time of reading print data for the Nth block during double pulse driving.

FIG. 17 shows a heating element No. corresponding to print data read in the forward direction for the N-th block during double pulse driving. FIG.

FIG. 18 shows a heating element No. corresponding to print data read in the reverse direction for the N-th block during double pulse driving. FIG.

FIG. 19 is an explanatory diagram of the timing of driving by the pre-pulse and the driving by the main pulse of the same block during double-pulse driving.

FIG. 20 is a timing chart at the time of reading print data during the 32nd of the E signal during double pulse driving.

FIG. 21 shows 4 in the forward direction during double pulse driving.
FIG. 4 is an explanatory diagram of an example of the operation of a bit ring counter.

FIG. 22: 8 in the forward direction during double pulse driving
FIG. 4 is an explanatory diagram of an example of the operation of a bit ring counter.

FIG. 23 is an explanatory diagram of an example of the operation of the 4-bit ring counter.

FIG. 24: 8 in reverse direction during double pulse drive
FIG. 4 is an explanatory diagram of an example of the operation of a bit ring counter.

FIG. 25 is a signal sequence diagram illustrating an example of one printing cycle during double pulse driving.

FIG. 26 is a timing chart when reading print data for the first block during single pulse driving.

FIG. 27 shows a heating element No. corresponding to print data read for the first block during single pulse driving. FIG.

FIG. 28 is a timing chart at the time of reading print data for the N-th block during single pulse driving.

FIG. 29 shows a heating element No. corresponding to print data read in the forward direction for the N-th block during single pulse driving. FIG.

FIG. 30 shows a heating element No. corresponding to print data read in the reverse direction for the N-th block during single pulse driving. FIG.

FIG. 31 shows ENABLE signal 3 during single pulse driving.
It is a timing chart at the time of reading of print data in the 1st and 32nd.

FIG. 32 is a diagram illustrating an example of the operation of a 4-bit ring counter during single pulse driving.

FIG. 33 is an explanatory diagram of an example of the operation of the 8-bit ring counter during single pulse driving.

FIG. 34 is a signal sequence diagram showing an example of one printing cycle at the time of single pulse driving.

FIG. 35 is a configuration diagram illustrating an example of a circuit provided on a substrate on which a heating element is mounted in the second embodiment of the inkjet recording apparatus of the present invention.

FIG. 36 is a timing chart showing an example of the operation of the inkjet recording apparatus according to the second embodiment of the present invention.

FIG. 37 is a schematic configuration perspective view showing an application example of the ink jet recording apparatus of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Common electrode, 2 ... Heating element, 3 ... Driver element, 4 ...
Pre-driver, 5 switching circuit, 6 data holding circuit, 7 4-bit ring counter, 8 8-bit ring counter, 9 clock generation circuit, 10 regulator, 11 D latch, 12 pre-driver power supply voltage monitor terminal, 13, 14 ... test signal output terminals, 21, 22
5, 29 ... load D-MOS transistor, 22 to 24,
26-28... Driving E-MOS transistors, 31-33
... D flip-flop, 34 ... AND circuit, 35 ... OR
Circuits, 36 selectors, 37 delay circuits, 41 shift registers, 42 latches, 43 D flip-flops, 44 selectors, 51 to 55 D flip-flops, 56 to 59 AND circuits, 61 to 70 selectors ,
71 to 74... OR circuit, 75, 76.
... AND circuit section, 81 ... 16-bit counter, 82 ... 6
4-bit latch, 83 ... 64-bit shift register, 9
DESCRIPTION OF SYMBOLS 1 ... Recording medium, 92 ... Recording head, 93 ... Carriage, 94 ... Ink cartridge, 95 ... Guide shaft, 96
... guide rail, 97 ... flexible cable.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2C056 EA17 EA25 EC04 EC07 EC29 EC38 FA03 2C057 AF55 AF72 AG46 AG83 AK02 AK09 AM04 AM16 BA03 BA13 2C061 AQ05 HH11 HJ01 HT06 HT07

Claims (6)

[Claims] 1. An ink jet printing apparatus comprising: a plurality of arranged heating elements; a driver for driving the heating elements; and a drive circuit for controlling the driver in accordance with image data. A drive circuit;
An intermediate voltage driving circuit that receives an output of the low voltage driving circuit and outputs a driving signal of an intermediate voltage level necessary for driving the driver to the driver, and an intermediate voltage supplied to the intermediate voltage driving circuit is An ink jet recording apparatus which is ON / OFF controlled and has switching means for ON / OFF controlling a low voltage supplied to at least a part of the low voltage driving circuit using the intermediate voltage. 2. The low-voltage drive circuit includes a time-division drive circuit that determines a drive timing of the heating element, and a data holding circuit that holds image data, and at least a low-voltage supply circuit that is supplied to the time-division drive circuit. 2. The ink jet recording apparatus according to claim 1, wherein ON / OFF control is performed. 3. The data holding circuit holds image data of twice or less the number of simultaneously driven heating elements, and a low voltage supplied to the data holding circuit is O.
3. The ink jet recording apparatus according to claim 2, wherein N / OFF control is performed. 4. The low-voltage driving circuit includes an N-channel MO
4. The semiconductor device according to claim 1, wherein said switching means is constituted by an S-transistor group, said switching means is also constituted by an N-channel MOS transistor, and said intermediate voltage is applied to a gate thereof. Item 6. The ink jet recording apparatus according to item 1. 5. A regulator circuit for supplying power to the intermediate voltage driving circuit unit on the same substrate, wherein the regulator circuit generates the intermediate voltage from a voltage supplied to the heating element, and The intermediate voltage driving circuit is supplied to the intermediate voltage driving circuit, and the intermediate voltage supplied to the intermediate voltage driving circuit is controlled on / off based on a control signal, and the switching means is turned on by the regulator circuit.
5. The ink jet recording apparatus according to claim 1, wherein ON / OFF control of the low voltage is performed according to the intermediate voltage that has been subjected to the ON / OFF control. 6. 6. After the driving of at least each of the plurality of heating elements is completed, the intermediate voltage is controlled to be turned off until the next driving is started, and the switching means controls the turning off of the intermediate voltage. The low voltage supplied to at least a part of the low voltage driving circuit under the control
6. The FF control is performed.
The inkjet recording device according to any one of the above.