JP2009099647A - Semiconductor mounting method - Google Patents

Semiconductor mounting method Download PDF

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JP2009099647A
JP2009099647A JP2007267517A JP2007267517A JP2009099647A JP 2009099647 A JP2009099647 A JP 2009099647A JP 2007267517 A JP2007267517 A JP 2007267517A JP 2007267517 A JP2007267517 A JP 2007267517A JP 2009099647 A JP2009099647 A JP 2009099647A
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electrode
copper pattern
pattern electrode
semiconductor chip
semiconductor
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Naoya Kusayanagi
直也 草柳
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Yokogawa Electric Corp
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Yokogawa Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item

Abstract

<P>PROBLEM TO BE SOLVED: To achieve reliable high-density mounting by achieving bonding with a gold-tin flip chip which is low in load and stable by devising the electrode structure of a package substrate. <P>SOLUTION: In a semiconductor mounting method of flip-chip mounting a semiconductor chip on a mounting substrate and fixing the semiconductor chip and mounting substrate with a resin, respective electrode portions of the substrate side coming into contact with respective bumps of the semiconductor chip side are separated in two portions and hole drilling of a conic shape is carried out from the upper portion, and the respective bumps come into contact with the respective electrode portions at conic shape portions thereof. Then alloy layers are formed between bump side surfaces and inner portions of the electrode holes to achieve bonding with a low load since gold bump tips need not be crushed, and the bump side surfaces and the inner portions of the electrode holes are rubbed against each other to peel oxide films of tin plating, thereby forming the more satisfactory alloy layers. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は、高速ＬＳＩチップの実装技術に関する。   The present invention relates to a high-speed LSI chip mounting technique.

従来の高速ＬＳＩチップの実装技術について、図４（ａ）、（ｂ）を参照して説明する。先ず、図４（ａ）、（ｂ）に示すように、フリップチップ実装方法は、半導体チップ７のパッド電極にバンプボンダを用いてバンプ８を形成する。次に、パッケージ基板絶縁体１０上の銅パターン電極１１に半田１３めっきをするか、または半田を印刷し、リフロー等をすることで銅パターン電極１１を半田コーティングする。また、金すず接合の場合は、すずを銅パターン電極１１にめっきする。フリップチップボンダを用いた熱圧着工程でバンプ８と半田１３又はすずの接合を形成する。そして、バンプ８と半田１３又はすずの接合後または同時に熱硬化性樹脂、例えばアンダーフィル樹脂を注入して硬化させることにより、半導体チップ７とパッケージ基板絶縁体１０の接合信頼性を確保している。   A conventional high-speed LSI chip mounting technique will be described with reference to FIGS. First, as shown in FIGS. 4A and 4B, in the flip chip mounting method, bumps 8 are formed on the pad electrodes of the semiconductor chip 7 using bump bonders. Next, the copper pattern electrode 11 on the package substrate insulator 10 is plated with solder 13, or solder is printed, and the copper pattern electrode 11 is solder coated by reflowing or the like. Further, in the case of gold tin bonding, tin is plated on the copper pattern electrode 11. The bump 8 and the solder 13 or tin are joined by a thermocompression bonding process using a flip chip bonder. The bonding reliability between the semiconductor chip 7 and the package substrate insulator 10 is ensured by injecting and curing a thermosetting resin such as an underfill resin after the bump 8 and the solder 13 or tin are bonded.

具体的には、半導体チップ７側のバンプ８の突出部９を、パッケージ基板絶縁体１０上の銅パターン電極１１上に押しつけて半田１３又はすず表面の酸化膜１２を突き破ることによって、半導体チップ７のバンプ８と半田１３又はすずの接合が行なわれる。   Specifically, the protrusion 9 of the bump 8 on the semiconductor chip 7 side is pressed onto the copper pattern electrode 11 on the package substrate insulator 10 to break through the solder 13 or the oxide film 12 on the surface of the tin. The bumps 8 and the solder 13 or tin are joined.

また、パッケージ基板は、図５（ａ）、（ｂ）に示すように、パッケージ基板絶縁体１上に銅パターン電極２を形成している。パッケージ基板絶縁体１と銅パターン電極２の端部には、保護等の目的で耐熱性コーティング材であるソルダーレジスト３をコーティングする。   Further, as shown in FIGS. 5A and 5B, the package substrate has a copper pattern electrode 2 formed on the package substrate insulator 1. The end portions of the package substrate insulator 1 and the copper pattern electrode 2 are coated with a solder resist 3 which is a heat resistant coating material for the purpose of protection or the like.

特開平１０−１１７０６５号公報Japanese Patent Laid-Open No. 10-117065

近年、半導体チップのパッド電極も高密度化に対応して、５０μｍ程度のサイズが実現可能になってきた。また、ワイヤーボンディング技術を利用することにより、直径５０μｍ程度のサイズで金バンプは、形成できるようになってきた。   In recent years, the pad electrode of a semiconductor chip can be realized in a size of about 50 μm corresponding to the increase in density. Moreover, gold bumps can be formed with a diameter of about 50 μm by using wire bonding technology.

しかしながら、このような小径バンプをフリップチップ接合するためのパッケージ基板の電極幅を高密度化に対応して狭めていくと、例えば接合時電極上５０μｍ幅の中央に金バンプ先端を合わせることが難しいことにより、場合によっては電極から金バンプがずれて滑り落ちるような問題がある。 However, if the electrode width of the package substrate for flip-chip bonding of such small-diameter bumps is reduced corresponding to the increase in density, for example, it is difficult to match the tip of the gold bump to the center of the 50 μm width on the electrode during bonding. As a result, there is a problem that the gold bump is displaced from the electrode and slides down.

また、高密度化に従ってフリップチップ接合ピン数が増えると、パッケージ基板の電極上で金バンプ先端を押しつけて接合する方式では、必要な荷重が金バンプ数に比例して増えていくという問題がある。例えば、１ピンあたり２０ｇの荷重が必要だとすると、２０００ピンの接合を行うためには４０ｋｇの荷重が必要になる。 In addition, when the number of flip chip bonding pins increases as the density increases, the method of pressing the gold bump tips on the electrodes of the package substrate to bond them has the problem that the required load increases in proportion to the number of gold bumps. . For example, if a load of 20 g per pin is required, a load of 40 kg is required to join 2000 pins.

一方、荷重をかけないために予めバンプ先端を押しつぶしておくことも考えられるが、この場合バンプと電極の間にアンダーフィル樹脂を挟みこんでしまうことにより、合金層形成の妨げとなる可能性があるという問題がある。 On the other hand, it is conceivable to crush the bump tip in advance in order not to apply a load, but in this case, if an underfill resin is sandwiched between the bump and the electrode, there is a possibility of hindering the formation of the alloy layer. There is a problem that there is.

本発明は、パッケージ基板の電極構造を工夫することにより、低荷重でありかつ安定な金すずフリップチップで接合できるようにし、信頼性の高い高密度実装を実現することを目的とする。   An object of the present invention is to devise the electrode structure of a package substrate so as to enable bonding with a low-load and stable gold tin flip chip, and to realize high-density mounting with high reliability.

上記のような目的を達成するために本発明は、請求項１に示すように、実装基板上に半導体チップをフリップチップ実装するとともに、前記半導体チップと前記実装基板とを樹脂にて固着する半導体実装方法において、前記半導体チップ側の各バンプと接触する基板側の各電極部は２つに分離されかつ上部より円錐形状の穴加工が施されるとともに、前記各バンプは前記各電極部とその円錐形状部分において接触することを特徴としている。 To achieve the above object, according to the present invention, a semiconductor chip is flip-chip mounted on a mounting substrate, and the semiconductor chip and the mounting substrate are fixed with a resin. In the mounting method, each electrode part on the substrate side that comes into contact with each bump on the semiconductor chip side is separated into two parts, and a conical hole is drilled from above, and each bump includes the electrode part and its electrode part. It is characterized by contacting at a conical portion.

また、請求項２に示すように、請求項１記載の半導体実装方法において、前記各電極部上に施されるめっき処理の材質はすずであり、前記各バンプの材質は金であることを前提としている。 Moreover, as shown in claim 2, in the semiconductor mounting method according to claim 1, it is assumed that the material of the plating treatment applied to each electrode portion is tin, and the material of each bump is gold. It is said.

また、請求項３に示すように、請求項１または２記載の半導体実装方法において、前記各電極部は、電気的に分離していることを特徴としている。 According to a third aspect of the present invention, in the semiconductor mounting method according to the first or second aspect, each of the electrode portions is electrically separated.

さらに、請求項４に示すように、請求項１乃至３いずれかに記載の半導体実装方法において、前記各バンプを前記各電極部の円錐形状部分における側面部に接触させることにより、前記各電極部上のすずめっきの酸化膜を剥がすことを特徴とした実装方法である。 Further, according to a fourth aspect of the present invention, in the semiconductor mounting method according to any one of the first to third aspects, each of the electrode portions is brought into contact with each side surface of a conical portion of each of the electrode portions. The mounting method is characterized by peeling off the tin-plated oxide film.

本願において開示される発明のうち代表的なものによって得られる効果を説明すれば下記の通りである。 The effects obtained by the typical inventions among those disclosed in the present application will be described as follows.

基板側の銅パターン電極部は２つに分離され、分離された銅パターン電極部の上部より円錐形状に穴加工を施すことにより、細い金バンプの先端は、上からの荷重により円錐形状の穴に習って入るようになる。金バンプが、円錐形状の穴に習って入るようになることにより、位置ずれが起こりにくくなる。 The copper pattern electrode part on the substrate side is separated into two parts, and the tip of the thin gold bump is formed into a conical hole by the load from above by drilling a hole in a conical shape from the upper part of the separated copper pattern electrode part. Learn to enter. As the gold bumps come into the conical hole, the positional deviation is less likely to occur.

また、基板側の２つに分離された銅パターン電極部の上部より円錐形状の穴を加工し、銅パターン電極部上の円錐形状の穴で金バンプの側面を接合することにより、金バンプの先端を押しつける必要がなくなり、低荷重での接合ができるようになる。 Further, by processing a conical hole from the upper part of the copper pattern electrode part separated into two on the substrate side, and joining the side surface of the gold bump with the conical hole on the copper pattern electrode part, There is no need to press the tip, and joining with a low load becomes possible.

次に、基板側の各銅パターン電極部を２つに分離することにより、銅パターン電極部の上部より形成された円錐形状の穴にアンダーフィル樹脂が入ったとしても、円錐形状の穴に金バンプを押し付けることで銅パターン電極部横からアンダーフィル樹脂が流れ出ることができる。 Next, by separating each copper pattern electrode part on the substrate side into two, even if the underfill resin enters the conical hole formed from the upper part of the copper pattern electrode part, the gold is placed in the conical hole. By pressing the bump, the underfill resin can flow out from the side of the copper pattern electrode portion.

そして、基板側の２つに分離された銅パターン電極部と半導体チップ側の金バンプでフリップチップ接合を行うことにより、銅パターン電極部の一端をＬＳＩへの信号または電源接続にし、別の銅パターン電極部の一端を信号または電源が接続されていることを確認するためのセンス端子にすることができる。 Then, by performing flip-chip bonding with the copper pattern electrode part separated into two on the substrate side and the gold bump on the semiconductor chip side, one end of the copper pattern electrode part is connected to the signal or power supply to the LSI, and another copper One end of the pattern electrode portion can be used as a sense terminal for confirming that a signal or a power source is connected.

つまり、銅パターン電極部を二分割することにより、一方の銅パターン電極部から半導体チップに信号を送り、もう一方の銅パターン電極部で正しく信号が接続されているかを確認することができるため、フリップチップ実装の検査カバレッジを向上することが可能となる半導体実装方法が得られる。 In other words, by dividing the copper pattern electrode part into two parts, it is possible to send a signal from one copper pattern electrode part to the semiconductor chip and check whether the signal is correctly connected in the other copper pattern electrode part. A semiconductor mounting method capable of improving the inspection coverage of flip chip mounting is obtained.

さらに、二分割された銅パターン電極部の円錐形状の穴において、半導体チップ側の金バンプの先端の側面が銅パターン電極部の円錐形状の穴と擦れ合うことにより、銅パターン電極部の円錐形状の穴のすずめっきの酸化膜を剥がすことができる。半導体チップ側の金バンプの先端が銅パターン電極部の円錐形状の穴のすずめっきの酸化膜を剥がすことにより、より良好な合金層を形成する半導体実装方法が得られる。 Further, in the conical hole of the copper pattern electrode part divided into two, the side surface of the tip of the gold bump on the semiconductor chip side rubs against the conical hole of the copper pattern electrode part, thereby forming the conical shape of the copper pattern electrode part. The tin-plated oxide film in the hole can be peeled off. The tip of the gold bump on the semiconductor chip side peels off the tin-plated oxide film in the conical hole of the copper pattern electrode portion, thereby obtaining a semiconductor mounting method for forming a better alloy layer.

以下、図面を用いて、本発明の半導体実装方法を説明する。   Hereinafter, the semiconductor mounting method of the present invention will be described with reference to the drawings.

図１（ａ）、（ｂ）は、本発明の半導体実装方法の一実施例を示す平面図および断面図である。図において、前記図５（ａ）、（ｂ）と同様のものは同一符号を付して示す。   1A and 1B are a plan view and a cross-sectional view showing an embodiment of a semiconductor mounting method of the present invention. In the figure, the same components as those in FIGS. 5A and 5B are denoted by the same reference numerals.

半導体実装方法において、図１（ａ）、（ｂ）に示すように、２つに分離した銅パターン電極２からなるパッケージ基板絶縁体１上の銅パターン電極２を基板の露光・めっき・エッチング工程を通じて形成する。その後、図２に示すように、ＵＶレーザー加工機など微細なスポット径をもつ穴加工機を用いて、分離された２つの銅パターン電極２の中央に金バンプ５の最大径よりやや小さい円錐形状の穴をあける。次に、ソルダーレジスト３で銅パターン電極２とパッケージ基板絶縁体１の端部を覆った部分以外の銅パターン電極２上にすずめっき４処理を行う。そして、図３に示すように、半導体チップ６側の金バンプ５の先端を銅パターン電極２上の円錐形状の穴に擦れ合せることでフリップチップ接合を実施する。 In the semiconductor mounting method, as shown in FIGS. 1A and 1B, a copper pattern electrode 2 on a package substrate insulator 1 made of a copper pattern electrode 2 separated into two parts is exposed to a substrate, plated, and etched. Form through. Thereafter, as shown in FIG. 2, using a hole processing machine having a fine spot diameter such as a UV laser processing machine, a conical shape slightly smaller than the maximum diameter of the gold bump 5 at the center of the two separated copper pattern electrodes 2 Drill a hole. Next, a tin plating 4 process is performed on the copper pattern electrode 2 other than the portion where the copper pattern electrode 2 and the end of the package substrate insulator 1 are covered with the solder resist 3. Then, as shown in FIG. 3, flip chip bonding is performed by rubbing the tip of the gold bump 5 on the semiconductor chip 6 side with a conical hole on the copper pattern electrode 2.

図１（ａ）、（ｂ）において、銅パターン電極２が２つに分離され、パッケージ基板絶縁体１と、パッケージ基板絶縁体１上におく銅パターン電極２の端部をソルダーレジスト３で覆う構成になっている。   1A and 1B, the copper pattern electrode 2 is separated into two, and the package substrate insulator 1 and the end portion of the copper pattern electrode 2 placed on the package substrate insulator 1 are covered with the solder resist 3. It is configured.

図２において、パッケージ基板絶縁体１上の銅パターン電極２が２つに分離された状態で、２つに分離した銅パターン電極２の中央に、金バンプ５の最大径よりもやや小さい円錐形状の穴をあけた構成になっている。   In FIG. 2, in a state where the copper pattern electrode 2 on the package substrate insulator 1 is separated into two, a conical shape slightly smaller than the maximum diameter of the gold bump 5 is formed at the center of the copper pattern electrode 2 separated into two. It has a structure with a hole.

図３において、銅パターン電極２上をソルダーレジスト３で覆っていない部分にすずめっき４処理を行い、半導体チップ６側の金バンプ５とパッケージ基板絶縁体１上の銅パターン電極２とがフリップチップ接合する構成になっている。   In FIG. 3, a tin plating 4 process is performed on a portion of the copper pattern electrode 2 not covered with the solder resist 3, and the gold bump 5 on the semiconductor chip 6 side and the copper pattern electrode 2 on the package substrate insulator 1 are flip-chiped. It is configured to join.

具体的には、細い金バンプ５の先端は、半導体チップ６側から荷重をかけることにより、金バンプ５の先端が銅パターン電極２上の円錐形状の穴に習って入るため接合位置が動きにくくなる。   Specifically, the tip of the thin gold bump 5 is loaded from the side of the semiconductor chip 6 so that the tip of the gold bump 5 enters the conical hole on the copper pattern electrode 2 so that the joining position is difficult to move. Become.

また、２分割した銅パターン電極２に円錐形状の穴を形成し、銅パターン電極２上の円錐形状の穴に金バンプ５の側面が接合することにより、金バンプ５の先端を潰す必要がなくなる。金バンプ５の先端を潰すことなく、半導体チップ６側の金バンプ５とパッケージ基板絶縁体１側の銅パターン電極２を接合できることにより、金バンプ５にかかる荷重が低荷重となり、低荷重での接合ができるようになる。   Further, a conical hole is formed in the copper pattern electrode 2 divided into two parts, and the side surface of the gold bump 5 is joined to the conical hole on the copper pattern electrode 2, thereby eliminating the need to crush the tip of the gold bump 5. . Since the gold bump 5 on the semiconductor chip 6 side and the copper pattern electrode 2 on the package substrate insulator 1 side can be joined without crushing the tip of the gold bump 5, the load applied to the gold bump 5 becomes low and the load is low. It becomes possible to join.

さらに、銅パターン電極２は２つに分離していることにより、銅パターン電極２の円錐形状の穴にアンダーフィル樹脂が入ったとしても、銅パターン電極２上の円錐形状の穴に金バンプ５の先端を押し付けることで銅パターン電極２の分離している部分からアンダーフィル樹脂が流れ出ることができる。   Further, since the copper pattern electrode 2 is separated into two, even if the underfill resin enters the conical hole of the copper pattern electrode 2, the gold bump 5 is placed in the conical hole on the copper pattern electrode 2. The underfill resin can flow out from the separated portion of the copper pattern electrode 2 by pressing the tip of the copper pattern electrode 2.

そして、パッケージ基板絶縁体１側の２つに分離した銅パターン電極２と半導体チップ６側の金バンプ５でフリップチップ接合を行うことにより、銅パターン電極２の一端を半導体チップ６への信号または電源接続にし、別の銅パターン電極２の一端を信号または電源が接続されていることを確認するためのセンス端子にすることができる。   Then, by performing flip chip bonding with the copper pattern electrode 2 separated into two on the package substrate insulator 1 side and the gold bump 5 on the semiconductor chip 6 side, one end of the copper pattern electrode 2 is connected to the signal to the semiconductor chip 6 or One end of another copper pattern electrode 2 can be used as a sense terminal for confirming that a signal or a power source is connected.

すなわち、銅パターン電極２を二分割することにより、一方の銅パターン電極２から半導体チップに信号を送り、もう一方の銅パターン電極２で信号が正しく接続されているかを確認することができるため、フリップチップ実装の検査カバレッジを向上することができる。 That is, by dividing the copper pattern electrode 2 into two parts, a signal can be sent from one copper pattern electrode 2 to the semiconductor chip, and it can be confirmed whether the signal is correctly connected at the other copper pattern electrode 2. The inspection coverage of flip chip mounting can be improved.

次に、銅パターン電極２上の円錐形状の穴があいているすずめっき４処理部分に半導体チップ６側の金バンプ５の先端を擦れ合せることにより、銅パターン電極２上のすずめっき４の酸化膜を剥がすことができる。酸化膜を剥がすことによって半導体チップ６側の金バンプ５とパッケージ基板絶縁体１側の銅パターン電極２との接合を行うことにより、より良好な合金層を形成することができる。 Next, the tip of the gold bump 5 on the semiconductor chip 6 side is rubbed against the tin plating 4 treatment portion where the conical hole is formed on the copper pattern electrode 2, thereby oxidizing the tin plating 4 on the copper pattern electrode 2. The film can be peeled off. A better alloy layer can be formed by bonding the gold bump 5 on the semiconductor chip 6 side and the copper pattern electrode 2 on the package substrate insulator 1 side by peeling the oxide film.

図１は本発明の半導体実装方法の実施の形態の中の一部分を示すものであり、（ａ）は２つに分離した電極からなるパッケージ基板電極部の一例を示す平面図、（ｂ）は（ａ）のＸ−Ｘ'断面図。FIG. 1 shows a part of an embodiment of a semiconductor mounting method according to the present invention. FIG. 1A is a plan view showing an example of a package substrate electrode portion composed of two separated electrodes, and FIG. XX 'sectional drawing of (a). 図２は本発明の半導体実装方法の２つに分離した電極の中央に円錐形状の穴加工を施した部分の一例を示す拡大図。FIG. 2 is an enlarged view showing an example of a portion in which a conical hole is formed in the center of an electrode separated into two according to the semiconductor mounting method of the present invention. 図３は本発明の半導体実装方法のバンプの先端を電極の円錐形状の穴に擦れ合せることにより行うフリップチップ接合方式の一例を示す断面図。FIG. 3 is a cross-sectional view showing an example of a flip-chip bonding method performed by rubbing the tip of a bump with a conical hole of an electrode in the semiconductor mounting method of the present invention. 図４は従来の半導体実装方法の一例を示すものであり、（ａ）はフリップチップ接合前の一例を示す断面図、（ｂ）はフリップチップ接合方式の一例を示す断面図。4A and 4B show an example of a conventional semiconductor mounting method. FIG. 4A is a cross-sectional view showing an example before flip-chip bonding, and FIG. 4B is a cross-sectional view showing an example of a flip-chip bonding method. 図５は従来の半導体実装方法の実施の形態の中の一部分を示すものであり、（ａ）はパッケージ基板と銅パターン電極の一例を示す平面図、（ｂ）は（ａ）のＸ−Ｘ' 断面図。FIG. 5 shows a part of an embodiment of a conventional semiconductor mounting method, (a) is a plan view showing an example of a package substrate and a copper pattern electrode, and (b) is an XX of (a). 'Cross section.

符号の説明Explanation of symbols

１ パッケージ基板絶縁体
２ 銅パターン電極
３ ソルダーレジスト
４ すずめっき
５ 金バンプ
６ 半導体チップ
７ 半導体チップ
８ バンプ
９ 突出部
１０ パッケージ基板絶縁体
１１ 銅パターン電極
１２ 酸化膜
１３ 半田 DESCRIPTION OF SYMBOLS 1 Package board | substrate insulator 2 Copper pattern electrode 3 Solder resist 4 Tin plating 5 Gold bump 6 Semiconductor chip 7 Semiconductor chip 8 Bump 9 Protruding part 10 Package board insulator 11 Copper pattern electrode 12 Oxide film 13 Solder

Claims (4)

実装基板上に半導体チップをフリップチップ実装するとともに、前記半導体チップと前記実装基板とを樹脂にて固着する半導体実装方法において、
前記半導体チップ側の各バンプと接触する基板側の各電極部は２つに分離されかつ上部より円錐形状の穴加工が施されるとともに、
前記各バンプは前記各電極部とその円錐形状部分において接触することを特徴とする半導体実装方法。 In a semiconductor mounting method in which a semiconductor chip is flip-chip mounted on a mounting substrate, and the semiconductor chip and the mounting substrate are fixed with a resin,
Each electrode part on the substrate side that comes into contact with each bump on the semiconductor chip side is separated into two, and a conical hole is processed from above,
The semiconductor mounting method according to claim 1, wherein the bumps are in contact with the electrode portions at the conical portions. 前記各電極部上に施されるめっき処理の材質はすずであり、前記各バンプの材質は金であることを特徴とする請求項１記載の半導体実装方法。   2. The semiconductor mounting method according to claim 1, wherein a material of the plating process applied to each of the electrode portions is tin, and a material of each of the bumps is gold. 前記各電極部は、電気的に分離していることを特徴とする請求項１または２に記載の半導体実装方法。   The semiconductor mounting method according to claim 1, wherein the electrode portions are electrically separated. 前記各バンプを前記各電極部の円錐形状部分における側面部に接触させることにより、前記各電極部上のすずめっきの酸化膜を剥がすことを特徴とする請求項１乃至３いずれかに記載の半導体実装方法。
4. The semiconductor according to claim 1, wherein the tin plating oxide film on each of the electrode parts is peeled off by bringing each of the bumps into contact with a side part of the conical portion of each of the electrode parts. Implementation method.
JP2007267517A 2007-10-15 2007-10-15 Semiconductor mounting method Pending JP2009099647A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014507804A (en) * 2011-01-28 2014-03-27 ソウル バイオシス カンパニー リミテッド Wafer level light emitting diode package and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014507804A (en) * 2011-01-28 2014-03-27 ソウル バイオシス カンパニー リミテッド Wafer level light emitting diode package and method of manufacturing the same

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