JP2009064845A - Mounting method of semiconductor device - Google Patents
Mounting method of semiconductor device Download PDFInfo
- Publication number
- JP2009064845A JP2009064845A JP2007229621A JP2007229621A JP2009064845A JP 2009064845 A JP2009064845 A JP 2009064845A JP 2007229621 A JP2007229621 A JP 2007229621A JP 2007229621 A JP2007229621 A JP 2007229621A JP 2009064845 A JP2009064845 A JP 2009064845A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electrode
- bump
- recess
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
Landscapes
- Wire Bonding (AREA)
Abstract
Description
本発明は、半導体パッケージ基板に関し、例えば一方の面に電子部品が実装される配線基板と、配線基板の一方の面に電子部品が実装されてなる半導体装置及び電子部品の実装方法に適用して好適なものである。 The present invention relates to a semiconductor package substrate, and is applied to, for example, a wiring substrate on which an electronic component is mounted on one surface, a semiconductor device in which an electronic component is mounted on one surface of the wiring substrate, and a method for mounting the electronic component. Is preferred.
実装技術の分野においては、電子機器の小型化・高機能化に伴い、高密度な実装が要求されている。その中で、半導体素子に突起電極を設け、回路基板のランドにフリップチップ実装して成る半導体装置が開発されている。 In the field of packaging technology, high-density packaging is required as electronic devices become smaller and more functional. Among them, a semiconductor device has been developed in which a protruding electrode is provided on a semiconductor element and flip-chip mounting is performed on a land of a circuit board.
特許文献２に開示された半導体装置について図４を参照して説明する。 The semiconductor device disclosed in Patent Document 2 will be described with reference to FIG.
図４において、半導体装置３１は、半導体素子３２と回路基板３５を電気的及び機械的に接続し、半導体素子３２と回路基板３５との間を封止して構成されている。半導体素子３２の電極３３上には、例えば金からなる突起電極３４が形成され、この突起電極３４を回路基板３５の対応する各ランド３６に形成された凹孔３７にて受けた状態で、突起電極３４とランド３６を機械的及び電気的に接合することにより、半導体素子３２と回路基板３５が機械的及び電気的に接続されている。また、封止樹脂３８にて、突起電極３４とランド３６の接続部が保護されている。このように、回路基板３５のランド３６に凹孔３７を形成し、その凹孔３７にて突起電極３４を受けることで、突起電極３４がランド３６上を滑って位置ずれすることを防止する構成とされている。 In FIG. 4, the semiconductor device 31 is configured by electrically and mechanically connecting a semiconductor element 32 and a circuit board 35 and sealing between the semiconductor element 32 and the circuit board 35. A protruding electrode 34 made of, for example, gold is formed on the electrode 33 of the semiconductor element 32, and the protruding electrode 34 is received in a recessed hole 37 formed in each corresponding land 36 of the circuit board 35. The semiconductor element 32 and the circuit board 35 are mechanically and electrically connected by mechanically and electrically joining the electrode 34 and the land 36. Further, the connecting portion between the protruding electrode 34 and the land 36 is protected by the sealing resin 38. As described above, the concave hole 37 is formed in the land 36 of the circuit board 35, and the protruding electrode 34 is received in the concave hole 37, thereby preventing the protruding electrode 34 from slipping and being displaced on the land 36. It is said that.
従来の半導体装置の製造方法について、図５を参照して説明する。先ず、図５（ａ）に示すように、下の層のパターンである金属の配線１を配置する。次に、図５（ｂ）に示すように、金属の配線１上に絶縁樹脂層２を形成する。そして、図５（ｃ）に示すように、絶縁樹脂層２は、例えばレーザー加工により、下の層のパターンと電気的な接続をするためのパターンを実装するために、穴３を加工する。 A conventional method for manufacturing a semiconductor device will be described with reference to FIG. First, as shown in FIG. 5A, a metal wiring 1 that is a pattern of a lower layer is disposed. Next, as shown in FIG. 5B, an insulating resin layer 2 is formed on the metal wiring 1. And as shown in FIG.5 (c), the insulating resin layer 2 processes the hole 3 in order to mount the pattern for electrically connecting with the pattern of a lower layer by laser processing, for example.
次に、図５（ｄ）に示すように、例えば周知の技術であるリソグラフィ工程を経て、絶縁樹脂層２にあけた穴３の面上に、金属の配線１のパターンを実装すると同時に、半導体素子側に設けられた電極パッド上の各バンプの位置に合わせて、電極５のパターンを実装する。また、図５（ｅ）に示すように、半導体素子側に設けた電極パッド上のバンプが電極５から滑り落ちるのを防止するために凹部９を加工する。 Next, as shown in FIG. 5D, the pattern of the metal wiring 1 is mounted on the surface of the hole 3 formed in the insulating resin layer 2 through a lithography process which is a well-known technique, for example, and at the same time, the semiconductor The pattern of the electrode 5 is mounted in accordance with the position of each bump on the electrode pad provided on the element side. Further, as shown in FIG. 5E, the recess 9 is processed to prevent the bump on the electrode pad provided on the semiconductor element side from sliding off the electrode 5.
図６において、半導体装置１０は、先ず、半導体素子６側に電極パッド７を実装し、電極パッド７上にバンプ８を形成している。一方、下の層のパターンである金属の配線１上に絶縁樹脂層２を形成している。そして、絶縁樹脂層２は穴３を加工し、穴３の面上に金属の配線１のパターンを実装すると同時に、絶縁樹脂層２に半導体素子６側に設けられた電極パッド７上のバンプ８の位置に合わせて電極５を実装している。また、電極５に凹部９の加工をした構成になっている。 In FIG. 6, the semiconductor device 10 first has an electrode pad 7 mounted on the semiconductor element 6 side, and bumps 8 are formed on the electrode pad 7. On the other hand, the insulating resin layer 2 is formed on the metal wiring 1 which is the pattern of the lower layer. Then, the insulating resin layer 2 processes the hole 3 and mounts the pattern of the metal wiring 1 on the surface of the hole 3, and at the same time, the bump 8 on the electrode pad 7 provided on the insulating resin layer 2 on the semiconductor element 6 side. The electrode 5 is mounted in accordance with the position. In addition, the electrode 5 has a recess 9 processed.
図６に示すように、半導体装置１０は、半導体素子６側に設けられた電極パッド７上のバンプ８から電極５を見た場合、バンプ８の中心が電極５の中心からずれて、バンプ８が電極５に接続する。 As shown in FIG. 6, in the semiconductor device 10, when the electrode 5 is viewed from the bump 8 on the electrode pad 7 provided on the semiconductor element 6 side, the center of the bump 8 is shifted from the center of the electrode 5. Is connected to the electrode 5.
次に、図７は、図６の構成と同様である。図７に示すように、バンプ８の中心が電極５の中心からずれても、電極５上の凹部９により、電極５からバンプ８がずれ落ちることなく、バンプ８と電極５は接続することができる。 Next, FIG. 7 is the same as the configuration of FIG. As shown in FIG. 7, even if the center of the bump 8 is deviated from the center of the electrode 5, the bump 8 and the electrode 5 can be connected without being displaced from the electrode 5 by the recess 9 on the electrode 5. it can.
しかしながら、半導体装置のフリップチップ接合において、半導体素子とパッケージ基板の位置ずれを防止することができる半導体装置の製造方法は工程数が多いため、製造コストが高くなるという問題がある。 However, in the flip chip bonding of the semiconductor device, there is a problem that the manufacturing cost of the semiconductor device manufacturing method that can prevent the positional deviation between the semiconductor element and the package substrate is high because the number of steps is large.
本発明は、半導体装置のフリップチップ接合において、位置ずれを防止することができる半導体装置の製造方法の工程数を減らすことによって、半導体装置の製造コストの削減を実現することを目的とする。 An object of the present invention is to realize a reduction in manufacturing cost of a semiconductor device by reducing the number of steps of a manufacturing method of a semiconductor device capable of preventing a positional shift in flip chip bonding of the semiconductor device.
上記のような目的を達成するために、本発明の請求項１では、半導体素子側に設けられた電極パッド上の各バンプを、パッケージ基板側の電極に当接させることにより、前記半導体素子と前記パッケージ基板とをフリップチップ接合する半導体装置の実装方法において、前記半導体素子側に設けられた前記電極パッド上の各前記バンプの位置に合わせて、前記パッケージ基板上を覆う絶縁樹脂層上にくぼみを形成することを特徴とする。 In order to achieve the above object, according to claim 1 of the present invention, the bumps on the electrode pads provided on the semiconductor element side are brought into contact with the electrodes on the package substrate side, whereby the semiconductor element and In the mounting method of the semiconductor device for flip-chip bonding to the package substrate, a recess is formed on the insulating resin layer covering the package substrate in accordance with the position of each bump on the electrode pad provided on the semiconductor element side. It is characterized by forming.
請求項２では、請求項１の半導体装置の実装方法において、前記くぼみは、この平面形状が楕円あるいは円であることを特徴とする。 According to a second aspect of the present invention, in the method for mounting a semiconductor device according to the first aspect of the present invention, the planar shape of the recess is an ellipse or a circle.
請求項３では、請求項１または２の半導体装置の実装方法において、前記くぼみは、この表面が曲面であることを特徴とする。 According to a third aspect of the present invention, in the method for mounting a semiconductor device according to the first or second aspect, the surface of the recess is a curved surface.
請求項４では、請求項１乃至３のいずれかの半導体装置の実装方法において、前記くぼみは、この径が前記半導体素子側に設けられた前記電極パッド上の各前記バンプの最大径よりも小さく、かつ、このバンプの先端の最大径よりも大きいことを特徴とする。 According to a fourth aspect of the present invention, in the semiconductor device mounting method according to any one of the first to third aspects, the diameter of the recess is smaller than a maximum diameter of the bumps on the electrode pad provided on the semiconductor element side. And it is larger than the maximum diameter of the tip of this bump.
本願において開示される発明のうち代表的なものによって得られる効果を説明すれば下記の通りである。 The effects obtained by the typical inventions among those disclosed in the present application will be described as follows.
すなわち、本発明は、半導体素子とパッケージ基板がフリップチップ接合する半導体装置の製造方法において、位置ずれを防止し、かつ製造工程の数を減らすことで、コストの削減をすることができる。 That is, according to the present invention, in a method for manufacturing a semiconductor device in which a semiconductor element and a package substrate are flip-chip bonded, it is possible to reduce costs by preventing misalignment and reducing the number of manufacturing steps.
詳細には、絶縁樹脂層のくぼみ加工は、絶縁樹脂層の穴加工と同じ工程で行なうことができるため、工程を新たに追加することなく、くぼみを形成することができる。また、加工工程が簡単であるため、コストが騰がらない。 Specifically, since the recess processing of the insulating resin layer can be performed in the same process as the hole processing of the insulating resin layer, the recess can be formed without adding a new process. In addition, since the processing process is simple, the cost does not increase.
そして、電極上のくぼみは、くぼみの平面形状が楕円あるいは円であり、かつ、くぼみの表面が曲面であるため、半導体素子と基板の隙間に封止樹脂を充填する場合、電極上のくぼみから封止樹脂が流れやすくなる。 The recess on the electrode has an ellipse or circle in the planar shape, and the surface of the recess is a curved surface. Therefore, when the sealing resin is filled in the gap between the semiconductor element and the substrate, the recess on the electrode The sealing resin can easily flow.
以下、図面を用いて、本発明の半導体装置の実装方法を説明する。 Hereinafter, a semiconductor device mounting method of the present invention will be described with reference to the drawings.
図１は、本発明の半導体装置の実装方法の一実施例を示す断面図である。図において、前記図５と同様のものは同一符号を付して示す。 FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device mounting method according to the present invention. In the figure, components similar to those in FIG.
図１に示すように、半導体装置の実装方法において、先ず、図１（ａ）に示すように、下の層のパターンである金属の配線１を配置する。次に、図１（ｂ）に示すように、金属の配線１上に絶縁樹脂層２を形成する。そして、図１（ｃ）に示すように、絶縁樹脂層２は、例えばレーザー加工により、下の層のパターンと電気的な接続をするためのパターンを穴３の面上に実装するために穴３を加工し、同時に、半導体素子側に設けた電極パッド上の各バンプの位置に合わせてくぼみ４を加工する。また、くぼみ４の径は、半導体素子側に設けられた電極パッド上の各バンプの最大径よりも小さく、かつ、バンプの先端の最大径よりも大きく加工する。 As shown in FIG. 1, in the semiconductor device mounting method, first, as shown in FIG. 1A, a metal wiring 1 which is a pattern of a lower layer is disposed. Next, as shown in FIG. 1B, an insulating resin layer 2 is formed on the metal wiring 1. Then, as shown in FIG. 1C, the insulating resin layer 2 has holes for mounting a pattern for electrical connection with the pattern of the lower layer on the surface of the hole 3 by, for example, laser processing. 3 is processed, and at the same time, the recess 4 is processed in accordance with the position of each bump on the electrode pad provided on the semiconductor element side. The diameter of the recess 4 is processed to be smaller than the maximum diameter of each bump on the electrode pad provided on the semiconductor element side and larger than the maximum diameter of the bump tip.
次に、図１（ｄ）に示すように、例えば周知の技術であるリソグラフィ工程を経て、絶縁樹脂層２にあけた穴３の面上に、金属の配線１のパターンを実装すると同時に、半導体素子と基板を電気的に接続するために、絶縁樹脂層２上のくぼみ４の表面形状に沿って電極５のパターンを実装する。また、電極５は、くぼみ４の表面形状に沿って実装されることにより、くぼみ５１を形成する。 Next, as shown in FIG. 1D, the pattern of the metal wiring 1 is mounted on the surface of the hole 3 formed in the insulating resin layer 2 through a lithography process which is a well-known technique, for example, and at the same time, the semiconductor In order to electrically connect the element and the substrate, the pattern of the electrode 5 is mounted along the surface shape of the recess 4 on the insulating resin layer 2. The electrode 5 is mounted along the surface shape of the recess 4 to form the recess 51.
本願発明に係る第１の実施形態の半導体装置の実装方法は、図２において、半導体装置１０は、先ず、半導体素子６側に電極パッド７を実装し、電極パッド７上にバンプ８を形成している。一方、下の層のパターンである金属の配線１上に絶縁樹脂層２を形成している。そして、絶縁樹脂層２は穴３を加工すると同時に、半導体素子６側に設けられた電極パッド７上のバンプ８の位置に合わせて、くぼみ４を加工している。また、くぼみ４の径は、半導体素子６側に設けられた電極パッド７上の各バンプ８の最大径よりも小さく、かつ、バンプ８の先端の最大径よりも大きく加工している。穴３とくぼみ４を加工後、穴３の面上に金属の配線１のパターンを実装すると同時に、絶縁樹脂層２上のくぼみ４の表面形状に沿って電極５を実装している。また、電極５は、くぼみ４の表面形状に沿って実装されることにより、くぼみ５１を形成する。 In the semiconductor device mounting method according to the first embodiment of the present invention, in FIG. 2, the semiconductor device 10 first mounts an electrode pad 7 on the semiconductor element 6 side, and forms bumps 8 on the electrode pad 7. ing. On the other hand, the insulating resin layer 2 is formed on the metal wiring 1 which is the pattern of the lower layer. The insulating resin layer 2 processes the hole 3 and simultaneously processes the recess 4 in accordance with the position of the bump 8 on the electrode pad 7 provided on the semiconductor element 6 side. The diameter of the recess 4 is processed to be smaller than the maximum diameter of each bump 8 on the electrode pad 7 provided on the semiconductor element 6 side and larger than the maximum diameter of the tip of the bump 8. After processing the hole 3 and the recess 4, the pattern of the metal wiring 1 is mounted on the surface of the hole 3, and at the same time, the electrode 5 is mounted along the surface shape of the recess 4 on the insulating resin layer 2. The electrode 5 is mounted along the surface shape of the recess 4 to form the recess 51.
図２に示すように、半導体装置１０は、半導体素子６側に設けられた電極パッド７上のバンプ８から電極５を見た場合、バンプ８の中心が電極５の中心からずれて、バンプ８が電極５に接続する。 As shown in FIG. 2, in the semiconductor device 10, when the electrode 5 is viewed from the bump 8 on the electrode pad 7 provided on the semiconductor element 6 side, the center of the bump 8 is shifted from the center of the electrode 5. Is connected to the electrode 5.
次に、図３は、図２の構成と同様である。図３に示すように、バンプ８の中心が電極５の中心からずれても、電極５上のくぼみ４により、電極５からバンプ８がずれ落ちることなく、バンプ８と電極５は接続することができる。 Next, FIG. 3 is similar to the configuration of FIG. As shown in FIG. 3, even if the center of the bump 8 is deviated from the center of the electrode 5, the bump 8 and the electrode 5 can be connected without the bump 8 being deviated from the electrode 5 by the depression 4 on the electrode 5. it can.
すなわち、半導体装置の製造方法工程において、本発明では、図１（ｃ）に示すように、絶縁樹脂層２に穴３をあけるのと同時に、バンプが電極５から滑り落ちるのを防止するためのくぼみ４を加工している。そして、絶縁樹脂層２に穴３およびくぼみ４を加工後、図１（ｄ）に示すように、絶縁樹脂層２に穴３をあけた面上に金属の配線１を実装すると同時に、くぼみ４の表面形状に沿って電極５を実装している。 That is, in the method of manufacturing a semiconductor device, in the present invention, as shown in FIG. 1C, a recess for preventing the bump from sliding off from the electrode 5 at the same time as making the hole 3 in the insulating resin layer 2. 4 is processed. And after processing the hole 3 and the dent 4 in the insulating resin layer 2, as shown in FIG.1 (d), the metal wiring 1 is mounted on the surface which made the hole 3 in the insulating resin layer 2, and at the same time, the dent 4 The electrode 5 is mounted along the surface shape.
これに対して、従来技術では、図５（ｃ）に示すように、絶縁樹脂層２に穴３をあける加工をしている。穴３を加工後、図５（ｄ）に示すように、絶縁樹脂層２に穴３をあけた面上に金属の配線１を実装すると同時に、半導体素子側に設けられた電極パッド上の各バンプの位置に合わせて、絶縁樹脂層２上に電極５を実装している。そして、図５（ｅ）に示すように、半導体素子側に設けられた電極パッド上のバンプが電極５から滑り落ちるのを防止するために凹部９を加工している。 On the other hand, in the prior art, as shown in FIG. 5C, the hole 3 is formed in the insulating resin layer 2. After the hole 3 is processed, as shown in FIG. 5D, the metal wiring 1 is mounted on the surface where the hole 3 is formed in the insulating resin layer 2, and at the same time, each of the electrodes on the electrode pad provided on the semiconductor element side is mounted. The electrode 5 is mounted on the insulating resin layer 2 in accordance with the position of the bump. Then, as shown in FIG. 5E, the recess 9 is processed to prevent the bump on the electrode pad provided on the semiconductor element side from sliding off the electrode 5.
このことにより、本発明の半導体装置１０の製造方法は、従来技術の半導体装置１０の製造方法の工程と比較すると、工程が少ない。
製造方法の工程数が少なくなることにより、製造コストが安くなる。
As a result, the manufacturing method of the semiconductor device 10 of the present invention has fewer steps than the manufacturing method of the conventional semiconductor device 10.
By reducing the number of steps of the manufacturing method, the manufacturing cost is reduced.
さらに、電極５は絶縁樹脂層２上のくぼみ４の表面形状に沿って形成し、くぼみ４の平面形状が楕円あるいは円であり、かつ、くぼみ４の表面が曲面であるため、半導体素子６と基板の隙間に封止樹脂を充填する場合において、電極５上のくぼみ５１から封止樹脂が流れやすくなる。 Further, the electrode 5 is formed along the surface shape of the recess 4 on the insulating resin layer 2, and the planar shape of the recess 4 is an ellipse or a circle, and the surface of the recess 4 is a curved surface. When the sealing resin is filled in the gap between the substrates, the sealing resin easily flows from the recess 51 on the electrode 5.
１ 金属の配線
２ 絶縁樹脂層
３ 穴
４ くぼみ
５ 電極
５１ くぼみ
６ 半導体素子
７ 電極パッド
８ バンプ
９ 凹部
１０ 半導体装置
３１ 半導体装置
３２ 半導体素子
３３ 電極
３４ 突起電極
３５ 回路基板
３６ ランド
３７ 凹孔
３８ 封止樹脂
DESCRIPTION OF SYMBOLS 1 Metal wiring 2 Insulation resin layer 3 Hole 4 Indentation 5 Electrode 51 Indentation 6 Semiconductor element 7 Electrode pad 8 Bump 9 Recess 10 Semiconductor device 31 Semiconductor device 32 Semiconductor element 33 Electrode 34 Projection electrode 35 Circuit board 36 Land 37 Concave hole 38 Sealing Resin
Claims (4)
前記半導体素子側に設けられた前記電極パッド上の各前記バンプの位置に合わせて、前記パッケージ基板上を覆う絶縁樹脂層上にくぼみを形成することを特徴とする半導体装置の実装方法。 In the mounting method of the semiconductor device in which each bump on the electrode pad provided on the semiconductor element side is brought into contact with the electrode on the package substrate side to flip-chip bond the semiconductor element and the package substrate.
A method of mounting a semiconductor device, comprising: forming a recess on an insulating resin layer covering the package substrate in accordance with a position of each bump on the electrode pad provided on the semiconductor element side.
2. The recess has a diameter smaller than a maximum diameter of each bump on the electrode pad provided on the semiconductor element side and larger than a maximum diameter of a tip of the bump. 4. A method for mounting a semiconductor device according to any one of claims 1 to 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007229621A JP2009064845A (en) | 2007-09-05 | 2007-09-05 | Mounting method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007229621A JP2009064845A (en) | 2007-09-05 | 2007-09-05 | Mounting method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2009064845A true JP2009064845A (en) | 2009-03-26 |
Family
ID=40559202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007229621A Pending JP2009064845A (en) | 2007-09-05 | 2007-09-05 | Mounting method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2009064845A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103959451A (en) * | 2012-01-17 | 2014-07-30 | 松下电器产业株式会社 | Semiconductor device manufacturing method and semiconductor device |
-
2007
- 2007-09-05 JP JP2007229621A patent/JP2009064845A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103959451A (en) * | 2012-01-17 | 2014-07-30 | 松下电器产业株式会社 | Semiconductor device manufacturing method and semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10580747B2 (en) | Semiconductor package and method for fabricating base for semiconductor package | |
| US20050103516A1 (en) | Flip-chip mounting circuit board, manufacturing method thereof and integrated circuit device | |
| TWI654730B (en) | Package structure and manufacturing method thereof | |
| JP2011142185A (en) | Semiconductor device | |
| US20130334684A1 (en) | Substrate structure and package structure | |
| US10276465B2 (en) | Semiconductor package assembly | |
| JP2010118522A (en) | Semiconductor device and method for manufacturing the semiconductor device | |
| TW201532231A (en) | Package and fabricating method thereof | |
| JP2005109088A (en) | Semiconductor device and its manufacturing method, circuit substrate, and electronic equipment | |
| TWI378546B (en) | Substrate and package for micro bga | |
| JP2009064845A (en) | Mounting method of semiconductor device | |
| JP4267549B2 (en) | SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE | |
| JP2008270446A (en) | Laminated type semiconductor apparatus and manufacturing method thereof | |
| KR20100002870A (en) | Method for fabricating semiconductor package | |
| JP2005353854A (en) | Wiring board and semiconductor device using the same | |
| JP2016162813A (en) | Printed circuit board and soldering method | |
| JP2007115789A (en) | Laminated semiconductor device and its manufacturing method | |
| JP2006147620A (en) | Method of manufacturing flip chip mounting semiconductor device, and flip chip mounting semiconductor device | |
| JP2004363319A (en) | Mount substrate and semiconductor device | |
| US7800237B2 (en) | Electronic device including a component stack and connecting elements, and connecting elements, and method for producing the electronic device | |
| JP2009158686A (en) | Semiconductor device | |
| JP4696712B2 (en) | Semiconductor device | |
| KR20070099378A (en) | A flexible printed circuit board having flip chip bonding domain aligned top layer bump and inner layer trace | |
| JP2011035242A (en) | Multilayer printed board | |
| KR20230117038A (en) | Surface finish structure of multi-layer substrate |