JP2009098694A - In-plane switching mode liquid crystal display and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an in-plane switching mode liquid crystal display and its manufacturing method, capable of improving an aperture ratio and preventing gate lines and common lines from being short-circuited upon fabricating data wiring lines. <P>SOLUTION: The liquid crystal display includes: gate lines arranged in a first direction on an array substrate; data lines arranged in a second direction perpendicular to the first direction, the data lines and the gate lines defining pixel regions; one or more storage electrodes provided on the array substrate; common electrodes extending across each pixel region; pixel electrodes arranged parallel to the common electrodes and alternately arranged with the common electrodes to generate an in-plane field in each pixel region; thin film transistors provided at intersection areas of the gate lines and data lines and each including a source electrode connected to the corresponding data line, a drain electrode connected to the corresponding pixel electrode, and a gate electrode; and at least one common line located under the common electrode in the pixel region, the common line being substantially parallel to the data lines. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an in-plane switching (IPS) type liquid crystal display device and a manufacturing method thereof, and more particularly to a horizontal electric field mode liquid crystal display device with improved aperture ratio and yield and a manufacturing method thereof.

  Recently, interest in information displays has increased, and demands for using portable information media have increased. Research on lightweight, thin flat panel displays (FPDs) that replace CRTs, which are conventional display devices. And commercialization is focused on. In particular, among such flat panel displays, a liquid crystal display (LCD) is a device that expresses an image using the optical anisotropy of liquid crystal, and is excellent in resolution, color display, image quality, and the like. It is often applied to notebooks and desktop monitors.

  The liquid crystal display device includes a color filter substrate as a first substrate, an array substrate as a second substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate. Here, the color filter substrate separates a color filter composed of a plurality of sub-color filters that realize red (R), green (G), and blue (B) colors, and the sub-color filter, It consists of a black matrix that blocks light transmitted through the liquid crystal layer and a transparent common electrode that applies a voltage to the liquid crystal layer.

  The array substrate includes a plurality of gate lines and data lines that are arranged vertically and horizontally to define a plurality of pixel regions, a thin film transistor (TFT) that is a switching element formed in an intersection region of the gate lines and the data lines, and The pixel electrode is formed on the pixel region.

  The color filter substrate and the array substrate thus configured are bonded to each other by a sealant formed on the outer periphery of the image display area to constitute a liquid crystal display panel, and the color filter substrate and the array substrate The bonding is performed by a bonding key formed on the color filter substrate or the array substrate.

  Here, the liquid crystal display device described above is a TN (Twisted Nematic) liquid crystal display device that drives nematic liquid crystal molecules in a direction perpendicular to the substrate, and the TN liquid crystal display device has a viewing angle. It has the disadvantage of being narrow at about 90 degrees. This is due to the refractive index anisotropy of the liquid crystal molecules, and the liquid crystal molecules aligned horizontally with respect to the substrate are substantially perpendicular to the substrate when a voltage is applied to the liquid crystal display panel. This is because it is oriented.

  On the other hand, the lateral electric field type liquid crystal display device has a viewing angle improved to 170 degrees or more by driving liquid crystal molecules in a horizontal direction with respect to the substrate. Hereinafter, the horizontal electric field type liquid crystal display device will be described in detail with reference to the drawings.

  FIG. 8 is a plan view showing a part of an array substrate of a general horizontal electric field type liquid crystal display device (see, for example, Patent Document 1). In an actual liquid crystal display device, N gate lines and M pieces of gate electrodes are used. Although the data lines intersect and there are M × N pixels, only one pixel is shown for convenience of explanation.

  FIG. 9 is a cross-sectional view taken along line I-I ′ of the array substrate shown in FIG. 8, and also shows the array substrate shown in FIG. 8 and a color filter substrate bonded to the array substrate.

  As shown in FIGS. 8 and 9, the transparent array substrate 10 is formed with gate lines 16 and data lines 17 which are arranged vertically and horizontally on the array substrate 10 to define pixel regions. A thin film transistor T, which is a switching element, is formed in the intersection region of the lines 17.

  Here, the thin film transistor T includes a gate electrode 21 connected to the gate line 16, a source electrode 22 connected to the data line 17, and a drain electrode 23 connected to the pixel electrode 18 through the pixel electrode line 18l. Composed. Further, the thin film transistor T includes a first insulating film 15 a for insulating the gate electrode 21 from the source electrode 22 and the drain electrode 23, and a gate voltage supplied to the gate electrode 21 between the source electrode 22 and the drain electrode 23. And an active pattern 24 that forms a conductive channel.

  Reference numeral 25 denotes an ohmic contact layer that makes ohmic contact between the source / drain regions of the active pattern 24 and the source / drain electrodes 22, 23.

  Here, in the pixel region, a common line 8 l and a storage electrode 18 s are arranged in a direction parallel to the gate line 16, and a plurality of common electrodes 8 and pixels that generate a lateral electric field 90 and switch the liquid crystal molecules 30. The electrodes 18 are arranged in substantially the same direction as the data lines 17.

  The plurality of common electrodes 8 are formed of the same conductive material as the gate line 16 and connected to the common line 8l. The plurality of pixel electrodes 18 are formed of the same conductive material as the data line 17 and are connected to the pixel electrode line 18l. Connected to the storage electrode 18s.

  Here, the pixel electrode 18 connected to the pixel electrode line 18l is electrically connected to the drain electrode 23 of the thin film transistor T via the pixel electrode line 18l.

  Further, the storage electrode 18s overlaps with a part of the common line 8l below the first insulating film 15a to form a storage capacitor Cst.

  The transparent color filter substrate 5 includes a black matrix 6 for preventing light from leaking into the thin film transistor T, the gate line 16 and the data line 17, and a color filter 7 for realizing red, green and blue colors. And are formed.

  An alignment film (not shown) for determining the initial alignment direction of the liquid crystal molecules 30 is applied to the opposing surfaces of the array substrate 10 and the color filter substrate 5 thus configured.

  In the general horizontal electric field type liquid crystal display device having the above-described structure, the common electrode 8 and the pixel electrode 18 are disposed on the same array substrate 10 to generate a horizontal electric field, so that the viewing angle is improved. Have advantages.

Korean Published Patent No. 10-2007-0119260

  However, the horizontal electric field type liquid crystal display device includes a common electrode formed of an opaque conductive material in order to form a storage capacitor in which a plurality of common electrodes and pixel electrodes formed of an opaque conductive material are arranged in a pixel region. Since the lines are arranged, there is a problem that the aperture ratio of the pixel region is lowered.

  In addition, since the common line is formed near the gate line in the same layer as the gate line, there is a problem that the common line is short-circuited with the gate line.

  It is an object of the present invention to form a plurality of common electrodes and pixel electrodes with a transparent conductive material, and to form a common line in a direction substantially parallel to a data line, thereby improving an aperture ratio and a lateral electric field method. An object of the present invention is to provide a liquid crystal display device and a manufacturing method thereof.

  Another object of the present invention is to form a common line in a data line direction shorter than the entire gate line, thereby reducing the overall resistance of the common line and stabilizing the common voltage, and a lateral electric field liquid crystal display device thereof It is to provide a manufacturing method.

  Still another object of the present invention is to provide a horizontal electric field type liquid crystal display capable of preventing a short circuit between the gate line and the common line by arranging the common line in a direction across the gate line with an insulating film interposed therebetween. It is to provide an apparatus and a manufacturing method thereof.

  In order to achieve the above object, a horizontal electric field type liquid crystal display device according to the present invention includes gate lines arranged in a first direction on an array substrate, and a second direction substantially perpendicular to the first direction. A data line defining a pixel region on the array substrate together with the gate line, one or more storage electrodes provided on the array substrate, and a common electrode extending across the respective pixel region; A pixel electrode arranged substantially parallel to the common electrode and alternately arranged with the common electrode to generate a lateral electric field in each pixel region; and an intersection region of the gate line and the data line A thin film transistor including a source electrode connected to a corresponding data line, a drain electrode connected to a corresponding pixel electrode, and a gate electrode , Located at the bottom of each of the common electrode in the pixel region, and at least one common line is substantially parallel to the said data lines.

  The method of manufacturing a horizontal electric field type liquid crystal display device according to the present invention includes a gate line arranged in a first direction on an array substrate and a second direction substantially perpendicular to the first direction. Forming a data line defining a pixel region together with the gate line; forming a storage electrode on the array substrate; forming a common electrode extending across the respective pixel region; and the common electrode Forming pixel electrodes arranged in parallel with each other and alternately arranged with the common electrodes to generate a lateral electric field in the respective pixel regions, and intersecting the gate lines and the data lines A thin film transistor including a source electrode provided in a region and connected to a corresponding data line, a drain electrode connected to a corresponding pixel electrode, and a gate electrode. Forming a star; and forming at least one common line in the pixel region below one of the common electrodes and substantially parallel to the data line. Including.

  According to another aspect of the present invention, there is provided a method of manufacturing a horizontal electric field type liquid crystal display device, comprising: forming a gate electrode, a gate line, and a storage electrode on a first substrate; and forming the gate electrode, the gate line, and the storage electrode. Forming a first insulating film on the formed first substrate; forming an active pattern on the first insulating film; and forming a source electrode and a drain electrode on the first substrate on which the active pattern is formed. Forming a data line defining a pixel region intersecting with the gate line; and forming the data line in a pixel region of the first substrate on which the active pattern is formed, and being substantially parallel to the data line. Forming at least one common line in a direction, and on the first substrate on which the source electrode, the drain electrode, the data line, and the common line are formed. And forming a plurality of common electrodes and pixel electrodes that are alternately disposed on the second insulating film in the pixel region and generate a lateral electric field, wherein at least one common electrode is the common line. Forming a common electrode and a pixel electrode so as to be positioned on the top of the substrate.

  Hereinafter, preferred embodiments of a horizontal electric field mode liquid crystal display device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a plan view schematically showing a part of an array substrate of a horizontal electric field mode liquid crystal display device according to a first embodiment of the present invention. Here, in the actual array substrate, N gate lines and M data lines intersect to have M × N pixels, but only one pixel is shown for convenience of explanation.

  As shown in FIG. 1, when the common electrode and the pixel electrode have a bent structure, liquid crystal molecules are arranged in two directions to form two domains, so that the viewing angle is further improved as compared with the mono domain. However, the present invention is not limited to the two-domain lateral electric field mode liquid crystal display device, and can be applied to a multi-domain lateral electric field mode liquid crystal display device having two or more domains. Thus, an IPS structure that forms a multi-domain of two or more domains is referred to as S-IPS (Super-IPS).

  As shown in FIG. 1, the array substrate 110 according to the first embodiment is formed with gate lines 116 and data lines 117 that are arranged vertically and horizontally on the array substrate 110 to define a pixel region. A thin film transistor, which is a switching element, is formed in the intersection region between the data line 117 and the data line 117.

  The thin film transistor includes a gate electrode 121 constituting a part of the gate line 116, a “U” -shaped source electrode 122 connected to the data line 117, and a drain electrode 123 connected to the pixel electrode 118. The The thin film transistor includes a first insulating film (not shown) for insulating the gate electrode 121 from the source electrode 122 and the drain electrode 123, and a gate voltage supplied to the gate electrode 121, and the source electrode 122 and the drain electrode 123. And an active pattern (not shown) that forms a conduction channel therebetween. Here, since the shape of the source electrode 122 is “U” shape in the drawing, the thin film transistor whose channel shape is “U” shape is shown; however, the present invention is not limited to this. The present invention can be applied regardless of the channel shape of the thin film transistor.

  In the pixel region, common electrodes 108, 108a, 108a ′ and a pixel electrode 118 for generating a horizontal electric field are alternately formed, and the common electrodes 108, 108a, 108a ′ are formed at the edge of the pixel region. The formed pair of outermost common electrodes 108a and 108a ′ are overlapped with the pair of storage electrodes 118a and 118a ′ below the first insulating film and the second insulating film (not shown), respectively. A storage capacitor Cst1 and a second storage capacitor Cst2 are configured. Here, the common electrodes 108, 108 a, 108 a ′ and the pixel electrode 118 are arranged in a direction substantially parallel to the data line 117.

  The first storage capacitor Cst1 and the second storage capacitor Cst2 serve to maintain the voltage applied to the liquid crystal capacitor constant until the next signal is input. The first storage capacitor Cst1 and the second storage capacitor Cst2 serve not only for maintaining the signal but also for stabilizing gray scale display, flicker, and reducing afterimage.

  Here, in the horizontal electric field type liquid crystal display device of the first embodiment, the outermost common electrodes 108a and 108a ′ and the storage electrodes 118a and 118a ′ are formed on the left and right edges of the pixel region, respectively, and the first storage capacitor Cst1. The second storage capacitor Cst2 is described as an example. However, the present invention is not limited to this, and a storage electrode is formed only at one side edge of the pixel region, and one storage capacitor is formed. It can also be configured.

  Further, one end of the common electrodes 108, 108a, 108a ′ is arranged in a direction substantially parallel to the gate line 116, and connects to one side of the common electrodes 108, 108a, 108a ′. Is formed. In addition, one end of the pixel electrode 118 is connected to one side of the pixel electrode 118, and drains are provided through a first contact hole 140a and a pair of second contact holes 140b and 140b ′ formed in the second insulating film. A second connection line 118L that is electrically connected to the electrode 123 and the pair of storage electrodes 118a and 118a ′ is formed.

  A common line 108l according to the first embodiment of the present invention is formed below the arbitrary common electrode 108 in the pixel region in a direction substantially parallel to the data line 117. The line 108l is formed of the same conductive material as the data line 117 and in the same layer as the data line 117.

  The common line 108l is electrically connected to the first connection line 108L through the third contact hole 140c formed in the second insulating film, and is connected to the first connection line 108L and the common electrodes 108, 108a, and 108a ′. Supply a common voltage.

  Here, a gate pad electrode 126p and a data pad electrode 127p that are electrically connected to the gate line 116 and the data line 117, respectively, are formed in the edge region of the array substrate 110, and the gate pad electrode 126p and the data pad electrode 127p are formed. Transmits a scanning signal and a data signal applied from an external driving circuit unit to the gate line 116 and the data line 117, respectively.

  That is, the data line 117 and the gate line 116 extend to the driving circuit portion side and are connected to the data pad line 117p and the gate pad line 116p, respectively. The data pad line 117p and the gate pad line 116p are formed in the second insulating film. A data signal and a scan signal are received from the driving circuit unit through the data pad electrode 127p and the gate pad electrode 126p, which are electrically connected through the fourth contact hole 140d and the fifth contact hole 140e, respectively.

  The horizontal electric field mode liquid crystal display device according to the first embodiment of the present invention configured as described above includes the common electrodes 108, 108a, 108a ′, the pixel electrode 118, the first connection line 108L, and the second connection line 118L. Since it is formed of a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), there is an advantage that the aperture ratio is improved.

  Furthermore, since the line width of the common line 108l can be reduced by forming the common line 108l in a direction substantially parallel to the data line 117, the aperture ratio of the pixel region is improved by about 8 to 30%. is there.

  Further, in the entire liquid crystal display panel, by forming the common line 108l in the direction of the data line 117 having a length of about 0.56 times the total length of the gate line 116, the overall resistance of the common line 108l is reduced. As a result, the common voltage is stabilized, and image quality degradation problems such as ripple and flicker can be prevented. In a common horizontal electric field type liquid crystal display device, since the common line is formed in the horizontal direction with respect to the liquid crystal display panel, that is, in the direction substantially parallel to the gate line, the common line is increased due to an increase in RC delay. The voltage fluctuation becomes a difference of about 200 mV between the both ends of the liquid crystal display panel, and ripple and flicker phenomenon occur.

  In the horizontal electric field mode liquid crystal display according to the first embodiment of the present invention, the common line 108l is not formed near the gate line 116 in the same layer as the gate line 116, but is formed in the same layer as the data line 117. By forming the common line 108l across the gate line 116 with one insulating film interposed, it is possible to prevent a short circuit between the gate line 116 and the common line 108l, and the yield is improved.

  Here, the horizontal electric field type liquid crystal display device according to the first embodiment of the present invention uses a halftone mask or a diffraction mask (hereinafter referred to as a halftone mask to include a diffraction mask) to perform a single mask. In the process, the array substrate can be manufactured in a total of four mask processes by simultaneously forming the data lines including the source electrode, the drain electrode, the data line, the data pad line, the common line, and the active pattern. This will be described in detail with reference to the following method for manufacturing a horizontal electric field type liquid crystal display device. However, the present invention is not limited to the number of mask processes described above.

  2A to 2D are cross-sectional views taken along lines IIIa-IIIa′-IIIa ″, IIIb-IIIb, and IIIc-IIIc of the array substrate shown in FIG. Shows the process of manufacturing the array substrate of the pixel part including the data line region, and the right side shows the process of manufacturing the array substrate of the data pad part and the gate pad part in order.

  3A to 3D are plan views sequentially showing manufacturing steps of the array substrate shown in FIG. As shown in FIGS. 2A and 3A, a gate electrode 121, a gate line 116, a first storage electrode 118a, a second storage electrode 118a ′, and a pixel portion of an array substrate 110 formed of a transparent insulating material such as glass. The gate pad line 116p is formed. Here, the first storage electrode 118a and the second storage electrode 118a ′ have a bent structure, are formed at the left and right edges of the pixel region, and are arranged in a direction substantially intersecting the gate line 116. .

  The gate electrode 121, the gate line 116, the first storage electrode 118a, the second storage electrode 118a ′, and the gate pad line 116p are formed by depositing a first conductive film on the entire surface of the array substrate 110 and then performing a photolithography process (first mask). And selectively patterning in step). Here, the first conductive film is made of a low-resistance opaque conductive material such as aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), and molybdenum alloy. Can be used. The first conductive film may be formed in a multilayer structure in which two or more low-resistance opaque conductive materials are stacked.

Next, as shown in FIGS. 2B and 3B, the first electrode is formed on the entire surface of the array substrate 110 on which the gate electrode 121, the gate line 116, the first storage electrode 118a, the second storage electrode 118a ′, and the gate pad line 116p are formed. After forming the 1 insulating film 115a, the amorphous silicon thin film, the n ⁺ amorphous silicon thin film, and the second conductive film, the array substrate 110 is selectively removed by a photolithography process (second mask process). The active pattern 124 formed of the amorphous silicon thin film is formed on the pixel portion of the pixel region, and at the same time, the source / drain electrode 122 formed of the second conductive film and electrically connected to the source / drain region of the active pattern 124. , 123 are formed.

In the second mask process, the data line 117 formed of the second conductive film is formed in the data line region of the array substrate 110, and the data pad portion of the array substrate 110 is formed of the second conductive film. The data pad line 117p thus formed is formed. In the second mask process, a common line 108l formed of the second conductive film is formed in the pixel region, and the common line 108l is formed in a direction substantially parallel to the data line 117.
Here, an ohmic contact layer 125 n formed of the n ⁺ amorphous silicon thin film and patterned in the same shape as the source / drain electrodes 122 and 123 is formed on the active pattern 124.

The common line 108l, the data line 117, and the data pad line 117p are formed of the amorphous silicon thin film and the n ⁺ amorphous silicon thin film, respectively. The first amorphous silicon thin film pattern 124 ′ and the second n ⁺ amorphous silicon thin film pattern 125 ″, the second amorphous silicon thin film pattern 124 ″ and the third n ⁺ non-patterned to the same shape as the line 117p. A crystalline silicon thin film pattern 125 ′ ″, a third amorphous silicon thin film pattern 124 ′ ″, and a fourth n ⁺ amorphous silicon thin film pattern 125 ″ ″ are formed.

Here, the active pattern 124, the source / drain electrodes 122 and 123, the data line 117, the data pad line 117p, and the common line 108l according to the first embodiment of the present invention are formed once using a halftone mask. Simultaneously formed in the mask process (second mask process). Hereinafter, the second mask process will be described in detail with reference to the drawings.
4A to 4F are cross-sectional views specifically showing a second mask process according to the first embodiment of the present invention in the array substrate shown in FIGS. 2B and 3B.

As shown in FIG. 4A, a gate insulating film 115a is formed on the entire surface of the array substrate 110 on which the gate electrode 121, the gate line 116, the first storage electrode 118a, the second storage electrode 118a ′, and the gate pad line 116p are formed. A crystalline silicon thin film 120, an n ⁺ amorphous silicon thin film 125, and a second conductive film 130 are formed. Here, the second conductive layer 130 may be formed of aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, molybdenum alloy, or the like to form a source electrode, a drain electrode, a data line, a data pad line, and a common line. It is formed of a low resistance opaque conductive material.

  Also, as shown in FIG. 4B, a photosensitive film 170 made of a photosensitive material such as a photoresist is formed on the entire surface of the array substrate 110, and then exposed using the halftone mask 180 according to the embodiment of the present invention. The film 170 is selectively irradiated with light. Here, the halftone mask 180 includes a first transmission region I that transmits all of the irradiated light, a second transmission region II that transmits a part of the light and blocks a part of the light, and all the irradiated light. A light blocking region III for blocking the light is provided, and only the light transmitted through the halftone mask 180 is irradiated onto the photosensitive film 170.

  Next, when the photosensitive film 170 exposed by the halftone mask 180 is developed, as shown in FIG. 4C, all light or part of the light is blocked by the blocking region III and the second transmission region II. The first photosensitive film pattern 170a to the sixth photosensitive film pattern 170f having a predetermined thickness remain, and the photosensitive film 170 is completely removed in the first transmission region I where all the light is transmitted. The surface is exposed.

  Here, the first photosensitive film pattern 170a to the fifth photosensitive film pattern 170e formed in the blocking region III are formed thicker than the sixth photosensitive film pattern 170f formed in the second transmission region II. Further, since the positive type photoresist is used in the region where all the light is transmitted through the first transmission region I, the photosensitive film is completely removed. However, the present invention is not limited to this. Alternatively, a negative type photoresist may be used.

Next, as shown in FIG. 4D, the first photosensitive film pattern 170a to the sixth photosensitive film pattern 170f formed as described above are used as a mask, and an amorphous silicon thin film formed below the n ⁺ When the crystalline silicon thin film and the second conductive film are selectively removed, an active pattern 124 formed of the amorphous silicon thin film is formed in the pixel portion of the array substrate 110, and the data line region of the array substrate 110 is formed in the data line region. A data line 117 formed of the second conductive film is formed.

  A data pad line 117p formed of the second conductive film is formed in the data pad portion of the array substrate 110, and a common line formed of the second conductive film is formed in the pixel region of the array substrate 110. 108l is formed.

  Here, the first embodiment of the present invention has described an example in which one common line 108l is formed in a pixel region, but the present invention is not limited to this, and two or more lines are formed. The present invention can also be applied to forming the common line 108l.

Also, a first n ⁺ amorphous silicon thin film pattern 125 ′ is formed on the active pattern 124 by the n ⁺ amorphous silicon thin film and the second conductive film, respectively, and is patterned in the same shape as the active pattern 124. As a result, a second conductive pattern 130 ′ is formed.

The common line 108l, the data line 117, and the data pad line 117p are formed of the amorphous silicon thin film and the n ⁺ amorphous silicon thin film, respectively. The first amorphous silicon thin film pattern 124 ′ and the second n ⁺ amorphous silicon thin film pattern 125 ″, the second amorphous silicon thin film pattern 124 ″ and the third n ⁺ non-patterned to the same shape as the line 117p. A crystalline silicon thin film pattern 125 ′ ″, a third amorphous silicon thin film pattern 124 ′ ″, and a fourth n ⁺ amorphous silicon thin film pattern 125 ″ ″ are formed.

  Thereafter, when an ashing process for removing a part of the first photosensitive film pattern 170a to the sixth photosensitive film pattern 170f is performed, the sixth photosensitive film pattern in the second transmission region II is completely removed as shown in FIG. 4E. The

  Here, the first photosensitive film pattern to the fifth photosensitive film pattern are the seventh photosensitive film pattern 170a ′ to the eleventh photosensitive film pattern 170e ′, which are removed by the thickness of the sixth photosensitive film pattern, and the blocking region III. Are left only on the source electrode region, drain electrode region, common line 108l, data line 117, and data pad line 117p.

Thereafter, as shown in FIG. 4F, one of the first n ⁺ amorphous silicon thin film pattern and the second conductive film pattern is formed using the remaining seventh photosensitive film pattern 170a ′ to eleventh photosensitive film pattern 170e ′ as a mask. By removing the portion, the source electrode 122 and the drain electrode 123 formed of the second conductive film are formed on the pixel portion of the array substrate 110.

Here, an ohmic contact layer 125 n formed of the n ⁺ amorphous silicon thin film and making ohmic contact between the source / drain regions of the active pattern 124 and the source / drain electrodes 122 and 123 is formed on the active pattern 124. It is formed.

  As described above, in the first embodiment of the present invention, the active pattern 124, the source / drain electrodes 122 and 123, the data line 117, the data pad line 117p, and the common line 108l are formed by using the halftone mask. It can be formed by a single mask process.

  Thereafter, as shown in FIGS. 2C and 3C, the second insulation is formed on the entire surface of the array substrate 110 on which the active pattern 124, the source / drain electrodes 122 and 123, the data line 117, the data pad line 117p, and the common line 108l are formed. A film 115b is formed.

  Next, a first contact hole 140a exposing a part of the drain electrode 123 by selectively removing a part of the second insulating film 115b in a photolithography process (third mask process), and the first A pair of second contact holes 140b and 140b ′ exposing a part of the storage electrode 118a and the second storage electrode 118a ′ are formed.

  Further, a third contact that exposes a part of the common line 108l, the data pad line 117p, and the gate pad line 116p by selectively removing a part of the second insulating film 115b in the third mask process. A hole 140c, a fourth contact hole 140d, and a fifth contact hole 140e are formed.

  Next, as shown in FIGS. 2D and 3D, a third conductive film made of a transparent conductive material is formed on the entire surface of the array substrate 110 where the first contact hole 140a to the fifth contact hole 140e are formed. Then, by selectively removing the third conductive film in the photolithography process (fourth mask process), it is electrically connected to the drain electrode 123 through the first contact hole 140a, and at the same time, a pair of second films A second connection line 118L electrically connected to the first storage electrode 118a and the second storage electrode 118a ′ through the contact holes 140b and 140b ′ is formed.

  In addition, by selectively removing the third conductive film in the fourth mask step, a plurality of common electrodes 108, 108a, 108a ′ and pixel electrodes which are alternately arranged in the pixel region and generate a lateral electric field. 118, and a data pad electrode 127p and a gate pad electrode 126p that are electrically connected to the data pad line 117p and the gate pad line 116p through the fourth contact hole 140d and the fifth contact hole 140e, respectively.

  Here, the first outermost common electrode 108a and the second outermost common electrode 108a ′ formed at the edge of the pixel region among the common electrodes 108, 108a, and 108a ′ are the first insulating film 115a and the second insulating film. A first storage capacitor Cst1 and a second storage capacitor Cst2 are formed by overlapping with the first storage electrode 118a and the second storage electrode 118a ′ below them via 115b, respectively.

  In the fourth mask process, one end of the common electrodes 108, 108a, 108a ′ is arranged in a direction substantially parallel to the gate line 116, and one side of the common electrodes 108, 108a, 108a ′ is connected. A first connection line 108L is formed.

  Further, the common line 108l according to the first embodiment of the present invention is formed below the arbitrary common electrode 108 in the pixel region in a direction substantially parallel to the data line 117. The common line 108l The first connection line 108L is electrically connected through the third contact hole 140c formed in the second insulating film 115b to supply a common voltage to the first connection line 108L and the common electrodes 108, 108a, 108a ′. .

  The third conductive film may be formed of indium tin oxide or indium zinc oxide to form the common electrodes 108, 108a, 108a ′, the first connection line 108L, the second connection line 118L, and the pixel electrode 118. It contains a transparent conductive material with excellent transmittance.

  As described above, in the horizontal electric field mode liquid crystal display device according to the first embodiment of the present invention, the common electrodes 108, 108a, 108a ′, the pixel electrode 118, the first connection line 108L, and the second connection line 118L are transparent. By forming the common line 108l in a direction substantially parallel to the data line 117, the line width of the common line 108l can be reduced and the aperture ratio of the pixel region is improved by about 8 to 30%. The effect is obtained. Further, by forming the common line 108l side by side with the common electrode 108 below the common electrode 108, the opening area can be expanded to the maximum.

  Further, as described above, in the entire liquid crystal display panel, the common line 108l is formed in the direction of the data line 117 having a length of about 0.56 times the total length of the gate line 116, whereby the entire common line 108l is formed. Resistance decreases. As a result, the common voltage is stabilized, and image quality degradation problems such as ripple and flicker can be prevented.

  Further, the horizontal electric field type liquid crystal display device according to the first embodiment of the present invention is common to the gate line 116 by forming the common line 108l in a direction crossing the gate line 116 with the first insulating film interposed. The yield can be improved because the short circuit of the line 108l can be prevented.

  In the horizontal electric field mode liquid crystal display device according to the first embodiment of the present invention configured as described above, the common electrodes 108, 108a, 108a ′, the pixel electrode 118, and the data line 117 are formed in a bent structure, and the liquid crystal is displayed. By forming a multi-domain structure in which the driving directions of the molecules are symmetric, the extraordinary light due to the birefringence characteristics of the liquid crystal cancel each other and the color shift phenomenon can be minimized. That is, due to the birefringence characteristics of the liquid crystal molecules, a color shift occurs depending on the viewing angle at which the liquid crystal molecules are viewed. In particular, a yellow shift is observed in the minor axis direction of the liquid crystal molecules, and a blue shift is observed in the major axis direction. A blue shift is observed. Therefore, when the minor axis and the major axis of the liquid crystal molecules are appropriately arranged, the color shift can be reduced by compensating the birefringence value.

  For example, in the case of two domains in which the liquid crystal molecules have a symmetrical arrangement, as shown in FIG. 5, the birefringence value of a1 of the first liquid crystal molecule 190a is the first having the molecular arrangement in the opposite direction of the first liquid crystal molecule 190a. The two liquid crystal molecules 190b are compensated by the birefringence value of a2, and as a result, the birefringence value becomes approximately zero. The birefringence value of c1 is compensated by c2. Therefore, by minimizing the color shift phenomenon due to the birefringence characteristics of the liquid crystal molecules, it is possible to prevent image quality deterioration due to viewing angle.

  Here, the horizontal electric field mode liquid crystal display device according to the first embodiment of the present invention has been described with respect to an example in which one common line is formed in the pixel region. However, the present invention is not limited to this. Absent. That is, two or more common lines may be designed depending on the resistance of the common line.

  Hereinafter, a horizontal electric field mode liquid crystal display device according to a second embodiment of the present invention in which two common lines are formed will be described in detail with reference to FIG.

  FIG. 6 is a plan view schematically showing a part of the array substrate of the horizontal electric field type liquid crystal display device according to the second embodiment of the present invention, except that there are two common lines. It has the same components as the array substrate of the horizontal electric field type liquid crystal display device of one embodiment.

  As shown in FIG. 6, the array substrate 210 according to the second embodiment includes a gate line 216 and a data line 217 that are arranged vertically and horizontally on the array substrate 210 to define a pixel region. A thin film transistor, which is a switching element, is formed in the intersection region of the data lines 217.

  The thin film transistor includes a gate electrode 221 that forms part of the gate line 216, a source electrode 222 connected to the data line 217, and a drain electrode 223 connected to the pixel electrode 218. Further, the thin film transistor includes a first insulating film (not shown) for insulating the gate electrode 221 and the source / drain electrodes 222 and 223, and the source electrode 222 and the drain according to the gate voltage supplied to the gate electrode 221. And an active pattern (not shown) for forming a conduction channel between the electrodes 223.

  Further, common electrodes 208, 208a, 208a ′ for generating a lateral electric field and pixel electrodes 218 are alternately formed in the pixel region, and the common electrodes 208, 208a, 208a ′ are formed at the edge of the pixel region. The pair of outermost common electrodes 208a and 208a ′ thus formed overlaps with the pair of storage electrodes 218a and 218a ′ below the first insulating film and the second insulating film (not shown), respectively. A storage capacitor Cst1 and a second storage capacitor Cst2 are configured. Here, the common electrodes 208, 208 a, 208 a ′ and the pixel electrode 218 are arranged in a direction substantially parallel to the data line 217.

  In addition, one end of the common electrodes 208, 208a, 208a ′ is arranged in a direction substantially parallel to the gate line 216, and connects to one side of the common electrodes 208, 208a, 208a ′. Is formed.

  In addition, one end of the pixel electrode 218 is connected to one side of the pixel electrode 218 via a first contact hole 240a and a pair of second contact holes 240b and 240b ′ formed in the second insulating film. A second connection line 218L that is electrically connected to the drain electrode 223 and the pair of storage electrodes 218a and 218a ′ is formed.

  In addition, below the arbitrary common electrode 208 in the pixel region, the first common line 2081 and the second common line 2081 of the second embodiment of the present invention are arranged in a direction substantially parallel to the data line 217. Here, the first common line 208l and the second common line 208l ′ are formed of the same conductive material as the data line 217 and in the same layer as the data line 217.

  The first common line 208l and the second common line 208l ′ are electrically connected to the first connection line 208L through a pair of third contact holes 240c and 240c ′ formed in the second insulating film. A common voltage is supplied to the one connection line 208L and the common electrodes 208, 208a, 208a ′.

  Here, in the edge region of the array substrate 210, a gate pad electrode 226p and a data pad electrode 227p that are electrically connected to the gate line 216 and the data line 217, respectively, are formed and applied from an external driving circuit unit. The scanning signal and the data signal are transmitted to the gate line 216 and the data line 217, respectively.

  That is, the data line 217 and the gate line 216 extend to the driving circuit portion side and are respectively connected to the data pad line 217p and the gate pad line 216p. The data pad line 217p and the gate pad line 216p are formed on the second insulating film. A data signal and a scanning signal are received from the driving circuit unit through the data pad electrode 227p and the gate pad electrode 226p, which are electrically connected through the formed fourth contact hole 240d and the fifth contact hole 240e, respectively.

  In addition, as described above, the horizontal electric field type liquid crystal display device according to the first embodiment and the second embodiment includes the first outermost common electrode, the second outermost common electrode, and the second outermost common electrode at the left and right edges of the pixel region. Although an example in which the first storage electrode and the second storage electrode are formed to form the first storage capacitor and the second storage capacitor has been described, the present invention is not limited to this, and one side of the pixel region The present invention can also be applied to a case where a storage electrode is formed only at the edge portion to constitute one storage capacitor.

  FIG. 7 is a plan view schematically showing a part of an array substrate of a horizontal electric field mode liquid crystal display device according to a third embodiment of the present invention, in which a storage electrode is formed only at one side edge of a pixel region. Except that one storage capacitor is configured, it has the same components as the array substrate of the horizontal electric field mode liquid crystal display device of the first embodiment.

  As shown in FIG. 7, on the array substrate 310 of the third embodiment, a gate line 316 and a data line 317 are formed on the array substrate 310 so as to be arranged vertically and horizontally to define a pixel region. A thin film transistor, which is a switching element, is formed in the intersection region of the data line 317.

  The thin film transistor includes a gate electrode 321 constituting a part of the gate line 316, a source electrode 322 connected to the data line 317, and a drain electrode 323 connected to the pixel electrode 318. Further, the thin film transistor includes a first insulating film (not shown) for insulating the gate electrode 321 and the source / drain electrodes 322 and 323, and a source electrode 322 and a drain electrode 323 according to a gate voltage supplied to the gate electrode 321. And an active pattern (not shown) that forms a conduction channel therebetween.

  Further, common electrodes 308, 308a, 308a ′ for generating a lateral electric field and pixel electrodes 318 are alternately formed in the pixel region, and the common electrode 308, 308a, 308a ′ is formed at the left edge of the pixel region. The formed outermost common electrode 308a overlaps with the storage electrode 318a below the first insulating film and the second insulating film (not shown) to form a storage capacitor Cst.

  As described above, the horizontal electric field mode liquid crystal display device according to the third embodiment of the present invention further improves the aperture ratio of the pixel region by forming the storage electrode 318a only on one side edge of the pixel region. be able to.

  Here, a first connection line is disposed at one end of the common electrodes 308, 308a, 308a ′ in a direction substantially parallel to the gate line 316 and connects one side of the common electrodes 308, 308a, 308a ′. 308L is formed.

  In addition, one end of the pixel electrode 318 is connected to one side of the pixel electrode 318, and the drain electrode 323 and the second contact hole 340b are formed in the second insulating film through the first contact hole 340a and the second contact hole 340b, respectively. A second connection line 318L that is electrically connected to the storage electrode 318a is formed.

  In addition, a common line 308l according to the third embodiment of the present invention is formed below the arbitrary common electrode 308 in the pixel region in a direction substantially parallel to the data line 317. The line 308l is electrically connected to the first connection line 308L through the third contact hole 340c formed in the second insulating film, and a common voltage is applied to the first connection line 308L and the common electrodes 308, 308a, 308a ′. Supply.

  Here, in the edge region of the array substrate 310, a gate pad electrode 326p and a data pad electrode 327p that are electrically connected to the gate line 316 and the data line 317, respectively, are formed and applied from an external driving circuit unit. The scanning signal and the data signal are transmitted to the gate line 316 and the data line 317, respectively.

  That is, the data line 317 and the gate line 316 extend to the driving circuit portion side and are respectively connected to the data pad line 317p and the gate pad line 316p. The data pad line 317p and the gate pad line 316p are formed on the second insulating film. A data signal and a scanning signal are received from the driving circuit unit through the data pad electrode 327p and the gate pad electrode 326p that are electrically connected through the formed fourth contact hole 340d and the fifth contact hole 340e, respectively.

  The array substrates of the first to third embodiments configured as described above are bonded to a color filter substrate (not shown) by a sealant formed on the outer periphery of the image display area. Here, a black matrix for preventing light from leaking into the thin film transistor, the gate line, and the data line, and a color filter for realizing red, green, and blue colors are formed on the color filter substrate. Is done. Here, the color filter substrate and the array substrate are bonded together by a bonding key formed on the color filter substrate or the array substrate.

  The present invention is applied not only to a liquid crystal display device but also to other display devices manufactured using thin film transistors, such as an organic light emitting display device in which an organic light emitting diode (OLED) is connected to a driving transistor. Available.

  The present invention can be realized in various forms and should not be limited by the above-described embodiments, but rather should be construed as preferred embodiments, and can be made within the scope of the claims of the present invention. Modifications and variations, and equivalents of the claims are included in the scope of the claims.

1 is a plan view schematically showing a part of an array substrate of a horizontal electric field mode liquid crystal display device according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view taken along line IIIa-IIIa′-IIIa ″, line IIIb-IIIb, and line IIIc-IIIc of the array substrate shown in FIG. FIG. 3 is a cross-sectional view taken along line IIIa-IIIa′-IIIa ″, line IIIb-IIIb, and line IIIc-IIIc of the array substrate shown in FIG. FIG. 3 is a cross-sectional view taken along line IIIa-IIIa′-IIIa ″, line IIIb-IIIb, and line IIIc-IIIc of the array substrate shown in FIG. FIG. 3 is a cross-sectional view taken along line IIIa-IIIa′-IIIa ″, line IIIb-IIIb, and line IIIc-IIIc of the array substrate shown in FIG. FIG. 4B is a cross-sectional view specifically showing a second mask process according to the first embodiment of the present invention in the array substrate shown in FIGS. 2B and 3B. FIG. 4B is a cross-sectional view specifically showing a second mask process according to the first embodiment of the present invention in the array substrate shown in FIGS. 2B and 3B. FIG. 4B is a cross-sectional view specifically showing a second mask process according to the first embodiment of the present invention in the array substrate shown in FIGS. 2B and 3B. FIG. 4B is a cross-sectional view specifically showing a second mask process according to the first embodiment of the present invention in the array substrate shown in FIGS. 2B and 3B. FIG. 4B is a cross-sectional view specifically showing a second mask process according to the first embodiment of the present invention in the array substrate shown in FIGS. 2B and 3B. FIG. 4B is a cross-sectional view specifically showing a second mask process according to the first embodiment of the present invention in the array substrate shown in FIGS. 2B and 3B. FIG. 3 is a plan view sequentially illustrating manufacturing steps of the array substrate shown in FIG. 1. FIG. 3 is a plan view sequentially illustrating manufacturing steps of the array substrate shown in FIG. 1. FIG. 3 is a plan view sequentially illustrating manufacturing steps of the array substrate shown in FIG. 1. FIG. 3 is a plan view sequentially illustrating manufacturing steps of the array substrate shown in FIG. 1. FIG. 3 is a diagram for explaining an outline of a viewing angle compensation principle in a horizontal electric field type liquid crystal display device of the present invention. It is a top view which shows roughly a part of array substrate of the horizontal electric field type liquid crystal display device by the 2nd Embodiment of this invention. It is a top view which shows roughly a part of array substrate of the horizontal electric field type liquid crystal display device by the 3rd Embodiment of this invention. It is a top view which shows roughly a part of array substrate of a general horizontal electric field system liquid crystal display device. It is sectional drawing which shows schematically the structure of a general horizontal electric field system liquid crystal display device.

Claims (24)

Gate lines arranged in a first direction on the array substrate;
A data line arranged in a second direction substantially perpendicular to the first direction and defining a pixel region in the array substrate together with the gate line;
At least one storage electrode provided on the array substrate;
A common electrode extending across the pixel region;
A pixel electrode arranged substantially parallel to the common electrode and alternately arranged with the common electrode to generate a horizontal electric field in the pixel region;
A thin film transistor including a source electrode connected to a corresponding data line, a drain electrode connected to a corresponding pixel electrode, and a gate electrode provided at an intersection region of the gate line and the data line;
A horizontal electric field type liquid crystal display device comprising: at least one common line located under each common electrode in the pixel region and disposed substantially parallel to the data line. The horizontal electric field mode LCD according to claim 1, wherein the common line and the data line are made of the same conductive material, and the common line is provided on a layer in which the data line is formed. apparatus. 2. The common line according to claim 1, wherein the common line crosses the corresponding gate line with an insulating film interposed between the gate line and the common line to prevent a short circuit with the corresponding gate line. The horizontal electric field type liquid crystal display device described.   The length of the common line extending and traversing the entire region of the horizontal electric field mode liquid crystal display device is shorter than the length of at least one gate line extending and traversing the entire region of the lateral electric field mode liquid crystal display device. 2. A horizontal electric field type liquid crystal display device according to 1. The horizontal electric field mode liquid crystal display device according to claim 1, wherein the common electrode and the pixel electrode have at least one bent structure. The horizontal electric field mode liquid crystal display device according to claim 1, further comprising a first connection line connected to the common electrode and substantially parallel to the gate line. The horizontal electric field mode liquid crystal display device according to claim 6, further comprising a second connection line connected to the pixel electrode and electrically connected to the drain electrode and the storage electrode. The horizontal electric field mode liquid crystal display according to claim 7, wherein the second connection line is electrically connected to the drain electrode and the storage electrode through the first contact hole and the second contact hole, respectively. apparatus. 8. The horizontal electric field mode liquid crystal display device according to claim 7, wherein at least one of the common electrode, the pixel electrode, the first connection line, and the second connection line is formed of a transparent conductive material. . The horizontal electric field type liquid crystal display device according to claim 1, wherein the common electrode includes an outermost common electrode provided at an edge of each pixel region. 11. The horizontal electric field type liquid crystal display device according to claim 10, wherein the outermost common electrode forms a storage capacitor by overlapping the storage electrode with a first insulating film and a second insulating film interposed therebetween. The common line is electrically connected to the first connection line through a third contact hole provided in the second insulating film, and supplies a common voltage to the first connection line and the common electrode. A horizontal electric field type liquid crystal display device according to claim 6. The at least one common line includes a first common line and a second common line provided under each common electrode in a corresponding pixel region, and the first common line and the second common line are: 2. The horizontal electric field mode liquid crystal display device according to claim 1, wherein the liquid crystal display device is substantially parallel to the data line. The horizontal electric field mode liquid crystal display according to claim 1, wherein the at least one storage electrode comprises one storage electrode provided at an edge region of the pixel region to form one storage capacitor. apparatus. Forming gate lines arranged in a first direction on the array substrate and data lines defining a pixel region together with the gate lines arranged in a second direction substantially perpendicular to the first direction; When,
Forming a storage electrode on the array substrate;
Forming a common electrode extending across the pixel region;
Forming a pixel electrode arranged substantially parallel to the common electrode and alternately arranged with the common electrode to generate a lateral electric field in the pixel region;
Forming a thin film transistor including a source electrode provided at an intersection region of the gate line and the data line and connected to the corresponding data line, a drain electrode connected to the corresponding pixel electrode, and a gate electrode;
Forming at least one common line in the pixel region below a common electrode of the common electrode and substantially parallel to the data line. Manufacturing method of electric field type liquid crystal display device. The gate line, the storage electrode, and the gate pad line are formed by forming a first conductive film on the array substrate and then selectively patterning the first conductive film in a first photolithography process. The method of manufacturing a horizontal electric field mode liquid crystal display device according to claim 15. The source electrode and the drain electrode, the common line, the data line, and the data pad line are formed on the array substrate on which the gate electrode, the gate line, the storage electrode, and the gate pad line are formed. film, an amorphous silicon thin film, after forming n ⁺ amorphous silicon thin film, and a second conductive film, the amorphous silicon thin film in the second photolithography step, n ⁺ amorphous silicon thin film, and a second The method according to claim 15, wherein the conductive film is formed by selective patterning. A second insulating film is formed on the array substrate on which the active pattern, the source and drain electrodes, the data line, and the data pad line are formed, and then the second insulating film is formed in a third photolithography process. The method may further include forming a plurality of contact holes exposing part of the drain electrode, the storage electrode, the common line, the data pad line, and the gate pad line by selective patterning. A method of manufacturing a horizontal electric field mode liquid crystal display device according to claim 15. The common electrode, the pixel electrode, the first connection line and the second connection line, the data pad electrode, and the gate pad electrode are formed of a second conductive film made of a transparent conductive material. 16. The method of manufacturing a lateral electric field liquid crystal display device according to claim 15, wherein the method is formed on the second insulating film of the array substrate in which one to fifth contact holes are formed. Forming a gate electrode, a gate line, and a storage electrode on the first substrate;
Forming a first insulating layer on the first substrate on which the gate electrode, the gate line, and the storage electrode are formed;
Forming an active pattern on the first insulating layer;
Forming a source electrode and a drain electrode on the first substrate on which the active pattern is formed, and forming a data line defining a pixel region across the gate line;
Forming in the pixel region of the first substrate on which the active pattern is formed, and forming at least one common line in a direction substantially parallel to the data line;
Forming a second insulating layer on the first substrate on which the source electrode, the drain electrode, the data line, and the common line are formed;
When forming a plurality of common electrodes and pixel electrodes that are alternately disposed on the second insulating film in the pixel region to generate a lateral electric field, the common electrode is positioned above the common line. And a step of forming a pixel electrode. A method of manufacturing a horizontal electric field mode liquid crystal display device. Forming a first connection line arranged in a direction substantially parallel to the gate line and connecting one side of the common electrode;
21. The horizontal electric field method according to claim 20, further comprising: forming a second connection line arranged in a direction substantially parallel to the gate line and connecting one side of the pixel electrode. A method for manufacturing a liquid crystal display device. The second connection line is formed to be electrically connected to the drain electrode through a first contact hole and to be electrically connected to the storage electrode through a second contact hole. Item 22. A manufacturing method of a transverse electric field mode liquid crystal display device according to Item 21. The gate electrode, the gate line, and the storage electrode are formed of a first conductive film, and the source electrode, the drain electrode, the data line, and the common line are formed of a second conductive film. 21. A method of manufacturing a horizontal electric field mode liquid crystal display device according to claim 20, The storage electrode is formed at a pixel region edge of the first substrate in a direction substantially parallel to the data line, and a first insulating film and a second insulating film are interposed between the common electrode and the storage electrode. 21. The method of manufacturing a horizontal electric field mode liquid crystal display device according to claim 20, wherein a storage capacitor is formed so as to overlap the common electrode.

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