JP2009070997A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2009070997A JP2009070997A JP2007237077A JP2007237077A JP2009070997A JP 2009070997 A JP2009070997 A JP 2009070997A JP 2007237077 A JP2007237077 A JP 2007237077A JP 2007237077 A JP2007237077 A JP 2007237077A JP 2009070997 A JP2009070997 A JP 2009070997A
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- plating layer
- melting point
- low melting
- external connection
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
【解決手段】外部接続用リード14b上にめっき層16を有する半導体装置において、めっき層16は、低融点めっき層16aと、低融点めっき層16a上に形成された高融点めっき層16bとを有し、高融点めっき層16bは、最高使用温度より固相線温度又は融点の高い金属で形成され、低融点めっき層16aは、最高使用温度より固相線温度又は融点の低い金属で形成される。
【選択図】図1
Description
前記めっき層は、低融点めっき層と、前記低融点めっき層上に形成された高融点めっき層とを有し、
前記高融点めっき層は、最高使用温度より固相線温度又は融点の高い金属で形成され、
前記低融点めっき層は、最高使用温度より固相線温度又は融点の低い金属で形成される。
14a 内部接続用リード
14b 外部接続用リード
16 めっき層
16a 低融点めっき層
16b 高融点めっき層
Claims (2)
- 外部接続用リード上にめっき層を有する半導体装置において、
前記めっき層は、低融点めっき層と、前記低融点めっき層上に形成された高融点めっき層とを有し、
前記高融点めっき層は、最高使用温度より固相線温度又は融点の高い金属で形成され、
前記低融点めっき層は、最高使用温度より固相線温度又は融点の低い金属で形成される半導体装置。 - 前記低融点めっき層は、Bi及びInのうち少なくとも何れか1つの元素を含むSn合金で形成される請求項1記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007237077A JP5493257B2 (ja) | 2007-09-12 | 2007-09-12 | 半導体装置の製造方法 |
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JP2007237077A JP5493257B2 (ja) | 2007-09-12 | 2007-09-12 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009070997A true JP2009070997A (ja) | 2009-04-02 |
JP5493257B2 JP5493257B2 (ja) | 2014-05-14 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP2007237077A Active JP5493257B2 (ja) | 2007-09-12 | 2007-09-12 | 半導体装置の製造方法 |
Country Status (1)
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JP (1) | JP5493257B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010245217A (ja) * | 2009-04-03 | 2010-10-28 | Kenichi Fuse | 半導体icの装填方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62219950A (ja) * | 1986-03-20 | 1987-09-28 | Shinko Electric Ind Co Ltd | リ−ドフレ−ム |
JPH07273263A (ja) * | 1994-03-30 | 1995-10-20 | Sony Corp | 電子部品の外部端子 |
JPH08132277A (ja) * | 1994-11-01 | 1996-05-28 | Ishikawa Kinzoku Kk | 無鉛はんだ |
JPH08206874A (ja) * | 1995-02-06 | 1996-08-13 | Matsushita Electric Ind Co Ltd | はんだ材料 |
JP2000174192A (ja) * | 1998-12-09 | 2000-06-23 | Nec Corp | 半導体装置の外部リード |
JP2002009428A (ja) * | 2000-06-16 | 2002-01-11 | Fujitsu Ltd | 電子部品の実装方法及び電子部品の実装構造 |
-
2007
- 2007-09-12 JP JP2007237077A patent/JP5493257B2/ja active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62219950A (ja) * | 1986-03-20 | 1987-09-28 | Shinko Electric Ind Co Ltd | リ−ドフレ−ム |
JPH07273263A (ja) * | 1994-03-30 | 1995-10-20 | Sony Corp | 電子部品の外部端子 |
JPH08132277A (ja) * | 1994-11-01 | 1996-05-28 | Ishikawa Kinzoku Kk | 無鉛はんだ |
JPH08206874A (ja) * | 1995-02-06 | 1996-08-13 | Matsushita Electric Ind Co Ltd | はんだ材料 |
JP2000174192A (ja) * | 1998-12-09 | 2000-06-23 | Nec Corp | 半導体装置の外部リード |
JP2002009428A (ja) * | 2000-06-16 | 2002-01-11 | Fujitsu Ltd | 電子部品の実装方法及び電子部品の実装構造 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010245217A (ja) * | 2009-04-03 | 2010-10-28 | Kenichi Fuse | 半導体icの装填方法 |
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JP5493257B2 (ja) | 2014-05-14 |
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