JP2009054829A - Electronic component and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic component which is formed by mounting an electronic component chip on a ceramic multilayer board using bumps and assures the excellent credibility of electrical connection by a plurality of bumps. <P>SOLUTION: Disclosed is the electronic component 1 which has the electronic component chip 3 with the plurality of bumps 14 to 16 mounted on a top surface 2a of the ceramic multilayer substrate 2 and also has a first electrode land 11, a second electrode land 12, and a first electrode land 13, where the bumps 14 to 16 are connected, in order on the ceramic multilayer substrate 2, the top surface 2a of the ceramic multilayer substrate 2 being made convex so that the height of the second electrode land 12 is larger than the height of the first electrode lands 11 and 13. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electronic component in which an electronic component chip is mounted on a ceramic multilayer substrate and a method for manufacturing the same. More specifically, the electronic component chip is mounted on a ceramic multilayer substrate by flip chip bonding using metal bumps. The present invention relates to an electronic component and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, various electronic component chips are mounted on a ceramic multilayer substrate by flip chip bonding in order to reduce the size and thickness of an electronic component mounting structure (see, for example, Patent Document 1 below).

  In an electronic component as described in Patent Document 1, metal bumps provided on the lower surface of the electronic component chip are bonded to electrode lands provided on the upper surface of the ceramic multilayer substrate. In this case, the upper surface of the ceramic multilayer substrate is required to be flat in order to reliably perform the bonding with the metal bumps.

  However, since the ceramic multilayer substrate is obtained using the ceramic integrated firing technique, the flatness of the upper surface is not always sufficient. Therefore, in Patent Document 2 below, in an electronic component in which an electronic component chip having metal bumps provided on the lower surface is mounted on a ceramic multilayer substrate, along a certain direction that is parallel to the upper surface of the ceramic multilayer substrate. Among the plurality of arranged bumps, an internal conductive film is provided in the ceramic multilayer substrate at least below the bump arranged on the center side. Thereby, the flatness of the upper surface of the ceramic multilayer substrate is improved.

  FIG. 14 is a diagram showing the height position of the upper surface of the ceramic multilayer substrate at the bump bonding portion in the conventional example and the example in Patent Document 2. Here, Z1 to Z5 on the horizontal axis indicate positions where the bumps Z1 to Z5 are joined in the ceramic multilayer substrate. The bumps Z1 and Z5 are bumps located at both ends in a certain direction, and the bumps Z2 to Z4 are bumps located on the center side. The height difference on the bump line on the vertical axis indicates the height position of the ceramic multilayer substrate relative to the height of the ceramic multilayer substrate where the bumps Z1 and Z5 are joined.

As is apparent from FIG. 14, in the conventional example indicated by Δ, the height position of the ceramic multilayer substrate at the portion where the bump Z3 located at the center is joined is higher than in the case of the example indicated by ◆ and ■. It can be seen that it is lower than the height position of the ceramic multilayer substrate where Z1 and Z5 are joined. In particular, in the embodiment indicated by ◆, the height position of the ceramic multilayer substrate where the central bumps Z3 and Z4 are joined is substantially the same as the height position of the ceramic multilayer substrate where the bumps Z1 and Z5 on both sides are joined. It can be seen that the flatness is extremely improved. In the embodiment shown by the above ◆ and the embodiment shown by ■, the bump Z2 located on the center side is located in the bump joint portion by disposing an internal conductive film below the bump in the ceramic multilayer substrate. This is because the height position of the ceramic multilayer substrate at the portion to which .about.Z4 is joined is increased.
Japanese Patent Laid-Open No. 2002-100787 JP-A-2005-116622

  Conventionally, if the upper surface of the ceramic multilayer substrate is flattened as described in Patent Document 2, the height positions of the bumps provided on the upper surface of the ceramic multilayer substrate are aligned. It was thought that the reliability of the electrical connection of the joint by the metal bumps thus improved could be improved.

  However, it has been found by the present inventor that the reliability of the connection by the metal bumps is not sufficient only by improving the flatness of the upper surface of the ceramic multilayer substrate, and a connection failure may occur.

  An object of the present invention is to provide an electronic component in which an electronic component chip having a metal bump on its lower surface is mounted on a ceramic multilayer substrate in view of the above-described state of the prior art, and a method for manufacturing the same, and an electrical connection using the metal bump It is an object of the present invention to provide an electronic component and a method for manufacturing the same that can further increase the reliability of the electronic component.

  An electronic component according to the present invention includes a ceramic multilayer substrate, at least two first electrode lands formed on the upper surface of the ceramic multilayer substrate, and a second electrode land formed on the upper surface of the ceramic multilayer substrate. And the second electrode land is disposed between at least two first electrode lands in a certain direction parallel to the upper surface of the ceramic multilayer substrate, and is mounted on the upper surface of the ceramic multilayer substrate. An electronic component chip further comprising an electronic component chip having first and second bumps bonded to the first and second electrode lands on the lower surface thereof, wherein the upper surface of the ceramic multilayer substrate is provided. The upper surface of the ceramic multilayer substrate is convex so that the second electrode land provided on the substrate is higher than the first electrode land. And butterflies.

  Preferably, the ceramic multilayer substrate has an internal conductive film in a portion located below the second electrode land. Thereby, the height position of the second electrode land is easily made higher than that of the first electrode land, and the upper surface of the ceramic multilayer substrate is surely made convex.

  Preferably, a plurality of internal conductive films are formed in the ceramic multilayer substrate, and the number of internal conductive films positioned below the second electrode land is positioned below the first electrode land. The number is larger than the number of internal conductive films. Even in this case, the upper surface of the ceramic multilayer substrate can be reliably made convex so that the height position of the second electrode land is higher than that of the first electrode land.

  In the electronic component of the present invention, preferably, the ceramic multilayer substrate is made of a ceramic sintered body obtained by a ceramic integrated firing technique. In this case, by adjusting the position and number of the internal conductive films, the upper surface of the ceramic multilayer substrate can be convex upward.

  The electronic component chip is not particularly limited, and examples thereof include those constituting a surface acoustic wave device. Further, the electronic component chip may constitute a duplexer including a transmission side band filter and a reception side band filter. In that case, a small duplexer obtained by the flip chip bonding method can be prepared as one electronic component.

  Preferably, a delay line disposed in the ceramic multilayer substrate is provided as the internal conductive film below the first and / or second bumps. In this case, it is possible to improve the reliability of electrical connection of an electronic component with a built-in delay line.

  An electronic component manufacturing method according to the present invention is an electronic component manufacturing method configured according to the present invention, comprising: preparing an unfired ceramic laminate having a plurality of ceramic layers; and firing the ceramic laminate A step of obtaining a ceramic sintered body having a convex upper surface, a step of forming the first and second electrode lands on the upper surface before or after firing the ceramic laminate, and the first The electronic component chip comprising the first and second bumps on the lower surface on a ceramic multilayer substrate made of a ceramic sintered body having the second electrode land formed on the upper surface is provided on the first and second electrode lands. And mounting by bonding the first and second bumps.

  In the method of manufacturing an electronic component according to the present invention, preferably, in obtaining the ceramic laminate, the plurality of unfired ceramic layers and the ceramic layers are arranged at least at one interface adjacent to each other in the thickness direction. A ceramic laminate having an internal conductive film is formed. Therefore, by arranging the internal conductive film, the ceramic multilayer substrate obtained by firing the ceramic laminate can be reliably made convex on the upper surface.

  More preferably, in obtaining the ceramic laminate, a ceramic laminate having a plurality of unfired ceramic layers and an internal conductive film disposed at at least one of the interfaces adjacent to each other in the thickness direction. The body is formed.

  In the manufacturing method according to the present invention, at least one of the plurality of internal conductive films may be a dummy pattern film for adjusting a height of the first and second electrode lands. . By forming the dummy pattern film, it becomes easy to make the upper surface of the ceramic multilayer substrate convex.

  In the electronic component according to the present invention, in the first and second electrode lands on the upper surface of the ceramic multilayer substrate to be bonded to the first and second bumps provided on the lower surface of the electronic component chip, the second electrode land is the first electrode land. Since the upper surface of the ceramic multilayer substrate is convex so as to be higher than one electrode land, the reliability of the electrical connection to the electrode land of the electronic component chip by the bumps is higher than when the upper surface of the ceramic multilayer substrate is flat. Sexually can be enhanced effectively. This is because the stress due to the bump connection tends to be applied to the central bump more than the bumps located at both ends, so that the stress applied to the central bump is increased by making the upper surface of the ceramic multilayer substrate convex. This is because the difference in stress applied to the first bump and the second bump can be reduced.

  Therefore, according to the present invention, it is possible to effectively improve the reliability of electrical connection in an electronic component obtained by a flip chip bonding method using metal bumps.

  Hereinafter, the present invention will be clarified by describing specific embodiments of the present invention with reference to the drawings.

  FIG. 1 is a front sectional view showing an electronic component according to the first embodiment of the present invention.

  The electronic component 1 includes a ceramic multilayer substrate 2, an electronic component chip 3 mounted on the ceramic multilayer substrate 2, and a frame member 4. Although not shown in particular, a lid made of an appropriate material is attached on the frame member 4 so as to close the opening surrounded by the frame member 4.

  The ceramic multilayer substrate 2 has a structure in which a plurality of ceramic layers 5 to 7 are laminated. Internal conductive films 8 and 9 are formed between the ceramic layers 5 and 6 and between the ceramic layers 6 and 7, respectively.

  The ceramic multilayer substrate 2 is formed by laminating a ceramic green sheet containing an appropriate insulating ceramic material or dielectric ceramic material and internal conductive films 8 and 9 made of an appropriate metal such as Ag, Cu and W, and firing the ceramics integrally. The ceramic sintered body is fired by the technique.

  The frame member 4 is made of an insulating ceramic such as alumina or an appropriate dielectric ceramic. Preferably, the frame member 4 is formed of the same ceramic material as the ceramic multilayer substrate 2. The frame material 4 may be fired at the same time as the ceramic multilayer substrate 2, or after obtaining the ceramic multilayer substrate 2, the frame material 4 may be bonded onto the ceramic multilayer substrate 2 using an adhesive or the like.

  On the upper surface 2a of the ceramic multilayer substrate 2, a first electrode land 11, a second electrode land 12, and a first electrode land 13 are provided in this order along a certain direction. That is, one or more second electrode lands 12 are arranged between at least two first electrode lands 11 and 13 in a certain direction.

  The upper surface 2 a of the ceramic multilayer substrate 2 is convex so that the height of the second electrode land 12 is higher than the height of the first electrode lands 11 and 13. Therefore, the height of the second electrode land 12 is higher than that of the first electrode lands 11 and 13.

  On the other hand, an electronic component chip 3 is mounted on the ceramic multilayer substrate 2. The electronic component chip 3 has electrodes 3a to 3c on the lower surface, and pumps 14 to 16 are provided on the electrodes 3a to 3c. The electronic component chip 3 is mounted on the ceramic multilayer substrate 2 so that these bumps 14 to 16 are bonded to the electrode lands 11 to 13, that is, by flip chip bonding.

  The pumps 14 to 16 are made of an appropriate metal. Examples of such metals include metals such as Au, Ag, Cu, and Pb or alloys.

  The said pumps 14-16 are arrange | positioned in order along the certain direction mentioned above so that it may join to the electrode lands 11-13.

  In the present embodiment, the internal conductive films 8 and 9 are located below the second electrode land 12 located on the center side, and the internal conductive film is located below the first electrode lands 11 and 13. Is not formed. Therefore, when the ceramic multilayer substrate 2 is obtained by the ceramic integrated firing technique, the center of the upper surface 2a of the ceramic multilayer substrate 2 is convex upward due to the presence of the internal conductive films 8 and 9. Therefore, the height of the second electrode land 12 is set higher than the height of the first electrode lands 11 and 13.

  In this embodiment, since the height of the second electrode land 12 is higher than the height of the first electrode lands 11 and 13, the electrical connection between the pumps 14 to 16 and the electrode lands 11 to 13 is achieved. Connection reliability is improved.

  This point will be described in detail later.

  The electronic component 1 constituting the electronic component chip 3 is not particularly limited, but in this embodiment, the transmission side frequency band is 824 to 849 MHz (bandwidth is 25 MHz), and the reception side frequency band is 869 to 894 MHz (bandwidth is 25 MHz) AMPS demultiplexer is configured. Here, the interval between the transmission side band and the reception side band is as narrow as 20 MHz. Therefore, both the transmission-side band and the reception-side band are required to have a sufficient attenuation amount in the other-side band and to have steep filter characteristics. In order to satisfy such characteristics, the circuit configuration shown in FIG. 2 is adopted in this embodiment. That is, the electronic component chip 3 includes a transmission side band filter 21 and a reception side band filter 22. Each band filter is formed of a ladder type filter having a plurality of series arm resonators and a plurality of parallel arm resonators. The series arm resonator and the parallel arm resonator are both constituted by surface acoustic wave resonators.

  The electronic component chip 3 has an antenna terminal 24, and the transmission side band filter 21 is connected to the antenna terminal 24. A reception side band filter 22 is connected to the antenna terminal 24 via a phase matching circuit 25.

  In FIG. 2, both the transmission-side band filter 21 and the reception-side band filter 22 are configured by a surface acoustic wave filter device having a ladder-type circuit configuration. However, the configurations of the transmission side band filter 21 and the reception side band filter 22 are not particularly limited.

  When the electronic component 1 is manufactured, ceramic green sheets for forming a plurality of ceramic layers 5 to 7 constituting the ceramic multilayer substrate 2 are laminated with the internal conductive films 8 and 9 interposed therebetween. Prepare a laminate. By firing this ceramic laminate, it is possible to obtain a ceramic sintered body whose upper surface is convex at the center. The ceramic multilayer substrate 2 can be obtained by forming the electrode lands 11 to 13 on the upper surface of the ceramic sintered body. Prior to obtaining the ceramic sintered body, the first and second electrode lands 11 to 13 may be formed on the upper surface, and then fired to obtain the ceramic multilayer substrate 2.

  The formation of the first and second electrode lands 11 to 13 can be appropriately performed by applying and baking a conductive paste, or a thin film forming method such as vapor deposition, plating, or sputtering.

  Finally, the electronic component chip 3 having the bumps 14 to 16 on the lower surface may be mounted on the ceramic multilayer substrate 2 so that the bumps 14 to 16 are bonded to the first and second electrode lands 11 to 13. .

  Next, in the electronic component 1 of the embodiment shown in FIG. 1, it will be described with reference to FIGS. 3 to 5 that the reliability of electrical connection between the bumps 14 to 16 and the electrode lands 11 to 13 can be improved. To do.

  FIG. 3 is a front end view showing the electronic component 101 prepared for reference. In this electronic component 101, an electronic component chip 103 is mounted on a ceramic multilayer substrate 102 having a flat upper surface. There is no internal conductive film below the second electrode land 12 so that the upper surface of the ceramic multilayer substrate 102 is flat. Since the other points are the same as those of the electronic component 1 of the above embodiment, the corresponding parts are denoted by the corresponding reference numerals.

  In the electronic component 101 of the reference example, the upper surface of the ceramic multilayer substrate 102 is flat. Conventionally, it has been considered that the reliability of the electrical connection between the bumps 14 to 16 and the electrode lands 11 to 13 can be improved if the upper surface 102a is flat.

  However, in reality, even when the ceramic multilayer substrate 102 having a flat upper surface 102a is used, the reliability of electrical connection may be impaired.

  Therefore, the inventor of the present application simulated a stress applied to the bump by applying a thermal shock after bonding when the upper surface of the ceramic multilayer substrate is not flat but warped. The stress applied to the central second bump 15 is affected by the warp of the upper surface of the ceramic multilayer substrate, and this stress is applied to the second bump 15 more than the first bumps 14 and 16 on both sides. I found.

Therefore, the influence of the warpage state of the ceramic multilayer substrate 102 was obtained by simulating the stress applied to the bump 15 after bonding in the same manner for the second bump 15 at the center where the greatest stress tends to be applied. The results are shown in FIG. FIG. 4 shows the stress applied to the bump 15 when the upper surface is flat like the ceramic multilayer substrate 102, when the upper surface of the ceramic multilayer substrate is concave, or when it is convex upward as in the above embodiment. FIG. The center 0 μm shows the result when the upper surface of the ceramic multilayer substrate is flat as in the reference example. In contrast, -2
μm indicates a result when the height of the bump 15 is 2 μm lower than that in the above reference example, in other words, when the upper surface of the ceramic multilayer substrate is warped so as to be concave.

  FIG. 5 is a diagram schematically showing the height positions of the first and second electrode lands 11 to 13 at the positions where the bumps 14 to 16 are connected.

  As apparent from FIG. 4, when the upper surface of the ceramic multilayer substrate is concave, that is, when the height of the second electrode land 12 is lower than that of the first electrode lands 11, 13, the second bump 15 It can be seen that a large stress is applied to.

  On the other hand, in the case of +3 μm, that is, when the upper surface of the ceramic multilayer substrate is convex upward as in the above embodiment, it can be seen that the stress applied to the second bump 15 is reduced. That is, when the upper surface 2a is convex upward like the ceramic multilayer substrate 2, the stress applied to the second bump 15 located in the center is higher than when the ceramic multilayer substrate 102 having a flat upper surface is used. You can see that it is getting smaller.

  Therefore, as in the above embodiment, the upper surface of the ceramic multilayer substrate 2 has a convex shape, whereby the height of the second electrode land 12 is higher than that of the first electrode lands 11 and 13. If so, the stress applied to the bump 15 by thermal shock or the like can be reduced. Thereby, the stress to the bump 15 to which the largest stress is applied can be reduced, and the reliability of the electrical connection can be improved. This will be described based on simulation.

  A thermal shock is applied to each electronic component using the electronic component and the conventional electronic component in which the upper surface of the ceramic multilayer substrate is flat and, conversely, the ceramic multilayer substrate in which the upper surface of the ceramic multilayer substrate is concave, The stress applied to the second bump located at the center was simulated. That is, as a thermal shock, a temperature change from 25 ° C. to 85 ° C. and a temperature change from 25 ° C. to −40 ° C. were applied to each electronic component. The stress applied to the central bump, that is, the force in the direction of separating the electronic component chip from the ceramic multilayer substrate, was obtained by stress simulation. The results are shown in Table 1 below.

  As can be seen from Table 1, when the upper surface of the ceramic multilayer substrate 2 is convex upward, the stress applied to the second bump 15 is the smallest, which is greater than when the upper surface of the ceramic multilayer substrate 2 is flat. It can be seen that the stress is small.

  The internal conductive film formed in the ceramic multilayer substrate 2 is not limited to the wiring pattern that electrically connects different portions, and may be the delay line, or for configuring an inductance or a capacitance. An internal conductive film may be used.

  In the above embodiment, the internal conductive films 8 and 9 are provided below the second electrode land 12. However, as shown in FIG. 6, one internal conductive film is provided below the second electrode land 12. Only 8 may be provided. In this case, since the number of internal conductive films is reduced, the height of the second electrode land 12 is lower than that in the above embodiment. However, the height of the second electrode land 12 can be increased as compared with the comparative example in which the internal conductive film does not exist only below the second electrode land 12.

  FIG. 7 shows a difference in height between the second electrode land 12 and the first electrode lands 11 and 13 in the above embodiment, the modification shown in FIG. 6 and the conventional example in which the upper surface of the ceramic multilayer substrate is flat. FIG.

  In the above embodiment, the internal conductive films 9 and 10 are provided below the second electrode land 12, and the internal conductive film is not provided below the first electrode lands 11 and 13 on both sides. As a result, the upper surface of the ceramic multilayer substrate 2 is convex upward. However, as shown in FIG. 8, not only the internal conductive films 8 and 9 are formed below the second electrode land 12, but also the internal conductive film 10 is formed below the first electrode lands 11 and 13. May be. That is, if the number of internal conductive films located below the second electrode land 12 located on the center side is made larger than the number of internal conductive films located below the first electrode lands 11 and 13 located on both sides. Even in such a case, the upper surface of the ceramic multilayer substrate 2 can be convex upward.

  In the direction in which a plurality of bumps and electrode lands are arranged, the first electrode lands 11 and 13 are electrode lands located on the side closer to the end of the ceramic multilayer substrate 2 in the direction, The second electrode land 12 positioned on the side means an electrode land positioned closer to the center on the upper surface of the ceramic multilayer substrate 2 in the direction than the end.

  In FIG. 1, only a portion where three bumps 14 to 16 are arranged among a large number of metal bumps is schematically shown in a sectional view. However, the ceramic multilayer substrate 2 on which the electronic component chip 3 is mounted is actually Has a more complex structure. This will be described with reference to FIGS.

  FIG. 9 is a schematic plan view of the upper surface 2a of the ceramic multilayer substrate 2, FIG. 10 is a schematic plan sectional view of the height position at the interface in the ceramic layers 5 and 6, and FIG. It is a typical plane sectional view of the height position in the interface in 6,7. FIG. 12 is a schematic plan view of the lower surface of the ceramic multilayer substrate 2 as viewed from above.

  As shown in FIG. 9, electrode lands 31 to 38 are formed on the upper surface 2 a of the ceramic multilayer substrate 2. One or a plurality of bumps are bonded to each of the electrode lands 31 to 38. That is, bumps on the electronic component chip side are bonded to the positions indicated by X1 to X24 in FIG. In other words, 24 bumps are bonded to the upper surface 2 a of the ceramic multilayer substrate 2.

  Note that bumps bonded to the positions indicated by X1 to X12 correspond to the reception-side band filter 22, and bumps bonded to positions indicated by X13 to X24 correspond to the transmission-side band filter 23.

  9 to 13, A1 to A8, B1 to B4, A8 to A11, and C1 to C6 respectively indicate via holes provided in the ceramic multilayer substrate.

  In the ceramic multilayer substrate 2, the bumps bonded to the positions X1 to X24 are connected as follows.

Transmission side input terminal: X24 bump Transmission side output terminal: X13 bump, X18 bump Transmission side ground terminal: X14 bump to X17 bump and X19 bump to X23 bump Reception side input terminal: X4 bump Reception side Output terminal: X2 bump Reception side ground terminal: X1 bump, X3 bump, X5 bump to X12 bump In addition, the signal path is as follows.

Via hole A1-> via hole A2-> via hole A3-> via hole A4-> via hole A5-> via hole A6-> via hole A7 (delay line)
Via hole A8-> via hole A9-> via hole A10-> via hole A11-> antenna terminal Via hole B1-> via hole B2-> via hole B3-> via hole B4-> reception side terminal In the present embodiment, the ceramic multilayer substrate 2 is actually configured as described above. In this case, as described above, bumps are bonded to a large number of positions X1 to X24 on the upper surface of the ceramic multilayer substrate 2. In the present invention, among the plurality of bumps arranged along a direction parallel to the upper surface of the ceramic multilayer substrate, an internal conductive film is provided in at least one layer below the bump corresponding to the signal side of the electronic component chip. That's fine. This will be described more specifically.

  In this embodiment, as shown in FIGS. 11 and 12, as one of the internal conductive films, a delay line composed of conductive films 26 and 27 meandering so as to have a long length is formed. ing. In the structure in which such a delay line is formed in the ceramic multilayer substrate 2, the delay line is positioned below the first electrode land, so that the height of the second electrode land 12 is increased. Also good.

  Further, not the delay line but the dummy pattern 28 shown in FIG. 11 may be provided to increase the position of the upper electrode land. The dummy pattern 28 refers to an internal conductive film having no electrical function such as a delay line and a connection wiring.

  10 to 13 show an example of a portion where the internal conductive film and the bump in the ceramic multilayer substrate 2 are joined. In the present invention, the shape of the internal conductive film in the ceramic multilayer substrate 2 is shown. Is not particularly limited, and the position of the bump bonded to the upper surface of the ceramic multilayer substrate 2 is not limited to the illustrated structure.

  FIG. 1 and FIG. 4 show the results of examination in a simplified sample in which three bumps 14 to 16 are provided. FIG. 13 shows a specific example having the laminated structure shown in FIG. 9 to FIG. The experimental result at the time of using a typical ceramic multilayer substrate is shown. Here, as shown in Table 2 below, the degree of overlap between the internal conductive film formed on the ceramic layer 6 and the ceramic layer 7 and the bump bonded on the upper side is represented by symbols ◯, Δ, and ×. It is shown in Table 2 below.

  In Table 2, “on the layer 6” and “on the layer 7” indicate the degree of overlap between the internal conductive film on the ceramic layer 6 and the internal conductive film on the ceramic layer 7 and the upper bump. Here, X1 to X5 in Table 2 are bump bonding positions arranged in order along a direction E indicated by a broken line in FIG.

  ◯ in Table 2 indicates the case where there is a portion where the internal conductive film overlaps in the entire region below the electrode land, and Δ indicates the case where there is a portion where the internal conductive film partially overlaps below the electrode land. X indicates a case where no internal conductive film exists below the corresponding electrode land.

  And FIG. 13 shows the result of having measured the height of each electrode land to which a bump is connected by position X1-X5 of the upper surface at the time of using the ceramic multilayer substrate 2 of the said samples 41-45 with the laser displacement meter. In addition, this measurement result shows the average value of the result measured in the same 10 samples.

  As is clear from FIG. 9, in Samples 41 to 43 and Sample 45, at least one of the electrode lands at the center positions X2, X3, and X4 on the upper surface of the ceramic multilayer substrate is positioned at both ends X1, It turns out that it is located below the electrode land of X5. That is, it can be seen that the upper surface of the ceramic multilayer substrate is concave. Therefore, in the samples 41 to 43 and the sample 45, the stress applied to the bumps at the positions X2 to X4 on the center side increases.

  On the other hand, in the sample 44, all the heights of the electrode lands at the positions X2 to X4 on the center side are higher than the heights of the first electrode lands at the positions X1 and X5 at both ends. Accordingly, the stress applied to the second electrode land located on the center side is reduced, and thereby the reliability of electrical connection by each bump is effectively enhanced.

1 is a schematic front sectional view showing an electronic component according to an embodiment of the present invention. It is a circuit diagram which shows the circuit structure of the electronic component of this embodiment. It is the schematic front sectional drawing of the electronic component using the ceramic multilayer substrate with which both surfaces were prepared as a reference example. It is a figure which shows the magnitude | size of the stress added to the 2nd bump | vamp of each center when the upper surface of a ceramic multilayer substrate is concave shape, flat, and convex shape. In the embodiment shown in FIG. 1, it is a figure which shows the height position of the 1st, 2nd electrode land. It is front sectional drawing which shows the electronic component which concerns on the modification of 1st Embodiment. It is a figure which shows the height difference of the 2nd electrode land in each of the 1st Embodiment, a modified example, and the conventional electronic component using the ceramic multilayer substrate with a flat upper surface, and a 1st electrode land. FIG. 6 is a schematic front sectional view for explaining an electronic component according to still another modification of the first embodiment. It is a top view for demonstrating the more specific structure of the ceramic multilayer substrate used by 1st Embodiment. It is a schematic plan view of the intermediate height position of the ceramic multilayer substrate used in the first embodiment. FIG. 11 is a schematic plan sectional view of an intermediate height position of the ceramic multilayer substrate used in the embodiment shown in FIG. 1, and shows a part below the part shown in FIG. 10. It is a top view which shows typically the electrode structure of the lower surface of the ceramic multilayer substrate used by embodiment shown in FIG. It is a figure which shows the stress added to each electrode land X1-X5 in the electronic component which concerns on 1st Embodiment, and the samples 41-45 as an electronic component of the comparative example prepared for the comparison. It is a figure which shows the height relationship of the bump position and bump junction position in the electronic component of embodiment described in a prior art, and a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Electronic component 2 ... Ceramic multilayer substrate 2a ... Upper surface 3 ... Electronic component chip 3a-3c ... Electrode 4 ... Frame material 5-7 ... Ceramic layer 8-10 ... Internal conductive film 11, 13 ... 1st electrode land 12 ... 2nd electrode land 14, 16 ... 1st bump 15 ... 2nd bump 21 ... Transmission side band filter 22 ... Reception side band filter 23 ... Transmission side band filter 24 ... Antenna input terminal 25 ... Circuit for phase matching 31- 38 ... Electrode land X1-X5 ... Bump bonding position or land

Claims (11)

A ceramic multilayer substrate, at least two first electrode lands formed on the upper surface of the ceramic multilayer substrate, and a second electrode land formed on the upper surface of the ceramic multilayer substrate,
The second electrode land is disposed between at least two first electrode lands in a certain direction parallel to the upper surface of the upper surface of the ceramic multilayer substrate;
An electronic component chip mounted on the upper surface of the ceramic multilayer substrate, further comprising an electronic component chip having first and second bumps bonded to the first and second electrode lands on the lower surface, respectively. In
The electronic component, wherein the upper surface of the ceramic multilayer substrate is convex so that the second electrode land provided on the upper surface of the ceramic multilayer substrate is higher than the first electrode land.   2. The electronic component according to claim 1, wherein the ceramic multilayer substrate has an internal conductive film in a portion located below the second electrode land.   A plurality of internal conductive films are formed in the ceramic multilayer substrate, and the number of internal conductive films positioned below the second electrode land is the number of internal conductive films positioned below the first electrode land. The electronic component according to claim 1, wherein the electronic component is greater than the number of the electronic components.   The electronic component according to claim 1, wherein the ceramic multilayer substrate is made of a ceramic sintered body obtained by an integrated ceramic firing technique.   The electronic component according to claim 1, wherein the electronic component chip is a surface acoustic wave device.   The electronic component according to any one of claims 1 to 6, wherein the electronic component chip is an electronic component chip constituting a duplexer including a transmission side band filter and a reception side band filter.   The electronic component according to claim 6, further comprising a delay line disposed in the ceramic multilayer substrate as the internal conductive film below the first and / or second electrode lands. A method for manufacturing an electronic component according to any one of claims 1 to 7,
Preparing a green ceramic laminate having a plurality of ceramic layers;
Firing the ceramic laminate to obtain a ceramic sintered body having a convex upper surface;
Forming the first and second electrode lands on the upper surface before or after firing the ceramic laminate; and
The electronic component chip comprising the first and second bumps on the lower surface on a ceramic multilayer substrate made of a ceramic sintered body having the first and second electrode lands formed on the upper surface. And a step of mounting the first and second bumps by bonding the first and second bumps to the electrode land.   In obtaining the ceramic laminate, a ceramic laminate having a plurality of unfired ceramic layers and an internal conductive film disposed at at least one of the interfaces adjacent to each other in the thickness direction is formed. The manufacturing method of the electronic component of Claim 8.   A plurality of internal conductive films are formed such that the number of internal conductive films positioned below the first electrode lands is larger than the number of internal conductive films positioned below the second electrode lands; The manufacturing method of the electronic component of Claim 9.   11. The manufacturing of an electronic component according to claim 10, wherein at least one of the plurality of internal conductive films is a dummy pattern film for adjusting a height of the first and second electrode lands. Method.

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