WO2015029942A1 - High-frequency circuit board, high-frequency semiconductor package using same, and high-frequency semiconductor device - Google Patents

High-frequency circuit board, high-frequency semiconductor package using same, and high-frequency semiconductor device Download PDF

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Publication number
WO2015029942A1
WO2015029942A1 PCT/JP2014/072149 JP2014072149W WO2015029942A1 WO 2015029942 A1 WO2015029942 A1 WO 2015029942A1 JP 2014072149 W JP2014072149 W JP 2014072149W WO 2015029942 A1 WO2015029942 A1 WO 2015029942A1
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WO
WIPO (PCT)
Prior art keywords
line
line conductor
conductor
circuit board
wide
Prior art date
Application number
PCT/JP2014/072149
Other languages
French (fr)
Japanese (ja)
Inventor
真広 辻野
Original Assignee
京セラ株式会社
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Publication date
Application filed by 京セラ株式会社 filed Critical 京セラ株式会社
Priority to JP2015534199A priority Critical patent/JPWO2015029942A1/en
Publication of WO2015029942A1 publication Critical patent/WO2015029942A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00—Coupling devices of the waveguide type
    • H01P5/02—Coupling devices of the waveguide type with invariable factor of coupling
    • H01P5/022—Transitions between lines of the same kind and shape, but with different dimensions
    • H01P5/028—Transitions between lines of the same kind and shape, but with different dimensions between strip lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths

Definitions

  • the present invention relates to a high-frequency circuit board on which a signal line for transmitting a high-frequency signal is formed, and more particularly to a high-frequency circuit board characterized by a connection portion between signal lines, a high-frequency semiconductor package and a high-frequency semiconductor device using the same.
  • connection pad makes the positions of the signal lines inconsistent and makes the signal lines that are not accurately aligned in a conductive state.
  • a first connection pad 101 is provided at the end of the first signal line 100, and a second connection pad 103 is provided at the end of the second signal line 102.
  • the first line conductor 100 and the second line conductor 102 are connected via a connection line 104 such as a bonding wire.
  • the first signal line 100, the connection line 104, and the second signal line 102 are arranged in a straight line. However, when these are not arranged on a straight line, for example, when the connection line 104 is arranged at a position off the center line of the first signal line 101 and the second signal line 102, the first line There is a case where the signal line 100 and the second signal line 102 cannot be electrically connected via the connection line 104.
  • first connection pad 101 and the second connection pad 103 are provided with a width wider than that of the first signal line 100 and the second signal line 102, the eccentricity of the connection line 104 is caused by the first eccentricity.
  • the first signal line 100 and the second signal line 102 are connected to each other within the width of the connection pad 101 and the second connection pad 103.
  • the impedance at a portion where the connection pads 101 and 103 are arranged is different from the characteristic impedance of the high-frequency line. Therefore, the transmission characteristics of the signal lines 100 and 102 are deteriorated.
  • the present invention has been completed in view of the above-described conventional problems, and the object of the present invention is to easily connect line conductors without causing a significant impedance mismatch when connecting high-frequency lines.
  • An object of the present invention is to provide a high-frequency circuit board having a line conductor, a high-frequency semiconductor package and a high-frequency semiconductor device using the same.
  • the high-frequency circuit board has a connection end to which one end of another connection conductor is connected at one end.
  • the connection end includes a line conductor having a plurality of wide portions having a wide line width and a narrow portion having a line width narrower than that of the wide portion disposed between the plurality of wide portions.
  • the high-frequency circuit board includes a first dielectric substrate having a first line conductor and a second dielectric substrate having a second line conductor, the one end of the first line conductor and the first dielectric
  • the high-frequency circuit board is formed by stacking one end of the second line conductor.
  • the high-frequency circuit board has a connection portion in which the first line conductor and the second line conductor are connected in an overlapping manner.
  • the connecting portion includes a plurality of wide portions having a wide line width and a narrow portion having a line width narrower than the wide portions disposed between the wide portions.
  • the wide portion may have a shape in which the width of the line conductor in the line direction becomes narrower as the distance from the line conductor increases.
  • a line width of the narrow portion may be narrower than a line width of the line conductor in a portion excluding the connection end or the connection portion.
  • the line conductor may have a second narrow portion with a narrow line width at a position adjacent to the connection end or the connection portion.
  • a high-frequency semiconductor package according to an embodiment of the present invention is characterized in that any one of the above-described high-frequency circuit boards is used for an input / output part of a container in which a high-frequency semiconductor element is stored.
  • a high-frequency semiconductor device includes the high-frequency semiconductor package, and a high-frequency semiconductor element housed in the container and connected to the line conductor of the high-frequency circuit board.
  • a high-frequency circuit board includes, at a connection end, a plurality of wide portions having a wide line width and a narrow portion having a narrower line width than the wide portion disposed between the plurality of wide portions. Because it has the line conductors it has, it can reduce the capacitance component of the connection end while maintaining the tolerance of the positional accuracy of the line conductors to be connected, and does not cause a significant impedance mismatch in the line conductors It can be.
  • connection portion where the first line conductor and the second line conductor are connected is disposed between a plurality of wide portions having a wide line width and the wide portions. Since the narrow portion having a narrower line width than the wide portion formed is provided, the capacitance component generated in the connection portion is small, and a significant impedance mismatch can be prevented from occurring in the line conductor.
  • the impedance of the second narrow part is obtained. Can be made high and the low impedance in the wide portion can be compensated to reduce impedance mismatch in the line direction.
  • the high-frequency semiconductor package since any one of the above-described high-frequency circuit boards is used in the input / output portion of the container in which the high-frequency semiconductor element is accommodated, the high-frequency signal input / output characteristics An excellent high-frequency semiconductor package can be obtained.
  • a high-frequency semiconductor device includes the high-frequency semiconductor package and a high-frequency semiconductor element housed in a container and connected to a line conductor of a high-frequency circuit board. It can be a device.
  • FIG. 2B is a perspective plan view showing a laminate of the dielectric substrate of FIG. 2A and the dielectric substrate of FIG. 2B. It is a principal part top view which shows the other example of embodiment of a line conductor. It is a principal part top view which shows the other example of embodiment of a line conductor.
  • FIG. 1 is an exploded perspective view showing an example of an embodiment of a high-frequency circuit board and an electric circuit board connected thereto.
  • the line conductor 3 is formed on the surface of the dielectric substrate 1 in the high-frequency circuit board.
  • a line conductor 4 is formed on the back surface of the dielectric substrate 2 in the electric circuit substrate.
  • the line conductor 4 of the electric circuit board is formed on the back surface of the dielectric substrate 2 (the lower surface of the dielectric substrate 2 in the figure).
  • the line conductor 4 is shown in a form seen through the dielectric substrate 2.
  • the dielectric substrate 2 is indicated by a two-dot chain line.
  • the line conductor 4 is another connection conductor connected to the line conductor 3.
  • the line conductor 3 or the line conductor 4 is formed on the surface of the dielectric substrate 1 or the dielectric substrate 2.
  • the line conductor 3 or the line conductor 4 may be formed of a metal plate-like material and may not be supported by the dielectric substrate 1 or the dielectric substrate 2.
  • the line conductor 3 has a wide portion 3a that is wider than the line width of the line conductor 3 at the connection end to which the line conductor 4 is connected.
  • the connection end is one end of the line conductor 3 and is a portion that is overlapped with one end of the line conductor 4 and connected to the line conductor 4.
  • a narrow portion 3b narrower than the wide portion 3a is formed between the plurality of wide portions 3a.
  • the wide part 3a is formed so that two may adjoin along the line direction of the line conductor 3.
  • FIG. The wide portion 3a is formed so that two or more are adjacent to each other, and a narrow portion 3b is formed between the wide portions 3a.
  • Such a connection end is used as a connection pad. From the viewpoint of reducing the capacitance component at the connection end and securing the bonding force, if the number of the wide portions 3a and the narrow portions 3b is excessively increased, it tends to be disadvantageous.
  • the line conductor 4 and the line conductor 3 are formed by superimposing the line conductor 4 on the connection end of the line conductor 3 and connecting the line conductor 4 and the line conductor 3 to silver (Ag) brazing, gold (Au) -tin (Sn) solder, What is necessary is just to join by electroconductive joining materials etc., such as Ag epoxy (epoxy resin containing the metal powder of Ag).
  • electroconductive joining materials etc. such as Ag epoxy (epoxy resin containing the metal powder of Ag).
  • the end of the line conductor 4 may be joined to the line conductor 3 beyond the innermost wide portion 3a, but preferably the end of the line conductor 4 is disposed within the formation range of the innermost wide portion 3a. It is good.
  • the wide portion 3 a is provided in the line conductor 3, it is possible to ensure electrical connection between the line conductor 4 and the line conductor 3 even if the line conductor 4 is displaced from the center of the line conductor 3. Even if the line direction of the line conductor 4 and the line direction of the line conductor 3 are not parallel and are arranged at a slight angle, at least two wide portions 3a protruding on both sides of the line conductor 3 are provided at the connection end. Therefore, conduction can be ensured. Moreover, it can connect so that the connection resistance of the line conductor 3 and the line conductor 4 may not become large too much.
  • the line conductor 3 or the line conductor 4 generates a capacitance component between the ground conductors 5 and 6 and the like.
  • the connection end of the line conductor 3 is formed by being divided into a plurality of wide portions 3a, and a narrow portion 3b narrower than the wide portion 3a is formed between the plurality of wide portions 3a. The increase in the capacitance component at the connection end of the line conductor 3 can be suppressed.
  • FIG. 2A is a plan view showing a dielectric substrate 2 having a line conductor 4 formed on the surface thereof.
  • FIG. 2B is a perspective plan view showing the dielectric substrate 1 having the line conductor 3 formed on the back surface.
  • the line conductor 3 is formed on the back surface of the dielectric substrate 1, and the shape in a state where the dielectric substrate 1 is seen through is shown.
  • the dielectric substrate 1 is indicated by a two-dot chain line.
  • FIG. 2C is a perspective plan view showing a state in which the dielectric substrate 1 is laminated on the dielectric substrate 2.
  • the dielectric substrate 1 is indicated by a two-dot chain line.
  • the dielectric substrate 1 is also called the first dielectric substrate 1
  • the line conductor 3 is also called the first line conductor 3
  • the dielectric substrate 2 is also called the second dielectric substrate 2
  • the line conductor 4 is also called the second line conductor 4. Then, since they can be distinguished by the signs, they are simply referred to as dielectric substrate 1, line conductor 3, dielectric substrate 2, and line conductor 4.
  • such a high-frequency circuit board includes a dielectric substrate 1 having a line conductor 3 and a dielectric substrate 2 having a line conductor 4 that overlap one end of the line conductor 3 and one end of the line conductor 4.
  • the line conductors 3 and 4 are formed between the laminated dielectric substrate 1 and dielectric substrate 2.
  • the line conductors 3 and 4 connected to each other have a connection portion to which the line conductor 3 and the line conductor 4 are connected.
  • the connection portion is a portion where one end of the line conductor 3 and one end of the line conductor 4 are overlapped and connected to each other.
  • a plurality of wide portions 3a having a wide line width and a narrow portion 3b having a narrower line width than the wide portion 3a disposed between the wide portions 3a are formed in the connection portion.
  • the line conductor 3 has the wide portion 3a at the connecting portion, even if a slight misalignment occurs when the dielectric substrate 1 and the dielectric substrate 2 are laminated, the line conductor 3 and the line conductor 4 Can be conducted.
  • a plurality of wide portions 3a are provided to ensure conduction. Since the narrow portion 3b is disposed between the plurality of wide portions 3a, the capacitance component of the connection portion can be reduced, and a large impedance difference on the high-frequency line formed by the line conductor 3 and the line conductor 4 can be obtained. It is possible to prevent alignment.
  • FIG. 7A is a diagram in which the result of simulating the reflection loss of the high-frequency circuit board shown in FIG. 2 is plotted.
  • the broken line shows the reflection loss when the line conductor is connected through the conventional rectangular connection pad as shown in FIG.
  • the solid line indicates the reflection loss of the high-frequency circuit board according to the embodiment of the present invention. It can be seen that the simulation result indicated by the solid line in which the wide portion 3a and the narrow portion 3b are arranged in the connection portion has less reflection loss.
  • FIG. 7B is a diagram showing a simulation result of insertion loss obtained in the same manner. It can be seen that the insertion loss is lower in the high-frequency circuit board according to the embodiment of the present invention indicated by the solid line than in the conventional one indicated by the broken line.
  • the line conductor 3 shown in FIGS. 1 and 2 has various shapes as shown in FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, and 3J. Can be.
  • FIG. 3A shows a case where two wide portions 3a are provided.
  • FIG. 3B shows a case where a plurality of (four) wide portions 3a are provided.
  • FIG. 3C and 3D show cases where the widths of the wide portions 3a are made different.
  • FIG. 3C shows a case where the wide portion 3a on the front end side (left side in the drawing) is wider than the wide portion 3a on the rear end side (right side in the drawing).
  • FIG. 3D shows a case where the width of the wide portion 3a on the rear end side is made wider than that of the wide portion 3a on the front end side.
  • FIG. 3E, FIG. 3F, FIG. 3G, FIG. 3H, FIG. 3I, and FIG. 3J show that the width of the line conductor 3 in the line direction increases as the shape of the wide portion 3a increases from the line conductor 3 in the width direction of the line conductor 3.
  • Each example is formed so as to be narrow.
  • the shape of the wide portion 3a may be any of a linear shape, a curved shape, or a combination thereof as the distance from the edge of the line conductor 3 increases.
  • the edges of the wide portion 3a intersect at an obtuse angle with respect to the line direction of the line conductor 3 instead of at right angles. By intersecting at an obtuse angle, the change in impedance at the site where the wide portion 3a is provided can be made gradual.
  • FIG. 3E shows an example in which the side of the second wide portion 3a (right side) from the front end side of the line conductor 3 is inclined among the two wide portions 3a.
  • the wide portion 3a is inclined toward the front end side of the line conductor 3 as the side opposite to the front end of the line conductor 3 is separated in the width direction.
  • FIG. 3F shows an example in which both sides of the two wide portions 3a are inclined. Both wide portions 3a are inclined toward the tip end side of the line conductor 3 as the side opposite to the tip end of the line conductor 3 is separated in the width direction.
  • FIG. 3G shows an example in which both sides are inclined in the second wide portion 3a (right side) from the front end side of the line conductor 3 among the two wide portions 3a. Both the front end side and the rear end side of the line conductor 3 of the wide portion 3a are provided to be inclined.
  • FIG. 3H shows an example in which both sides are inclined in the wide portion 3a on the tip end side of the line conductor 3 among the two wide portions 3a. Both the front end side and the rear end side of the line conductor 3 of the wide portion 3a are provided to be inclined.
  • FIG. 3I shows an example in which the sides of both of the two wide portions 3a are inclined. Both wide portions 3a are provided with both sides on the front end side and rear end side of the line conductor 3 inclined.
  • FIG. 3J shows an example in which the sides of both of the two wide portions 3a are inclined in a semicircular shape or an arc shape. Both of the wide portions 3a are provided such that both the front end side and the rear end side of the line conductor 3 are inclined in a semicircular shape or an arc shape.
  • the line width of the line conductor 3 of the narrow portion 3b sandwiched between the plurality of wide portions 3a may be formed narrower than the line width of the portion excluding the connection portion of the line conductor 3. . Since the narrow portion 3b sandwiched between the wide portions 3a is overlapped and joined to the line conductor 4, the amount of the conductor increases, and the capacitance component tends to increase accordingly. By increasing the line width of the line conductor 3, the increase in the capacitance component can be reduced.
  • the line width of the narrow portion 3b means the length of the narrow portion 3b in the direction perpendicular to the line direction of the line conductor 3, that is, the width of the line conductor 3.
  • the minimum width value is referred to as the line width of the narrow portion 3b.
  • the line width of the wide portion 3a refers to the maximum width value of the wide portion 3a as the line width of the wide portion 3a.
  • a region 3c in which the line width of the line conductor 3 is narrowed may be provided at a connection end of the line conductor 3 where the wide portion 3a is formed or a position adjacent to the connection portion.
  • a wide portion 3a is formed at the connection end or the connection portion, the capacitance component is increased, and the impedance is decreased. Therefore, if the high impedance region 3c is arranged at a position adjacent to the connection end or the connection portion, it is possible to compensate for a decrease in impedance at the connection end or the connection portion. And the impedance mismatch on the high frequency line formed by the line conductor 3 and the line conductor 4 can be reduced.
  • the line width of the region 3c may be 70 to 80% of the line width of the line conductor 3 away from the connection end or connection portion, for example.
  • the line conductor 4 it is preferable to provide a conductor region 4c in which the line width of the line conductor 4 is narrowed at a position adjacent to the connection end or the connection portion.
  • the region 3c or the region 4c is also referred to as a second narrow portion with respect to the narrow portion 3b between the wide portions 3a.
  • ground conductors 5 and 6 are arranged close to each other on both sides of the line conductor 3 and the line conductor 4 in parallel with the line conductor 3 and the line conductor 4 at a predetermined distance.
  • the line conductor 3 and the line conductor 4 operate as a so-called coplanar line.
  • a ground conductor is also provided on the inner layer.
  • the line conductor 3 and the line conductor 4 operate as a so-called grounded coplanar line.
  • the line conductor 3 and the line conductor 4 may be microstrip lines.
  • the dielectric substrate 1 or the dielectric substrate 2 was selected from an alumina sintered body, an aluminum nitride sintered body, a mullite sintered body, ceramics such as glass ceramics, or a resin such as an epoxy resin or a polyimide film. Made of material.
  • the high-frequency circuit board composed of the dielectric substrate 1 or the dielectric substrate 2 is manufactured as such a ceramic substrate, a glass epoxy substrate, or a flexible substrate (FPC).
  • the line conductors 3 and 4 and the ground conductors 5 and 6 are formed by a metal conductor layer by, for example, a metallization method.
  • the line conductor 3 and the ground conductor 5 are formed on the dielectric substrate 1, the line is formed on the back surface of the ceramic green sheet to be the dielectric substrate 1.
  • a metal paste made of tungsten (W), molybdenum (Mo), manganese (Mn) or the like to be the conductor 3 and the ground conductor 5 is applied by screen printing.
  • the dielectric substrate 2 is printed with a metal paste made of W, Mo, Mn or the like to be the line conductor 4 and the ground conductor 6 on the surface by screen printing.
  • the connection end of the metal paste that becomes the line conductor 3 of the ceramic green sheet that becomes the dielectric substrate 1 and the line of the ceramic green sheet that becomes the dielectric substrate 2 The ceramic green sheets to be the dielectric substrate 1 and the dielectric substrate 2 are stacked one above the other so that one end of the metal paste to be the conductor 4 overlaps. If there are other wiring layers, the ceramic green sheets on which the wiring layers are formed are further stacked, pressure is applied from both sides, and the ceramic green sheets are pressed together.
  • the ceramic green sheet is fired by putting this laminate into a high-temperature furnace to form a ceramic substrate.
  • the metal paste is fired to obtain a high-frequency circuit board having the line conductors 3 and 4.
  • the line conductor 3, the ground conductor 5, the line conductor 4 and the ground conductor 6 may be formed by a thin film forming method.
  • the line conductors 3 and 4 and the ground conductors 5 and 6 are made of tantalum nitride (Ta 2 N ), Nichrome (Ni—Cr alloy), Titanium (Ti), Palladium (Pd), Platinum (Pt), etc., and after firing the ceramic green sheet to be the dielectric substrate 1 or the dielectric substrate 2, sputtering, etc. It is formed by a thin film forming method.
  • a foil such as copper (Cu) may be laminated on the surfaces of the dielectric substrates 1 and 2 and then the Cu foil may be etched to form the line conductors 3 and 4.
  • Cu copper
  • a circuit board for high frequency transmission capable of transmitting a high frequency signal between the dielectric substrates 1 and 2 can be manufactured.
  • the line width of the line conductor 3 is about 0.1 mm
  • the width of the wide portion 3a is about 0.3 mm
  • the length of the wide portion 3a (in the line direction of the line conductor 3) is The length of the narrow portion 3b between about 0.08 to 0.1 mm and the wide portion 3a is about 0.25 mm. If the length of the wide portion 3a is 10% or less of the wavelength of the high-frequency signal flowing through the line conductor 3, the influence of the impedance change can be reduced.
  • FIGS. are perspective views showing examples of embodiments of the high-frequency semiconductor package and the high-frequency device, respectively, 11 is a base, 12 is a frame, and 13 is an input / output terminal.
  • the package has a base 11 having a mounting portion 11a on which a semiconductor element is mounted at the center of the upper surface, and is attached to the upper surface of the base 11 so as to surround the mounting portion 11a, and is formed on a side portion.
  • the input / output terminal 13 is formed by laminating a plurality of ceramic green sheets.
  • the second layer 13a and the third layer 13b correspond to the dielectric substrate 2 and the dielectric substrate 1, respectively, and the line conductor 4 and the ground conductor 6 are formed on the upper surface of the second layer 13a.
  • a line conductor 3 and a ground conductor 5 are formed on the lower surface of the third layer 13b.
  • a ground conductor layer and other line conductor patterns are formed on the other layers, respectively.
  • a metal having excellent corrosion resistance such as nickel (Ni) or gold (Au) is about 1 to 20 ⁇ m. It is good to make it adhere by thickness. Prevents oxidative corrosion of these metal conductors. Further, the connection between the line conductor 3 and the external high-frequency line (not shown) and the connection between the electronic component 16 and the line conductor 4 via an electrical connection means such as a bonding wire are facilitated.
  • a Ni plating layer having a thickness of 0.5 ⁇ m to 10 ⁇ m and an Au plating layer having a thickness of about 0.1 to 5 ⁇ m are sequentially coated by an electrolytic plating method or an electroless plating method. Preferably it is worn.
  • the base 11 has a mounting portion 11a on the top surface for mounting semiconductor elements such as IC, LSI, semiconductor laser (LD), photodiode (PD) and the like.
  • FIG. 6 shows an example in which the mounting portion 11 a is a bottom surface of a recess surrounded by the base body 11 and the frame body 12.
  • a semiconductor element 16 may be mounted on the mounting portion 11 a on the upper surface of the base 11 via a mounting table 15 such as a Peltier element or a circuit board.
  • Base 11 Fe-Ni-Co alloy, copper (Cu) - tungsten (W) metal such as alloy, or Al 2 O 3 sintered material,, AlN sintered material, 3Al 2 O 3 ⁇ 2SiO 2 Quality grilled Consists of ceramics such as ligatures.
  • the ingot is manufactured in a predetermined shape by applying a conventionally known metal processing method such as rolling or punching.
  • a conventionally known metal processing method such as rolling or punching.
  • an appropriate organic binder, solvent, or the like is added to and mixed with the raw material powder to form a paste.
  • This paste is made into a ceramic green sheet by the doctor blade method or the calender roll method, etc., and then, appropriate punching is performed on the ceramic green sheet, and a plurality of these are laminated and fired at a high temperature of about 1600 ° C. Produced.
  • the substrate 11 has excellent corrosion resistance and wettability with the brazing material, specifically, a Ni layer having a thickness of 0.5 to 9 ⁇ m and a thickness of 0.5. It is preferable to deposit a gold (Au) layer of ⁇ 5 ⁇ m sequentially by a plating method.
  • a metallized layer such as W or Mo is formed as a base layer on the part to which the frame 12 is attached or the mounting portion 11a, and a thickness of 0.5 to A 9 ⁇ m Ni layer and a 0.5 to 5 ⁇ m thick Au layer are preferably deposited sequentially by plating.
  • the frame body 12 and the semiconductor element 16 can be firmly bonded and fixed to the upper surface of the base body 11 through a bonding material such as a brazing material or solder to the part to which the frame body 12 is attached or the mounting portion 11a. it can.
  • the frame 12 is joined to the base 11 by a high melting point metal brazing material such as Ag brazing or Ag—Cu brazing so as to surround the mounting portion 11 a, and is made of ceramic or metal like the base 11. Further, a mounting portion 12a of the input / output terminal 13 formed of a through hole or a notch is formed on a side portion of the frame body 12.
  • a high melting point metal brazing material such as Ag brazing or Ag—Cu brazing
  • the mounting portion 12a has a metal layer such as a metallized layer formed on the inner surface. This metal layer is grounded by being connected to the base body 11 and the frame body 12 or a ground conductor deposited on one of them.
  • the above-mentioned input / output terminal 13 is fitted and joined to the mounting portion 12a with a high melting point metal brazing material such as an Ag brazing material or an Ag-Cu brazing material.
  • a high melting point metal brazing material such as an Ag brazing material or an Ag-Cu brazing material.
  • the frame body 12 and the base body 11 are made of metal
  • the lower ground conductor, the upper ground conductor, and the side ground conductor of the input / output terminal 13 are connected to the metal frame body 12 and the base body 11 and grounded to form a case ground.
  • the frame body 12 and the base body 11 are made of ceramics
  • the lower ground conductor, the upper ground conductor, and the side ground conductor of the input / output terminal 13 are joined to the metal layer formed on the inner surface of the mounting portion 12a.
  • the input / output terminals 13 may be integrally laminated as a part of the frame 12.
  • FIG. 5 and 6 show an example of an optical semiconductor element package in which an optical fiber fixing member 14 is provided on the side surface of the frame 12 opposite to the input / output terminal 13.
  • the frame body 12 is provided with various input / output terminals in addition to the input / output terminals 13 as necessary.
  • the package according to the present invention includes the input / output terminal 13, the loss generated when a high-frequency signal is input / output can be suppressed and the transmission characteristic can be improved. Moreover, it can be excellent in airtightness.
  • the electrode of the semiconductor element 16 and the line conductor 4 and the ground conductor 6 are connected to a connecting means (not shown) such as a bonding wire. ), And a lead terminal made of a metal such as an Fe—Ni—Co alloy or a line conductor of a flexible substrate is connected to the line conductor 3 or the ground conductor 5 outside the package, or a conductive adhesive such as Ag solder or solder. Join through. Then, the semiconductor element 16 and the external electric circuit board are electrically connected via the input / output terminal 13.
  • a lid 17 made of Fe—Ni—Co alloy or the like is attached to the upper surface of the frame 12 by soldering or a seam weld method, so that the semiconductor element 16 is accommodated in the package. It becomes a semiconductor device as a product.
  • the lid body 17 may be attached to the upper surface of the frame body 12 via a seal ring.
  • Such a semiconductor device uses a package including the input / output terminal 13 according to the present invention. Therefore, the high-frequency signal transmission characteristics are good, the airtightness is excellent, and the highly reliable high output.
  • the semiconductor device can be made. Moreover, it can be made into a multifunctional thing provided with many line conductors 3 and 4 for inputting and outputting many high frequency signals.
  • the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.
  • it may be a high-frequency circuit board in which wide portions 3 a are formed at both ends of the line conductor 3.
  • a wide portion may be formed at the connection end of the line conductor 4. Further, the wide portion 3 a may be formed on both the line conductor 3 and the line conductor 4.
  • one wide portion 3a is formed at each connection end of the line conductor 3 and the line conductor 4, and when these are connected, a plurality of wide portions 3a are formed at the connection ends of both lines. It may be what you do.

Abstract

A high-frequency circuit board provided with a dielectric substrate (1) and line conductors (3). The line conductors (3) are formed on the surface of the dielectric substrate (1), and each line conductor (3) has a connection end at one end, said connection end having wide sections (3a) in which the line width has been widened, and a narrow section (3b) disposed between a plurality of the wide sections (3a). A high-frequency circuit board in which the tolerance range for the accuracy of alignment between line conductors to be connected is large, while an increase in the capacitance component at the connection end is suppressed.

Description

高周波回路基板ならびにこれを用いた高周波半導体パッケージおよび高周波半導体装置High frequency circuit board, high frequency semiconductor package and high frequency semiconductor device using the same
　本発明は、高周波信号が伝送される信号線路が形成された高周波回路基板に関し、特に信号線路同士の接続部に特徴を有する高周波回路基板、これを用いた高周波半導体パッケージおよび高周波半導体装置に関する。 The present invention relates to a high-frequency circuit board on which a signal line for transmitting a high-frequency signal is formed, and more particularly to a high-frequency circuit board characterized by a connection portion between signal lines, a high-frequency semiconductor package and a high-frequency semiconductor device using the same.
　マイクロ波帯やミリ波帯等の高周波信号線路同士を接続する際は、２本の信号線路同士を一直線に配置して接続するのが好ましい。しかしながら、実際は、信号線路同士を一直線上に精確に並べて接続するのは容易なことではない。 When connecting high-frequency signal lines such as a microwave band and a millimeter wave band, it is preferable to connect the two signal lines in a straight line. However, in practice, it is not easy to connect the signal lines accurately in a straight line.
　従来、線路導体の接続端に線路導体よりも幅の広い接続パッドを設ける方法がよく用いられる（例えば、特許文献１参照）。接続パッドは、信号線路同士の位置が食い違い、精確に一直線に並んでいない信号線路同士を導通させる。 Conventionally, a method of providing a connection pad wider than the line conductor at the connection end of the line conductor is often used (see, for example, Patent Document 1). The connection pad makes the positions of the signal lines inconsistent and makes the signal lines that are not accurately aligned in a conductive state.
　図８に示すように、第１の信号線路１００の端部に第１の接続パッド１０１が設けられ、第２の信号線路１０２の端部には第２の接続パッド１０３が設けられている。そして、第１の線路導体１００と第２の線路導体１０２とは、ボンディングワイヤ等の接続線路１０４を介して接続される。 As shown in FIG. 8, a first connection pad 101 is provided at the end of the first signal line 100, and a second connection pad 103 is provided at the end of the second signal line 102. The first line conductor 100 and the second line conductor 102 are connected via a connection line 104 such as a bonding wire.
　図８に於いては、第１の信号線路１００と接続線路１０４と第２の信号線路１０２とが一直線上に並ぶように配置されている。しかし、これらが一直線上に配置されなかった場合には、例えば、接続線路１０４が第１の信号線路１０１および第２の信号線路１０２の中心線から外れた位置に配置された場合、第１の信号線路１００と第２の信号線路１０２とは接続線路１０４を介して導通が取れなくなってしまう場合がある。 In FIG. 8, the first signal line 100, the connection line 104, and the second signal line 102 are arranged in a straight line. However, when these are not arranged on a straight line, for example, when the connection line 104 is arranged at a position off the center line of the first signal line 101 and the second signal line 102, the first line There is a case where the signal line 100 and the second signal line 102 cannot be electrically connected via the connection line 104.
　ところが、第１の接続パッド１０１および第２の接続パッド１０３が第１の信号線路１００および第２の信号線路１０２よりも広い幅で設けられているため、接続線路１０４の偏心が、これら第１の接続パッド１０１および第２の接続パッド１０３の幅以内であれば、第１の信号線路１００と第２の信号線路１０２とは接続される。 However, since the first connection pad 101 and the second connection pad 103 are provided with a width wider than that of the first signal line 100 and the second signal line 102, the eccentricity of the connection line 104 is caused by the first eccentricity. The first signal line 100 and the second signal line 102 are connected to each other within the width of the connection pad 101 and the second connection pad 103.
特開２０１２－１８６７２４号公報JP 2012-186724 A
　しかしながら、周波数が高い高周波信号を伝送する信号線路において、接続パッド１０１，１０３が配置される部分におけるインピーダンスは、高周波線路の特性インピーダンスとは異なる。それ故に、信号線路１００，１０２の伝送特性を劣化させる原因となってしまう。 However, in a signal line that transmits a high-frequency signal having a high frequency, the impedance at a portion where the connection pads 101 and 103 are arranged is different from the characteristic impedance of the high-frequency line. Therefore, the transmission characteristics of the signal lines 100 and 102 are deteriorated.
　従って、本発明は上記従来の問題点に鑑みて完成されたものであり、その目的は、高周波線路を接続する際に、著しいインピーダンス不整合を招来せずに、線路導体の接続を容易に行なえる線路導体を有する高周波回路基板、ならびにこれを用いた高周波半導体パッケージおよび高周波半導体装置を提供することにある。 Accordingly, the present invention has been completed in view of the above-described conventional problems, and the object of the present invention is to easily connect line conductors without causing a significant impedance mismatch when connecting high-frequency lines. An object of the present invention is to provide a high-frequency circuit board having a line conductor, a high-frequency semiconductor package and a high-frequency semiconductor device using the same.
　本発明の一実施形態に係る高周波回路基板は、一端に、他の接続導体の一端が接続される接続端を有している。そして、この接続端に、線幅が広い複数の幅広部と、複数の幅広部の間に配置された幅広部よりも線幅の狭い幅狭部とを有した線路導体を具備している。 The high-frequency circuit board according to an embodiment of the present invention has a connection end to which one end of another connection conductor is connected at one end. The connection end includes a line conductor having a plurality of wide portions having a wide line width and a narrow portion having a line width narrower than that of the wide portion disposed between the plurality of wide portions.
　また、本発明の一実施形態に係る高周波回路基板は、第１線路導体を有する第１誘電体基板と、第２線路導体を有する第２誘電体基板とが前記第１線路導体の一端と前記第２線路導体の一端とを重ねて積層された高周波回路基板である。高周波回路基板は、前記第１線路導体と前記第２線路導体とが重ねて接続された接続部を有する。そして、前記接続部は、線幅が広い複数の幅広部と、この幅広部の間に配置されたこの幅広部よりも線幅の狭い幅狭部とを有している。 The high-frequency circuit board according to an embodiment of the present invention includes a first dielectric substrate having a first line conductor and a second dielectric substrate having a second line conductor, the one end of the first line conductor and the first dielectric The high-frequency circuit board is formed by stacking one end of the second line conductor. The high-frequency circuit board has a connection portion in which the first line conductor and the second line conductor are connected in an overlapping manner. The connecting portion includes a plurality of wide portions having a wide line width and a narrow portion having a line width narrower than the wide portions disposed between the wide portions.
　上記高周波回路基板において、前記幅広部は、前記線路導体から幅方向に離れるに従って前記線路導体の線路方向の幅が狭くなる形状を有してもよい。 In the high-frequency circuit board, the wide portion may have a shape in which the width of the line conductor in the line direction becomes narrower as the distance from the line conductor increases.
　また上記高周波回路基板において、前記幅狭部の線幅は、前記接続端または前記接続部を除く部分の前記線路導体の線幅よりも狭いものとしてもよい。 In the high-frequency circuit board, a line width of the narrow portion may be narrower than a line width of the line conductor in a portion excluding the connection end or the connection portion.
　また上記高周波回路基板において、前記線路導体は、前記接続端または前記接続部に隣接した位置に、線幅を狭くした第２幅狭部を有してもよい。 In the high-frequency circuit board, the line conductor may have a second narrow portion with a narrow line width at a position adjacent to the connection end or the connection portion.
　本発明の一実施形態に係る高周波半導体パッケージは、高周波半導体素子が収納される容器の入出力部に、上記いずれか１つの高周波回路基板が用いられていることを特徴とする。 A high-frequency semiconductor package according to an embodiment of the present invention is characterized in that any one of the above-described high-frequency circuit boards is used for an input / output part of a container in which a high-frequency semiconductor element is stored.
　本発明の一実施形態に係る高周波半導体装置は、上記高周波半導体パッケージと、前記容器内に収納され、前記高周波回路基板の前記線路導体に接続された高周波半導体素子とを有することを特徴とする。 A high-frequency semiconductor device according to an embodiment of the present invention includes the high-frequency semiconductor package, and a high-frequency semiconductor element housed in the container and connected to the line conductor of the high-frequency circuit board.
　本発明の一実施形態に係る高周波回路基板は、接続端に、線幅が広い複数の幅広部と、複数の幅広部の間に配置された幅広部よりも線幅の狭い幅狭部とを有した線路導体を具備していることから、接続する線路導体同士の位置精度の許容範囲を保ちながら、接続端の容量成分を少なくすることができ、線路導体に著しいインピーダンス不整合を生じないものとすることができる。 A high-frequency circuit board according to an embodiment of the present invention includes, at a connection end, a plurality of wide portions having a wide line width and a narrow portion having a narrower line width than the wide portion disposed between the plurality of wide portions. Because it has the line conductors it has, it can reduce the capacitance component of the connection end while maintaining the tolerance of the positional accuracy of the line conductors to be connected, and does not cause a significant impedance mismatch in the line conductors It can be.
　また、本発明の一実施形態に係る高周波回路基板は、第１線路導体と第２線路導体とが接続された接続部は、線幅が広い複数の幅広部と、この幅広部の間に配置された幅広部よりも線幅の狭い幅狭部とを有していることから、接続部に生じる容量成分が少なく、線路導体に著しいインピーダンス不整合が生じないようにすることができる。 In the high-frequency circuit board according to one embodiment of the present invention, the connection portion where the first line conductor and the second line conductor are connected is disposed between a plurality of wide portions having a wide line width and the wide portions. Since the narrow portion having a narrower line width than the wide portion formed is provided, the capacitance component generated in the connection portion is small, and a significant impedance mismatch can be prevented from occurring in the line conductor.
　上記高周波回路基板において、幅広部が、線路導体から幅方向に離れるに従って線路導体の線路方向の幅が狭くなる形状を有する場合、幅広部によって生じるインピーダンス不整合を少なくすることができる。 In the above high-frequency circuit board, when the wide portion has a shape in which the width in the line direction of the line conductor becomes narrower as the distance from the line conductor increases, impedance mismatch caused by the wide portion can be reduced.
　また上記高周波回路基板において、幅狭部の線幅を、線路導体の接続端または接続部を除く線路導体の線幅よりも狭い場合には、幅広部の容量成分によって生じるインピーダンス不整合を少なくすることができる。 In the high-frequency circuit board, when the line width of the narrow portion is narrower than the line width of the line conductor excluding the connection end or connection portion of the line conductor, impedance mismatch caused by the capacitance component of the wide portion is reduced. be able to.
　また上記高周波回路基板において、線路導体は、接続端または接続部の外側の幅広部に隣接した位置に、線幅を狭くした第２幅狭部を有する場合には、第２幅狭部のインピーダンスを高くし、幅広部における低いインピーダンスを補償して、線路方向のインピーダンス不整合を少なくすることができる。 In the high-frequency circuit board, when the line conductor has a second narrow part with a narrow line width at a position adjacent to the wide part outside the connection end or the connection part, the impedance of the second narrow part is obtained. Can be made high and the low impedance in the wide portion can be compensated to reduce impedance mismatch in the line direction.
　本発明の一実施形態に係る高周波半導体パッケージは、高周波半導体素子が収納される容器の入出力部に、上記いずれか１つの高周波回路基板が用いられていることから、高周波信号の入出力特性に優れた高周波半導体パッケージとすることができる。 In the high-frequency semiconductor package according to an embodiment of the present invention, since any one of the above-described high-frequency circuit boards is used in the input / output portion of the container in which the high-frequency semiconductor element is accommodated, the high-frequency signal input / output characteristics An excellent high-frequency semiconductor package can be obtained.
　本発明の一実施形態に係る高周波半導体装置は、上記高周波半導体パッケージと、容器内に収納され、高周波回路基板の線路導体に接続された高周波半導体素子とを有することから、高周波特性に優れた高周波装置とすることができる。 A high-frequency semiconductor device according to an embodiment of the present invention includes the high-frequency semiconductor package and a high-frequency semiconductor element housed in a container and connected to a line conductor of a high-frequency circuit board. It can be a device.
本発明の実施の形態の一例を示す高周波回路基板およびこれに接続される電気回路基板を示す分解斜視図である。It is a disassembled perspective view which shows the high frequency circuit board which shows an example of embodiment of this invention, and the electric circuit board connected to this. 表面に線路導体が形成された誘電体基板の配線パターンを示す平面図である。It is a top view which shows the wiring pattern of the dielectric substrate in which the line conductor was formed in the surface. 裏面に線路導体が形成された誘電体基板の配線パターンを示す透視平面図である。It is a perspective top view which shows the wiring pattern of the dielectric substrate in which the line conductor was formed in the back surface. 図２Ａの誘電体基板と図２Ｂの誘電体基板とを積層したものを示す透視平面図である。FIG. 2B is a perspective plan view showing a laminate of the dielectric substrate of FIG. 2A and the dielectric substrate of FIG. 2B. 線路導体の実施の形態の他の例を示す要部平面図である。It is a principal part top view which shows the other example of embodiment of a line conductor. 線路導体の実施の形態の他の例を示す要部平面図である。It is a principal part top view which shows the other example of embodiment of a line conductor. 線路導体の実施の形態の他の例を示す要部平面図である。It is a principal part top view which shows the other example of embodiment of a line conductor. 線路導体の実施の形態の他の例を示す要部平面図である。It is a principal part top view which shows the other example of embodiment of a line conductor. 線路導体の実施の形態の他の例を示す要部平面図である。It is a principal part top view which shows the other example of embodiment of a line conductor. 線路導体の実施の形態の他の例を示す要部平面図である。It is a principal part top view which shows the other example of embodiment of a line conductor. 線路導体の実施の形態の他の例を示す要部平面図である。It is a principal part top view which shows the other example of embodiment of a line conductor. 線路導体の実施の形態の他の例を示す要部平面図である。It is a principal part top view which shows the other example of embodiment of a line conductor. 線路導体の実施の形態の他の例を示す要部平面図である。It is a principal part top view which shows the other example of embodiment of a line conductor. 線路導体の実施の形態の他の例を示す要部平面図である。It is a principal part top view which shows the other example of embodiment of a line conductor. 線路導体の実施の形態のさらに他の例を示す要部平面図である。It is a principal part top view which shows the further another example of embodiment of a line conductor. 線路導体の実施の形態のさらに他の例を示す要部平面図である。It is a principal part top view which shows the further another example of embodiment of a line conductor. 本発明の高周波半導体パッケージの実施の形態の一例を示す分解斜視図である。It is a disassembled perspective view which shows an example of embodiment of the high frequency semiconductor package of this invention. 本発明の高周波半導体装置の実施の形態の一例を示す分解斜視図である。It is a disassembled perspective view which shows an example of embodiment of the high frequency semiconductor device of this invention. 本発明の一実施形態に係る高周波回路基板の反射損失をシミュレーションで求めた線図である。It is the diagram which calculated | required the reflection loss of the high frequency circuit board based on one Embodiment of this invention by simulation. 本発明の一実施形態に係る高周波回路基板の挿入損失をシミュレーションで求めた線図である。It is the diagram which calculated | required the insertion loss of the high frequency circuit board based on one Embodiment of this invention by simulation. 従来の高周波回路基板の例を示す平面図である。It is a top view which shows the example of the conventional high frequency circuit board.
　本発明の一実施形態に係る高周波回路基板について、以下に詳細に説明する。図１は高周波回路基板とこれに接続される電気回路基板との実施の形態の一例を示す分解斜視図である。 A high-frequency circuit board according to an embodiment of the present invention will be described in detail below. FIG. 1 is an exploded perspective view showing an example of an embodiment of a high-frequency circuit board and an electric circuit board connected thereto.
　高周波回路基板には、誘電体基板１の表面に線路導体３が形成されている。一方、電気回路基板には、誘電体基板２の裏面に線路導体４が形成されている。電気回路基板の線路導体４は誘電体基板２の裏面（図中、誘電体基板２の下面）に形成されている。図１において、線路導体４は誘電体基板２を透視した形で示されている。誘電体基板２は二点鎖線で示されている。線路導体４は線路導体３に接続される他の接続導体となる。 The line conductor 3 is formed on the surface of the dielectric substrate 1 in the high-frequency circuit board. On the other hand, a line conductor 4 is formed on the back surface of the dielectric substrate 2 in the electric circuit substrate. The line conductor 4 of the electric circuit board is formed on the back surface of the dielectric substrate 2 (the lower surface of the dielectric substrate 2 in the figure). In FIG. 1, the line conductor 4 is shown in a form seen through the dielectric substrate 2. The dielectric substrate 2 is indicated by a two-dot chain line. The line conductor 4 is another connection conductor connected to the line conductor 3.
　なお、誘電体基板１または誘電体基板２の表面に線路導体３または線路導体４が形成されることは必須なことではない。例えば、線路導体３または線路導体４が金属板様のもので形成され、誘電体基板１または誘電体基板２によって支持されていなくてもよい。 In addition, it is not essential that the line conductor 3 or the line conductor 4 is formed on the surface of the dielectric substrate 1 or the dielectric substrate 2. For example, the line conductor 3 or the line conductor 4 may be formed of a metal plate-like material and may not be supported by the dielectric substrate 1 or the dielectric substrate 2.
　そして、線路導体３は、線路導体４が接続される接続端に線路導体３の線幅よりも広い幅広部３ａが形成されている。接続端とは、線路導体３の一端であって、線路導体４の一端と重ねられて線路導体４と接続される部分である。接続端において、複数の幅広部３ａの間には幅広部３ａよりも幅の狭い幅狭部３ｂが形成されている。 The line conductor 3 has a wide portion 3a that is wider than the line width of the line conductor 3 at the connection end to which the line conductor 4 is connected. The connection end is one end of the line conductor 3 and is a portion that is overlapped with one end of the line conductor 4 and connected to the line conductor 4. At the connection end, a narrow portion 3b narrower than the wide portion 3a is formed between the plurality of wide portions 3a.
　図１において、幅広部３ａは、線路導体３の線路方向に沿って２つが隣接するように形成されている。幅広部３ａは、２以上の複数を隣接させるように形成され、それら幅広部３ａの間に幅狭部３ｂが形成される。このような接続端が接続パッドとして用いられる。接続端の容量成分を少なくする観点および接合力を確保する観点からは、幅広部３ａおよび幅狭部３ｂの数を多くし過ぎると不利になる傾向がある。 In FIG. 1, the wide part 3a is formed so that two may adjoin along the line direction of the line conductor 3. FIG. The wide portion 3a is formed so that two or more are adjacent to each other, and a narrow portion 3b is formed between the wide portions 3a. Such a connection end is used as a connection pad. From the viewpoint of reducing the capacitance component at the connection end and securing the bonding force, if the number of the wide portions 3a and the narrow portions 3b is excessively increased, it tends to be disadvantageous.
　線路導体４と線路導体３とは、線路導体４を線路導体３の接続端に重ねて、線路導体４と線路導体３とを銀（Ａｇ）ろう、金（Ａｕ）－錫（Ｓｎ）半田やＡｇエポキシ（Ａｇの金属粉末を含有するエポキシ樹脂）等の導電性接合材等で接合すればよい。接合位置に関しては、線路導体４の端が線路導体３の上記の一端と反対側に位置する他端側の一番奥に形成されている幅広部３ａと重なり合うように接合するのが好ましい。線路導体４の端が一番奥の幅広部３ａを超えて線路導体３に接合されてもよいが、好ましくは、一番奥の幅広部３ａの形成範囲内に線路導体４の端を配置するのがよい。 The line conductor 4 and the line conductor 3 are formed by superimposing the line conductor 4 on the connection end of the line conductor 3 and connecting the line conductor 4 and the line conductor 3 to silver (Ag) brazing, gold (Au) -tin (Sn) solder, What is necessary is just to join by electroconductive joining materials etc., such as Ag epoxy (epoxy resin containing the metal powder of Ag). As for the joining position, it is preferable that the end of the line conductor 4 is joined so as to overlap with the wide portion 3a formed at the innermost end on the other end side opposite to the one end of the line conductor 3. The end of the line conductor 4 may be joined to the line conductor 3 beyond the innermost wide portion 3a, but preferably the end of the line conductor 4 is disposed within the formation range of the innermost wide portion 3a. It is good.
　線路導体３に幅広部３ａが設けられているので、その分、線路導体４が線路導体３の中心からずれて配置されても線路導体４と線路導体３との導通を確保することができる。線路導体４の線路方向と線路導体３の線路方向とが平行ではなく、少し角度をもって配置されたとしても、線路導体３の両側に突出する幅広部３ａが接続端に少なくとも２つ設けられているので、導通を確保することができる。また、線路導体３と線路導体４との接続抵抗が大きくなり過ぎないように接続することができる。 Since the wide portion 3 a is provided in the line conductor 3, it is possible to ensure electrical connection between the line conductor 4 and the line conductor 3 even if the line conductor 4 is displaced from the center of the line conductor 3. Even if the line direction of the line conductor 4 and the line direction of the line conductor 3 are not parallel and are arranged at a slight angle, at least two wide portions 3a protruding on both sides of the line conductor 3 are provided at the connection end. Therefore, conduction can be ensured. Moreover, it can connect so that the connection resistance of the line conductor 3 and the line conductor 4 may not become large too much.
　この場合、線路導体３または線路導体４は、接地導体５，６等との間で容量成分を生ずる。ところが、線路導体３の接続端が複数の幅広部３ａに分けて形成されているとともに、複数の幅広部３ａの間には幅広部３ａよりも幅の狭い幅狭部３ｂが形成されているので、線路導体３の接続端における容量成分の増加を抑えることができる。 In this case, the line conductor 3 or the line conductor 4 generates a capacitance component between the ground conductors 5 and 6 and the like. However, the connection end of the line conductor 3 is formed by being divided into a plurality of wide portions 3a, and a narrow portion 3b narrower than the wide portion 3a is formed between the plurality of wide portions 3a. The increase in the capacitance component at the connection end of the line conductor 3 can be suppressed.
　次に、本発明の一実施形態に係る線路導体３，４を高周波用多層回路基板に用いた例について説明する。 Next, an example in which the line conductors 3 and 4 according to an embodiment of the present invention are used for a high-frequency multilayer circuit board will be described.
　図２Ａは、表面に線路導体４が形成された誘電体基板２を示す平面図である。図２Ｂは、裏面に線路導体３が形成された誘電体基板１を示す透視平面図である。線路導体３は誘電体基板１の裏面に形成されており、誘電体基板１を透視した状態の形状が示されている。誘電体基板１は二点鎖線で示されている。図２Ｃは、これら誘電体基板２に誘電体基板１を積層した状態を示す透視平面図である。誘電体基板１は二点鎖線で示されている。 FIG. 2A is a plan view showing a dielectric substrate 2 having a line conductor 4 formed on the surface thereof. FIG. 2B is a perspective plan view showing the dielectric substrate 1 having the line conductor 3 formed on the back surface. The line conductor 3 is formed on the back surface of the dielectric substrate 1, and the shape in a state where the dielectric substrate 1 is seen through is shown. The dielectric substrate 1 is indicated by a two-dot chain line. FIG. 2C is a perspective plan view showing a state in which the dielectric substrate 1 is laminated on the dielectric substrate 2. The dielectric substrate 1 is indicated by a two-dot chain line.
　誘電体基板１は第１誘電体基板１、線路導体３は第１線路導体３、誘電体基板２は第２誘電体基板２、線路導体４は第２線路導体４とも呼称するが、以下説明では、符合によって区別可能なので、単に誘電体基板１、線路導体３、誘電体基板２、線路導体４と記す。 The dielectric substrate 1 is also called the first dielectric substrate 1, the line conductor 3 is also called the first line conductor 3, the dielectric substrate 2 is also called the second dielectric substrate 2, and the line conductor 4 is also called the second line conductor 4. Then, since they can be distinguished by the signs, they are simply referred to as dielectric substrate 1, line conductor 3, dielectric substrate 2, and line conductor 4.
　かかる高周波回路基板は、図２Ｃに示すように、線路導体３を有する誘電体基板１と線路導体４を有する誘電体基板２とが、線路導体３の一端と線路導体４の一端とを重ね合わせて積層されたものである。すなわち高周波回路基板は、線路導体３，４が、積層された誘電体基板１および誘電体基板２の層間に形成されている。一本に繋ぎ合わされた線路導体３，４は、線路導体３と線路導体４とが接続された接続部を有する。接続部は、線路導体３の一端と線路導体４の一端とが重ねられて、互いに接続されている部分である。接続部には線幅が広い複数の幅広部３ａと、幅広部３ａの間に配置された幅広部３ａよりも線幅の狭い幅狭部３ｂとが形成されている。 As shown in FIG. 2C, such a high-frequency circuit board includes a dielectric substrate 1 having a line conductor 3 and a dielectric substrate 2 having a line conductor 4 that overlap one end of the line conductor 3 and one end of the line conductor 4. Are stacked. That is, in the high-frequency circuit board, the line conductors 3 and 4 are formed between the laminated dielectric substrate 1 and dielectric substrate 2. The line conductors 3 and 4 connected to each other have a connection portion to which the line conductor 3 and the line conductor 4 are connected. The connection portion is a portion where one end of the line conductor 3 and one end of the line conductor 4 are overlapped and connected to each other. A plurality of wide portions 3a having a wide line width and a narrow portion 3b having a narrower line width than the wide portion 3a disposed between the wide portions 3a are formed in the connection portion.
　線路導体３は、接続部に幅広部３ａを有しているので、誘電体基板１と誘電体基板２とを積層する際に多少の積層ずれが生じたとしても、線路導体３と線路導体４とを導通させることができる。 Since the line conductor 3 has the wide portion 3a at the connecting portion, even if a slight misalignment occurs when the dielectric substrate 1 and the dielectric substrate 2 are laminated, the line conductor 3 and the line conductor 4 Can be conducted.
　しかも、接続端に一体の大きな接続パッドを形成するのに対し、複数の幅広部３ａを設けて導通を確保している。複数の幅広部３ａの間には幅狭部３ｂが配置されているので、接続部の容量成分を小さくすることができ、線路導体３および線路導体４で形成される高周波線路上の大きなインピーダンス不整合を来さないようにすることができる。 Moreover, in contrast to forming a large connection pad integrally formed at the connection end, a plurality of wide portions 3a are provided to ensure conduction. Since the narrow portion 3b is disposed between the plurality of wide portions 3a, the capacitance component of the connection portion can be reduced, and a large impedance difference on the high-frequency line formed by the line conductor 3 and the line conductor 4 can be obtained. It is possible to prevent alignment.
　図７Ａは、図２に示す高周波回路基板の反射損失をシミュレーションした結果をプロットした線図である。破線は、図８に示されるような従来の四角形の接続パッドを介して線路導体を接続した場合の反射損失を示す。また、実線は、本発明の一実施形態に係る高周波回路基板の反射損失を示す。接続部に幅広部３ａと幅狭部３ｂとを配置した実線で示されるシミュレーション結果の方が、反射損失が少ないことが判る。 FIG. 7A is a diagram in which the result of simulating the reflection loss of the high-frequency circuit board shown in FIG. 2 is plotted. The broken line shows the reflection loss when the line conductor is connected through the conventional rectangular connection pad as shown in FIG. The solid line indicates the reflection loss of the high-frequency circuit board according to the embodiment of the present invention. It can be seen that the simulation result indicated by the solid line in which the wide portion 3a and the narrow portion 3b are arranged in the connection portion has less reflection loss.
　図７Ｂは、同様にして求めた挿入損失のシミュレーション結果を示す線図である。破線で示される従来のものに比べ、実線で示される本発明の一実施形態に係る高周波回路基板の方が、挿入損失が少ないことが判る。 FIG. 7B is a diagram showing a simulation result of insertion loss obtained in the same manner. It can be seen that the insertion loss is lower in the high-frequency circuit board according to the embodiment of the present invention indicated by the solid line than in the conventional one indicated by the broken line.
　図１および図２に示す線路導体３は、図３Ａ，図３Ｂ，図３Ｃ，図３Ｄ，図３Ｅ，図３Ｆ，図３Ｇ，図３Ｈ，図３Ｉ，図３Ｊに示すように、様々な形状のものとすることができる。図３Ａは、幅広部３ａを２つ設けた場合を示す。図３Ｂは、複数の幅広部３ａを、２つより多く（４つ）設けた場合を示す。 The line conductor 3 shown in FIGS. 1 and 2 has various shapes as shown in FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I, and 3J. Can be. FIG. 3A shows a case where two wide portions 3a are provided. FIG. 3B shows a case where a plurality of (four) wide portions 3a are provided.
　図３Ｃ，図３Ｄは、それぞれの幅広部３ａの幅を異ならせた場合を示す。図３Ｃは、先端側（図中左側）の幅広部３ａを後端側（図中右側）の幅広部３ａよりも広い幅とした場合を示す。図３Ｄは、逆に先端側の幅広部３ａよりも後端側の幅広部３ａの幅を広くした場合を示す。 3C and 3D show cases where the widths of the wide portions 3a are made different. FIG. 3C shows a case where the wide portion 3a on the front end side (left side in the drawing) is wider than the wide portion 3a on the rear end side (right side in the drawing). FIG. 3D shows a case where the width of the wide portion 3a on the rear end side is made wider than that of the wide portion 3a on the front end side.
　また、図３Ｅ，図３Ｆ，図３Ｇ，図３Ｈ，図３Ｉ，図３Ｊは、幅広部３ａの形状を線路導体３から線路導体３の幅方向に離れるに従って、線路導体３の線路方向の幅が狭くなるように形成する各例を示すものである。幅広部３ａの形状は、線路導体３のエッジから離れるに従って、直線状，曲線状またはその組合せ等、いずれでもよい。長方形の幅広部３ａとした場合に比べて、線路導体３の線路方向に対して幅広部３ａのエッジが直角に交わらず鈍角で交わることになる。鈍角で交わることによって、幅広部３ａが設けられた部位におけるインピーダンスの変化を緩やかなものにすることができる。 3E, FIG. 3F, FIG. 3G, FIG. 3H, FIG. 3I, and FIG. 3J show that the width of the line conductor 3 in the line direction increases as the shape of the wide portion 3a increases from the line conductor 3 in the width direction of the line conductor 3. Each example is formed so as to be narrow. The shape of the wide portion 3a may be any of a linear shape, a curved shape, or a combination thereof as the distance from the edge of the line conductor 3 increases. Compared with the case of the rectangular wide portion 3a, the edges of the wide portion 3a intersect at an obtuse angle with respect to the line direction of the line conductor 3 instead of at right angles. By intersecting at an obtuse angle, the change in impedance at the site where the wide portion 3a is provided can be made gradual.
　図３Ｅは、２つの幅広部３ａの内、線路導体３の先端側から２つ目（右側）の幅広部３ａの辺を傾斜させた例を示す。幅広部３ａは、線路導体３の先端と反対側の辺が幅方向に離れるに従って線路導体３の先端側に傾斜している。 FIG. 3E shows an example in which the side of the second wide portion 3a (right side) from the front end side of the line conductor 3 is inclined among the two wide portions 3a. The wide portion 3a is inclined toward the front end side of the line conductor 3 as the side opposite to the front end of the line conductor 3 is separated in the width direction.
　図３Ｆは、２つの幅広部３ａの両方の辺を傾斜させた例を示す。両方の幅広部３ａは、線路導体３の先端と反対側の辺が幅方向に離れるに従って線路導体３の先端側に傾斜している。 FIG. 3F shows an example in which both sides of the two wide portions 3a are inclined. Both wide portions 3a are inclined toward the tip end side of the line conductor 3 as the side opposite to the tip end of the line conductor 3 is separated in the width direction.
　図３Ｇは、２つの幅広部３ａの内、線路導体３の先端側から２つ目（右側）の幅広部３ａにおいて、両方の辺を傾斜させた例を示す。幅広部３ａの線路導体３の先端側および後端側の両方の辺が、傾斜させて設けられている。 FIG. 3G shows an example in which both sides are inclined in the second wide portion 3a (right side) from the front end side of the line conductor 3 among the two wide portions 3a. Both the front end side and the rear end side of the line conductor 3 of the wide portion 3a are provided to be inclined.
　図３Ｈは、２つの幅広部３ａの内、線路導体３の先端側の幅広部３ａにおいて、両方の辺を傾斜させた例を示す。幅広部３ａの線路導体３の先端側および後端側の両方の辺が、傾斜させて設けられている。 FIG. 3H shows an example in which both sides are inclined in the wide portion 3a on the tip end side of the line conductor 3 among the two wide portions 3a. Both the front end side and the rear end side of the line conductor 3 of the wide portion 3a are provided to be inclined.
　図３Ｉは、２つの幅広部３ａの両方とも辺を傾斜させた例を示す。両方の幅広部３ａは、線路導体３の先端側および後端側の両方の辺が、傾斜させて設けられている。 FIG. 3I shows an example in which the sides of both of the two wide portions 3a are inclined. Both wide portions 3a are provided with both sides on the front end side and rear end side of the line conductor 3 inclined.
　図３Ｊは、２つの幅広部３ａの両方とも辺を半円状または円弧状に傾斜させた例を示す。両方の幅広部３ａは、線路導体３の先端側および後端側の両方の辺が、半円状または円弧状に傾斜させて設けられている。 FIG. 3J shows an example in which the sides of both of the two wide portions 3a are inclined in a semicircular shape or an arc shape. Both of the wide portions 3a are provided such that both the front end side and the rear end side of the line conductor 3 are inclined in a semicircular shape or an arc shape.
　また、図４Ａに示すように、複数の幅広部３ａに挟まれる幅狭部３ｂの線路導体３の線幅は、線路導体３の接続部を除く部分の線幅よりも狭く形成してもよい。幅広部３ａに挟まれる幅狭部３ｂは、線路導体４と重ねて接合されるので、導体量が多くなり、その分、容量成分が大きくなる傾向がある。線路導体３の線幅を狭くすることによって、この容量成分の増加を少なくすることができる。 Further, as shown in FIG. 4A, the line width of the line conductor 3 of the narrow portion 3b sandwiched between the plurality of wide portions 3a may be formed narrower than the line width of the portion excluding the connection portion of the line conductor 3. . Since the narrow portion 3b sandwiched between the wide portions 3a is overlapped and joined to the line conductor 4, the amount of the conductor increases, and the capacitance component tends to increase accordingly. By increasing the line width of the line conductor 3, the increase in the capacitance component can be reduced.
　なお、幅狭部３ｂの線幅とは、幅狭部３ｂにおける線路導体３の線路方向に対して直角な方向の長さ、すなわち線路導体３の幅を意味する。また、幅狭部３ｂにおいて、最小の幅の値を幅狭部３ｂの線幅という。一方、幅広部３ａの線幅とは、幅広部３ａにおいて最大の幅の値を幅広部３ａの線幅という。 Note that the line width of the narrow portion 3b means the length of the narrow portion 3b in the direction perpendicular to the line direction of the line conductor 3, that is, the width of the line conductor 3. In the narrow portion 3b, the minimum width value is referred to as the line width of the narrow portion 3b. On the other hand, the line width of the wide portion 3a refers to the maximum width value of the wide portion 3a as the line width of the wide portion 3a.
　また、図４Ｂに示すように、線路導体３の、幅広部３ａが形成される接続端または接続部に隣接する位置に、線路導体３の線幅を狭くした領域３ｃを設けてもよい。接続端または接続部では幅広部３ａが形成されて、容量成分が大きくなり、インピーダンスが低くなる。そこで、接続端または接続部の隣接する位置にインピーダンスの高い領域３ｃを配置すると、接続端または接続部におけるインピーダンスの低下を補償させることができる。そして線路導体３および線路導体４によって形成される高周波線路上のインピーダンス不整合を緩和することができる。領域３ｃ部分の線幅は、例えば接続端または接続部から離れた線路導体３の線幅の７０～８０％の幅とすればよい。 Further, as shown in FIG. 4B, a region 3c in which the line width of the line conductor 3 is narrowed may be provided at a connection end of the line conductor 3 where the wide portion 3a is formed or a position adjacent to the connection portion. A wide portion 3a is formed at the connection end or the connection portion, the capacitance component is increased, and the impedance is decreased. Therefore, if the high impedance region 3c is arranged at a position adjacent to the connection end or the connection portion, it is possible to compensate for a decrease in impedance at the connection end or the connection portion. And the impedance mismatch on the high frequency line formed by the line conductor 3 and the line conductor 4 can be reduced. The line width of the region 3c may be 70 to 80% of the line width of the line conductor 3 away from the connection end or connection portion, for example.
　同様に、線路導体４においても、接続端または接続部に隣接する位置に線路導体４の線幅を狭くした導体領域４ｃを設けておくのがよい。領域３ｃまたは領域４ｃを、幅広部３ａの間の幅狭部３ｂに対して第２幅狭部とも呼称する。 Similarly, in the line conductor 4, it is preferable to provide a conductor region 4c in which the line width of the line conductor 4 is narrowed at a position adjacent to the connection end or the connection portion. The region 3c or the region 4c is also referred to as a second narrow portion with respect to the narrow portion 3b between the wide portions 3a.
　なお、図１，図２Ａ，図２Ｂ，図２Ｃにおいて、線路導体３および線路導体４の両側には、所定距離を隔てて線路導体３および線路導体４と平行に接地導体５，６が近接配置されている。線路導体３および線路導体４は、いわゆるコプレーナ線路として動作する。 In FIG. 1, FIG. 2A, FIG. 2B, and FIG. 2C, ground conductors 5 and 6 are arranged close to each other on both sides of the line conductor 3 and the line conductor 4 in parallel with the line conductor 3 and the line conductor 4 at a predetermined distance. Has been. The line conductor 3 and the line conductor 4 operate as a so-called coplanar line.
　また、図には示していないが、誘電体基板１および誘電体基板２の線路導体３および線路導体４が形成されている面と反対側の面、または誘電体基板１および誘電体基板２の内層にも、接地導体を設ける場合がある。これによって、線路導体３および線路導体４は、いわゆるグランデッドコプレーナ線路として動作する。また、線路導体３および線路導体４は、マイクロストリップ線路としてもよい。 Although not shown in the drawing, the surface of the dielectric substrate 1 and the dielectric substrate 2 opposite to the surface on which the line conductor 3 and the line conductor 4 are formed, or the dielectric substrate 1 and the dielectric substrate 2. In some cases, a ground conductor is also provided on the inner layer. Thereby, the line conductor 3 and the line conductor 4 operate as a so-called grounded coplanar line. The line conductor 3 and the line conductor 4 may be microstrip lines.
　誘電体基板１または誘電体基板２は、アルミナ質焼結体や窒化アルミニウム質焼結体，ムライト質焼結体，ガラスセラミックス等のセラミックス、または、エポキシ樹脂、ポリイミドフィルム等の樹脂から選択された材料から成る。誘電体基板１または誘電体基板２から成る高周波回路基板は、このようなセラミック基板、ガラスエポキシ基板、またはフレキシブル基板（ＦＰＣ）として作製される。 The dielectric substrate 1 or the dielectric substrate 2 was selected from an alumina sintered body, an aluminum nitride sintered body, a mullite sintered body, ceramics such as glass ceramics, or a resin such as an epoxy resin or a polyimide film. Made of material. The high-frequency circuit board composed of the dielectric substrate 1 or the dielectric substrate 2 is manufactured as such a ceramic substrate, a glass epoxy substrate, or a flexible substrate (FPC).
　誘電体基板１または誘電体基板２がセラミックスから成る場合には、線路導体３，４および接地導体５，６は、例えばメタライズ法による金属導体層により形成される。 When the dielectric substrate 1 or the dielectric substrate 2 is made of ceramics, the line conductors 3 and 4 and the ground conductors 5 and 6 are formed by a metal conductor layer by, for example, a metallization method.
　例えば、まず、図１，図２Ｂに示されるように、線路導体３と接地導体５とが誘電体基板１に形成される場合であれば、誘電体基板１となるセラミックグリーンシートの裏面に線路導体３および接地導体５となるタングステン（Ｗ），モリブデン（Ｍｏ），マンガン（Ｍｎ）等から成る金属ペーストをスクリーン印刷法によって印刷塗布する。誘電体基板２も同様に、その表面に線路導体４および接地導体６となるＷ，Ｍｏ，Ｍｎ等から成る金属ペーストをスクリーン印刷法によって印刷塗布する。 For example, as shown in FIG. 1 and FIG. 2B, first, if the line conductor 3 and the ground conductor 5 are formed on the dielectric substrate 1, the line is formed on the back surface of the ceramic green sheet to be the dielectric substrate 1. A metal paste made of tungsten (W), molybdenum (Mo), manganese (Mn) or the like to be the conductor 3 and the ground conductor 5 is applied by screen printing. Similarly, the dielectric substrate 2 is printed with a metal paste made of W, Mo, Mn or the like to be the line conductor 4 and the ground conductor 6 on the surface by screen printing.
　次に、図２Ｃに示す積層された高周波回路基板とする場合は、誘電体基板１となるセラミックグリーンシートの線路導体３となる金属ペーストの接続端と誘電体基板２となるセラミックグリーンシートの線路導体４となる金属ペーストの一端とが重なるようにして誘電体基板１および誘電体基板２となるセラミックグリーンシート同士を上下に重ねあわせる。その他配線層があれば、それら配線層が形成されたセラミックグリーンシートをさらに重ねて、両面から圧力を加え、セラミックグリーンシート同士を圧着する。 Next, when the laminated high frequency circuit board shown in FIG. 2C is used, the connection end of the metal paste that becomes the line conductor 3 of the ceramic green sheet that becomes the dielectric substrate 1 and the line of the ceramic green sheet that becomes the dielectric substrate 2 The ceramic green sheets to be the dielectric substrate 1 and the dielectric substrate 2 are stacked one above the other so that one end of the metal paste to be the conductor 4 overlaps. If there are other wiring layers, the ceramic green sheets on which the wiring layers are formed are further stacked, pressure is applied from both sides, and the ceramic green sheets are pressed together.
　最後に、この積層体を高温炉に投入することによって、セラミックグリーンシートが焼成され、セラミック基板となる。同時に、金属ペーストが焼成されて線路導体３，４を有する高周波回路基板となる。 Finally, the ceramic green sheet is fired by putting this laminate into a high-temperature furnace to form a ceramic substrate. At the same time, the metal paste is fired to obtain a high-frequency circuit board having the line conductors 3 and 4.
　なお、線路導体３、接地導体５、線路導体４および接地導体６は、薄膜形成法によって形成されてもよく、その場合、線路導体３，４および接地導体５，６は窒化タンタル（Ｔａ２Ｎ），ニクロム（Ｎｉ－Ｃｒ合金），チタン（Ｔｉ），パラジウム（Ｐｄ），白金（Ｐｔ）等から形成され、誘電体基板１または誘電体基板２と成るセラミックグリーンシートを焼成した後にスパッタリング等の薄膜形成法により形成される。 The line conductor 3, the ground conductor 5, the line conductor 4 and the ground conductor 6 may be formed by a thin film forming method. In this case, the line conductors 3 and 4 and the ground conductors 5 and 6 are made of tantalum nitride (Ta 2 N ), Nichrome (Ni—Cr alloy), Titanium (Ti), Palladium (Pd), Platinum (Pt), etc., and after firing the ceramic green sheet to be the dielectric substrate 1 or the dielectric substrate 2, sputtering, etc. It is formed by a thin film forming method.
　また、誘電体基板１，２の表面に銅（Ｃｕ）等の箔をラミネートし、その後、Ｃｕ箔をエッチングして線路導体３，４等を形成してもよい。 Further, a foil such as copper (Cu) may be laminated on the surfaces of the dielectric substrates 1 and 2 and then the Cu foil may be etched to form the line conductors 3 and 4.
　以上により、誘電体基板１，２の間で高周波信号の伝送を行なうことが可能な高周波伝送用の回路基板を作製できる。 As described above, a circuit board for high frequency transmission capable of transmitting a high frequency signal between the dielectric substrates 1 and 2 can be manufactured.
　高周波回路基板の典型的な一例として、線路導体３の線幅は、０．１ｍｍ程度、幅広部３ａの幅は０．３ｍｍ程度、幅広部３ａの長さ（線路導体３の線路方向の）は０．０８～０．１ｍｍ程度、幅広部３ａの間の幅狭部３ｂの長さは０．２５ｍｍ程度である。幅広部３ａの長さは線路導体３を流れる高周波信号の波長の１０％以下とすれば、インピーダンス変化の影響を小さくすることができる。 As a typical example of the high-frequency circuit board, the line width of the line conductor 3 is about 0.1 mm, the width of the wide portion 3a is about 0.3 mm, and the length of the wide portion 3a (in the line direction of the line conductor 3) is The length of the narrow portion 3b between about 0.08 to 0.1 mm and the wide portion 3a is about 0.25 mm. If the length of the wide portion 3a is 10% or less of the wavelength of the high-frequency signal flowing through the line conductor 3, the influence of the impedance change can be reduced.
　次に、上記高周波回路基板を用いた高周波半導体パッケージ（以下、単にパッケージともいう）および高周波装置の一例について図５，図６に基づいて説明する。これら図は、それぞれ高周波半導体パッケージおよび高周波装置の実施の形態の一例を示す斜視図であり、１１は基体、１２は枠体、１３は入出力端子である。 Next, an example of a high-frequency semiconductor package (hereinafter also simply referred to as a package) and a high-frequency device using the above-described high-frequency circuit board will be described with reference to FIGS. These drawings are perspective views showing examples of embodiments of the high-frequency semiconductor package and the high-frequency device, respectively, 11 is a base, 12 is a frame, and 13 is an input / output terminal.
　パッケージは、上面の中央部に半導体素子が載置される載置部１１ａを有する基体１１と、この基体１１の上面に載置部１１ａを囲繞するように取着され、側部に形成された貫通孔または切欠きからなる入出力端子１３の取付部１２ａが形成された枠体１２と、取付部１２ａに嵌着された入出力端子１３とを具備している。 The package has a base 11 having a mounting portion 11a on which a semiconductor element is mounted at the center of the upper surface, and is attached to the upper surface of the base 11 so as to surround the mounting portion 11a, and is formed on a side portion. The frame body 12 in which the attaching part 12a of the input / output terminal 13 which consists of a through-hole or a notch was formed, and the input / output terminal 13 fitted by the attaching part 12a are comprised.
　入出力端子１３は複数のセラミックグリーンシートを積層して形成したものである。入出力端子１３のうち、第２層１３ａおよび第３層１３ｂがそれぞれ上述の誘電体基板２および誘電体基板１に相当し、第２層１３ａの上面に線路導体４および接地導体６が形成されている。第３層１３ｂの下面には、線路導体３および接地導体５が形成されている。他の層には、それぞれ接地導体層や他の線路導体パターンが形成されている。 The input / output terminal 13 is formed by laminating a plurality of ceramic green sheets. Of the input / output terminal 13, the second layer 13a and the third layer 13b correspond to the dielectric substrate 2 and the dielectric substrate 1, respectively, and the line conductor 4 and the ground conductor 6 are formed on the upper surface of the second layer 13a. ing. A line conductor 3 and a ground conductor 5 are formed on the lower surface of the third layer 13b. A ground conductor layer and other line conductor patterns are formed on the other layers, respectively.
　そして、これらセラミックグリーンシートを積層した後、高温で焼成すると入出力端子１３が完成する。なお、焼成後において積層された入出力端子１３は一体のものとなる。図５において層間として示した破線は便宜上のものである。 Then, after laminating these ceramic green sheets, firing at a high temperature completes the input / output terminal 13. Note that the input / output terminals 13 stacked after firing are integrated. The broken lines shown as layers in FIG. 5 are for convenience.
　また、線路導体３，線路導体４，接地導体５，接地導体６等の金属導体層の露出する表面には、ニッケル（Ｎｉ）や金（Ａｕ）等の耐食性に優れる金属を１～２０μｍ程度の厚さで被着させておくとよい。これら金属導体の酸化腐食を防止する。また、線路導体３と外部高周波線路（図示せず）との接続、および電子部品１６と線路導体４とのボンディングワイヤ等の電気的接続手段を介しての接続を容易にする。従って、金属導体層の露出表面には、例えば、厚さ０．５μｍ～１０μｍのＮｉメッキ層と厚さ０．１～５μｍ程度のＡｕめっき層とが電解めっき法や無電解めっき法により順次被着されているのが好ましい。 Further, on the exposed surface of the metal conductor layer such as the line conductor 3, the line conductor 4, the ground conductor 5, and the ground conductor 6, a metal having excellent corrosion resistance such as nickel (Ni) or gold (Au) is about 1 to 20 μm. It is good to make it adhere by thickness. Prevents oxidative corrosion of these metal conductors. Further, the connection between the line conductor 3 and the external high-frequency line (not shown) and the connection between the electronic component 16 and the line conductor 4 via an electrical connection means such as a bonding wire are facilitated. Therefore, on the exposed surface of the metal conductor layer, for example, a Ni plating layer having a thickness of 0.5 μm to 10 μm and an Au plating layer having a thickness of about 0.1 to 5 μm are sequentially coated by an electrolytic plating method or an electroless plating method. Preferably it is worn.
　基体１１は、上面にＩＣ，ＬＳＩ，半導体レーザ（ＬＤ），フォトダイオード（ＰＤ）等の半導体素子を載置するための載置部１１ａを有している。図６では載置部１１ａを基体１１および枠体１２で囲まれる凹部の底面とした例を示した。載置部１１ａには、基体１１の上面にペルチェ素子や回路基板等の載置台１５を介して半導体素子１６を載置してもよい。 The base 11 has a mounting portion 11a on the top surface for mounting semiconductor elements such as IC, LSI, semiconductor laser (LD), photodiode (PD) and the like. FIG. 6 shows an example in which the mounting portion 11 a is a bottom surface of a recess surrounded by the base body 11 and the frame body 12. A semiconductor element 16 may be mounted on the mounting portion 11 a on the upper surface of the base 11 via a mounting table 15 such as a Peltier element or a circuit board.
　基体１１は、Ｆｅ－Ｎｉ－Ｃｏ合金，銅（Ｃｕ）－タングステン（Ｗ）合金等の金属、またはＡｌ２Ｏ３質焼結体，ＡｌＮ質焼結体，３Ａｌ２Ｏ３・２ＳｉＯ２質焼結体等のセラミックスから成る。 Base 11, Fe-Ni-Co alloy, copper (Cu) - tungsten (W) metal such as alloy, or Al 2 O 3 sintered material,, AlN sintered material, 3Al 2 O 3 · 2SiO 2 Quality grilled Consists of ceramics such as ligatures.
　基体１１が金属から成る場合は、そのインゴットに圧延加工や打ち抜き加工等の従来周知の金属加工法を施すことによって所定形状に製作される。一方、基体１１がセラミックスから成る場合は、その原料粉末に適当な有機バインダや溶剤等を添加混合してペースト状とする。このペーストをドクターブレード法やカレンダーロール法等によってセラミックグリーンシートとし、しかる後、このセラミックグリーンシートに適当な打ち抜き加工を施して、さらにこれらを複数枚積層し約1600℃の高温で焼成することによって作製される。 When the substrate 11 is made of metal, the ingot is manufactured in a predetermined shape by applying a conventionally known metal processing method such as rolling or punching. On the other hand, when the substrate 11 is made of ceramics, an appropriate organic binder, solvent, or the like is added to and mixed with the raw material powder to form a paste. This paste is made into a ceramic green sheet by the doctor blade method or the calender roll method, etc., and then, appropriate punching is performed on the ceramic green sheet, and a plurality of these are laminated and fired at a high temperature of about 1600 ° C. Produced.
　なお、基体１１が金属からなる場合は、その表面に耐蝕性に優れ、かつろう材との濡れ性に優れる金属、具体的には厚さ０．５～９μｍのＮｉ層と厚さ０．５～５μｍの金（Ａｕ）層とを順次めっき法により被着させておくのがよい。一方、基体１１がセラミックスから成る場合、枠体１２が取着される部位や載置部１１ａに、Ｗ，Ｍｏ等のメタライズ層を下地層として形成し、この表面に、厚さ０．５～９μｍのＮｉ層と厚さ０．５～５μｍのＡｕ層とを順次めっき法により被着させておくのがよい。これにより、枠体１２が取着される部位や載置部１１ａにろう材や半田等の接合材を介して、枠体１２や半導体素子１６を基体１１の上面に強固に接着固定することができる。 In the case where the substrate 11 is made of metal, the surface thereof has excellent corrosion resistance and wettability with the brazing material, specifically, a Ni layer having a thickness of 0.5 to 9 μm and a thickness of 0.5. It is preferable to deposit a gold (Au) layer of ˜5 μm sequentially by a plating method. On the other hand, when the substrate 11 is made of ceramics, a metallized layer such as W or Mo is formed as a base layer on the part to which the frame 12 is attached or the mounting portion 11a, and a thickness of 0.5 to A 9 μm Ni layer and a 0.5 to 5 μm thick Au layer are preferably deposited sequentially by plating. Accordingly, the frame body 12 and the semiconductor element 16 can be firmly bonded and fixed to the upper surface of the base body 11 through a bonding material such as a brazing material or solder to the part to which the frame body 12 is attached or the mounting portion 11a. it can.
　枠体１２は、基体１１上に載置部１１ａを囲繞するようにＡｇろう、Ａｇ－Ｃｕろう材等の高融点金属ろう材により接合されており、基体１１と同様にセラミックスまたは金属から成る。また、枠体１２の側部には、貫通孔または切欠きから成る入出力端子１３の取付部１２ａが形成されている。なお、枠体１２に基体１１と同じ材料を用いるとき、基体１１と枠体１２とは一体形成としてもよい。 The frame 12 is joined to the base 11 by a high melting point metal brazing material such as Ag brazing or Ag—Cu brazing so as to surround the mounting portion 11 a, and is made of ceramic or metal like the base 11. Further, a mounting portion 12a of the input / output terminal 13 formed of a through hole or a notch is formed on a side portion of the frame body 12. When the same material as that of the base body 11 is used for the frame body 12, the base body 11 and the frame body 12 may be integrally formed.
　取付部１２ａは、枠体１２および基体１１がセラミックスからなる場合には、内面にメタライズ層等の金属層が形成されている。この金属層は、基体１１および枠体１２またはこれらのうち一方に被着形成された接地導体に接続されて接地される。 When the frame 12 and the base body 11 are made of ceramics, the mounting portion 12a has a metal layer such as a metallized layer formed on the inner surface. This metal layer is grounded by being connected to the base body 11 and the frame body 12 or a ground conductor deposited on one of them.
　取付部１２ａには上述の入出力端子１３がＡｇろう、Ａｇ－Ｃｕろう材等の高融点金属ろう材により嵌着接合される。枠体１２および基体１１が金属からなる場合、入出力端子１３の下部接地導体、上部接地導体および側面接地導体は、金属製の枠体１２や基体１１に接続されて接地され、ケースグランドとなる。あるいは、枠体１２および基体１１がセラミックスからなる場合には、入出力端子１３の下部接地導体、上部接地導体および側面接地導体は、取付部１２ａの内面に形成された金属層に接合される。 The above-mentioned input / output terminal 13 is fitted and joined to the mounting portion 12a with a high melting point metal brazing material such as an Ag brazing material or an Ag-Cu brazing material. When the frame body 12 and the base body 11 are made of metal, the lower ground conductor, the upper ground conductor, and the side ground conductor of the input / output terminal 13 are connected to the metal frame body 12 and the base body 11 and grounded to form a case ground. . Alternatively, when the frame body 12 and the base body 11 are made of ceramics, the lower ground conductor, the upper ground conductor, and the side ground conductor of the input / output terminal 13 are joined to the metal layer formed on the inner surface of the mounting portion 12a.
　なお、枠体１２がセラミックスから成る場合は、入出力端子１３は枠体１２の一部として一体的に積層されてもよい。 In addition, when the frame 12 is made of ceramics, the input / output terminals 13 may be integrally laminated as a part of the frame 12.
　また、図５，図６は、入出力端子１３の反対側の枠体１２の側面に光ファイバ固定部材１４を設けた光半導体素子パッケージの例を示している。この例のように、枠体１２には、必要に応じて入出力端子１３の他に各種入出力端子が設けられる。 5 and 6 show an example of an optical semiconductor element package in which an optical fiber fixing member 14 is provided on the side surface of the frame 12 opposite to the input / output terminal 13. As in this example, the frame body 12 is provided with various input / output terminals in addition to the input / output terminals 13 as necessary.
　このような本発明のパッケージは、入出力端子１３を具備していることから、高周波信号が入出力される際に生じる損失を抑え、良好な伝送特性を有するものとできる。また、気密性に優れたものとすることができる。 Since the package according to the present invention includes the input / output terminal 13, the loss generated when a high-frequency signal is input / output can be suppressed and the transmission characteristic can be improved. Moreover, it can be excellent in airtightness.
　そして、このようなパッケージの載置部１１ａに載置台１５および半導体素子１６を載置した後、半導体素子１６の電極と線路導体４や接地導体６とをボンディングワイヤ等の接続手段（図示せず）を介して接続し、パッケージの外側の線路導体３や接地導体５にＦｅ－Ｎｉ－Ｃｏ合金等の金属からなるリード端子またはフレキシブル基板の線路導体等をＡｇろうまたは半田などの導電性接着材を介して接合する。そして、半導体素子１６と外部電気回路基板とを入出力端子１３を介して電気的に接続する。 Then, after placing the mounting table 15 and the semiconductor element 16 on the mounting part 11a of such a package, the electrode of the semiconductor element 16 and the line conductor 4 and the ground conductor 6 are connected to a connecting means (not shown) such as a bonding wire. ), And a lead terminal made of a metal such as an Fe—Ni—Co alloy or a line conductor of a flexible substrate is connected to the line conductor 3 or the ground conductor 5 outside the package, or a conductive adhesive such as Ag solder or solder. Join through. Then, the semiconductor element 16 and the external electric circuit board are electrically connected via the input / output terminal 13.
　次に、必要に応じて枠体１２の上面にＦｅ－Ｎｉ－Ｃｏ合金等から成る蓋体１７を半田付けやシームウエルド法等によって取着することにより、半導体素子１６がパッケージ内部に収納された製品としての半導体装置となる。なお、枠体１２の上面にシールリングを介して蓋体１７を取着してもよい。 Next, if necessary, a lid 17 made of Fe—Ni—Co alloy or the like is attached to the upper surface of the frame 12 by soldering or a seam weld method, so that the semiconductor element 16 is accommodated in the package. It becomes a semiconductor device as a product. The lid body 17 may be attached to the upper surface of the frame body 12 via a seal ring.
　このような本発明の半導体装置は、上記本発明の入出力端子１３を具備しているパッケージを用いていることから、高周波信号の伝送特性がよく、気密性に優れた信頼性の高い高出力な半導体装置とすることができる。また多数本の高周波信号を入出力するための多数の線路導体３，４を備えた多機能なものとすることができる。 Such a semiconductor device according to the present invention uses a package including the input / output terminal 13 according to the present invention. Therefore, the high-frequency signal transmission characteristics are good, the airtightness is excellent, and the highly reliable high output. The semiconductor device can be made. Moreover, it can be made into a multifunctional thing provided with many line conductors 3 and 4 for inputting and outputting many high frequency signals.
　なお、本発明は以上の実施の形態の例に限定されず、本発明の要旨を逸脱しない範囲内であれば種々の変更を行なうことは何等支障ない。例えば、線路導体３の両端に幅広部３ａを形成した高周波回路基板であってもよい。 It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. For example, it may be a high-frequency circuit board in which wide portions 3 a are formed at both ends of the line conductor 3.
　また、線路導体４と接続される線路導体３の一端に幅広部３ａを形成する代わりに、線路導体４の接続端に幅広部を形成してもよい。さらに、線路導体３および線路導体４の両方に幅広部３ａを形成してもよい。 Further, instead of forming the wide portion 3 a at one end of the line conductor 3 connected to the line conductor 4, a wide portion may be formed at the connection end of the line conductor 4. Further, the wide portion 3 a may be formed on both the line conductor 3 and the line conductor 4.
　またさらに、線路導体３および線路導体４の両方の接続端にそれぞれ１つずつ幅広部３ａを形成しておき、これらを接続したときに両線路の接続端に複数の幅広部３ａが形成されるようにしたものでもよい。 Furthermore, one wide portion 3a is formed at each connection end of the line conductor 3 and the line conductor 4, and when these are connected, a plurality of wide portions 3a are formed at the connection ends of both lines. It may be what you do.
　１，２：（第１，第２）誘電体基板
　３，４：（第１，第２）線路導体
　３ａ：幅広部
　３ｂ：幅狭部
　３ｃ，４ｃ：第２幅狭部
　５，６：接地導体
　１１：基板
　１２：枠体
　１３：入出力端子
　１４：光ファイバ取付部
　１５：載置台
　１６：半導体素子
　１７蓋体 1, 2: (first and second) dielectric substrates 3, 4: (first and second) line conductors 3a: wide portion 3b: narrow portion 3c, 4c: second narrow portion 5, 6: ground Conductor 11: Substrate 12: Frame 13: Input / output terminal 14: Optical fiber mounting portion 15: Mounting table 16: Semiconductor element 17 Lid

Claims (7)

  1. 一端に、他の接続導体の一端が接続される接続端を有し、該接続端に、線幅が広い複数の幅広部と、複数の該幅広部の間に配置された該幅広部よりも線幅の狭い幅狭部とを有した線路導体を具備する高周波回路基板。 One end has a connection end to which one end of another connection conductor is connected, and the connection end has a plurality of wide portions having a wide line width, and the wide portions disposed between the plurality of wide portions. A high-frequency circuit board including a line conductor having a narrow portion having a narrow line width.
  2. 第１線路導体を有する第１誘電体基板と第２線路導体を有する第２誘電体基板とが、前記第１線路導体の一端と前記第２線路導体の一端とを重ねて積層されて、前記第１線路導体と前記第２線路導体とが接続された接続部を有する線路導体を具備する高周波回路基板であって、前記接続部が、線幅が広い複数の幅広部と、該幅広部の間に配置された該幅広部よりも線幅の狭い幅狭部とを有していることを特徴とする高周波回路基板。 A first dielectric substrate having a first line conductor and a second dielectric substrate having a second line conductor are laminated with one end of the first line conductor and one end of the second line conductor being stacked, A high-frequency circuit board comprising a line conductor having a connection portion to which a first line conductor and the second line conductor are connected, wherein the connection portion includes a plurality of wide portions having a wide line width, and the wide portion A high-frequency circuit board having a narrow portion with a line width narrower than that of the wide portion disposed therebetween.
  3. 前記幅広部は、前記線路導体から幅方向に離れるに従って前記線路導体の線路方向の幅が狭くなる形状を有することを特徴とする請求項１または２記載の高周波回路基板。 The high-frequency circuit board according to claim 1, wherein the wide portion has a shape in which a width of the line conductor in a line direction becomes narrower as the distance from the line conductor increases in a width direction.
  4. 前記幅狭部の線幅は、前記接続端または前記接続部を除く部分の前記線路導体の線幅よりも狭いことを特徴とする請求項１乃至３のいずれか１つに記載の高周波回路基板。 4. The high-frequency circuit board according to claim 1, wherein a line width of the narrow part is narrower than a line width of the line conductor in a portion excluding the connection end or the connection part. 5. .
  5. 前記線路導体は、前記接続端または前記接続部に隣接した位置に、線幅を狭くした第２幅狭部を有することを特徴とする請求項１乃至４のいずれか１つに記載の高周波回路基板。 5. The high-frequency circuit according to claim 1, wherein the line conductor has a second narrow portion having a narrow line width at a position adjacent to the connection end or the connection portion. 6. substrate.
  6. 高周波半導体素子が収納される容器の入出力部に、請求項１乃至５のいずれか１つに記載の高周波回路基板が用いられていることを特徴とする高周波半導体パッケージ。 A high-frequency semiconductor package, wherein the high-frequency circuit board according to any one of claims 1 to 5 is used in an input / output portion of a container in which the high-frequency semiconductor element is stored.
  7. 請求項６記載の高周波半導体パッケージと、前記容器内に収納され、前記高周波回路基板の前記線路導体に接続された高周波半導体素子とを有することを特徴とする高周波半導体装置。 7. A high-frequency semiconductor device comprising: the high-frequency semiconductor package according to claim 6; and a high-frequency semiconductor element housed in the container and connected to the line conductor of the high-frequency circuit board.
PCT/JP2014/072149 2013-08-26 2014-08-25 High-frequency circuit board, high-frequency semiconductor package using same, and high-frequency semiconductor device WO2015029942A1 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017212451A1 (en) * 2016-06-10 2017-12-14 Te Connectivity Corporation Electrical contact pad for electrically contacting a connector
US9997868B1 (en) 2017-07-24 2018-06-12 Te Connectivity Corporation Electrical connector with improved impedance characteristics
US10263352B2 (en) 2016-06-10 2019-04-16 Te Connectivity Corporation Electrical contact pad for electrically contacting a connector
US10320099B2 (en) 2016-06-10 2019-06-11 Te Connectivity Corporation Connector with asymmetric base section

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0685341B2 (en) * 1991-09-27 1994-10-26 帝国通信工業株式会社 Flexible board terminal structure
JP2702245B2 (en) * 1988-11-04 1998-01-21 カスケード マイクロテック インコーポレーテッド Overlapping interface between coplanar transmission lines to allow longitudinal and width misalignment
EP1555712A1 (en) * 2004-01-13 2005-07-20 Alcatel High frequency mode converter

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01276901A (en) * 1988-04-28 1989-11-07 Matsushita Electric Ind Co Ltd Microwave transmission circuit device
JP4685614B2 (en) * 2005-12-06 2011-05-18 富士通オプティカルコンポーネンツ株式会社 Board and board module
JP4108099B2 (en) * 2006-04-06 2008-06-25 日本特殊陶業株式会社 Electronic component package

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2702245B2 (en) * 1988-11-04 1998-01-21 カスケード マイクロテック インコーポレーテッド Overlapping interface between coplanar transmission lines to allow longitudinal and width misalignment
JPH0685341B2 (en) * 1991-09-27 1994-10-26 帝国通信工業株式会社 Flexible board terminal structure
EP1555712A1 (en) * 2004-01-13 2005-07-20 Alcatel High frequency mode converter

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017212451A1 (en) * 2016-06-10 2017-12-14 Te Connectivity Corporation Electrical contact pad for electrically contacting a connector
US10128597B2 (en) 2016-06-10 2018-11-13 Te Connectivity Corporation Electrical contact pad for electrically contacting a connector
CN109315063A (en) * 2016-06-10 2019-02-05 泰连公司 Electrical contact pad for electrical contact connector
US10263352B2 (en) 2016-06-10 2019-04-16 Te Connectivity Corporation Electrical contact pad for electrically contacting a connector
US10320099B2 (en) 2016-06-10 2019-06-11 Te Connectivity Corporation Connector with asymmetric base section
CN109315063B (en) * 2016-06-10 2022-03-29 泰连公司 Electrical contact pad for electrical contact connector
US9997868B1 (en) 2017-07-24 2018-06-12 Te Connectivity Corporation Electrical connector with improved impedance characteristics

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