JP2009044870A - Charge-pump circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charge pump circuit which reduces influence by noise superimposed on a clock signal and outputs stable voltage by reducing overshooting or undershooting of the clock signal in a part affecting an output voltage. <P>SOLUTION: Current i3 flowing in an inverter INV3 is made small. Time required for rising a signal level of the clock signal CLK4 being an output signal of the inverter INV3 is made long. Rise of the clock signal CLK4 from low level to high level is made gentle, and unnecessary overshooting of output voltage Vout is reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a booster circuit and a negative voltage generation circuit using a charge pump circuit in a semiconductor integrated circuit.

Conventionally, a booster circuit is used as a means for obtaining a voltage higher than the positive power supply voltage, and a negative voltage generating circuit is used as a means for obtaining a voltage lower than the ground voltage GND. In the semiconductor field, a charge pump circuit that does not require an inductor that is difficult to integrate has been used.
In such a charge pump circuit, a circuit in which one switching element 101 and one capacitor 102 are combined as shown in FIG. 10 has a basic configuration, which is referred to as one stage.
In FIG. 10, when performing the boosting operation, the switching element 101 is in an open state when the clock signal CLK is at a high level, and the switching element 101 is in a short circuit state when the clock signal CLK is at a low level. When performing a negative voltage generation operation, the switching element 101 is short-circuited when the clock signal CLK is high level, and the switching element 101 is open when the clock signal CLK is low level.

  In the charge pump booster circuit, when the clock signal CLK having the amplitude VDD is input in a state where the power supply voltage VDD is input to the end A of the switching element 101 in the configuration of FIG. Only a voltage up to 2 × VDD can be output to the connection with the element 102. In order to obtain a higher voltage, the circuit of FIG. 10 is connected in series in N (N is an integer of 2 or more) stages to form an N-stage charge pump circuit.

FIG. 11 is a diagram illustrating an example of a charge pump type booster circuit having a two-stage configuration.
FIG. 11A shows a state when the clock signal CLK is at a high level and the clock signal CLKB obtained by inverting the signal level of the clock signal CLK is at a low level. FIG. 11B shows a state when the clock signal CLK is at a low level. The level indicates a state when the clock signal CLKB is at a high level. The power supply voltage VDD is input to the end A of the switching element 111, and the boosted voltage is output from the connection portion between the end D of the switching element 112 and the capacitor 114. As can be seen from FIG. 11, the switching element 111 and the switching element 112 perform contradictory switching.

  In the case of a charge pump type negative voltage generating circuit, FIG. 11 is as shown in FIG. 12A shows a state when the clock signal CLK is at a high level and the clock signal CLKB is at a low level, and FIG. 12B shows a state where the clock signal CLK is at a low level and the clock signal CLKB is at a high level. Shows the state. As can be seen from FIG. 12, the switching element 111 and the switching element 112 perform switching that is exactly the reverse of the case of FIG.

FIG. 13 is a diagram showing an example of a booster circuit constituted by a charge pump circuit using the operation principle of such a basic circuit (see, for example, Patent Document 1).
The booster circuit of FIG. 13 boosts the power supply voltage VDD input to the positive power supply terminal 121 and outputs it from the output terminal 122. φ1 is a positive phase clock signal and φ2 is a negative phase clock signal. It is. FIG. 14 is a diagram showing a specific circuit example for generating the clock signals φ1 and φ2 of FIG. 13, and FIG. 15 is a waveform example and output of each connection portion Pa to Pd in the charge pump circuit of FIG. FIG. 6 is a diagram illustrating a waveform example of a terminal 122.
In the booster circuit of FIGS. 13 and 14, boosting is performed by superimposing the voltage Vclk of the clock signal on the voltage signal received from the previous stage.

Such a voltage variation ΔV in the output voltage of the charge pump circuit can be expressed by the following equation (a) using the charge pump capacitance Ccp and the load capacitance Co if the influence of the parasitic capacitance is ignored.
ΔV = Ccp / (Ccp + Co) × Vclk (a)
From the equation (a), when the load capacitance Co is large, the influence of noise included in the clock voltage Vclk is reduced.

On the other hand, when the negative voltage generating circuit is formed using the charge pump circuit, the polarity of the diodes 123 to 127 in FIG. 14 may be changed and the input terminal IN may be connected to the ground voltage GND. The basic operation principle is the same as in FIG. 14, and in this case as well, when the load capacitance Co is large, the influence of noise included in the clock voltage Vclk is reduced.
Special table 2007-501599 gazette

However, it is difficult to realize a large load capacity in a semiconductor integrated circuit in which the area occupied by the element is limited. Therefore, when the load capacity is set to a small value, there is a problem that the output voltage of the charge pump circuit fluctuates due to noise included in the clock signal.
In the case of a booster circuit, the overshoot of the clock signal affects the voltage at the connection between the cathode of the diode and the capacitive element via the capacitive element, and in the case of the negative voltage generating circuit, the undershoot of the clock signal is affected. It affects the voltage at the connection between the cathode of the diode and the capacitive element via the capacitive element. Since the absolute value of such a voltage is set larger than the original value, there is an adverse effect from the viewpoint of the withstand voltage of the circuit.

In the case of FIG. 14, it is the clock signal output from the inverter 135 that directly affects the output voltage. The voltage of the connection portion Pd is a voltage obtained by superimposing the clock voltage of the clock signal output from the inverter 135 on the voltage input via the diode 126, and the voltage is output to the output terminal 122 via the diode 127. Therefore, the influence of noise superimposed on the clock voltage output from the inverter 135 is serious.
Further, in the case of FIG. 14, when the forward voltage of each of the diodes 123 to 127 is Vth, the voltage of the connection portion Pd that becomes the highest voltage is (5 × VDD−4 × Vth) in principle. When an overshoot occurs at the rising edge of the clock signal output from the inverter 135, the voltage of the connection portion Pd instantaneously becomes a value larger than (5 × VDD−4 × Vth), and a request for the withstand voltage of the capacitor 131 is made. It was even more demanding.

On the other hand, when the negative voltage generating circuit is formed by the charge pump circuit, the influence of the undershoot of the clock signal output from the inverter 135 on the voltage signal of the connection portion Pd via the capacitive element 131 becomes a particular problem.
As described above, when the transition of the clock voltage output from the inverter is steep due to the influence of the parasitic capacitance or the like, spike-like noise may be superimposed on the clock voltage, and the charge pump circuit may have an output terminal 122. There was a problem that spike noise was output.

  The present invention has been made to solve such problems, and reduces the influence of noise superimposed on the clock signal by reducing the overshoot or undershoot of the portion of the clock signal that affects the output voltage. An object of the present invention is to obtain a charge pump circuit that can output a stable voltage.

A charge pump circuit according to the present invention is a charge pump circuit that converts a voltage input to an input terminal into a predetermined voltage and outputs the voltage from an output terminal.
One or more switching elements connected in series between the input terminal and the output terminal;
A capacitive element that is charged / discharged by switching of the switching element, one end of which is connected to the output terminal of the corresponding switching element;
A clock signal generation circuit unit that generates a clock signal composed of a predetermined pulse signal and outputs the clock signal to the other end of the capacitive element;
With
The clock signal generation circuit unit makes a transition time of a signal level of a clock signal output to a capacitive element connected closest to the output terminal on the circuit to be a predetermined value or more.

  And a plurality of the switching elements and the respective capacitive elements provided corresponding to the respective switching elements, wherein the clock signal generation circuit unit is connected to the output terminal closest to the circuit. Each clock signal is generated such that the transition time of the signal level of the clock signal to be output to is longer than the clock signal to be output to the other capacitive elements.

  Further, the clock signal generation circuit unit outputs clock signals having signal levels opposite to those of adjacent capacitive elements on the circuit.

The clock signal generation circuit unit includes
A clock signal generation circuit that generates a predetermined clock signal and outputs the predetermined clock signal to a capacitive element provided corresponding to the switching element connected to the input terminal;
One or more inverters connected in series to the output terminal of the clock signal generating circuit, inverting the signal level of the input signal and outputting the inverted signal as a clock signal to the corresponding capacitive element;
With
In the final stage inverter, which is the inverter whose output terminal is connected to the capacitive element connected closest to the output terminal on the circuit, the transition time of the signal level of the output clock signal is input to another capacitive element. Longer than the clock signal.

The clock signal generation circuit unit includes
A clock signal generation circuit that generates a predetermined clock signal and outputs the generated clock signal to the corresponding capacitive element;
One or more inverters for generating an inverted clock signal obtained by inverting the signal level of the clock signal output from the clock signal generation circuit and outputting the inverted clock signal to the corresponding capacitive element;
With
In the final stage inverter, which is the inverter whose output terminal is connected to the capacitive element connected closest to the output terminal on the circuit, the transition time of the signal level of the output clock signal is input to another capacitive element. It may be longer than the clock signal.

The clock signal generation circuit unit includes
A clock signal generation circuit that generates a predetermined clock signal and outputs the generated clock signal to the corresponding capacitive element;
A first inverter that generates and outputs an inverted clock signal obtained by inverting the signal level of the clock signal output from the clock signal generation circuit;
One or more second inverters that invert the signal level of the clock signal from the clock signal generation circuit and output the inverted signal level to the corresponding capacitive element;
One or more third inverters that invert the signal level of the inverted clock signal from the first inverter and output it to the corresponding capacitive element;
With
Among the third inverters, the inverter at the final stage, which is an inverter whose output terminal is connected to the capacitive element connected closest to the output terminal on the circuit, has a transition time of the signal level of the output clock signal, You may make it become longer than the clock signal input into another capacitive element.

  In addition, a booster circuit that converts the positive voltage input to the input terminal into a predetermined voltage and outputs the voltage from the output terminal is formed.

In this case, the final stage inverter is
A PMOS transistor having a small channel width W / channel length L so that the rising of the clock signal to be output from the low level to the high level exceeds a predetermined time and connected between the positive power supply voltage and the output terminal; ,
An NMOS transistor connected between the output terminal and the negative power supply voltage, the control electrode being connected to the control electrode of the PMOS transistor and forming an input terminal;
Was made up of.

The final stage inverter is:
A PMOS transistor having a drain connected to the output terminal;
An NMOS transistor connected between the output terminal and the negative power supply voltage, the control electrode being connected to the control electrode of the PMOS transistor and forming an input terminal;
A constant current source connected between the positive side power supply voltage and the source of the PMOS transistor, which generates and outputs a constant current so that the rising of the clock signal to be output from the low level to the high level exceeds a predetermined time. When,
You may make it comprise.

The final stage inverter is:
A PMOS transistor having a drain connected to the output terminal;
An NMOS transistor having a control electrode connected to the control electrode of the PMOS transistor to form an input terminal, and a drain connected to an output terminal;
A first current connected between the positive side power supply voltage and the source of the PMOS transistor, which generates and outputs a constant current such that the rising of the clock signal to be output from the low level to the high level exceeds a predetermined time. A constant current source;
A second constant current source connected between the source of the NMOS transistor and a negative power supply voltage;
You may make it comprise.

  In addition, a negative voltage generation circuit that generates a predetermined negative voltage from the ground voltage input to the input terminal and outputs the negative voltage from the output terminal is formed.

In this case, the final stage inverter is
A PMOS transistor connected between the positive power supply voltage and the output terminal;
The channel width W / channel length L is formed small so that the falling of the output clock signal from the high level to the low level is longer than a predetermined time, and the control electrode is connected to the control electrode of the PMOS transistor so that the input terminal is connected. An NMOS transistor connected between the output terminal and the ground voltage which is the negative power supply voltage;
Was made up of.

The final stage inverter is:
A PMOS transistor connected between the positive power supply voltage and the output terminal;
An NMOS transistor having a control electrode connected to the control electrode of the PMOS transistor to form an input terminal, and a drain connected to an output terminal;
Connected between the source of the NMOS transistor and the ground voltage, which is the negative power supply voltage, to generate and output a constant current that causes the falling of the clock signal to be output from the high level to the low level for a predetermined time or more. A constant current source,
Was made up of.

The final stage inverter is:
A PMOS transistor having a drain connected to the output terminal;
An NMOS transistor having a control electrode connected to the control electrode of the PMOS transistor to form an input terminal, and a drain connected to an output terminal;
A first constant current source connected between a positive power supply voltage and a source of the PMOS transistor;
Connected between the source of the NMOS transistor and the ground voltage, which is the negative power supply voltage, to generate and output a constant current that causes the falling of the clock signal to be output from the high level to the low level for a predetermined time or more. A second constant current source,
Was made up of.

  Further, in place of the switching element, one or more diodes connected in series in the forward direction from the input terminal to the output terminal are used.

  Further, in place of the switching element, one or more diodes connected in series in the forward direction from the output terminal to the input terminal are used.

  According to the charge pump circuit of the present invention, since the transition time of the signal level of the clock signal output to the capacitive element connected closest to the output terminal side on the circuit is set to a predetermined value or more, the booster circuit Can be used to reduce output voltage overshoot, and when used as a negative voltage generating circuit, output voltage undershoot can be reduced.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a circuit example of the charge pump circuit according to the first embodiment of the present invention, and FIG. 2 is a waveform example and output terminals of each connection portion P1 to P4 in the charge pump circuit of FIG. It is the figure which showed the waveform example of OUT.
In FIG. 1, the charge pump circuit 1 forms a booster circuit that boosts the power supply voltage VDD input to the input terminal IN and outputs the boosted voltage as an output voltage Vout from the output terminal OUT.
The charge pump circuit 1 includes diodes D1 to D5, capacitive elements C1 to C4, inverters INV1 to INV3, and a clock signal generation circuit 2 that generates and outputs a predetermined clock signal CLK1. The inverters INV1 to INV3 and the clock signal generation circuit 2 constitute a clock signal generation circuit unit, and the inverter INV3 constitutes a final stage inverter.

  The diodes D1 to D5 are connected in series in the forward direction from the input terminal IN to the output terminal OUT, and one end of the capacitor C1 is connected to a connection part P1 between the cathode of the diode D1 and the anode of the diode D2, and The clock signal CLK1 is input to the other end and the input terminal of the inverter INV1, respectively. One end of the capacitor C2 is connected to the connection portion P2 between the cathode of the diode D2 and the anode of the diode D3, and the other end of the capacitor C2 and the input end of the inverter INV2 are respectively output signals of the inverter INV1, that is, the signal level of the clock signal CLK1. The clock signal CLK2 having the opposite phase is inverted.

  Similarly, one end of the capacitor C3 is connected to the connection portion P3 between the cathode of the diode D3 and the anode of the diode D4, and the output signal of the inverter INV2, that is, the clock signal CLK1 is connected to the other end of the capacitor C3 and the input end of the inverter INV3, respectively. The same phase clock signal CLK3 is input. Further, one end of the capacitor C4 is connected to a connection part P4 between the cathode of the diode D4 and the anode of the diode D5, and the output signal of the inverter INV3, that is, the clock signal CLK4 having a phase opposite to that of the clock signal CLK1 is connected to the other end of the capacitor C4. Have been entered.

In such a configuration, an unnecessary overshoot of the output voltage Vout is reduced by slowing the rising from the low level to the high level in the clock signal CLK4 that is the output signal of the inverter INV3. The clock voltage Vclk4, which is the voltage of the clock signal CLK4, is expressed by the following equation (1), where time is t, current flowing through the inverter INV3 is i3, and the capacitance of the capacitive element C4 is Ccp.
Vclk4 = i3 × t / Ccp (1)
From the equation (1), in order to moderate the rise of the clock signal CLK4 from the low level to the high level, the time t represented by t = (Vclk4 × Ccp) / i3 may be increased.

In order to increase the time t, it is conceivable to increase the capacitance Ccp. However, increasing the capacitance Ccp increases the chip area, which is not a good method. Although it is conceivable to increase the clock voltage Vclk4, this does not only increase the voltage fluctuation of the output voltage Vout, but also increases the overshoot superimposed on the clock signal CLK4. Absent.
For this reason, a method for reducing the current i3 and increasing the time required for the rising of the signal level of the clock signal CLK4 will be considered.

FIG. 3 is a diagram illustrating a circuit example of the inverter INV3.
In FIG. 3, the inverter INV3 includes a PMOS transistor M1 and an NMOS transistor M2 connected in series between the power supply voltage VDD and the ground voltage GND, and the gates of the PMOS transistor M1 and the NMOS transistor M2 are connected to each other. The section constitutes the input terminal of the inverter INV3, and the connection section between the PMOS transistor M1 and the NMOS transistor M2 constitutes the output terminal of the inverter INV3.
In such a configuration, in order to increase the rise time of the clock signal CLK4 that is the output signal of the inverter INV3, the PMOS transistor M1 may be formed so that the channel width W / channel length L is decreased. By doing so, the rising of the clock signal CLK4 from the low level to the high level can be moderated, and unnecessary overshoot of the output voltage Vout can be reduced.

FIG. 4 is a diagram illustrating another circuit example of the inverter INV3.
In FIG. 4, the inverter INV3 includes a constant current source 11, a PMOS transistor M11, and an NMOS transistor M12. A constant current source 11 is connected between the power supply voltage VDD and the source of the PMOS transistor M11, and an NMOS transistor M12 is connected between the drain of the PMOS transistor M11 and the ground voltage GND. The gates of the PMOS transistor M11 and the NMOS transistor M12 are connected to each other, and the connection portion forms the input end of the inverter INV3, and the connection portion of the PMOS transistor M11 and the NMOS transistor M12 forms the output end of the inverter INV3.

  In such a configuration, in order to increase the rise time of the clock signal CLK4 that is the output signal of the inverter INV3, the current supplied from the constant current source 11 may be reduced, and the constant current supplied from the constant current source 11 may be reduced. By setting the value in this way, the rise time of the clock signal CLK4 can be lengthened. In this way, the rising time of the clock signal CLK4 can be kept within a certain range. Although a resistor may be used in place of the constant current source 11, the variation in the rise time of the clock signal CLK4 increases.

  As described above, since the rising speed of the signal level of the clock signal CLK4 output from the inverter INV3 is reduced to reduce overshoot, the influence of noise superimposed on the clock signal is reduced and a stable voltage is reduced. Can be output.

Here, although the clock signals CLK1 to CLK4 are respectively generated in FIG. 1, the clock signal CLK1 and the clock signal CLK1B obtained by inverting the signal level of the clock signal CLK1 are generated, and the clock signal CLK3 of FIG. The clock signal CLK1B may be used as the signal CLK1 for the clock signals CLK2 and CLK4 of FIG. 1, and in this case, the charge pump circuit 1 of FIG. 1 becomes as shown in FIG. In FIG. 5, the same or similar parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted here, and only differences from FIG. 1 will be described.
5 differs from FIG. 1 in that the inverter INV2 in FIG. 1 is eliminated and the clock signal CLK1 is input to the connection portion between the input terminal of the inverter INV3 and the capacitor C3. The inverter INV3 in FIG. 5 is exactly the same as the inverter INV3 in FIG. 1. By doing so, the same effect as in the case of FIG. 1 can be obtained, and the number of inverters used can be reduced. it can.

On the other hand, in a charge pump circuit, the charge pump capacity may be increased in order to drive a large capacity load connected to the output terminal. However, if this is done, the drive capability of the inverter is not sufficient and the capacity element is supplied. There is a possibility that the voltage of the clock signal to be lowered is lowered and a sufficient boosting operation cannot be performed.
In order to solve such a problem, a circuit configuration as shown in FIG. 6 may be used. 6 that are the same as or similar to those in FIG. 1 are denoted by the same reference numerals, description thereof is omitted here, and only differences from FIG. 1 are described.
6 differs from FIG. 1 in that the inverters INV4 and INV5 are added and the connection of the input terminals in the inverters INV1 to INV3 in FIG. 1 is changed. The inverter INV5 serves as a first inverter, the inverters INV2 and INV4 serve as a second inverter, and the inverters INV1 and INV3 serve as a third inverter, respectively.

In FIG. 6, a clock signal CLK1 is input to each input terminal of inverters INV2, INV4, and INV5. The inverter INV5 inverts the signal level of the clock signal CLK1 to generate a clock signal CLK1B. The clock signal CLK1B is an inverter. The signals are input to the input terminals of INV1 and INV3, respectively. In addition, a capacitor C1 is connected between the output terminal of the inverter INV4 and the connection part P1.
In such a configuration, the inverters INV1, INV2, INV4, and INV5 each generate and output a clock signal having a short transition time, and the inverter INV3 in FIG. 6 is exactly the same as the inverter INV3 in FIG. By doing so, the same effect as in the case of FIG. 1 can be obtained, and the charge pump capacity can be increased in order to drive a large capacity load connected to the output terminal. In FIG. 6, the signal levels of the clock signals supplied to the capacitive elements C1 to C4 are inverted from those in FIG. 1, but the boosting operation is the same as in FIG.

  As described above, the charge pump circuit according to the first embodiment reduces the overshoot by reducing the rising speed of the signal level of the clock signal CLK4 output from the inverter INV3 when the booster circuit is formed. Therefore, it is possible to reduce the influence of noise superimposed on the clock signal and output a stable voltage.

Second embodiment.
In the first embodiment, the case where the charge pump circuit is used for the booster circuit has been described. However, the charge pump circuit according to the present invention may be used for the negative voltage generation circuit. The second embodiment of the present invention will be described.
FIG. 7 is a diagram illustrating a circuit example of the charge pump circuit according to the second embodiment of the present invention. In FIG. 7, the same or similar parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted here, and only differences from FIG. 1 will be described.
7 differs from FIG. 1 in that the polarities of the diodes D1 to D5 are changed, the input terminal IN is connected to the ground voltage GND, and the inverter INV3 in FIG. 1 is changed to the inverter INV3a. The charge pump circuit 1 in FIG. 1 is replaced with a charge pump circuit 1a.

In FIG. 7, the charge pump circuit 1a forms a negative voltage generating circuit that generates a predetermined negative voltage from the ground voltage GND input to the input terminal IN and outputs the negative voltage from the output terminal OUT as the output voltage -Vout.
The charge pump circuit 1a includes diodes D1 to D5, capacitive elements C1 to C4, inverters INV1, INV2, and INV3a, and a clock signal generation circuit 2. The inverter INV3a is a final stage inverter.
The diodes D1 to D5 are connected in series in the forward direction from the output terminal OUT to the input terminal IN. One end of the capacitor C1 is connected to a connection part P1 between the anode of the diode D1 and the cathode of the diode D2, and the capacitor C1 The clock signal CLK1 is input to the other end and the input terminal of the inverter INV1, respectively. One end of the capacitor C2 is connected to a connection portion P2 between the anode of the diode D2 and the cathode of the diode D3, and the clock signal CLK2 is input to the other end of the capacitor C2 and the input end of the inverter INV2.

  Similarly, one end of the capacitor C3 is connected to a connection portion P3 between the anode of the diode D3 and the cathode of the diode D4, and the clock signal CLK3 is input to the other end of the capacitor C3 and the input end of the inverter INV3a. Further, one end of the capacitor C4 is connected to a connection part P4 between the anode of the diode D4 and the cathode of the diode D5, and an output signal of the inverter INV3a, that is, a clock signal CLK4 having a phase opposite to that of the clock signal CLK1 is connected to the other end of the capacitor C4. Have been entered.

  In such a configuration, the unnecessary undershoot of the output voltage Vout is reduced by making the falling from the high level to the low level in the clock signal CLK4 that is the output signal of the inverter INV3a gentle. The circuit example of the inverter INV3a is the same as that of the inverter INV3 in FIG. 2, except that the channel width W / channel length L of the NMOS transistor M2 is formed to be small instead of the PMOS transistor M1. . By doing so, the rising of the clock signal CLK4 from the high level to the low level can be made gentle, and unnecessary undershoot of the output voltage Vout can be reduced.

FIG. 8 is a diagram showing another circuit example of the inverter INV3a. In FIG. 8, the same or similar parts as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted here, and only differences from FIG. 4 will be described.
8 is different from FIG. 4 in that the source of the PMOS transistor M11 is connected to the power supply voltage VDD and the constant current source 21 is connected between the source of the NMOS transistor M12 and the ground voltage GND. is there.

In such a configuration, in order to increase the falling time of the clock signal CLK4 that is the output signal of the inverter INV3a, the current supplied from the constant current source 21 may be reduced, and the constant current supplied from the constant current source 21 may be reduced. By setting the current value in this way, the falling time of the clock signal CLK4 can be lengthened. By doing so, the falling time of the clock signal CLK4 can be kept within a certain range. Although a resistor may be used instead of the constant current source 21, the variation in the falling time of the clock signal CLK4 becomes large.
FIG. 7 shows an example in which the negative voltage generating circuit is formed by the charge pump circuit having the circuit configuration of FIG. 1, but the negative voltage generating circuit is formed by the charge pump circuit having the circuit configuration of FIGS. In this case, the polarity of the diodes D1 to D5 may be changed and the input terminal IN may be connected to the ground voltage GND as in the case of FIG.

  As described above, in the charge pump circuit according to the second embodiment, when the negative voltage generation circuit is formed, the signal level falling speed of the clock signal CLK4 output from the inverter INV3a is reduced to cause undershoot. Since it is made to reduce, the influence by the noise superimposed on the clock signal can be reduced, and a stable voltage can be output.

  On the other hand, in each of the first and second embodiments, the inverters INV3 and INV3a may be a circuit as shown in FIG. 9, which is a combination of the circuits shown in FIGS. In FIG. 9, the constant current source 11 is connected between the power supply voltage VDD and the source of the PMOS transistor M11, and the constant current source 21 is connected between the source of the NMOS transistor M12 and the ground voltage GND. By doing so, the inverter INV3 when the booster circuit is formed by the charge pump circuit as in the first embodiment, and the negative voltage generation circuit is formed as the charge pump circuit as in the second embodiment. In this case, the inverter INV3a can be made the same circuit. That is, when the booster circuit is formed by the charge pump circuit as in the first embodiment, the current supplied from the constant current source 11 in FIG. 9 may be reduced, as in the second embodiment. When the negative voltage generating circuit is formed as the charge pump circuit, the current supplied from the constant current source 21 in FIG. 9 may be reduced.

  In each of the first and second embodiments, the charge pump circuit having a four-stage configuration has been described as an example. However, the present invention is not limited to this, and the one-stage configuration and the multi-stage configuration are used. This is applied to each charge pump circuit. In each of the first and second embodiments, a switching element may be used instead of the diodes D1 to D5. In this case, each switching element is generated by a clock signal input to the capacitive elements C1 to C4. Switching control may be performed, or switching control may be performed by a control signal input from an external control circuit.

It is the figure which showed the circuit example of the charge pump circuit in the 1st Embodiment of this invention. FIG. 2 is a diagram illustrating a waveform example of each connection portion and a waveform example of an output voltage in the charge pump circuit of FIG. 1. It is the figure which showed the circuit example of inverter INV3 of FIG. It is the figure which showed the other circuit example of the inverter INV3 of FIG. It is the figure which showed the other circuit example of the charge pump circuit in the 1st Embodiment of this invention. It is the figure which showed the other circuit example of the charge pump circuit in the 1st Embodiment of this invention. It is the figure which showed the circuit example of the charge pump circuit in the 2nd Embodiment of this invention. It is the figure which showed the circuit example of inverter INV3a of FIG. It is the figure which showed the other circuit example of inverter INV3 and INV3a. It is the figure which showed the circuit example of the conventional charge pump circuit. It is the figure which showed the circuit example of the conventional charge pump type | mold booster circuit. It is the figure which showed the circuit example of the conventional charge pump type negative voltage generation circuit. It is the figure which showed the circuit example of the booster circuit comprised with the conventional charge pump circuit. It is the figure which showed the specific circuit example of FIG. It is the figure which showed the example of a waveform of each connection part in the charge pump circuit of FIG. 14, and the example of a waveform of output voltage.

Explanation of symbols

1, 1a Charge pump circuit 2 Clock signal generation circuit D1-D5 Diode C1-C4 Capacitance element INV1-INV5, INV3a Inverter

Claims (16)

In the charge pump circuit that converts the voltage input to the input terminal to a predetermined voltage and outputs it from the output terminal,
One or more switching elements connected in series between the input terminal and the output terminal;
A capacitive element that is charged / discharged by switching of the switching element, one end of which is connected to the output terminal of the corresponding switching element;
A clock signal generation circuit unit that generates a clock signal composed of a predetermined pulse signal and outputs the clock signal to the other end of the capacitive element;
With
The charge pump circuit, wherein the clock signal generation circuit unit sets a transition time of a signal level of a clock signal output to a capacitive element connected closest to the output terminal on the circuit to a predetermined value or more.   A plurality of the switching elements and the respective capacitive elements provided corresponding to the respective switching elements, wherein the clock signal generation circuit unit outputs to the capacitive element connected closest to the output terminal on the circuit 2. The charge pump circuit according to claim 1, wherein each clock signal is generated such that a transition time of a signal level of the clock signal to be generated is longer than a clock signal output to another capacitor element.   3. The charge pump circuit according to claim 2, wherein the clock signal generation circuit unit outputs a clock signal having a signal level opposite to that of an adjacent capacitive element on the circuit. The clock signal generation circuit unit
A clock signal generation circuit that generates a predetermined clock signal and outputs the predetermined clock signal to a capacitive element provided corresponding to the switching element connected to the input terminal;
One or more inverters connected in series to the output terminal of the clock signal generating circuit, inverting the signal level of the input signal and outputting the inverted signal as a clock signal to the corresponding capacitive element;
With
In the final stage inverter, which is the inverter whose output terminal is connected to the capacitive element connected closest to the output terminal on the circuit, the transition time of the signal level of the output clock signal is input to another capacitive element. 4. The charge pump circuit according to claim 3, wherein the charge pump circuit is longer than the clock signal. The clock signal generation circuit unit
A clock signal generation circuit that generates a predetermined clock signal and outputs the generated clock signal to the corresponding capacitive element;
One or more inverters for generating an inverted clock signal obtained by inverting the signal level of the clock signal output from the clock signal generation circuit and outputting the inverted clock signal to the corresponding capacitive element;
With
In the final stage inverter, which is the inverter whose output terminal is connected to the capacitive element connected closest to the output terminal on the circuit, the transition time of the signal level of the output clock signal is input to another capacitive element. 4. The charge pump circuit according to claim 3, wherein the charge pump circuit is longer than the clock signal. The clock signal generation circuit unit
A clock signal generation circuit that generates a predetermined clock signal and outputs the generated clock signal to the corresponding capacitive element;
A first inverter that generates and outputs an inverted clock signal obtained by inverting the signal level of the clock signal output from the clock signal generation circuit;
One or more second inverters that invert the signal level of the clock signal from the clock signal generation circuit and output the inverted signal level to the corresponding capacitive element;
One or more third inverters that invert the signal level of the inverted clock signal from the first inverter and output it to the corresponding capacitive element;
With
Among the third inverters, the inverter at the final stage, which is an inverter whose output terminal is connected to the capacitive element connected closest to the output terminal on the circuit, has a transition time of the signal level of the output clock signal, 4. The charge pump circuit according to claim 3, wherein the charge pump circuit is longer than a clock signal input to another capacitor element.   7. The charge pump circuit according to claim 4, wherein the charge pump circuit comprises a booster circuit that converts the positive voltage input to the input terminal into a predetermined voltage and outputs the voltage from the output terminal. The final stage inverter is:
A PMOS transistor having a small channel width W / channel length L so that the rising of the clock signal to be output from the low level to the high level exceeds a predetermined time and connected between the positive power supply voltage and the output terminal; ,
An NMOS transistor connected between the output terminal and the negative power supply voltage, the control electrode being connected to the control electrode of the PMOS transistor and forming an input terminal;
The charge pump circuit according to claim 7, comprising: The final stage inverter is:
A PMOS transistor having a drain connected to the output terminal;
An NMOS transistor connected between the output terminal and the negative power supply voltage, the control electrode being connected to the control electrode of the PMOS transistor and forming an input terminal;
A constant current source connected between the positive side power supply voltage and the source of the PMOS transistor, which generates and outputs a constant current so that the rising of the clock signal to be output from the low level to the high level exceeds a predetermined time. When,
The charge pump circuit according to claim 7, comprising: The final stage inverter is:
A PMOS transistor having a drain connected to the output terminal;
An NMOS transistor having a control electrode connected to the control electrode of the PMOS transistor to form an input terminal, and a drain connected to an output terminal;
A first current connected between the positive side power supply voltage and the source of the PMOS transistor, which generates and outputs a constant current such that the rising of the clock signal to be output from the low level to the high level exceeds a predetermined time. A constant current source;
A second constant current source connected between the source of the NMOS transistor and a negative power supply voltage;
The charge pump circuit according to claim 7, comprising:   7. The charge pump circuit according to claim 4, wherein the charge pump circuit forms a negative voltage generation circuit that generates a predetermined negative voltage from the ground voltage input to the input terminal and outputs the negative voltage from the output terminal. The final stage inverter is:
A PMOS transistor connected between the positive power supply voltage and the output terminal;
The channel width W / channel length L is formed small so that the falling of the output clock signal from the high level to the low level is longer than a predetermined time, and the control electrode is connected to the control electrode of the PMOS transistor so that the input terminal is connected. An NMOS transistor connected between the output terminal and the ground voltage which is the negative power supply voltage;
The charge pump circuit according to claim 11, comprising: The final stage inverter is:
A PMOS transistor connected between the positive power supply voltage and the output terminal;
An NMOS transistor having a control electrode connected to the control electrode of the PMOS transistor to form an input terminal, and a drain connected to an output terminal;
Connected between the source of the NMOS transistor and the ground voltage, which is the negative power supply voltage, to generate and output a constant current that causes the falling of the clock signal to be output from the high level to the low level for a predetermined time or more. A constant current source,
The charge pump circuit according to claim 11, comprising: The final stage inverter is:
A PMOS transistor having a drain connected to the output terminal;
An NMOS transistor having a control electrode connected to the control electrode of the PMOS transistor to form an input terminal, and a drain connected to an output terminal;
A first constant current source connected between a positive power supply voltage and a source of the PMOS transistor;
Connected between the source of the NMOS transistor and the ground voltage, which is the negative power supply voltage, to generate and output a constant current that causes the falling of the clock signal to be output from the high level to the low level for a predetermined time or more. A second constant current source,
The charge pump circuit according to claim 11, comprising:   11. The charge pump circuit according to claim 7, wherein one or more diodes connected in series in a forward direction from the input terminal to the output terminal are used instead of the switching element. .   15. The charge pump circuit according to claim 11, 12, 13 or 14, wherein, instead of the switching element, one or more diodes connected in series in a forward direction from the output terminal to the input terminal are used. .

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