JPH11146634A - Charge pump circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to obtain a desired, stable charge up voltage. SOLUTION: Diodes 11a-11d are series connected between a power supply terminal 20 and a booster terminal 30, and the positive terminals of capacitors 12a, 12b, 12c are connected with the connecting points of the respective diodes. The outputs of signal inverter circuits 13, 14, 15 are connected with the negative terminals of the capacitors 12a, 12b, 12c, respectively. The signal inverter circuits 13, 14, 15 are series connected with one another in a ring to form a ring oscillator 100. Due to the oscillating operation of the ring oscillator 100, electric charges are moved from the capacitor 12a to the capacitor 12b, and further electric charges are moved from the capacitor 12b to the capacitor 12c. As a result, a boosted voltage is produced in the capacitor 12c.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge-up circuit that charges up a voltage supplied from the outside (for example, a power supply line) and outputs a charge-up voltage.

[0002]

2. Description of the Related Art FIG. 11 shows a configuration of a conventional charge pump circuit. The + terminal of the first capacitor 3 is connected to the power supply line 1 via the diode 2, and the + terminal of the second capacitor 5 is connected via the diode 4 from the connection point between the diode 2 and the + terminal of the capacitor 3. It is connected. The negative terminal of the capacitor 3 is connected to the output terminal of the oscillator 7 via the inverter 8, and the negative terminal of the capacitor 5 is
It is connected to the output terminal of the oscillator 7 via the inverters 9 and 10. The oscillator 7 outputs an oscillation signal (clock signal) having a constant frequency. Then, a boosted voltage is output from an output terminal 6 connected to a connection point between the diode 4 and the + terminal of the capacitor 5. The inverters 8 to 1
0 is constituted by a CMOS circuit.

In such a configuration, when the output of the oscillator 7 is at the high level, the output of the inverter 8 is at the low level, so that the positive side of the capacitor 3 is changed from the power supply line 1 to the power supply voltage level via the diode 2. Charged. When the output of the oscillator 7 changes from this state to a low level,
Since the output of the inverter 8 becomes high level, the minus side of the capacitor 3 becomes the power supply voltage, and the plus side of the capacitor 3 becomes
The drop voltage V of the diode 2 from the power supply voltage doubled
Charged up to the voltage minus _F.

When the output of the oscillator 7 is at a low level, the output of the inverter 10 is at a low level, so that the voltage on the + side of the capacitor 5 is reduced from the voltage on the + side of the capacitor 3 by the voltage drop V _F of the diode 4. If the voltage is lower than the subtracted voltage, the charge on the + side of the capacitor 3 flows to the + side of the capacitor 5 due to the rectifying action of the diode 4, and
The + side of the diode is the diode 2,
It is charged to the voltage drop 2 × voltage obtained by subtracting the V _F at 4.

Next, when the output of the oscillator 7 goes high, the output of the inverter 10 goes high, and the minus side of the capacitor 5 becomes the power supply voltage.
Side is charged up to the power supply voltage from 3 times the intended voltage minus the voltage drop 2 × V _F of the diode 2 and 4. This charged-up voltage is applied to the output terminal 6
From the load connected to it.

[0006]

In the conventional charge pump circuit described above, since the oscillator 7 is provided externally, there is a problem that it is difficult to obtain a stable desired charge-up voltage. For example, when the oscillation frequency of the oscillator 7 is high, the charging and discharging of the capacitors 3 and 5 cannot keep up, and the charge-up voltage does not reach a desired voltage.

The present invention has been made in view of the above problems, and has as its object to provide a stable and desired charge-up voltage.

[0008]

In order to achieve the above object, according to the first aspect of the present invention, there are provided first and second capacitors (12a, 12b) and first and second rectifiers (11a). , 11b), and the first capacitor (12
a) to one terminal side and the second capacitor (12
In the charge pump circuit which alternately charges one terminal side of b) and sets one terminal voltage of the second capacitor (12b) as a charge-up voltage, a plurality of signal inverting circuits (13 to 15) are ring-shaped. A ring oscillation circuit (100) connected in a cascade and performing an oscillation operation is provided, and the other terminal of the first capacitor (12a) is connected to the second capacitor (12
The characteristic feature is that the outputs of different signal inverting circuits in the plurality of signal inverting circuits are respectively connected to the other terminal of b).

In this case, a plurality of signal inverting circuits (13 to 1)
The output of the different signal inverting circuit in 5) is connected to the other terminal of the first capacitor (12a) and the second capacitor (1).
2b), the ring oscillation circuit (100) is connected to the first and second capacitors (1
An oscillation operation is performed in accordance with the charge / discharge operation of 2a, 12b). Therefore, a stable desired charge-up voltage can be obtained.

In this case, a signal is transmitted from the ring oscillation circuit (100) in the direction from the first signal inversion circuit (13) to the second signal inversion circuit (14). The first capacitor (12a) is connected to the output of the first signal inverting circuit (13) to the other terminal of the first capacitor (12a).
Can be connected to the output of the second signal inverting circuit (14).

Further, according to the third aspect of the present invention, the ring oscillation circuit (100) is oscillated by transmitting a signal from the first signal inversion circuit (14) to the second signal inversion circuit (15). The first capacitor (1
The output of the second signal inversion circuit (15) is connected to the other terminal of 2a), and the output of the first signal inversion circuit (14) is connected to the other terminal of the second capacitor (12b). You can also.

According to the third aspect of the present invention, the output of the second signal inversion circuit (15) is obtained by inverting the output of the first signal inversion circuit (14). When the output of the inverting circuit (15) becomes low level, the charge is prevented from being extracted from the second capacitor (12b) to the first capacitor (12a) by the parasitic capacitance of the second rectifier (11b). And the efficiency of the charge pump circuit can be increased.

The signal inverting circuits (13, 14, 15) constituting the ring oscillation circuit (100) have the same construction as the inverters (131, 141, 15).
1) and buffers (132, 142, 152). In this case, the inverter (131, 141, 15)
1) is replaced with NPN transistors (131b, 141b, 15).
1b), and the NPN transistor (13
1b, 141b, 151b), a resistor (131d, 141d, 151d) is connected between the emitter and the base of the NPN transistor (131b, 141b, 151b).
Since the charge can be removed from the base when the transistor 51b) changes from on to off, the NPN transistor (131)
b, 141b, 151b)
High-speed operation becomes possible.

According to the present invention, the buffer (132, 142, 152) performs emitter follower output by the NPN transistor (132a, 142a, 152a) and the PNP transistor (132b, 142b, 152b). , The buffer (13
2, 142, and 152) can be minimized, so that high-speed operation is also possible in this case.

Note that the reference numerals in parentheses above indicate the correspondence with specific means described in the embodiment described later, and are attached to the first and second capacitors, the first and second rectifying means, and the like. The reference numerals indicate parts related to the invention in the embodiment described later. The number of capacitors and rectifiers is not limited to two, and the numbers are appropriately set according to the number of stages of the charge pump circuit. .

[0016]

FIG. 1 shows the configuration of a charge pump circuit according to a first embodiment of the present invention. In this embodiment, an input terminal (power supply terminal) 2
0 and an output terminal (boost terminal) 30
a to 11d are connected in series, and a first capacitor 1 is connected to a connection point between the first diode 11a and the second diode 11b.
The second capacitor 1a is connected to the + terminal of the second diode 11b and the second capacitor 11 is connected to the connection point of the second diode 11b and the third diode 11c.
2b is connected to the + terminal, and the third capacitor 11 is connected to the connection point between the third diode 11c and the fourth diode 12d.
The + terminal of 2c is connected.

The output of the signal inversion circuit 13 is connected to the negative terminal of the first capacitor 12a, and the output of the signal inversion circuit 14 is connected to the negative terminal of the second capacitor 12b. The negative terminal of the capacitor 12c of No. 3
The output of the signal inversion circuit 15 is connected. The signal inverting circuits 13, 14, and 15 are connected in series in a ring shape to form a ring oscillator (ring oscillator) 100.

The signal inverting circuit 13 includes an inverter 13
Similarly, the signal inverting circuit 14 includes an inverter 141 and a buffer 142, and the signal inverting circuit 15 includes an inverter 151 and a buffer 152. The operation of the above configuration will be described. The ring oscillator 100 performs an oscillating operation by an odd number of signal inverting circuits 13, 14, and 15 connected in a ring. Here, a node 101 at a connection point between the signal inversion circuits 13 and 14, a node 102 at a connection point between the signal inversion circuits 14 and 15, and a node 103 at a connection point between the signal inversion circuits 15 and 13. The signal waveform of
It becomes as shown in. It is assumed that the signal waveform in FIG. 2 has no rounding.

Now, when the node 101 goes low,
The capacitor 12a is charged from the power supply terminal 20 via the first diode 11a. Next, when the node 101 goes to a high level and the node 102 goes to a low level, the charge charged in the capacitor 12a moves to the second capacitor 12b via the diode 11b. Next, the node 102 changes from the low level to the high level, and the node 1
When 03 goes low, the charge charged in the capacitor 12b moves to the third capacitor 12c via the diode 11c.

As described above, by the oscillating operation of the ring oscillator 100, charges move from the first capacitor 12a to the second capacitor 12b, and further move to the third capacitor 12c. Due to this transfer of electric charges, the third
A boosted voltage is generated in the capacitor 12b.
In this case, the outputs of the signal inverting circuits 13, 14, 15 are connected to the negative terminals of the first, second, and third capacitors 12a, 12b, 12c, respectively. The output changes in accordance with the negative terminal potentials of the first, second, and third capacitors 12a, 12b, and 12c, respectively. Therefore, the ring oscillator 100
Are the first, second and third capacitors 12a, 12b, 1
Since the oscillation operation is performed in accordance with the charging / discharging operation of 2c, a stable desired charge-up voltage can be obtained. (Second Embodiment) In the first embodiment, the node 1
01 changes from the low level to the high level, electric charge moves from the first capacitor 12a to the second capacitor 12b via the second diode 11b, and then the node 102
Before the node goes to the high level, the node 101 has shifted from the high level to the low level.

At this time, the potential of the node 104 that is capacitively coupled to the node 101 decreases with a change in the level of the node 101. Further, since the node 104 and the node 105 are coupled by a parasitic capacitance generated at both ends of the second diode 11b, the potential of the node 105 is
It is decreased by the level fluctuation of 1. Therefore, capacitor 1
Part of the electric charge that has moved from 2a to the capacitor 12b returns to the capacitor 12a, and the amount of electric charge transmitted to the next stage decreases. Similarly, since the nodes 105 and 106 are also coupled by the parasitic capacitance generated between both ends of the third diode 11c, the amount of charges to be transferred decreases even when the charges are transferred from the capacitor 12b to the capacitor 12c. become. When the amount of charges transmitted in this manner decreases, particularly when the number of stages is increased, it causes a reduction in the performance as a charge pump circuit.

Therefore, the present embodiment has a configuration that solves such a problem. FIG. 3 shows the configuration. Compared to the configuration shown in FIG.
The signal transmission direction of 0 is reversed. In the figure, the ring oscillator 100 is the same as that of FIG.
0, the signal transmission direction between the boost terminals 30 is reversed from that in FIG.

The operation of the configuration shown in FIG. 3 will be described. Now, when the node 103 becomes low level, the capacitor 12a is connected from the power supply terminal 20 to the first diode 11
Charged via a. Next, when the node 103 becomes high level, the electric charge charged in the capacitor 12a moves to the second capacitor 12b via the diode 11b.

Here, the potential of the node 103 is
2 is inverted by the signal inverting circuit 15, and the signal transmission is delayed. Therefore, as shown in the waveform diagram of FIG. Has shifted to a high level. Therefore,
Before the charge is extracted from the capacitor 12b due to the parasitic capacitance of the second diode 11b, the capacitor 12b
The transfer of charge from the capacitor to the capacitor 12c can be completed. This operation is the same in the next stage. Thus, a charge pump circuit with higher efficiency than that of the first embodiment can be provided.

Next, a specific configuration of the ring oscillator 100 in the first and second embodiments will be described. FIG. 4 shows a specific circuit configuration. The signal inverting circuit 13 includes an impedance element 131a including a constant current circuit or a resistor, and an NPN transistor 131.
b, impedance element 131c such as resistor, buffer 1
32. The impedance element 13
1a, an NPN transistor 131b, and an impedance element 131c constitute an inverter 131.

Similarly, the signal inverting circuit 14 includes an impedance element 141a, an NPN transistor 141b, an impedance element 141c, and a buffer 142.
The signal inverting circuit 15 includes impedance elements 151a, N
PN transistor 151b, impedance element 151
c, and a buffer 152. With this configuration, the NPN transistors 131b, 141
b and 151b can be turned on and off alternately to perform ring oscillation.

Reference numerals 40 and 50 in the figure denote a power terminal and a ground terminal of the ring oscillator 100. FIG. 5 shows a more specific configuration. This figure 5
The constant current circuit 17 is provided, and the impedance elements 131a, 141a, and 151a are PNP transistors, and the PNP transistor 17 in the constant current circuit 17 is provided.
a and a current mirror circuit to flow a constant current. The constant current circuit 17 includes a PNP transistor 17a, a PNP transistor 17b, a constant current source 17
c.

The impedance elements 131c, 14
1c and 151c are formed of resistors, and resistors 131d, 141d and 151d are connected between the base and the emitter of the NPN transistors 131b, 141b and 151b, respectively. These resistors 131b to 151b,
The transistors 131b to 131d
It is possible to change the operating point of 151b. Also,
By providing the resistors 131d, 141d, and 151d, the NPN transistors 131b, 141b, and 151b are provided.
When the voltage changes from on to off, the charge can be removed from the base, so that the NPN transistors 131b and 14b
The switching speed of 1b and 151b can be increased, and high-speed operation can be performed.

Further, in the example shown in FIG. 5, the buffer 132 comprises an NPN transistor 132a and a PNP transistor 132b. Similarly, the buffer 142 is composed of an NPN transistor 142a and a PNP transistor 142b, and the buffer 152 is
N transistor 152a and PNP transistor 152b
It consists of. In this case, each buffer is configured to perform an emitter follower output by the NPN transistor and the PNP transistor, so that the delay in the buffer can be minimized. In addition, one diode or a series-connected 2 diode is connected between the bases of the NPN transistor and the PNP transistor that constitute each buffer.
The configuration may be such that a plurality of diodes are interposed.

In contrast to the configuration shown in FIG. 5, as shown in FIG. 6, the transistors 131a, 131a,
41a, 151a, 131b, 141b, 151b,
The PNP type and the NPN type can be reversed. In the conventional charge-up circuit, a MOS element is used to secure the performance of the charge pump circuit.
Even when a bipolar element having a low switching speed is used as in the example shown in FIG. 1, the capacity of the charge pump circuit can be sufficiently secured by using a ring oscillator configuration that effectively utilizes the delay time.

It should be noted that the ring oscillator 100 can be formed using MOS devices. FIG. 7 shows N-channel type MOS transistors 131b ′, 141b ′, 151
An example configured using b ′ is shown. In this case, Zener diodes 131d ', 141d', and 151d 'are provided to protect the gate of the MOS transistor. Thus, the MOS transistors 131b 'and 141
Since the switching speed can be increased by using b ′ and 151b ′, the oscillation frequency increases,
The capacity of the charge pump circuit can be increased. (Third Embodiment) In the first and second embodiments, the inverters 131, 141, 151 and the buffers 132, 14
2 and 152 are connected in series.
As shown in FIG. 8, the buffers 132, 142, and 152 may be arranged between each output terminal of the ring oscillator 100 and the negative terminal of each capacitor. Although the configuration shown in FIG. 8 corresponds to the second embodiment, the same configuration can be applied to the first embodiment.

FIG. 9 shows a specific configuration of the one shown in FIG. NPN transistors 131b, 141b, 151b
Is supplied to the bases of the transistors at the next stage to cause ring oscillation. Although the configuration shown in FIG. 9 corresponds to the configuration of FIG. 5, it can be configured as shown in FIGS.

In the various embodiments described above,
The number of stages of the charge pump circuit is not limited to three, and may be four or more. Further, the number of signal inversion circuits can be set individually with the number of stages of the charge pump circuit.
FIG. 10 shows a configuration in a case where the voltage is boosted in five stages. The configuration of the ring oscillator 100 is the same as the configuration shown in FIG. 3, and includes diodes 11e, 11f, capacitors 12d,
2e is added to make the connection as shown in the figure.

The diodes 11a to 11a
Although an example using 11d is shown, a bipolar transistor, a MOS transistor, or the like may be used as long as it has a rectifying action. In addition, buffer 132,
Although the ring oscillator 100 is configured using the inverters 142, 152, the inverters 131, 141, 15
1 has sufficient output capacity, the buffers 132, 142,
It is also possible to omit 152.

In the various embodiments described above,
The output terminal 30 can be grounded and used to generate a negative voltage at the power supply terminal 20. When the oscillation operation of the ring oscillator 100 is stopped, for example, the base potential of the NPN transistor 131b of the inverter 131 is forcibly set to the ground potential via another NPN transistor, and the NPN transistor 131b is forcibly turned off. I just need.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a charge pump circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a signal waveform of a ring oscillator 100 in FIG.

FIG. 3 is a diagram illustrating a configuration of a charge pump circuit according to a second embodiment of the present invention.

FIG. 4 shows a ring oscillator 1 according to the first and second embodiments.
It is a figure which shows the specific structure of 00.

FIG. 5 is a diagram showing a more specific configuration of the one shown in FIG. 4;

FIG. 6 shows a ring oscillator 1 according to the first and second embodiments.
FIG. 10 is a diagram showing another specific configuration of 00.

FIG. 7 shows a ring oscillator 1 according to the first and second embodiments.
It is a figure which shows the further another specific structure of 00.

FIG. 8 is a diagram illustrating a configuration of a charge pump circuit according to a third embodiment of the present invention.

FIG. 9 is a diagram showing a specific configuration of the one shown in FIG.

FIG. 10 is a configuration diagram of a charge pump circuit showing still another embodiment of the present invention.

FIG. 11 is a diagram showing a configuration of a conventional charge pump circuit.

[Explanation of symbols]

11a to 11d: diodes, 12a, 12b, 12
c: capacitor, 13 to 15: signal inverting circuit, 100:
Ring oscillator.

Claims (6)

[Claims] The first and second capacitors (12a, 12a)
b), first rectifying means (11a) for charging one terminal side of the first capacitor (12a), and the second capacitor from one terminal side of the first capacitor (12a). A second rectifier (11b) for charging one terminal of the second capacitor (12b), and charging the one terminal of the first capacitor (12a) and charging the second capacitor (12b). The second capacitor (12b) is charged alternately with one terminal.
A charge pump circuit that uses one terminal voltage as a charge-up voltage, comprising: a ring oscillation circuit (100) in which a plurality of signal inversion circuits (13 to 15) are connected in a ring to perform an oscillation operation; Outputs of different signal inverting circuits in the plurality of signal inverting circuits (13 to 15) are respectively connected to the other terminal of the capacitor (12a) and the other terminal of the second capacitor (12b). Charge pump circuit. 2. The first and second capacitors (12a, 12a).
b), first rectifying means (11a) for charging one terminal side of the first capacitor (12a), and the second capacitor from one terminal side of the first capacitor (12a). A second rectifier (11b) for charging one terminal of the second capacitor (12b), and charging the one terminal of the first capacitor (12a) and charging the second capacitor (12b). The second capacitor (12b) is charged alternately with one terminal.
A plurality of signal inverting circuits (13 to 15) including first and second signal inverting circuits (13, 14) are connected in a ring shape; A ring oscillation circuit (100) that transmits a signal in a direction from the first signal inversion circuit (13) to the second signal inversion circuit (14) and performs an oscillating operation; The output of the first signal inverting circuit (13) is connected to the other terminal, and the second signal inverting circuit (13) is connected to the second terminal.
The output of the second signal inverting circuit (14) is connected to the other terminal of the capacitor (12b). 3. The first and second capacitors (12a, 12a,
b), first rectifying means (11a) for charging one terminal side of the first capacitor (12a), and the second capacitor from one terminal side of the first capacitor (12a). A second rectifier (11b) for charging one terminal of the second capacitor (12b), and charging the one terminal of the first capacitor (12a) and charging the second capacitor (12b). The second capacitor (12b) is charged alternately with one terminal.
A plurality of signal inverting circuits (13 to 15) including first and second signal inverting circuits (14, 15) are connected in a ring shape; A ring oscillation circuit (100) for transmitting a signal from the first signal inversion circuit (14) to the second signal inversion circuit (15) to perform an oscillating operation; The output of the second signal inverting circuit (15) is connected to the other terminal,
A charge pump circuit, wherein the output of the first signal inverting circuit (14) is connected to the other terminal of the capacitor (12b). 4. A signal inverting circuit (13, 14, 15) constituting the ring oscillation circuit (100) includes an inverter (131, 141, 151) and a buffer (132, 14).
The charge pump circuit according to any one of claims 1 to 3, wherein each of the charge pump circuits is configured to include: 5. The inverter (131, 141, 15)
1) are NPN transistors (131b, 141b, 1)
51b), wherein a resistor (131d, 141d, 151d) is connected between the emitter and the base of the NPN transistor (131b, 141b, 151b). Charge pump circuit. 6. The buffer (132, 142, 15)
2) are NPN transistors (132a, 142a, 1)
52a) and PNP transistors (132b, 142b,
The charge pump circuit according to claim 4 or 5, wherein the charge pump circuit is configured to perform an emitter follower output according to 152b).