JP2009044153A - 脆化面に沿って複合基板を破砕する方法および装置 - Google Patents
脆化面に沿って複合基板を破砕する方法および装置 Download PDFInfo
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- JP2009044153A JP2009044153A JP2008203200A JP2008203200A JP2009044153A JP 2009044153 A JP2009044153 A JP 2009044153A JP 2008203200 A JP2008203200 A JP 2008203200A JP 2008203200 A JP2008203200 A JP 2008203200A JP 2009044153 A JP2009044153 A JP 2009044153A
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- 239000002131 composite material Substances 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 title claims description 80
- 238000000137 annealing Methods 0.000 claims description 17
- 239000003795 chemical substances by application Substances 0.000 claims description 17
- 230000001186 cumulative effect Effects 0.000 claims description 10
- 239000004848 polyfunctional curative Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 description 13
- 239000010453 quartz Substances 0.000 description 6
- 229910052594 sapphire Inorganic materials 0.000 description 6
- 239000010980 sapphire Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000004064 recycling Methods 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 239000003351 stiffener Substances 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- -1 helium ions Chemical class 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/11—Methods of delaminating, per se; i.e., separating at bonding face
- Y10T156/1168—Gripping and pulling work apart during delaminating
- Y10T156/1189—Gripping and pulling work apart during delaminating with shearing during delaminating
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/19—Delaminating means
- Y10T156/1961—Severing delaminating means [e.g., chisel, etc.]
- Y10T156/1967—Cutting delaminating means
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Abstract
【解決手段】本発明は、2つの層により画定される脆化面に沿って複合構造(100)を破砕する方法に関する。破砕の間、この複合構造は、ボートハウジング(120)内に配置され、また、この構造の両側に配置され、かつ互いに平行に整列された硬化剤(118)と接触した状態に保たれる。
【選択図】図3
Description
12 ドナー基板の平坦な面
14 脆化面
16 薄層
18 ネガ
20 支持基板
22 支持基板の平坦な面
100 複合構造
102 ボート
104 ローダ
106 ドア
108 アセンブリ
110 炉構造
112 石英処理管
114 加熱素子
116 パイロメータ
118 硬化剤
120 ハウジング
Claims (12)
- 2つの層の間に画定される脆化面に沿って複合構造(100)を破砕する方法であって、
前記脆化面に沿って前記複合構造の中に割れ目を生成するステップを含み、
破砕の間、前記複合構造は、前記複合構造の両側に配置され、かつ前記複合構造から離間された硬化剤(118)に対して保持されることを特徴とする方法。 - 前記複合構造(100)は、2つの硬化剤(118)の間に置かれ、
各硬化剤と前記複合構造との間の累積的間隔は、破砕の間、0ではなく、500マイクロメートル未満であることを特徴とする請求項1に記載の方法。 - 前記硬化剤(118)は、前記複合構造の直径の少なくとも50%より大きいことを特徴とする請求項2に記載の方法。
- 前記複合構造(100)は、破砕の間、実質的に垂直に配置されることを特徴とする請求項1から3のいずれかに記載の方法。
- 前記複合構造(100)は、破砕の間、実質的に水平に配置されることを特徴とする請求項1から3のいずれかに記載の方法。
- 前記複合構造(100)の前記脆化面は、イオン注入により形成されることを特徴とする請求項1から5のいずれかに記載の方法。
- 前記破砕は、前記複合構造の熱アニールにより実行されることを特徴とする請求項1から6のいずれかに記載の方法。
- 前記複合構造は、異なる熱膨張係数を有する2つの基板で構成されることを特徴とする請求項1から7のいずれかに記載の方法。
- 前記複合構造は、2つの基板(10、20)を互いに組み合わせることにより作製され、前記2つの基板のうちの1つは、脆化面を備えることを特徴とする請求項1から8のいずれかに記載の方法。
- 破砕される複合構造の熱アニール装置ボート(102)のハウジング(120)であって、
前記ハウジングは、2つの層の間に画定される脆化面に沿って破砕される複合構造(100)を収容可能であり、
前記ハウジングは、互いに離間され、かつ互いに平行に整列された2つの硬化素子(118)をさらに備え、
各硬化素子と前記複合構造との間の累積的間隔は、0ではなく、500マイクロメートル未満であることを特徴とするハウジング。 - 前記硬化剤(118)の直径は、破砕される前記複合構造の直径の少なくとも50%より大きいことを特徴とする請求項10に記載のハウジング。
- 2つの層の間に画定される脆化面に沿って破砕される複合構造の熱アニール装置であって、
炉(110)と、
複数の複合構造(100)を収容可能なボート(102)と
を備え、
各複合構造は、請求項10又は11のハウジング(120)内に配置されることを特徴とする熱アニール装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0756997 | 2007-08-08 | ||
FR0756997A FR2919960B1 (fr) | 2007-08-08 | 2007-08-08 | Procede et installation pour la fracture d'un substrat composite selon un plan de fragilisation |
Publications (2)
Publication Number | Publication Date |
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JP2009044153A true JP2009044153A (ja) | 2009-02-26 |
JP4971266B2 JP4971266B2 (ja) | 2012-07-11 |
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JP2008203200A Active JP4971266B2 (ja) | 2007-08-08 | 2008-08-06 | 脆化面に沿って複合基板を破砕する方法および装置 |
Country Status (8)
Country | Link |
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US (1) | US8324078B2 (ja) |
EP (1) | EP2023380A1 (ja) |
JP (1) | JP4971266B2 (ja) |
KR (1) | KR101010592B1 (ja) |
CN (1) | CN101364534B (ja) |
FR (1) | FR2919960B1 (ja) |
SG (2) | SG150431A1 (ja) |
TW (1) | TW200913130A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7505151B2 (ja) | 2019-03-15 | 2024-06-25 | ソイテック | 複数のウエハ組立体を破砕するためのシステム |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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FR3009428B1 (fr) * | 2013-08-05 | 2015-08-07 | Commissariat Energie Atomique | Procede de fabrication d'une structure semi-conductrice avec collage temporaire via des couches metalliques |
JP6390898B2 (ja) | 2014-08-22 | 2018-09-19 | アイシン精機株式会社 | 基板の製造方法、加工対象物の切断方法、及び、レーザ加工装置 |
KR101664621B1 (ko) * | 2014-12-12 | 2016-10-10 | 한국항공우주연구원 | 충격 흡수를 위한 구조물, 의도된 파손 유도를 위한 최초 파손 유발 구조, 및 이를 제조하는 방법 |
FR3091620B1 (fr) * | 2019-01-07 | 2021-01-29 | Commissariat Energie Atomique | Procédé de transfert de couche avec réduction localisée d’une capacité à initier une fracture |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2002353082A (ja) * | 2001-05-28 | 2002-12-06 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
JP2003224042A (ja) * | 2001-12-21 | 2003-08-08 | Soi Tec Silicon On Insulator Technologies | 半導体薄層の移し換え方法とそれに使用するドナーウエハの製造方法 |
JP2005005708A (ja) * | 2003-06-11 | 2005-01-06 | Soi Tec Silicon On Insulator Technologies | 異質構造の製造方法 |
WO2005024916A1 (ja) * | 2003-09-05 | 2005-03-17 | Sumco Corporation | Soiウェーハの作製方法 |
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FR2681472B1 (fr) * | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
US6033974A (en) * | 1997-05-12 | 2000-03-07 | Silicon Genesis Corporation | Method for controlled cleaving process |
US6162705A (en) * | 1997-05-12 | 2000-12-19 | Silicon Genesis Corporation | Controlled cleavage process and resulting device using beta annealing |
US20030049372A1 (en) * | 1997-08-11 | 2003-03-13 | Cook Robert C. | High rate deposition at low pressures in a small batch reactor |
FR2828428B1 (fr) * | 2001-08-07 | 2003-10-17 | Soitec Silicon On Insulator | Dispositif de decollement de substrats et procede associe |
FR2834820B1 (fr) * | 2002-01-16 | 2005-03-18 | Procede de clivage de couches d'une tranche de materiau | |
FR2839385B1 (fr) | 2002-05-02 | 2004-07-23 | Soitec Silicon On Insulator | Procede de decollement de couches de materiau |
US20050150597A1 (en) * | 2004-01-09 | 2005-07-14 | Silicon Genesis Corporation | Apparatus and method for controlled cleaving |
US9011598B2 (en) * | 2004-06-03 | 2015-04-21 | Soitec | Method for making a composite substrate and composite substrate according to the method |
US7772088B2 (en) | 2005-02-28 | 2010-08-10 | Silicon Genesis Corporation | Method for manufacturing devices on a multi-layered substrate utilizing a stiffening backing substrate |
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- 2007-08-08 FR FR0756997A patent/FR2919960B1/fr active Active
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- 2008-07-10 US US12/170,937 patent/US8324078B2/en active Active
- 2008-07-18 TW TW097127506A patent/TW200913130A/zh unknown
- 2008-07-18 EP EP08160680A patent/EP2023380A1/fr not_active Withdrawn
- 2008-07-21 SG SG200805374-6A patent/SG150431A1/en unknown
- 2008-07-21 SG SG201100872-9A patent/SG169393A1/en unknown
- 2008-07-22 KR KR1020080071244A patent/KR101010592B1/ko active IP Right Grant
- 2008-08-06 JP JP2008203200A patent/JP4971266B2/ja active Active
- 2008-08-07 CN CN2008101449154A patent/CN101364534B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002353082A (ja) * | 2001-05-28 | 2002-12-06 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
JP2003224042A (ja) * | 2001-12-21 | 2003-08-08 | Soi Tec Silicon On Insulator Technologies | 半導体薄層の移し換え方法とそれに使用するドナーウエハの製造方法 |
JP2005005708A (ja) * | 2003-06-11 | 2005-01-06 | Soi Tec Silicon On Insulator Technologies | 異質構造の製造方法 |
WO2005024916A1 (ja) * | 2003-09-05 | 2005-03-17 | Sumco Corporation | Soiウェーハの作製方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7505151B2 (ja) | 2019-03-15 | 2024-06-25 | ソイテック | 複数のウエハ組立体を破砕するためのシステム |
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Publication number | Publication date |
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TW200913130A (en) | 2009-03-16 |
SG169393A1 (en) | 2011-03-30 |
KR101010592B1 (ko) | 2011-01-25 |
CN101364534B (zh) | 2011-03-16 |
EP2023380A1 (fr) | 2009-02-11 |
KR20090015814A (ko) | 2009-02-12 |
CN101364534A (zh) | 2009-02-11 |
FR2919960A1 (fr) | 2009-02-13 |
SG150431A1 (en) | 2009-03-30 |
FR2919960B1 (fr) | 2010-05-21 |
JP4971266B2 (ja) | 2012-07-11 |
US8324078B2 (en) | 2012-12-04 |
US20090038758A1 (en) | 2009-02-12 |
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