JP2009043803A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress carrier trapping and compensate a failure of a semiconductor layer, for example, in a TFT to be used as a pixel switching element. <P>SOLUTION: A semiconductor layer 1a is made of Si, and LDD areas 1b and 1c are formed by implanting impurities into both sides of a gate electrode 3a1. The gate electrode 3a1 is overlaid over a channel area 1a', and for example, it is comprised of a part of a scanning line 3a. A gate insulating film 43g extends between the semiconductor layer 1a and the gate electrode 3a1, and it is made of SiO<SB>2</SB>. In particular, a TFT 30 is an N channel transistor that easily generates unpaired coupling hand and carrier trapping than a P channel transistor, and a predetermined treatment such as annealing or the like effectively suppresses the degradation of operational characteristic or reliability after BT testing caused by the unpaired coupling hand or carrier trapping. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technical field of a semiconductor device such as a liquid crystal device that employs a transistor element such as a thin film transistor as a pixel switching element, and a manufacturing method thereof.

In this type of semiconductor device, when a thin film transistor (hereinafter referred to as TFT) is formed on a substrate such as a glass substrate, it is necessary to form a semiconductor layer at 650 ° C. or lower from the strain point of the substrate. When a low-melting point metal such as aluminum is used for the electrode structure, the process temperature needs to be 400 ° C. or lower, and silicon constituting the semiconductor layer compared to the high-temperature process for forming TFTs at 650 ° C. or higher. Si) and defects existing in the silicon oxide film (SiO ₂ ) constituting the gate insulating film cannot be sufficiently compensated. In particular, defects such as Si dangling bonds present at the interface between the gate insulating film and the semiconductor layer contribute to a decrease in the operating characteristics and reliability of the TFT.

  Therefore, Patent Document 1 discloses that the gate insulating film and the semiconductor layer are formed at a relatively low temperature by performing thermal annealing at 400 to 700 ° C. in a highly reactive gas atmosphere having nitrogen oxide by utilizing photoexcitation and decomposition. A method of manufacturing a semiconductor device that compensates for dangling bonds by bonding thermally stable nitrogen atoms to dangling bonds of Si existing at the interface has been proposed.

JP-A-8-125197

  However, according to the method proposed in Patent Document 1, since the annealing process is performed after the gate insulating film is formed, it is difficult to sufficiently compensate for defects generated in a portion located in the vicinity of the gate electrode in the interlayer insulating film, Depending on the method of forming the interlayer insulating film, it becomes difficult to improve the operating characteristics and reliability of the transistor element. In addition, when the annealing process is performed after the interlayer insulating film is formed, if a low melting point metal such as aluminum is used for the gate electrode, it is necessary to reduce the temperature to 400 ° C. or lower, Depending on the diffusion state, the nitrogen concentration becomes high, and the dangling bonds of nitrogen atoms act as carrier traps, deteriorating the reliability of the transistor element. For example, after applying a predetermined voltage to the gate electrode of a transistor element at a temperature of 200 ° C., the on-current after the test decreases in a BT test in which a current flowing during operation of the transistor element (that is, an on-current) is measured. As a result, the operating characteristics and the reliability of the transistor element are deteriorated.

  Accordingly, the present invention has been made in view of the above-described problems, and provides, for example, a semiconductor device on which a transistor element capable of suppressing deterioration in operating characteristics and reliability after a BT test and a manufacturing method thereof are provided. The task is to do.

  In order to solve the above problems, a semiconductor device according to the present invention includes: (i) a semiconductor layer formed on a substrate and including a channel region, a source region, and a drain region; and (ii) the channel region on the semiconductor layer. And (iii) a transistor element having a gate insulating film extending between the semiconductor layer and the gate electrode, a first interlayer insulating film formed on the gate electrode, and the first interlayer insulating film And a second interlayer insulating film having a nitrogen concentration higher than that of the first interlayer insulating film, wherein the semiconductor layer and the gate insulating film are defects included in the semiconductor layer and the gate insulating film, respectively. Is provided with a predetermined process so as to be compensated.

  According to the semiconductor device of the present invention, the transistor element is a thin film transistor formed on a substrate such as a glass substrate, and the gate electrode thereof is a channel region included in a semiconductor layer made of a semiconductor such as silicon. Is formed on the channel region with a gate insulating film interposed therebetween.

  The first interlayer insulating film is formed on the gate electrode, and electrically insulates the transistor element and the circuit portion formed thereon together with the second interlayer insulating film. The second interlayer insulating film is formed on the first interlayer insulating film and has a higher nitrogen concentration than the first interlayer insulating film. That is, a two-layer structure of an insulating film including at least a first interlayer insulating film and a second interlayer insulating film having a nitrogen concentration higher than that of the first interlayer insulating film is formed on the gate electrode of the transistor element.

The semiconductor layer and the gate insulating film are formed in a predetermined manner so that defects included in the semiconductor layer and the gate insulating film are compensated after the first and second interlayer insulating films are formed on the semiconductor layer and the gate insulating film. Processing has been applied. “Predetermined treatment” means, for example, so as to compensate for defects such as unpaired bonds existing at the interface between a semiconductor layer such as silicon (Si) and a gate insulating film such as silicon oxide (SiO ₂ ). Alternatively, during the operation of the transistor element, heat is generated so that carrier traps that capture carriers such as holes or electrons are not generated in the vicinity of the gate electrode in the interlayer insulating film, more specifically, in the region beside the gate electrode. This means that each of the semiconductor layer and the gate insulating film is processed either chemically or chemically. That is, “to compensate for defects” in the present invention means to compensate for existing defects so as not to cause a new defect by performing a predetermined process. Such a predetermined process does not simply depend on the processing conditions, but also depends on the level of nitrogen concentration in each of the first and second interlayer insulating films.

  Here, by diffusing nitrogen from the upper layer side of the gate insulating film toward the interface, nitrogen atoms are bonded to the dangling bonds, and the dangling bonds at the interface between the semiconductor layer and the gate insulating film are compensated. Can be considered. However, if the nitrogen diffuses excessively in the interlayer insulating film in the vicinity of the gate electrode, for example, in the region extending to the side of the gate electrode, the dangling bonds of the diffused nitrogen become carrier traps, and the transistor element operates. Sometimes the on-current that can flow through the transistor element is reduced.

  Therefore, in the semiconductor device according to the present invention, the first interlayer insulating film is formed on the gate electrode, and the second interlayer insulating film having a relatively high nitrogen concentration is formed thereon. An increase in carrier traps in the vicinity of the gate electrode can be suppressed while reducing dangling bonds at the interface between the layer and the gate insulating film. More specifically, defects such as dangling bonds can be compensated with nitrogen atoms by diffusing nitrogen atoms from the second interlayer insulating film to the interface between the semiconductor layer and the gate insulating film. In addition, the amount of nitrogen contained in the gate insulating film in the vicinity of the gate electrode is larger than that in the case where the predetermined treatment is performed with the second interlayer insulating film formed directly on the gate electrode because the first interlayer insulating film exists. An increase in the concentration of atoms can be suppressed.

  Therefore, according to the semiconductor device of the present invention, the reduction of dangling bonds at the interface between the semiconductor layer and the gate insulating film and the reduction of carrier traps that can occur as a side effect of the dangling bonds are simultaneously realized. For example, even when a predetermined treatment can be performed only in a low temperature range of 400 ° C. or lower, it is possible to suppress a decrease in operating characteristics and a decrease in reliability of the transistor element.

  In one aspect of the semiconductor device according to the present invention, the predetermined treatment is an annealing treatment for heat-treating the gate insulating film and the semiconductor layer in a water vapor or nitrogen atmosphere, or the first interlayer insulating film and the second interlayer insulating film. High-pressure steam treatment may be used in which steam is supplied at high pressure to the gate insulating film and the semiconductor layer through an interlayer insulating film.

  According to this aspect, since the processing temperature when the annealing process is performed is, for example, 400 ° C. or less, the glass substrate may be damaged by heat even when the transistor element is formed on the glass substrate. Absent. The high-pressure steam treatment is, for example, heat-treating a semiconductor device in which up to the second interlayer insulating film is formed in a steam atmosphere having a pressure of about 1 to 2 MPa and maintained at a temperature of 400 ° C. or lower. Say. By each of these treatments, nitrogen atoms in the second interlayer insulating film can be diffused to the interface between the semiconductor layer and the gate insulating film, and an excessive increase in the concentration of nitrogen atoms in the gate insulating film can be suppressed. In addition, according to these processes, not only compensation of defects such as dangling bonds but also crystal defects in the semiconductor layer and the gate insulating film can be compensated by nitrogen.

  In another aspect of the semiconductor device according to the present invention, the semiconductor layer may have LDD regions formed on both sides of the channel region.

  According to this aspect, defects can be effectively compensated in an LDD region where defects such as dangling bonds are likely to occur, and electrical resistance and off-current can be reduced in the LDD region.

  In another aspect of the semiconductor device according to the present invention, the transistor element may be an N-channel transistor.

  According to this aspect, it is possible to suppress a decrease in operating characteristics and reliability after the BT test for an N-channel transistor in which generation of unpaired bonds and generation of carrier traps are remarkable.

  In another aspect of the semiconductor device according to the present invention, the transistor element may be a pixel switching element formed in each of a plurality of pixel portions constituting a display region on the substrate.

  According to this aspect, a potential corresponding to an image signal can be supplied to the pixel portion via the pixel switching element, and for example, display performance of a semiconductor device such as a liquid crystal device can be improved.

In this aspect, the first interlayer insulating film is a SiO ₂ film formed by a PE-CVD method using a mixed gas of TEOS (tetraethylorthosilicate) gas and oxygen (O ₂ ) gas as a reaction gas. The second interlayer insulating film may be a SiO ₂ film formed by a PE-CVD method (plasma assisted chemical vapor deposition method) using a SiH ₄ + N ₂ O-based gas as a reaction gas. .

  According to this aspect, the first interlayer insulating film and the second interlayer insulating film having different nitrogen concentrations can be formed by using a CVD method and a PE-CVD method which are widely used as a method for forming the insulating film. In addition, insulating films having different nitrogen concentrations can be formed by a simple method.

  In this aspect, the film thickness of the second interlayer insulating film formed by the PE-CVD method is 1/7 to 15 times the film thickness of the first interlayer insulating film formed by the PE-CVD method. May be.

  According to this aspect, it is possible to realize in a balanced manner compensation for dangling bonds and suppression of excessive diffusion of nitrogen atoms in the gate insulating film, and it is possible to suppress a decrease in on-current after the BT test. Has been confirmed.

In another aspect of the semiconductor device according to the present invention, the nitrogen concentration contained in the first interlayer insulating film formed by the PE-CVD method is 1 × 10 ^{18 to} 1 × 10 ²⁰ [atoms · cm ⁻³ ]. The nitrogen concentration contained in the second interlayer insulating film formed by the PE-CVD method is included in the range of 1 × 10 ^{20 to} 1 × 10 ²² [atoms · cm ⁻³ ]. May be.

  According to this aspect, it has been confirmed that the decrease in the on-state current of the transistor element after the BT test can be suppressed by the experiments and considerations of the present inventors.

  In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes (i) a semiconductor layer formed on a substrate and including a channel region, a source region, and a drain region, and (ii) the semiconductor layer on the semiconductor layer. Forming a transistor element having a gate electrode overlapping the channel region, and (iii) the semiconductor layer and a gate insulating film extending between the gate electrodes, and a first interlayer insulating film formed on the gate electrode, A step of forming a second interlayer insulating film having a nitrogen concentration higher than that of the first interlayer insulating film on the first interlayer insulating film; and a defect included in each of the semiconductor layer and the gate insulating film. A step of performing a predetermined process on the semiconductor layer and the gate insulating film so as to be compensated.

  According to the method for manufacturing a semiconductor device according to the present invention, as in the semiconductor device according to the present invention described above, the reduction of dangling bonds at the interface between the semiconductor layer and the gate insulating film and the reduction of dangling bonds are performed. It is possible to simultaneously reduce carrier traps that may occur as a side effect. For example, even when a predetermined treatment can be performed only in a low temperature range of 500 ° C. or lower, the operating characteristics of the transistor element are reduced. Reduction in reliability can be suppressed.

  Such an operation and other advantages of the present invention will become apparent from the embodiments described below.

  Hereinafter, embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described with reference to the drawings. In the present embodiment, a liquid crystal device including a transistor element such as a TFT is given as an example of the semiconductor device according to the present invention, and a manufacturing method thereof will be described.

<1: Liquid crystal device>
First, the overall configuration of the liquid crystal device 1 according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view of the liquid crystal device 1 as seen from the counter substrate side together with the components formed on the TFT array substrate, and FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. The liquid crystal device 1 according to the present embodiment is a reflective display device that is driven by a TFT active matrix driving method with a built-in driving circuit and reflects light by a reflective film described later.

  1 and 2, in the liquid crystal device 1, a TFT array substrate 10, which is an example of the “substrate” of the present invention, and a counter substrate 20 are disposed to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are sealed regions located around the image display region 10a, which is a display region in which a plurality of pixel portions are provided. Are adhered to each other by a sealing material 52 provided on the surface.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates, and is applied on the TFT array substrate 10 in the manufacturing process and then cured by ultraviolet irradiation, heating, or the like. It is. In the sealing material 52, a gap material such as glass fiber or glass beads for dispersing the distance (inter-substrate gap) between the TFT array substrate 10 and the counter substrate 20 to a predetermined value is dispersed.

  A light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the seal material 52 is disposed. However, part or all of the frame light shielding film 53 may be provided as a built-in light shielding film on the TFT array substrate 10 side. There is a peripheral area located around the image display area 10a. In other words, particularly in the present embodiment, when viewed from the center of the TFT array substrate 10, the distance from the frame light shielding film 53 is defined as the peripheral region.

  A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. The scanning line driving circuit 104 is provided along two sides adjacent to the one side so as to be covered with the frame light shielding film 53. Further, in order to connect the two scanning line driving circuits 104 provided on both sides of the image display area 10 a in this way, a plurality of the pixel lines are covered along the remaining side of the TFT array substrate 10 and covered with the frame light shielding film 53. Wiring 105 is provided.

  A sensor control circuit unit 201 for controlling a sensor unit (not shown) including an optical sensor provided in the pixel unit in order to ensure a touch panel function is formed in the peripheral region on the TFT array substrate 10. The external circuit connection terminal 102 is connected to a connection terminal provided on the flexible substrate 200 which is an example of a connection means for electrically connecting the external circuit and the liquid crystal device 1. The sensor control circuit unit 201 may be built in the liquid crystal device 1 or may be formed outside the liquid crystal device 1.

  Vertical conductive members 106 functioning as vertical conductive terminals between the two substrates are disposed at the four corners of the counter substrate 20. On the other hand, the TFT array substrate 10 is provided with vertical conduction terminals in a region facing these corner portions. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  In FIG. 2, on the TFT array substrate 10, an alignment film is formed on the pixel electrode 9a after the pixel switching TFT, the scanning line, the data line and the like are formed. On the other hand, on the counter substrate 20, in addition to the counter electrode 21, a lattice-shaped or striped light-shielding film 23 and an alignment film are formed on the uppermost layer portion. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films. The image displayed by the liquid crystal device 1 is displayed on the display surface 20 s on the side of the opposite substrate 20 that does not face the liquid crystal layer 50.

  In the present embodiment, illustration of the polarizing plate and the color filter is omitted for convenience of explanation, but when the polarizing plate and the color filter are arranged on the counter substrate 20, the liquid crystal device is shown in the drawing. The top surface of 1 becomes the display surface. In addition, the liquid crystal device 1 is a reflective display device that reflects light incident from the display surface 20s side by a reflective film described later and modulates the reflected light by the liquid crystal layer 50 to display a desired image.

  On the TFT array substrate 10 shown in FIGS. 1 and 2, in addition to the drive circuits such as the data line drive circuit 101 and the scanning line drive circuit 104, the image signal on the image signal line is sampled and used as the data line. A sampling circuit to be supplied, a precharge circuit for supplying a precharge signal of a predetermined voltage level to a plurality of data lines in advance of an image signal, in order to inspect the quality, defects, etc. of the electro-optical device during manufacturing or at the time of shipment An inspection circuit or the like may be formed.

  Next, the circuit configuration of the liquid crystal device 1 will be described with reference to FIG. FIG. 3 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix that forms the image display region 10a of the liquid crystal device 1.

  In FIG. 3, a plurality of pixel portions 72 formed in a matrix that forms the image display region 10 a of the liquid crystal device 1 are provided. The pixel portion 72 includes a pixel electrode 9a, a TFT 30 as an example of the “transistor element” of the present invention, and a liquid crystal element 50a. The TFT 30 is electrically connected to the pixel electrode 9a, and performs switching control of the pixel electrode 9a when the liquid crystal device 1 operates. The data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. May be.

  The scanning line 3a is electrically connected to the gate of the TFT 30, and the liquid crystal device 1 sequentially applies the scanning signals G1, G2,..., Gm to the scanning line 3a in a pulse sequence in this order at a predetermined timing. It is comprised so that it may apply. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,... Supplied from the data line 6a is closed by closing the switch of the TFT 30 serving as a switching element for a certain period. Sn is written at a predetermined timing. Image signals S1, S2,..., Sn written to the liquid crystal via the pixel electrode 9a are held for a certain period with the counter electrode formed on the counter substrate.

  The liquid crystal contained in the liquid crystal layer 50 modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light decreases according to the voltage applied in units of each sub-pixel unit. In the normally black mode, the voltage applied in units of each sub-pixel unit. Accordingly, the transmittance for incident light is increased, and light having a contrast corresponding to an image signal is emitted from the liquid crystal device 1 as a whole. The storage capacitor 70 is electrically connected to the fixed potential line 300, and is added in parallel with the liquid crystal element 50a formed between the pixel electrode 9a and the counter electrode in order to prevent the image signal from leaking. Yes.

  Next, a specific configuration of the liquid crystal device 1 will be described with reference to FIG. FIG. 4 is a cross-sectional view showing a part of the structure of the pixel portion of the liquid crystal device 1 together with a part of the peripheral circuit portion.

  In FIG. 4, the liquid crystal device 1 includes a TFT 30, a TFT array substrate 10 formed of a transparent substrate such as a glass substrate, a terminal portion 84, an insulating film 43 as an example of the “first interlayer insulating film” of the present invention, and the present invention. The pixel portion 72 includes the insulating film 44, the reflective film 86, the insulating films 45, 46 and 47, and the pixel electrode 9a, which are examples of the “second interlayer insulating film”.

  The pixel electrode 9 a is formed in each of the plurality of pixel portions 72 constituting the image display area 10 a that is a display area on the TFT array substrate 10. The terminal portion 84 is composed of a single or a plurality of metal layers, and constitutes a part of a pixel circuit that drives the pixel portion 72. More specifically, the terminal portion 84 is electrically connected to the TFT 30 as the pixel switching element through the contact hole 82 and is also electrically connected to the pixel electrode 9a. Then, during the operation of the liquid crystal device 1, a potential corresponding to the image signal is supplied to the pixel electrode 9 a via the terminal portion 84.

  The semiconductor layer 1a included in the TFT 30 includes a source region 1d, a channel region 1a ′, a drain region 1e, and LDD regions 1b and 1c. An image signal supplied from a data line through a contact hole 81 is a gate electrode. It is supplied to the pixel electrode 9a through the contact hole 82 in accordance with the gate voltage applied to 3a1. On the TFT array substrate 10, a transistor element 130 constituting a part of a peripheral circuit portion such as the data line driving circuit 101 is formed in the same layer as the TFT 30.

  The hole portion 85 penetrating the insulating films 45 and 46 overlaps the terminal portion 84. For example, the insulating films 45 and 46 are partially removed by a photo-patterning method of irradiating the insulating films 45 and 46 with light. Is formed. The terminal portion 84 is exposed to the hole portion 85 in a state where the insulating film 47 and the pixel electrode 9a are not formed, and functions as a contact hole for electrically connecting the terminal portion 84 and the pixel electrode 9a.

  The reflective film 86 is formed in a region where the hole portion 85 on the insulating film 46 is not provided in a region occupied by the pixel portion 72 on the TFT array substrate 10. The reflection film 86 is made of a conductive film such as metal, and reflects light incident from the upper side in the drawing when the liquid crystal device 1 is in operation.

The semiconductor layer 1a is made of Si, and the LDD regions 1b and 1c are formed by implanting impurities on both sides of the gate electrode 3a1. The gate electrode 3a1 overlaps with the channel region 1a ′ and is constituted by, for example, a part of the scanning line 3a. The gate insulating film 43g is formed on the insulating films 41 and 42 that are sequentially formed on the TFT array substrate 10. The gate insulating film 43g extends between the semiconductor layer 1a and the gate electrode 3a1, is composed of SiO _2. In particular, in this embodiment, the TFT 30 is an LDD structure transistor in which unpaired bonds and carrier traps are more likely to occur than an SD structure transistor. The TFT 30 is converted into unpaired bonds and carrier traps by a predetermined process such as annealing described later. The resulting deterioration in operating characteristics and reliability after the BT test is effectively suppressed.

The insulating film 43 is formed on the gate electrode 3a1, and electrically insulates the TFT 30 and the circuit portion formed thereon together with the insulating film 44. Insulating film 43, a TEOS (tetraethyl orthosilicate) gas, a SiO ₂ film formed by PE-CVD method using a mixed gas of oxygen gas (O ₂₎ as a reaction gas.

The insulating film 44 is a SiO ₂ film formed by a PE-CVD method (plasma assisted chemical vapor deposition method) using SiH ₄ + N ₂ O-based gas as a reaction gas. Is expensive. That is, an insulating film multilayer structure including at least the insulating film 43 and the insulating film 44 having a higher nitrogen concentration than the insulating film 43 is formed on the gate electrode 3a1. In addition, according to the liquid crystal device 1 according to the present embodiment, the insulating films 43 and 44 having different nitrogen concentrations can be formed using a simple method such as a CVD method and a PE-CVD method that are widely used as a method for forming the insulating film. It can be formed.

  For the semiconductor layer 1a and the gate insulating film 43g, an annealing process for heat-treating the gate insulating film 43g and the semiconductor layer 1a in a water vapor or nitrogen atmosphere when the insulating films 43 and 44 are formed on the TFT 30, or an insulating film High-pressure steam treatment for supplying steam at high pressure to the gate insulating film 43g and the semiconductor layer 1a through 43 and 44 is performed. Since the annealing temperature is 400 ° C. or less, the TFT 30 is formed on the TFT array substrate 10 made of a transparent substrate such as a glass substrate, or the gate electrode 3a1 is an Al electrode. Even when formed of a low melting point metal, the TFT array substrate 10 and the gate electrode 3a1 are not damaged by heat. When the high-pressure steam treatment is performed, the liquid crystal device 1 having the insulating film 44 formed therein is heat-treated in a steam atmosphere having a pressure of about 1 to 2 MPa and maintained at a temperature of 400 ° C. or lower. The

  It is considered that the following phenomena are caused by these processes. Nitrogen atoms in the insulating film 44 can be diffused to the interface between the semiconductor layer 1a and the gate insulating film 43g, and it is possible to compensate so that dangling bonds existing at the interface are terminated with nitrogen atoms. In particular, in the present embodiment, defects can be effectively compensated in the LDD regions 1b and 1c where defects such as dangling bonds are likely to occur, and the electrical resistance and the off-current in the LDD regions 1b and 1c can be reduced. It is. In addition, in the liquid crystal device 1 according to the present embodiment, an excessive increase in the concentration of nitrogen atoms in the gate insulating film 43g can be suppressed, and the LDD region 1b formed beside the gate electrode 3a1 in the gate insulating film 43g and Carrier traps generated in 1c can be reduced.

  Next, the configuration of main parts of the liquid crystal device 1 according to the present embodiment will be described in detail with reference to FIGS. 5 to 9 and compared with the configuration of the comparative example. In the comparative example described below, the same reference numerals are assigned to the portions common to the liquid crystal device 1 according to the present embodiment. In addition, for convenience of explanation, each of the pixel switching TFTs included in the liquid crystal device according to the comparative example is referred to as TFTs 30a and 30b, and the TFTs 30 are distinguished. In the following, illustration of upper layer portions on the insulating films 43 and 44 is omitted.

  As shown in FIG. 5A, in the liquid crystal device 1, in a state where the insulating films 43 and 44 are formed, the TFT 30 is subjected to a predetermined process such as an annealing process or a high-pressure steam process in a steam or nitrogen atmosphere. It has been subjected. In particular, in a part of the liquid crystal device 1 shown in FIG. 5A, defect compensation is performed for the LDD regions 1b and 1c of the semiconductor layer 1a while suppressing generation of carrier traps in the region C1. As shown in FIG. 5B, in the liquid crystal device according to one comparative example, only the insulating film 43 is formed on the TFT 30b, and then the above-described predetermined processing is performed. However, since the insulating film 43 has a lower nitrogen concentration than the insulating film 44, when a predetermined process such as an annealing process is performed with only the insulating film 43 formed, defect compensation is sufficient in the region C2 in the figure. It has not been made. As shown in FIG. 5C, in the liquid crystal device according to another comparative example, only the insulating film 44 is formed on the TFT 30c, and then the predetermined processing described above is performed. However, since the insulating film 44 has a higher nitrogen concentration than the insulating film 43, carrier traps are generated in a region corresponding to the region C1. Further, although the high-pressure steam treatment has a large nitrogen diffusion effect, the nitrogen concentration in the vicinity of the gate electrode of the interlayer insulating film is higher than the treatment performed in the example shown in FIG. A trap will occur.

  Here, referring to FIG. 6, a BT test was performed for each of FIGS. 5A to 5C in a nitrogen atmosphere and before and after annealing in a condition of a temperature of 400 ° C. Then, the change in the operating characteristics of the TFT before and after that, more specifically, the change in the on-current Id with respect to the gate voltage Vg is compared. 6A to 6C are graphs showing changes in on-state current before and after the BT test of the TFTs 30, 30a, and 30b shown in FIGS. 5A to 5C, respectively. In the figure, the solid line shows the change in on-current with respect to the gate voltage Vg before the BT test, and the dotted line shows the change in on-current with respect to the gate voltage Vg after the BT test. In the following, the change before and after the BT test is compared for the on-current Id when the gate voltage Vg is 5V.

  As shown in FIG. 6A, the on-current change amount ΔId1 of the TFT 30 in a state where the gate voltage Vg is set to 5 V is the on-current change amount of each of the TFTs 30a and 30b shown in FIGS. 6B and 6C. It was confirmed that the decrease in the on-current due to the BT test was suppressed by forming the insulating films 43 and 44 on the TFT 30 that are smaller than ΔId2 and Id3.

Further, according to experiments and considerations by the inventor of the present application, in order to obtain both the defect compensation effect in the semiconductor layer 1a and the carrier trap reduction effect in a good balance, the film thickness t2 of the insulating film 44 (FIG. 5A). The thickness of the SiO ₂ film formed by the PE-CVD method is 1/7 to 15 times the thickness t1 of the insulating film 43, that is, the thickness of the SiO ₂ film formed by the CVD method. It is considered preferable to be within the range.

  Next, changes in the concentration of nitrogen contained in the semiconductor layer 1a to the insulating film 44 before and after the high-pressure steam treatment will be described with reference to FIG. FIG. 7 is a graph showing measurement results obtained by measuring the nitrogen concentration along the depth direction for a part of the liquid crystal device 1 shown in FIG. In the figure, the solid line indicates the nitrogen concentration before the high-pressure steam treatment, the dotted line indicates the nitrogen concentration after the high-pressure steam treatment, and a secondary ion mass spectrometer (SIMS: Secondary Lonization) is used to measure the nitrogen concentration. Mass Spectrometer) was used. In the drawing, a range D1 is a range of the film thickness of the insulating film 44, a range D2 is a range of the film thickness of the insulating film 43, and a range D3 is a range of the film thickness of the semiconductor layer 1a.

  As shown in FIG. 7, by performing the high-pressure steam treatment, the nitrogen concentration in the range D1 is decreased, and the nitrogen concentrations in the ranges D2 and D3 are increased. Therefore, nitrogen atoms contained in the insulating film 44 are diffused toward the insulating film 43 and the semiconductor layer 1a. Therefore, the diffused nitrogen atoms compensate for defects existing at the interface between the semiconductor layer 1a and the gate insulating film 43g, that is, dangling bonds, and as a result, a decrease in on-current before and after the BT test is suppressed. It was supported.

According to the measurement result shown in FIG. 7 and the consideration by the inventors of the present application, the concentration of nitrogen contained in the insulating film 43, that is, the SiO ₂ film formed by the CVD method is 1 × 10 ^{18 to} 1 × 10 ²⁰ [ is preferably included in the scope of atoms · ^{cm -3],} the nitrogen concentration in the SiO ₂ film formed by the insulating film 44, i.e., PE-CVD method, 1 × ^{10 20} to 1 × ^{10 22} [ A range of atoms · cm ⁻³ ] is considered preferable for suppressing the occurrence of carrier traps while compensating for defects.

  Next, with reference to FIG. 8, the on-currents of the TFT 30 that is an N-channel transistor and the TFT that is a P-channel transistor are compared. FIG. 8A is a graph showing a change in the on-current Id with respect to the gate voltage Vg when the insulating films 43 and 44 are formed on the TFT. FIG. 8B is a graph showing only the insulating film 43 on the TFT. 5 is a graph showing a change in the on-current Id with respect to the gate voltage Vg. In each of FIGS. 8A and 8B, the on-current is measured after the high-pressure steam treatment.

  As shown in FIG. 8A, it can be seen that the on-current Id of the N-channel transistor is suppressed when the gate voltage Vg is negative. On the other hand, in the P-channel transistor, the on-current Id is not sufficiently suppressed when the gate voltage Vg is positive.

  On the other hand, as shown in FIG. 8B, the on-current Id can be suppressed for the N-channel transistor in the range where the gate voltage Vg is negative only by performing high-pressure steam treatment on the TFT with only the insulating angle 43 formed. Similarly, the on-current is not sufficiently suppressed when the gate voltage Vg is in the positive range for the P-channel transistor.

  Therefore, it can be seen that the high-pressure steam treatment performed after forming the two-layer structure of the insulating films 43 and 44 is effective for the N-channel transistor. Therefore, as in the liquid crystal device 1 according to the present embodiment, after the insulating films 43 and 44 are formed on the N-channel TFT 30 provided in each pixel portion 72 as a pixel switching element, high-pressure steam treatment is performed. Is effective in enhancing the operating characteristics of the TFT 30.

  As described above, according to the liquid crystal device 1 according to the present embodiment, not only compensation for defects such as dangling bonds in the LDD regions 1b and 1c but also in the semiconductor layer 1a and the gate insulating film 43g, respectively. The crystal defects in can be compensated by nitrogen atoms.

  Therefore, according to the liquid crystal device 1 according to the present embodiment, defects in the semiconductor layer 1a and the gate insulating film 43g can be compensated even when a predetermined process such as an annealing process can be performed only in a low temperature range of 400 ° C. or lower. As a result, according to the liquid crystal device 1, a potential corresponding to the image signal can be supplied to each pixel electrode 9a through the TFT 30, and the display performance can be improved.

<2: Manufacturing method of liquid crystal device>
Next, a manufacturing method of the liquid crystal device for manufacturing the above-described liquid crystal device 1 will be described with reference to FIGS. 9 and 10. 9 and 10 are process cross-sectional views sequentially illustrating main processes for manufacturing the liquid crystal device 1.

As shown in FIG. 9A, a TFT 30 is formed on the TFT array substrate 10. Next, as shown in FIG. 9 (b), it was composed of SiO ₂ by a PE-CVD method using a mixed gas of TEOS (tetraethylorthosilicate) gas and oxygen (O ₂ ) gas as a reaction gas. An insulating film 43 is formed. Next, as shown in FIG. 10 (c), it was composed of SiO ₂ by PE-CVD method (plasma assisted chemical vapor deposition method) using SiH ₄ + N ₂ O-based gas as a reaction gas. An insulating film 44 is formed. Next, as shown in FIG. 10D, defects existing at the interface between the semiconductor layer 1a and the gate insulating film 43g are compensated by nitrogen atoms while suppressing the generation of carrier traps. Here, if the concentration of nitrogen in the interlayer insulating film 43 in the vicinity of the gate electrode 3a1 is set to 4 × 10 ²⁰ [atoms / cm ³ ] or more, the nitrogen atoms work as carrier traps. Therefore, in order to enhance the effect of defect compensation in the LDD regions 1b and 1c while suppressing the occurrence of carrier traps, the nitrogen concentration in the insulating film 44 is preferably 1 × 10 ²⁰ [atoms / cm ³ ].

  In addition, when the TFT 30 is subjected to high-pressure steam treatment at the stage where the insulating films 43 and 44 are formed, the off current (Ioff) of the TFT 30 can be reduced. In addition, the sheet resistance of the LDD regions 1b and 1c can be reduced. More specifically, the sheet resistance can be reduced to about 60% compared to the case where high-pressure steam treatment is not performed. Such a reduction in off current and sheet resistance is thought to be due to the improved crystallinity of the LDD regions 1b and 1c due to the high-pressure steam treatment. In addition, when the high-pressure steam treatment is performed, the nitrogen concentration in the semiconductor layer 1a increases similarly to the change in the nitrogen concentration shown in FIG. 7, so that defects are terminated by nitrogen in each of the LDD regions 1b and 1c. It is thought that defect compensation was performed. More specifically, in the LDD regions 1b and 1c, various bonds such as Si≡N bond, Si = N—O bond, and Si—N═O bond are realized, and defects in the LDD regions 1b and 1c are compensated. Conceivable.

  Such defect compensation is possible with hydrogen atoms, but in order to perform defect compensation with high efficiency and in a thermally stable state, it is preferable to use nitrogen atoms instead of hydrogen atoms. Even if only the insulating film 44 is formed on the TFT 30 without forming the insulating film 43, the defect compensation effect can be obtained. However, if the insulating film 44 is formed in the vicinity of the gate electrode 3a1, the nitrogen concentration in the gate insulating film 43g is increased. A high region is formed and carrier traps are generated. Therefore, in order to compensate for defects in the semiconductor layer 1a and suppress the generation of carrier traps, the two-layer structure of the insulating films 43 and 44 is formed on the TFT 30 as in the method of manufacturing the liquid crystal device according to this embodiment. It is preferable to form it.

<3: Electronic equipment>
Next, an example of an electronic device including the above-described liquid crystal device will be described with reference to FIGS.

  FIG. 11 is a perspective view of a mobile personal computer to which the above-described liquid crystal device is applied. In FIG. 11, a computer 1200 includes a main body 1204 having a keyboard 1202 and a liquid crystal display unit 1206 including the liquid crystal device described above. The liquid crystal display unit 1206 is configured by adding a backlight to the back surface of the liquid crystal panel 1005, and can display a high-quality image.

  Next, an example in which the above-described liquid crystal device 1 is applied to a mobile phone will be described. FIG. 12 is a perspective view of a mobile phone which is an example of an electronic apparatus. In FIG. 9, a mobile phone 1300 includes a liquid crystal device 1005 that adopts a reflective display format and has the same configuration as the above-described liquid crystal device, together with a plurality of operation buttons 1302. Therefore, according to the mobile phone 1300, high-quality image display is possible.

It is a top view of the liquid crystal device concerning this embodiment. It is II-II 'sectional drawing of FIG. 4 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix that forms an image display region of the liquid crystal device according to the present embodiment. It is sectional drawing which showed a part of structure of the pixel part of the liquid crystal device which concerns on this embodiment with a part of peripheral circuit part. It is sectional drawing which showed a part of liquid crystal device which concerns on this embodiment with the comparative example. It is the graph which showed the change of the on current with respect to the gate voltage before and after the BT test. It is the graph which showed the nitrogen concentration measured before and after each annealing treatment. 6 is a graph showing changes in gate voltage and on-current of each of a P-channel TFT and an N-channel TFT. It is process sectional drawing (the 1) which showed the main processes of the manufacturing method of the liquid crystal device which concerns on this embodiment. It is process sectional drawing (the 2) which showed the main processes of the manufacturing method of the liquid crystal device which concerns on this embodiment. It is the perspective view which showed an example of the electronic device which comprises the liquid crystal device which concerns on this embodiment. It is the perspective view which showed the other example of the electronic device which comprises the liquid crystal device which concerns on this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Liquid crystal device, 1a ... Semiconductor layer, 1a '... Channel region, 1 ... Source region, 1b, 1c ... LDD region, 1e ... Drain region, 43, 44, 45 , 46, 47 ... Insulating film

Claims (9)

(I) a semiconductor layer formed on the substrate and including a channel region, a source region, and a drain region; (ii) a gate electrode overlapping the channel region on the semiconductor layer; and (iii) the semiconductor layer and the gate. A transistor element having a gate insulating film extending between the electrodes;
A first interlayer insulating film formed on the gate electrode;
A second interlayer insulating film formed on the first interlayer insulating film and having a nitrogen concentration higher than that of the first interlayer insulating film;
The semiconductor device, wherein the semiconductor layer and the gate insulating film are subjected to predetermined processing so as to compensate for defects contained in the semiconductor layer and the gate insulating film, respectively. The predetermined treatment may be an annealing treatment in which the gate insulating film and the semiconductor layer are heat-treated in a water vapor or nitrogen atmosphere, or the gate insulating film and the second interlayer insulating film through the first interlayer insulating film and the second interlayer insulating film. The semiconductor device according to claim 1, wherein the semiconductor device is high-pressure steam treatment for supplying steam to the semiconductor layer at high pressure. The semiconductor device according to claim 1, wherein the semiconductor layer has LDD regions formed on both sides of the channel region. The semiconductor device according to any one of claims 1 to 3, wherein the transistor element is an N-channel transistor. 5. The semiconductor device according to claim 1, wherein the transistor element is a pixel switching element formed in each of a plurality of pixel portions constituting a display region on the substrate. 6. . The first interlayer insulating film is a SiO ₂ film formed by a PE-CVD method using a mixed gas of TEOS (tetraethylorthosilicate) gas and oxygen (O ₂ ) gas as a reaction gas,
The second interlayer insulating film is a SiO ₂ film formed by a PE-CVD method (plasma assisted chemical vapor deposition method) using a SiH ₄ + N ₂ O-based gas as a reaction gas. The semiconductor device according to any one of claims 1 to 5. The film thickness of the second interlayer insulating film formed by the PE-CVD method is 1/7 to 15 times the film thickness of the first interlayer insulating film formed by the PE-CVD method. The semiconductor device according to claim 6. The nitrogen concentration contained in the first interlayer insulating film formed by the PE-CVD method is in the range of 1 × 10 ^{18 to} 1 × 10 ²⁰ [atoms · cm ⁻³ ],
The nitrogen concentration contained in the second interlayer insulating film formed by the PE-CVD method is in the range of 1 × 10 ^{20 to} 1 × 10 ²² [atoms · cm ⁻³ ]. Item 8. The semiconductor device according to Item 6 or 7. (I) a semiconductor layer formed on the substrate and including a channel region, a source region, and a drain region; (ii) a gate electrode overlapping the channel region on the semiconductor layer; and (iii) the semiconductor layer and the gate. Forming a transistor element having a gate insulating film extending between the electrodes;
Forming a first interlayer insulating film formed on the gate electrode;
Forming a second interlayer insulating film having a nitrogen concentration higher than that of the first interlayer insulating film on the first interlayer insulating film;
And a step of performing a predetermined treatment on the semiconductor layer and the gate insulating film so that defects contained in each of the semiconductor layer and the gate insulating film are compensated for. .

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