JP2009038127A - 半導体装置 - Google Patents
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Abstract
【解決手段】半導体チップ20には、再配線を持つ第1の外部電極23B〜23Dと、下端は、仮想線Lhの下まで、右端は、仮想線Lvの右端またはそれを超えるように延在されている。そのため、発熱する部分では、従来の再配線が無く、面積の大きい外部電極を配置できるため、放熱性の向上が実現できる。
【選択図】図1
Description
特に、リードフレームや実装基板を用いないW−CSP技術(Wafer Level−Chip Size Package または Wafer Level−Chip Scale Package)は、製造コストの低減などが期待でき、最終的な小型のパッケージを実現するものとして注目を集めている。
第2のコンタクトが設けられた位置から、前記半導体チップの縦の中心線および横の中心線の近傍またはそれらを超えて延在する第2の外部電極を有する事で解決するものである。
続いて第2の構造として、
第1のコンタクトと接続され、前記第1のコンタクトの位置と異なる領域に延在するため、前記外部電極の幅よりも狭い再配線が設けられた第1の外部電極と、
第2のコンタクトと接続され、前記短辺方向には、前記半導体チップの周囲から、前記半導体チップの長辺と平行な前記半導体チップの中心線近傍またはそれを超え、長辺方向には、表面に設けられる端子の先まで延在する第2の外部電極を有する事で解決するものである。
また従来構造の様なネックがないため、熱膨張係数αの違いにより外部電極23の部分のクラック発生を抑止することができる。
つまり、従来の再配線5を用いて製造すれば、その再配線5の周りには、空き領域が存在し、この空き領域を有効に活用しようとして考えられたものである。
では、具体的に、図1Aの構造について説明する。
本発明は、前述した外部電極23Aにその特徴がある。
S(23A)≒S/4 、または S(23A)>S/4
の関係を有する。ここで外部電極の面積は、外部電極外周とチップ周囲までのスペースLにも影響はあるが、このスペースLは、常識的な範囲である。
また膜厚は、例えば3〜10μmの内、厚めの膜厚を選択することで、ヒートシンクの機能も持たせられ、熱伝導が良好に成る。
ここで構造の説明は、端子の数と外部電極の構造だけが異なるだけであり、それ以外は実質同じ説明となるため、異なる部分のみを説明する。
また保護シートは、フィラーの入った放熱性の優れたものでも良い。
21A:第2のコンタクト
21B〜21D:第1のコンタクト
22:端子
23A:第2の外部電極
23B〜23D:第1の外部電極
24:半導体装置
Lh、Lv:中心線
Claims (8)
- 半導体チップの表面にフェイスダウン用の外部電極が複数設けられた半導体装置であり、
前記複数の外部電極は、前記半導体チップに設けられたコンタクトを介して前記半導体チップに形成された能動素子と電気的に接続され、
第1のコンタクトの位置と異なる領域に延在するため、前記外部電極の幅よりも狭い再配線が設けられた第1の外部電極と、
第2のコンタクトが設けられた位置から、前記半導体チップの縦の中心線および横の中心線の近傍またはそれらを超えて延在する第2の外部電極を有する事を特徴とした半導体装置。 - 前記複数の外部電極を被覆する絶縁性被膜の開口部には、ロウ材が設けられる請求項1記載の半導体装置。
- 前記半導体チップは、低温の第1の領域と、前記第1の領域よりも高温な第2の領域があり、前記第2の外部電極は、前記第2の領域を被覆する請求項1または請求項2記載の半導体装置。
- 表面が長方形の半導体チップの表面にフェイスダウン用の外部電極が複数設けられた半導体装置であり、
前記複数の外部電極は、前記半導体チップに形成された能動素子とコンタクトを介して電気的に接続され、
第1のコンタクトと接続され、前記第1のコンタクトの位置と異なる領域に延在するため、前記外部電極の幅よりも狭い再配線が設けられた第1の外部電極と、
第2のコンタクトと接続され、前記短辺方向には、前記半導体チップの周囲から、前記半導体チップの長辺と平行な前記半導体チップの中心線近傍またはそれを超え、長辺方向には、表面に設けられる端子の先まで延在する第2の外部電極を有する事を特徴とした半導体装置。 - 前記第2の外部電極は、実質矩形で、短辺と平行に延在する側辺に沿って複数の前記第2のコンタクトが設けられる請求項4に記載の半導体装置。
- 前記第2の電極は複数設けられ、一は前記半導体チップの一方の長辺から前記長辺と平行な中心線の近傍またはそれを超えて延在され、一は前記半導体チップの他方の長辺から前記長辺と平行な中心線の近傍またはそれを超えて延在される請求項4に記載の半導体装置。
- 前記半導体チップは、低温の第1の領域と、前記第1の領域よりも高温な第2の領域があり、前記第2の外部電極は、前記第2の領域を被覆する請求項4から請求項6のいずれかに記載の半導体装置。
- 前記半導体チップの裏面には、チッピング防止としてフィルムが貼りあわされている請求項1〜請求項7のいずれかに記載の半導体装置。
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JP2009038127A5 JP2009038127A5 (ja) | 2010-08-19 |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH062687U (ja) * | 1992-06-03 | 1994-01-14 | 新電元工業株式会社 | 半導体装置 |
JP2004214556A (ja) * | 2003-01-08 | 2004-07-29 | Denso Corp | チップサイズパッケージ |
JP2005158777A (ja) * | 2003-11-20 | 2005-06-16 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005340590A (ja) * | 2004-05-28 | 2005-12-08 | Yamaha Corp | 半導体装置及びこれを備えた半導体ユニット |
JP2007012756A (ja) * | 2005-06-29 | 2007-01-18 | Rohm Co Ltd | 半導体装置 |
JP2007115760A (ja) * | 2005-10-18 | 2007-05-10 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH062687U (ja) * | 1992-06-03 | 1994-01-14 | 新電元工業株式会社 | 半導体装置 |
JP2004214556A (ja) * | 2003-01-08 | 2004-07-29 | Denso Corp | チップサイズパッケージ |
JP2005158777A (ja) * | 2003-11-20 | 2005-06-16 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005340590A (ja) * | 2004-05-28 | 2005-12-08 | Yamaha Corp | 半導体装置及びこれを備えた半導体ユニット |
JP2007012756A (ja) * | 2005-06-29 | 2007-01-18 | Rohm Co Ltd | 半導体装置 |
JP2007115760A (ja) * | 2005-10-18 | 2007-05-10 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
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