JP2009031208A - Tft array inspection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a time needed for detecting various defects in a TFT array substrate and to improve detection efficiency of detection signals by optimizing a voltage condition of an energy filter. <P>SOLUTION: A TFT array inspection device supplies a drive signal to a TFT array substrate to drive it, energy-selects secondary electrons obtained by irradiating pixels of the TFT array substrate which is driven by the drive signal and detects them with electron beams, and detects defects of the TFT array substrate by the secondary electron signal intensity obtained. The TFT array inspection device includes the energy filter for energy-selecting and a secondary electron detector for detecting secondary electrons which pass through the energy filter. In the device, the potential of the energy filter is switched by synchronizing with the signal waveform of the drive signal. By synchronizing the potential of the energy filter with the signal waveform of the drive signal, the detection condition of the secondary electrons can be set at an optimum detection condition in response to a drive pattern. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a TFT array inspection apparatus used for inspecting a TFT array substrate used for a liquid crystal display, an organic EL display, and the like, and more particularly, a TFT for detecting a defect of a substrate by measuring the potential of a sample using an electron beam. The present invention relates to an array inspection apparatus.

  A manufacturing process of a semiconductor substrate on which a TFT array such as a liquid crystal substrate or an organic EL substrate is formed includes a TFT array inspection process in the manufacturing process, and the TFT array is inspected for defects in this TFT array inspection process.

  The TFT array is used as a switching element for selecting a pixel electrode of a liquid crystal display device, for example. In a substrate including a TFT array, for example, a plurality of gate lines functioning as scanning lines are arranged in parallel, and a plurality of source lines described as signal lines are arranged orthogonal to the gate lines. A TFT (Thin Film Transistor) is disposed in the vicinity of a portion where the lines intersect, and a pixel electrode is connected to the TFT.

  The liquid crystal display device is configured by sandwiching a liquid crystal layer between a substrate provided with the TFT array described above and a counter substrate, and a pixel capacitor is formed between the counter electrode and the pixel electrode provided in the counter substrate. In addition to the pixel capacitor, an additional capacitor (Cs) is connected to the pixel electrode. One of the additional capacitors (Cs) is connected to the pixel electrode, and the other is connected to the common line or the gate line. The TFT array configured to be connected to the common line is a Cs on Com type TFT array, and the TFT array configured to be connected to the gate line is a Cs on Gate type TFT array.

  In this TFT array, a scanning line (gate line) or a signal line (source line) is disconnected, a scanning line (gate line) and a signal line (source line) are short-circuited, or a pixel defect due to a characteristic defect of a TFT driving a pixel. In the defect inspection, for example, the counter electrode is grounded, a DC voltage of, for example, −15 V to +15 V is applied to all or part of the gate line at a predetermined interval, and an inspection signal is applied to all or part of the source line. By doing that. (For example, the prior art of patent document 1.) TFT array test | inspection can detect a defect by inputting the drive signal for a test | inspection into a TFT array, and detecting the voltage state at that time.

  Various defects can occur in a TFT array during its manufacturing process. 9 to 12 are diagrams for explaining examples of defects.

  FIG. 9 is a diagram for explaining a defect generated in each element portion constituting the TFT array. Each defect indicated by a broken line in FIG. 9 includes a short-circuit defect (S-DSshort) between the pixel 12oe and the source line 15e, a short-circuit defect (G-DSshort) between the pixel 12eo and the gate line 14e, and a source line 15o. In addition to a short-circuit defect (S-Gshort) between the pixel 12ee and the gate line 14e, a disconnection (D-open) between the pixel 12ee and the TFT 11ee is shown.

  In addition to the above-described defect in each pixel, there is an adjacent defect that occurs between adjacent pixels. As this adjacent defect, a defect between adjacent pixels in the horizontal direction (horizontal PP), a defect between adjacent pixels in the vertical direction (vertical PP), a short circuit between adjacent source lines (SSshort), and between adjacent gate lines A short circuit (GGshort) is known.

  FIG. 10 is a view for explaining adjacent defects in the horizontal direction. The broken lines in FIG. 10 indicate a short-circuit defect (lateral PP) between the pixels 12eo and 12ee adjacent in the horizontal direction and a short-circuit defect (SSshort) between the source lines So and Se adjacent in the horizontal direction, respectively. Yes.

  FIG. 11 is a diagram for explaining the adjacent defect in the vertical direction. The broken lines in FIG. 11 indicate short-circuit defects (vertical PP1) between pixels 12oo and 12eo adjacent in the vertical direction, short-circuit defects (vertical PP2) between pixels 12oe and 12ee adjacent in the vertical direction, and vertical direction. In FIG. 1, short-circuit defects (GGshort) between adjacent gate lines Go and Ge are shown.

  In a TFT array inspection apparatus using an electron beam, the pixel (ITO electrode) is irradiated with an electron beam, and secondary electrons emitted by this electron beam irradiation are detected and applied to the pixel (ITO electrode). The voltage waveform is changed to a secondary electron waveform and imaged by a signal, whereby the TFT array is electrically inspected.

  As a driving pattern for inspecting a defect generated in each pixel, for example, a driving pattern in which a positive voltage (for example, 10 v) and a negative voltage (for example, −10 v) are alternately applied to all the pixels of the TFT array to drive uniformly is used. is there. When a defect inspection is performed using this uniformly driven driving pattern, adjacent defects cannot be detected.

  Therefore, in the conventional defect inspection, in order to detect adjacent defects, an inspection pattern for laterally adjacent defects and an inspection pattern for longitudinally adjacent defects are used as independent inspection patterns. A laterally adjacent defect and a longitudinally adjacent defect are detected independently.

  For example, when detecting a laterally adjacent defect, a voltage is applied so that a voltage distribution formed by a positive voltage pixel (ITO) and a negative voltage pixel (ITO) on the TFT array becomes a vertical stripe pattern. In this vertical stripe pattern, the pixels in the vertical direction of the TFT array have the same voltage, and the adjacent pixel rows in the horizontal direction have different voltages. Thereby, a laterally adjacent defect is detected.

  Further, when detecting vertical adjacent defects, a voltage is applied so that the voltage distribution formed by the positive voltage pixel (ITO) and the negative voltage pixel (ITO) on the TFT array becomes a horizontal stripe pattern. In this horizontal stripe pattern, the pixels in the horizontal direction of the TFT array have the same voltage, and the adjacent vertical pixel columns have different voltages. Thereby, the vertical adjacent defect is detected.

  In addition to the above-described stripe-shaped drive pattern driving pattern, adjacent defect detection is also known as a checker pattern that detects adjacent defects by applying a positive potential and a negative potential in a checkered pattern.

  On the other hand, an inspection method using potential contrast is known as a technique for measuring the potential of a sample without contact. According to this potential contrast, the potential of the sample can be measured by measuring the energy of secondary electrons emitted from the sample surface by irradiating the sample with an electron beam.

  Moreover, in the TFT array substrate, in the inspection of the defective pixel etc. of the TFT array substrate, it is non-contact by applying the above-described inspection method using the potential contrast instead of the method in which the mechanical probe is brought into contact with the TFT array. A TFT inspection apparatus for inspecting by measurement has been proposed. In this TFT array inspection apparatus, a TFT array substrate used for a liquid crystal display, an organic EL display, etc. is irradiated with an electron beam, and a secondary electron generated from the TFT array substrate is measured to obtain a predetermined signal on the TFT array substrate. Whether or not a defective cell such as a short circuit is determined based on the measurement result. For example, Patent Documents 2, 3, and 4 are known as such TFT array inspection apparatuses.

  In the TFT array inspection apparatus using the electron beam, a configuration in which a secondary electron filter grid is provided between the sample and the detector is used to detect secondary electrons emitted from the sample. FIG. 12 is a diagram for explaining an outline of a detection portion used in a conventional TFT array inspection apparatus.

  In FIG. 12, a TFT array inspection apparatus 101 includes an electron beam source 102 that irradiates a sample TFT array substrate 110 with an electron beam, a secondary electron detector 103 that detects secondary electrons emitted from the substrate 110, Recoil secondary electron suppression that increases the collection rate of secondary electrons by the secondary electron filter grid 106 (106A, 106B) constituting the energy filter that allows passage of secondary electrons of a predetermined energy or higher and the secondary electron detector 103. A vacuum chamber 104 is provided for accommodating the grid 105, the substrate 110, the grids 105, 106, and the like in a vacuum state. The recoil secondary electrons are secondary electrons generated when reflected electrons from the sample collide with the wall surface.

  Secondary electrons generated from the TFT array substrate are filtered with a predetermined energy by the energy filter of the secondary electron filter grid 106 and detected by the secondary electron detector 103.

  The detected secondary electron intensity signal is converted into an analog signal by a secondary electron detector 103 such as a photomultiplier. The obtained data is allocated by simply calculating the detected coordinates in association with the pixels, extracting defects by image processing, and outputting the defect data.

JP-A-5-307192 Japanese Patent Laid-Open No. 11-265678 (FIGS. 2 and 20) Japanese Unexamined Patent Publication No. 2000-3142 (FIGS. 1, 5, 29) JP 2004-228431 A

  The drive pattern for detecting a defect in the TFT array substrate has a difference in detection applicability depending on the type of defect. For example, in an adjacent defect (pixel short) caused by short-circuiting ITO between pixels, a driving pattern in which a different potential is charged to the adjacent pixel is used, and the shorted pixel becomes −potential. In addition, a short circuit (SD short) between the drain and source of the TFT can be detected at any potential of a positive potential charge or a negative potential charge, but can be detected by using a negative potential charge. Becomes better.

  In addition, when the ITO and the source line are not metal but have a defect in which a capacitive component is connected, such as α-Si, driving to charge to a positive potential in order to detect leakage of the charge charged in the capacitor. A pattern is required.

  Therefore, to detect different types of defects, it is necessary to detect with a plurality of drive patterns. Therefore, the drive pattern is selected according to the type of defect to be detected, the detection signal using this drive pattern is acquired multiple times, and the obtained signals are integrated to improve detection accuracy. Yes. For example, using a driving pattern such as a uniform pattern for charging the entire surface to + potential or -potential, a stripe pattern for detecting adjacent defects, etc., and acquiring and integrating a plurality of detection signals for each driving pattern as a frame unit. Various defects are detected by switching and repeating the drive pattern.

  In addition, when performing defect inspection of a TFT array substrate using potential contrast, a difference in secondary electron signals obtained between a normal pixel and a defective pixel is greatly increased by applying a predetermined voltage using an energy filter. Thus, the detection efficiency of secondary electrons can be increased. Conventionally, even when different driving patterns are used to detect various defects, the same voltage condition is applied to the energy filter. Is set.

  In the defect inspection of the TFT array substrate, it is required to reduce the inspection time in order to increase the inspection throughput. As described above, in order to detect various defects on the TFT array substrate, depending on the type of defect. It is necessary to switch the driving pattern, and repetition of signal acquisition by switching the driving pattern is a factor that prolongs the inspection time.

  In addition, by optimizing the voltage condition applied to the energy filter, it is expected that the detection efficiency of the detection signal is increased, thereby reducing the inspection time. However, the conventional voltage filter has the same voltage condition. Since it is set, there is a problem that the optimum voltage condition is not always set in the energy filter when the drive pattern is switched.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above problems and shorten the time required for detecting various defects of a TFT array substrate.

  More specifically, an object is to improve the detection efficiency of the detection signal by optimizing the voltage condition of the energy filter. In addition, by reducing the number of drive patterns used, the number of detection signal acquisition operations is reduced, and by setting the voltage conditions of the energy filter according to this drive pattern, various defect detections of the TFT array substrate are detected. The purpose is to shorten the time required for.

  For various defects on the TFT array substrate, the detection signal detection efficiency can be improved by switching and setting the voltage applied to the energy filter in accordance with the drive pattern used for defect detection. In addition, by using a checkered checker pattern as the defect detection drive pattern, the number of operations required to change the voltage state of the TFT array substrate is reduced, and the potential change applied to the energy filter is applied to the electron beam irradiation. By performing the synchronization, the time required for detecting various defects of the TFT array substrate is shortened.

  According to the present invention, a drive signal is supplied to the TFT array substrate to drive, and secondary electrons obtained by irradiating an electron beam to the pixels of the TFT array substrate driven thereby are detected by energy selection and obtained. A TFT array inspection apparatus that detects defects in a TFT array substrate based on secondary electron signal intensity, and includes an energy filter that performs energy selection and a secondary electron detector that detects secondary electrons that have passed through the energy filter.

  The present invention switches the potential of the energy filter in synchronization with the signal waveform of the drive signal. By synchronizing the potential of the energy filter and the signal waveform of the drive signal, the detection conditions for secondary electron detection can be set to an optimum one according to the drive pattern, and the detection efficiency can be improved.

  Further, when secondary electrons from each pixel are detected by causing the pixels on the TFT array substrate to scan the electron beam, the switching of the potential of the energy filter is synchronized with the electron beam irradiation, and the electron beam is irradiated. The potential of the energy filter is switched in units of a region including a single pixel or a plurality of pixels on the TFT array substrate.

  Thereby, the detection efficiency of secondary electrons emitted from the pixel or the region including a plurality of pixels can be improved.

  As the drive pattern used in the TFT array inspection apparatus of the present invention, various drive patterns such as a checker pattern, a stripe pattern, or an entire surface pattern can be used according to the type of defect of the TFT array substrate.

  The driving pattern of the checker pattern is a signal waveform for driving a pixel or a region including a plurality of pixels on the TFT array substrate in different potential states in a two-dimensional pattern alternately.

  The drive pattern of the stripe pattern is a signal waveform that drives a pixel or a region including a plurality of pixels on the TFT array substrate in different potential states in a two-dimensional manner in a column or row direction.

  When driving the driving TFT array substrate with each of these driving patterns, the potential of each pixel on the TFT array substrate differs depending on the driving pattern. In the present invention, when the TFT array substrate is scanned with an electron beam, the potential of the energy filter is switched in synchronization with the potential of the pixel irradiated with the electron beam during scanning.

  Further, as a drive pattern used in the FT array substrate inspection apparatus of the present invention, a signal waveform of a full pattern that drives all pixels on the TFT array substrate to the same potential state can be used. In the driving by the entire surface pattern, for example, the potential of the energy filter is switched in synchronization with the driving with the entire surface being a high potential and the driving with the entire surface being a low potential.

  The energy filter may include at least two grids and apply a different voltage to each grid.

  The inventor of the present invention has a secondary electron detection intensity characteristic in which the detection amount of secondary electrons detected by the secondary electron detector varies depending on the potential of the substrate and the potential of the energy filter. It has been found that the secondary electron detection intensity characteristics can be changed by using a plurality of grids and varying the voltage applied to each grid.

  By changing the secondary electron detection intensity characteristics according to the voltage applied to each grid, the potential change on the substrate can be detected with high accuracy, and the defect type of the substrate that cannot be detected by the conventional array inspection apparatus Can also be detected.

  The energy filter is disposed between the substrate and the secondary electron detector, and the voltage applied to the grid disposed on the side far from the substrate is set higher than the voltage applied to the grid disposed on the side close to the substrate. . Depending on the mode of the applied voltage, the amount of secondary electrons detected by the secondary electron detector can be greatly changed for different potentials on the substrate. The TFT array inspection apparatus detects a difference in potential on the substrate based on a change in the detected amount of secondary electrons detected by the secondary electron detector, and detects a substrate defect caused by the difference in voltage. Can do.

  According to the present invention, the time required for detecting various defects of the TFT array substrate can be shortened.

  Further, the detection efficiency of the detection signal can be improved by optimizing the voltage condition of the energy filter.

  By reducing the number of drive patterns used, the number of detection signal acquisition operations is reduced, and by setting the voltage conditions of the energy filter in accordance with the drive patterns, it is necessary to detect various defects on the TFT array substrate. Time can be shortened.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic view of a TFT array inspection apparatus of the present invention.

  The TFT array inspection apparatus 1 includes an inspection signal generation unit 4 that generates an inspection signal for array inspection on the TFT array substrate 10, a prober 8 that applies the inspection signal generated by the inspection signal generation unit 4 to the TFT array substrate 10, A mechanism for detecting the voltage application state of the TFT array substrate (electron beam source 2, secondary electron detector 3) and a mechanism for detecting defects in the TFT array based on the detection signal (signal processing unit 31, defect detection unit 32) Is provided.

  The prober 8 includes a prober frame provided with probe pins (not shown). The prober 8 brings probe pins into contact with electrodes formed on the TFT array substrate 10 by placing them on the TFT array substrate 10 and applies an inspection signal to the TFT array.

  The TFT array substrate 10 is in a potential state according to the applied inspection signal, and is in a different potential state if the array has a defect. By detecting this potential state, an array defect of the TFT array substrate can be detected.

  The mechanism for detecting the voltage application state of the TFT array substrate can have various configurations. The configuration shown in FIG. 1 is a detection configuration using an electron beam, and an electron beam source 2 that irradiates an electron beam onto the TFT array substrate 10, and secondary electrons emitted from the TFT array substrate 10 are detected by the irradiated electron beam. A secondary electron detector 3, and a signal processing unit 5 that detects a potential state on the TFT array substrate 10 by processing a detection signal of the secondary electron detector 3.

  Since the TFT array irradiated with the electron beam emits secondary electrons corresponding to the voltage of the applied inspection signal, the potential state of the TFT array can be detected by detecting the secondary electrons.

  The signal processing unit 31 detects the potential state of the TFT array based on the detection signal of the secondary electron detector 3, and the defect detection unit 32 compares the potential state acquired by the signal processing unit 31 with the potential state in the normal state. By doing so, defects in the TFT array are detected.

  The inspection signal generation unit 4 generates a driving pattern of inspection signals for driving the TFT array formed on the TFT array substrate 10. This drive pattern will be described later.

  The control unit 21 controls the electron source 2 and the stage 7 in order to scan the electron beam and irradiate the inspection position of the TFT array on the TFT array substrate 10. The electron source 2 swings the electron beam irradiating the TFT array substrate 10 in the XY direction, and the stage 7 moves the TFT array substrate 10 placed on the stage in the XY direction, thereby changing the irradiation position of the electron beam. Scan. The scanning position becomes the detection position.

  The above-described configuration of the TFT array inspection apparatus is an example, and is not limited to this configuration.

  Next, an equivalent circuit of the TFT array of the TFT array substrate of the present invention will be described with reference to FIG. 2 for the Cs on Com type TFT array and will be described with reference to FIG. 3 for the Cs on Gate type TFT array. . Here, the Cs on Com type TFT array has a configuration in which one connection end of the additional capacitor (Cs) connected to the pixel electrode is connected to a common line (Cs line). One connecting end of the additional capacitor (Cs) connected to the pixel electrode is connected to a gate line (Gate line).

  First, the case of a Cs on Com type TFT array will be described. On the TFT array substrate, TFTs are provided in a TFT area 11A in the vicinity of a portion where the array gate line 14 and the source line 15 intersect. Further, a Cs line 16 for connecting an additional capacitor (Cs) is provided between adjacent gate lines 14.

  FIG. 2 shows an equivalent circuit of a Cs on Com type TFT array. In this equivalent circuit, the gate line 14 and the source line 15 are shown divided into two even-numbered and odd-numbered line groups.

  A pixel 12oo is provided in the vicinity of a portion where the odd-numbered gate line 14o and the odd-numbered source line 15o intersect. One end of the pixel (Pixel) 12oo is connected to the TFT 11oo, and the other end is connected to the additional capacitor (Cs) 13oo. The other end of the additional capacitor (Cs) 13oo is connected to the Cs line 16. The drain D of the TFT 11oo is connected to the pixel 12oo, the gate G is connected to the odd-numbered gate line 14o, and the source S is connected to the odd-numbered source line 15o.

  Similarly, a pixel 12oe is provided in the vicinity of a portion where the odd-numbered gate line 14o and the even-numbered source line 15e intersect. One end of the pixel (Pixel) 12oe is connected to the TFT 11oe, and the other end is connected to the additional capacitor (Cs) 13oe. The other end of the additional capacitor (Cs) 13oe is connected to the Cs line 16. The drain D of the TFT 11oe is connected to the pixel 12oe, the gate G is connected to the odd-numbered gate line 14o, and the source S is connected to the even-numbered source line 15e.

  Further, a pixel 12eo is provided in the vicinity of a portion where the even-numbered gate line 14e and the odd-numbered source line 15o intersect. One end of the pixel (Pixel) 12eo is connected to the TFT 11eo, and the other end is connected to an additional capacitor (Cs) 13eo. The other end of the additional capacitor (Cs) 13eo is connected to the Cs line 16. The drain D of the TFT 11eo is connected to the pixel 12eo, the gate G is connected to the even-numbered gate line 14e, and the source S is connected to the odd-numbered source line 15o.

  Further, a pixel 12ee is provided in the vicinity of a portion where the even-numbered gate line 14e and the even-numbered source line 15e intersect. One end of the pixel 12ee is connected to the TFT 11ee, and the other end is connected to the additional capacitor (Cs) 13ee. The other end of the additional capacitor (Cs) 13ee is connected to the Cs line 16. The drain D of the TFT 11ee is connected to the pixel 12ee, the gate G is connected to the even-numbered gate line 14e, and the source S is connected to the even-numbered source line 15e.

  Therefore, the voltage of the odd-numbered source line 15o is applied to the pixel (Pixel) 12oo according to the on-pulse signal of the odd-numbered gate line 14o, and the on-pulse of the odd-numbered gate line 14o is applied to the pixel (Pixel) 12oe. The voltage of the even-numbered source line 15e is applied according to the signal, and the voltage of the odd-numbered source line 15o is applied to the pixel (Pixel) 12eo according to the on-pulse signal of the even-numbered gate line 14e. Pixel) 12ee is applied with the voltage of the even-numbered source line 15e in accordance with the on-pulse signal of the even-numbered gate line 14e.

  Next, the case of a Cs on Gate type TFT array will be described. On the TFT array substrate, TFTs are provided in a TFT area 11A in the vicinity of a portion where the array gate line 14 and the source line 15 intersect.

  FIG. 3 shows an equivalent circuit of the Cs on Gate type TFT array. In this equivalent circuit, the gate line 14 and the source line 15 are shown divided into two even-numbered and odd-numbered line groups.

  A pixel 12oo is provided in the vicinity of a portion where the odd-numbered gate line 14o and the odd-numbered source line 15o intersect. One end of the pixel (Pixel) 12oo is connected to the TFT 11oo, and the other end is connected to the additional capacitor (Cs) 13oo. The other end of the additional capacitor (Cs) 13oo is connected to the even-numbered gate line 14e. The drain D of the TFT 11oo is connected to the pixel 12oo, the gate G is connected to the odd-numbered gate line 14o, and the source S is connected to the odd-numbered source line 15o.

  Similarly, a pixel 12oe is provided in the vicinity of a portion where the odd-numbered gate line 14o and the even-numbered source line 15e intersect. One end of the pixel (Pixel) 12oe is connected to the TFT 11oe, and the other end is connected to the additional capacitor (Cs) 13oe. The other end of the additional capacitor (Cs) 13oe is connected to the even-numbered gate line 14e. The drain D of the TFT 11oe is connected to the pixel 12oe, the gate G is connected to the odd-numbered gate line 14o, and the source S is connected to the even-numbered source line 15e.

  Further, a pixel 12eo is provided in the vicinity of a portion where the even-numbered gate line 14e and the odd-numbered source line 15o intersect. One end of the pixel (Pixel) 12eo is connected to the TFT 11eo, and the other end is connected to the additional capacitor (Cs) 13eo. The other end of the additional capacitor (Cs) 13eo is connected to the odd-numbered gate line 14o. The drain D of the TFT 11eo is connected to the pixel 12eo, the gate G is connected to the even-numbered gate line 14e, and the source S is connected to the even-numbered source line 15e.

  Further, a pixel 12ee is provided in the vicinity of a portion where the even-numbered gate line 14e and the even-numbered source line 15e intersect. One end of the pixel 12ee is connected to the TFT 11ee, and the other end is connected to the additional capacitor (Cs) 13ee. The other end of the additional capacitor (Cs) 13ee is connected to the odd-numbered gate line 14o. The drain D of the TFT 11ee is connected to the pixel 12ee, the gate G is connected to the even-numbered gate line 14e, and the source S is connected to the even-numbered source line 15e.

  Therefore, the voltage of the odd-numbered source line 15o is applied to the pixel (Pixel) 12oo according to the on-pulse signal of the odd-numbered gate line 14o, and the on-pulse of the odd-numbered gate line 14o is applied to the pixel (Pixel) 12oe. The voltage of the even-numbered source line 15e is applied according to the signal, and the voltage of the odd-numbered source line 15o is applied to the pixel (Pixel) 12eo according to the on-pulse signal of the even-numbered gate line 14e. Pixel) 12ee is applied with the voltage of the even-numbered source line 15e in accordance with the on-pulse signal of the even-numbered gate line 14e.

  Hereinafter, a test signal drive pattern example according to the present invention will be described with reference to FIG. 4 and FIG. 5 example test signal examples and FIG. 6 pixel applied voltage example.

  4 and 5 show the driving pattern of the inspection signal within one gate period of the present invention, which can be commonly used for the Cs on Com type TFT array and the Cs on Gate type TFT array. Hereinafter, description will be given using an example of the Cs on Com type TFT array shown in FIG.

  In the test signal drive patterns shown in FIGS. 4 and 5, for example, within one gate period, the gate lines 14o ((Go in FIG. 4A, Go in FIG. 5A), 14e (FIG. 4B) , Ge of FIG. 5B)) are output at equal time intervals, and source lines 15o ((So of FIGS. 4C and 5C)), 15e (FIG. d), the voltage applied to Se) in FIG. 4D is applied to the ITO of each pixel (Pixel) 12 (12oo, 12oe, 12eo, 12ee) at each intersection, and each TFT 11 (11oo, 11oe, 11eo, 11ee). ).

  At this time, depending on the combination of the voltage of the gate line 14 and the voltage of the source line 15 and the switching of the voltages, each pixel (Pixel) 12 (12oo, 12oe, 12eo, 12ee) has a different voltage for the adjacent pixels. Applied.

  Note that one gate period (period shown by 1 to 10 in FIGS. 4 and 5) can be set to an arbitrary time width, but can be set to 16 msec as an example.

  In the example of FIG. 4, for convenience of explanation, one gate period is indicated by 10 time intervals of 1 to 10, and this one gate period is indicated by a first period (shown by 1 to 5) and a second period (6 to 6). In the first period, the pixel (Pixel) holds + voltage (+10 V), and in the second period, the pixel (Pixel) holds −voltage (−10 V).

  In the first period (period shown by 1 to 5 in FIG. 4), on-pulse signals are generated on the gate line Go and the gate line Ge (FIGS. 4A and 4B). At this time, a positive voltage (+10 V) is applied to the source line So in a period corresponding to the on-pulse signal of the gate line Go, and then a negative voltage (−10 V) is applied (FIG. 4C). Further, a positive voltage (+10 V) is applied to the source line Se in a period corresponding to the on-pulse signal of the gate line Ge, and then a negative voltage (−10 V) is applied (FIG. 4D).

  In the period indicated by “6” in the second period in FIG. 4, an on-pulse signal is generated in the gate line Go and the gate line Ge (FIGS. 4A and 4B). At this time, the source line So and the source line Se are kept in a state where a negative voltage (-10V) is applied (FIGS. 4C and 4D).

  Due to the on-pulse signal and the applied voltage, the pixels (pixels) 12oo, 12ee, 12oe, and 12eo are held at a positive voltage (+ 10V) in the first period, and the pixels (pixels) 12oo, 12ee, and 12eo in the second period. 12oe and 12eo are held at -voltage (-10V).

  FIG. 6A shows the voltage state of the pixel 12 in the first period, and all the pixels are held at + voltage (+10 V). FIG. 6B shows the voltage state of the pixel 12 in the second period, and all the pixels are held at a negative voltage (−10 V).

  With this drive pattern, an entire surface pattern is formed in which all pixels on the TFT array substrate are set to a positive potential or a negative potential.

  When the TFT array on the TFT array substrate is subjected to a defect inspection with a driving pattern for uniformly driving as shown in FIG. 13, the adjacent defect cannot be detected. In order to detect an adjacent defect, for example, an inspection pattern for a laterally adjacent defect and an inspection pattern for a longitudinally adjacent defect are used as independent inspection patterns. Vertically adjacent defects can be detected independently.

  For example, when detecting a laterally adjacent defect, a voltage is applied so that a voltage distribution formed by a positive voltage pixel (ITO) and a negative voltage pixel (ITO) on the TFT array becomes a vertical stripe pattern. In this vertical stripe pattern, the pixels in the vertical direction of the TFT array have the same voltage, and the adjacent pixel rows in the horizontal direction have different voltages. Thereby, a laterally adjacent defect is detected.

  Further, when detecting vertical adjacent defects, a voltage is applied so that the voltage distribution formed by the positive voltage pixel (ITO) and the negative voltage pixel (ITO) on the TFT array becomes a horizontal stripe pattern. In this horizontal stripe pattern, the pixels in the horizontal direction of the TFT array have the same voltage, and the adjacent vertical pixel columns have different voltages. Thereby, the vertical adjacent defect is detected.

  FIG. 5 shows another example of the drive pattern of the inspection signal, in which the vertical and horizontal adjacent defects are formed with one drive pattern. Also in the example of FIG. 5, for convenience of explanation, one gate period is indicated by 10 time intervals of 1 to 10, and this one gate period is indicated by a first period (indicated by 1 to 5) and a second period (6 In the first period and the second period, a positive voltage (+10 V) and a negative voltage (−10 V) are alternately held in the pixel (Pixel).

  In the first period (period shown by 1 to 5 in FIG. 5), on-pulse signals are generated on the gate line Go and the gate line Ge (FIGS. 5A and 5B).

  First, an on-pulse signal is generated on the gate line Go (FIG. 5A), and then an on-pulse signal is generated on the gate line Ge (FIG. 5B). At this time, a negative voltage (−10 V) is applied to the source line So after a positive voltage (+10 V) is applied in a period corresponding to the on-pulse signal of the gate line Go (FIG. 5C). Further, a negative voltage (−10 V) is applied to the source line Se after applying a positive voltage (+10 V) in a period corresponding to the on-pulse signal of the gate line Ge (FIG. 5D).

  Depending on the on-pulse signal of the gate line and the applied voltage of the source line, in the first period, the positive voltage (+10 V) is applied between the period 1 to 5 and the period 6 to 10 in FIGS. ) And -voltage (-10V) are held alternately.

  FIG. 6C shows the voltage state of the pixel 12 in the first period, and FIG. 6D shows the voltage state of the pixel 12 in the second period. Among the pixels of the TFT array, adjacent pixels hold alternately a + voltage (+10 V) and a −voltage (−10 V), and the positive and negative are switched between the first period and the second period.

  With this drive pattern, a checker pattern is formed in which the pixels on the TFT array substrate have a + potential and a −potential set in a two-dimensional grid pattern.

  FIG. 7 is a schematic view for explaining the configuration of the TFT array inspection apparatus of the present invention. In FIG. 7, the TFT array inspection apparatus 1 includes an electron beam source 2 (electron beam source) that irradiates a substrate 10 disposed in a vacuum chamber 4 with primary electrons, and a substrate 10 that is irradiated with primary electrons. A secondary electron detector 3 for detecting the emitted secondary electrons is provided. An energy filter 6 is provided between the substrate 10 and the secondary electron detector 3. The energy filter 6 is composed of a plurality of grids. In FIG. 1, two grids 6 </ b> A and 6 </ b> B are configured, the grid 6 </ b> B is provided on the side closer to the substrate 10, and the grid 6 </ b> A is provided on the side far from the substrate 10.

  The energy of the secondary electrons reaching the energy filter 6 among the secondary electrons generated from the TFT array substrate depends on the potential difference between the TFT array substrate 10 and the energy filter 6 and the initial velocity energy of the secondary electrons. The energy when the secondary electrons pass through the energy filter is expressed by (energy by (filter potential−sample potential) + initial velocity energy of secondary electrons).

  When the energy when the secondary electrons pass through the energy filter is positive (> 0), the secondary electrons can pass through the energy filter. Accordingly, as the negative potential applied to the TFT array substrate is increased, secondary electrons can pass through the energy filter, and as the potential of the TFT array substrate becomes lower than the potential of the energy filter, the energy filter The proportion of secondary electrons passing through becomes higher. On the other hand, when the potential of the TFT array substrate is increased and the potential difference between the TFT array substrate and the energy filter is reduced, the secondary electrons passing through the filter are reduced.

  The grids 6A and 6B of the energy filter 6 may be provided so as to be parallel to the stage 7 on which the substrate 10 is arranged. According to the configuration in which the grids 6A and 6B of the energy filter 6 are provided in parallel to the stage 7, the grids 6A and 6B are parallel to the substrate 10 and thereby suitable for measurement over a wide range of the substrate 10. Can be

  Further, the grids 6A and 6B of the energy filter 6 have openings for irradiating the substrate 10 with primary electrons from the electron beam source 2 on a line connecting the electron beam source 2 and the irradiation position on the substrate 10. It may be provided. A detector grid 8 is provided in front of the secondary electron detection intensity 3.

  In the vacuum chamber 4, in addition to the grids 6 </ b> A and 6 </ b> B of the energy filter 6 described above, a recoil secondary electron suppression grid 5 is provided so as to surround the internal space along the inner peripheral wall surface. The recoil secondary electron suppression grid 5 recoils secondary electrons that have traveled in the lateral direction to increase the collection rate of the secondary electron detector 3.

  Power sources 26A and 26B are connected to the grid 6A and the grid 6B of the energy filter 6 described above, and different voltages can be applied to each grid. The voltage applied to the grids 6A and 6B by the power supplies 26A and 26B is controlled by the grid power supply control unit 24. An inspection signal is applied to the TFT array substrate 10 from the inspection signal supply unit 23 based on the drive pattern of the detection signal generated by the inspection signal generation unit 22.

  The control device 21 controls the grid power supply control unit 24 and the inspection signal generation unit 22 and controls the driving pattern of the grid voltage and the inspection signal according to the type of defect of the substrate 10 to be inspected. In this control, the grid voltage is switched in synchronization with the drive pattern of the inspection signal, and the grid voltage is switched in synchronization with scanning of the electron beam from the electron beam source 2 to the TFT array substrate 10.

  When synchronizing the drive pattern of the inspection signal and the switching of the grid voltage, for example, the grid voltage applied to each of the grids 6A and 6B and the inspection signal supply unit 23 for the type of substrate and the defect type to be inspected. The correspondence relationship with the drive pattern of the inspection signal supplied from the memory is stored, the grid voltage and the drive pattern are read based on the substrate type and the defect type to be inspected by the TFT array inspection apparatus, and the read grid voltage is read from the grid power supply. A predetermined voltage is applied to the grids 6A and 6B by instructing the control unit 24, and an inspection signal applied to the substrate 10 is controlled by instructing the read driving pattern to the inspection signal generating unit 22.

  Further, when synchronizing the scanning of the electron beam and the switching of the grid voltage, the potential of the energy filter is switched in units of a pixel or a region including a plurality of pixels irradiated by the electron beam by scanning.

  Further, a power supply 25 is connected to the recoil secondary electron suppression grid 5 and a predetermined voltage is applied to cause the secondary electrons to recoil.

  The grid power supply control unit 24 individually controls the voltages applied to the grids 6A and 6B by the power supplies 26A and 26B, thereby making the potential of the energy filter 6 variable. The energy filter 6 sorts the secondary electrons emitted from the substrate 10 according to the potential with a predetermined energy value, and the secondary electron detector 3 detects only the secondary electrons that have passed.

  The energy filter 6 of the present invention makes the potentials of the grids 6A and 6B individually variable. The characteristics of the secondary electron detection intensity detected by the secondary electron detector 3 are changed by changing the potentials of the grids 6A and 6B. By changing the voltage applied to the grids 6A and 6B in accordance with the defect type of the substrate, it is possible to detect a defect that is difficult to discriminate when one kind of common voltage is applied to the grid.

  This is because, in the secondary electron detection intensity characteristics when a single type of common voltage is applied to the grid, even if the difference in secondary electron detection intensity for different potentials on the substrate is small and difficult to discriminate, the grid is different. This is because, by applying a voltage to change the secondary electron detection intensity characteristics, the difference in secondary electron detection intensity with respect to different substrate potentials is increased, thereby making it possible to determine the presence or absence of defects.

  FIG. 8 is a diagram showing secondary electron detection intensity characteristics. In FIG. 8, the horizontal axis indicates the substrate potential, and the vertical axis indicates the secondary electron detection intensity. Also, three setting examples of the secondary electron detection intensity characteristics when different voltages are applied to the grids 6A and 6B are shown. FIG. 8 shows a first setting example (secondary electron detection intensity characteristic of c1 indicated by “□” in the figure) when 0V is applied to the grid 6A and −6V is applied to the grid 6B, and 30V is applied to the grid 6A. Second setting example when −5V is applied to 6B (secondary electron detection intensity characteristic of c2 indicated by “◇” in the figure), third setting when 60V is applied to grid 6A and 5V is applied to grid 6B A third setting example of a setting example (c3 secondary electron detection intensity characteristic indicated by “◯” in the drawing) is shown.

  In FIG. 8, it is assumed that the ITO of the substrate is in the potential range of −10V to 10V, the potential when the pixel is normal shows 10V, and the potential when the pixel is defective shows 5V.

  In the case of the first setting example, the intensity of the secondary electron detection intensity at the defective pixel potential (5V) and the secondary electron detection intensity at the normal pixel potential (10V) from the secondary electron detection intensity characteristic c1. The difference is ΔI1. In the first setting example, since the intensity difference ΔI1 of the secondary electron detection intensity when the pixel is normal and when there is a defect is small, it is difficult to determine the defect of the pixel based on the intensity difference.

  In the case of the second and third setting examples, the secondary electron detection intensity at the defective pixel potential (5V) and the secondary electron detection at the normal pixel potential (10V) from the secondary electron detection intensity characteristics c2 and c3. The difference in intensity from the intensity is ΔI2 and ΔI3. In these setting examples, the difference in intensity of secondary electron detection intensity ΔI2 and ΔI3 is sufficiently large, so that it is possible to easily determine a pixel defect from this intensity difference.

  Therefore, in this setting example, secondary voltage detection is made easier by applying a low voltage to the grid closer to the substrate and applying a higher voltage to the grid farther from the substrate. Strength characteristics can be obtained.

  This voltage setting can be performed by the control device 21. The control by the control device 21 generates, for example, an inspection pattern of a voltage to be applied to the inspection signal generation unit 12 according to the substrate type and the defect type, and the grid voltage control unit 24 applies the inspection pattern to the grids 6A and 6B. It can also be performed by controlling the voltage to be applied. The voltage setting example described above is merely an example, and is not limited to the above setting example.

  Next, an example in which the grid voltage switching is performed in synchronization with the drive pattern will be described with reference to FIG. 4, and an example in which the grid voltage switching is performed in synchronization with scanning of the electron beam will be described with reference to FIG.

  4E and 4F show the timing of switching the grid voltage. The driving pattern of the inspection signal shown in FIGS. 4A to 4D is one in which the entire surface of the TFT array substrate is switched to a uniform potential and the entire surface is switched as a unit. The grid voltage of the energy filter is switched in synchronization with the switching of the potential on the entire surface of the TFT array substrate. In FIG. 4, the potential of the entire surface of the TFT array substrate is switched by switching between the first period (1-5) and the second period (6-10). The switching of the grid voltage is performed in synchronization with the switching of the potential of the TFT array substrate. In the first period (1 to 5), the voltage of the grid 6A is 30V, the voltage of the grid 6B is 5V, and the second period ( 6 to 10), the voltage of the grid 6A is set to 0V, and the voltage of the grid 6B is set to -6V.

  FIGS. 5E and 5F show the timing of switching the grid voltage. The test signal drive patterns shown in FIGS. 5A to 5D form a checkered potential distribution by applying different voltages alternately in the vertical and horizontal directions in units of pixels of the TFT array substrate. The potential distribution is switched between the first period (1 to 5) and the second period (6 to 10). FIG. 5G shows an electron beam scanning signal. Here, an example is shown in which the scanning signal is made to coincide with the ten periods defined during the first period and the second period, but this is an example, and the period of the scanning signal is arbitrarily determined. be able to. The grid voltage of the energy filter is switched in synchronism with the scanning timing of the electron beam. The grid 6A voltage is 30V, the grid 6B voltage is 5V, the grid 6A voltage is 0V, and the grid 6B voltage. Is switched in synchronization with the scanning signal.

  The present invention can be applied to a repair device that repairs a detected defect in addition to detecting the presence or absence of a defect on a substrate and detecting a defect type.

It is the schematic of the TFT array test | inspection apparatus of this invention. It is a figure which shows the equivalent circuit of the TFT array (Cs on Com type TFT array) of the TFT array substrate of this invention. It is a figure which shows the equivalent circuit of TFT array (Cs on Gate type TFT array) of the TFT array substrate of this invention. It is a figure which shows the drive pattern of the test | inspection signal within 1 gate period of this invention. It is a figure which shows the drive pattern of the test | inspection signal within 1 gate period of this invention. It is a figure which shows the example of the applied voltage of the pixel of this invention. It is the schematic for demonstrating the structure of the TFT array test | inspection apparatus of this invention. It is a figure which shows a secondary electron detection intensity characteristic. It is a figure for demonstrating the defect which arises in each element part which comprises a TFT array. It is a figure for demonstrating the adjacent defect of a horizontal direction. It is a figure for demonstrating the adjacent defect of a vertical direction. It is an equivalent circuit of a TFT array for explaining a defect example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... TFT array test | inspection apparatus, 2 ... Electron beam source, 3 ... Secondary electron detector, 4 ... Vacuum chamber, 5 ... Rebound secondary electron suppression grid, 6 ... Energy filter, 6a, 6b ... Grid, 7 ... Stage: 8 ... Prober, 10 ... Substrate, 11 ... TFT, 12 ... Pixel, 13 ... Additional capacitance, 14 ... Gate line, 15 ... Source line, 21 ... Control device, 22 ... Test signal generator, 23 ... Test signal supply , 24 ... grid voltage control unit, 25 ... power source, 26A, 26B ... power source, 31 ... signal processing unit, 32 ... defect detection unit, 101 ... TFT array inspection device, 102 ... electron beam source, 103 ... secondary electron detection 104 ... Vacuum chamber, 105 ... Grid for rebounding secondary electron suppression, 106 (106a, 106b) ... Energy filter grid, 107 ... Stage, 110 ... Substrate.

Claims (6)

The TFT array substrate is driven by supplying a drive signal, and secondary electrons obtained by irradiating the TFT array substrate with an electron beam are detected by energy selection, and the TFT is determined by the secondary electron signal intensity obtained by the detection. In a TFT array inspection apparatus for detecting defects in the array substrate,
An energy filter for performing the energy selection;
A secondary electron detector that detects secondary electrons that have passed through the energy filter;
A TFT array inspection apparatus, wherein the potential of the energy filter is switched in synchronization with the signal waveform of the drive signal.   The potential switching of the energy filter is synchronized with electron beam irradiation, and the energy filter potential is switched in units of a region including a single pixel or a plurality of pixels of the TFT array substrate irradiated with the electron beam. The TFT array inspection apparatus according to claim 1. The signal waveform of the drive signal is a checker pattern that drives a pixel array or a region including a plurality of pixels on the TFT array substrate in different potential states in a two-dimensional pattern alternately.
3. The TFT array inspection according to claim 2, wherein on the TFT array substrate driven by the checker pattern, the potential of the energy filter is switched in synchronization with a potential of a pixel irradiated with an electron beam during scanning. apparatus. The signal waveform of the drive signal is a stripe pattern for driving a pixel or a region including a plurality of pixels on the TFT array substrate in different potential states in two-dimensional stripes in the column direction or row direction,
3. The TFT array inspection according to claim 2, wherein the potential of the energy filter is switched in synchronization with a potential of a pixel irradiated with an electron beam during scanning on the TFT array substrate driven by the stripe pattern. apparatus. The signal waveform of the drive signal is an overall pattern that drives all the pixels on the TFT array substrate in the same potential state,
3. The TFT array inspection apparatus according to claim 2, wherein the potential of the energy filter is switched in synchronization with the switching of the potential driven by the entire surface pattern.   The TFT array inspection apparatus according to claim 1, wherein the energy filter includes a plurality of grids, and different voltages are applied to the grids.