JP2009026833A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin semiconductor device capable of withstanding a fall in a mounted state and deformation of a substrate. <P>SOLUTION: The semiconductor device which includes a semiconductor element 1 having a circuit formed on a principal surface, an electrode portion as an electrode pad 2 and a copper post 5 formed on a circuit surface of the semiconductor element 1, a copper wire 4 connected to the electrode portion, and a first resin layer 6 covering and sealing the principal surface of the semiconductor element 1 except the electrode portion, and has an outer shape size defined by side surfaces of the semiconductor element 1 is provided with a reverse-surface reinforcing layer 10 which has a larger Young's modulus than the first resin layer 6 on a reverse surface of the semiconductor element 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having the same size as a semiconductor element.

  With the recent demand for smaller and thinner electronic devices (such as mobile phones), the package of semiconductor devices has changed from peripheral lead type packages to BGA (ball grid array) type packages, and to chip size packages (CSP). is doing. As a further thin, small, and lightweight package, a wafer level chip size package (WLCSP) is proposed, which replaces a bare chip that is inconvenient to handle when mounted on an electronic device, and is now in practical use.

  One typical example is a semiconductor device disclosed in Patent Document 1. As shown in FIG. 4, an electrode pad 2 is provided on the circuit surface of a semiconductor element 1 having a circuit formed on the main surface, and a copper wiring 4 connected to the electrode pad 2 is formed, thereby providing an electronic product. The pad pitch is expanded to an arrangement interval that can be soldered to the mounting substrate, and copper posts 5 protruding from the respective copper wirings 4 in the surface normal direction are formed.

  And the 1st resin layer 6 which seals the said main surface of the semiconductor element 1 is formed so that the circumference | surroundings of the copper post 5 may be filled to the height vicinity. The first resin layer 6 also serves to secure a height between the two when the semiconductor element 1 is soldered to the circuit mounting board and to reduce shear stress due to a difference in thermal expansion between the two. In many cases, a spherical crown-shaped solder ball 7 for connection to an external substrate is formed at the end of the copper post 5 as shown in the figure. The diameter of the solder ball 7 is about 300 to 500 μm.

  The above structure is formed in a wafer state, and the wafer is diced to form individual semiconductor devices. Therefore, the size of the semiconductor element 1 is directly the size of the semiconductor device, and the chip cut surface is often exposed on the side surface of the semiconductor device as shown in the figure.

  There are several problems with wafer level chip size packages. The first problem is that the brittle material silicon is exposed on the end face / back face (opposite side of the circuit active face) of the semiconductor element 1, so that foreign matter such as silicon scrap is exposed on the back face of the equipment / mold in the process. When the contact is made, fine scratches are generated and the semiconductor element 1 is damaged.

  For this reason, for example, Patent Document 2 proposes reinforcing coating other than the active surface (back surface / side surface) of the bare chip using a resin solvent. By dipping in a resin solvent, a resin film is formed on the chip surface, filling fine scratches on the chip surface, and preventing damage due to vibration during vacuum suction during the process.

  Further, in Patent Document 3, a protective tape is adhered to the back surface to prevent foreign matter from being caught during process assembly in a wafer state, and damage due to vibration associated with handling or conveyance during sealing or vacuum suction. I am doing so.

  The second problem of the wafer level chip size package is a structure in which the first resin layer 6 is provided on the chip surface (circuit active surface) as described above in order to overcome the secondary mounting reliability that was a problem of the bare chip. This is a new problem.

  That is, a resin with a large thermal expansion coefficient (10 to 40 ppm / ° C.) is applied to one side of a silicon wafer having a low thermal expansion coefficient of 3 ppm / ° C., which causes warping due to the difference in thermal expansion coefficient. It is. When warping occurs, evacuation at the polishing stage is not successful, and surface polishing cannot be performed, or a conveyance failure due to warping occurs, which causes problems that affect mounting quality.

  In Patent Document 4, it is proposed that the front and side surfaces of a semiconductor element be resin-sealed by a transfer mold molding method. In this case, since it is a transfer mold, both the front and back surfaces of the semiconductor element are used. Since the resin is formed on the substrate, the package becomes thick.

On the other hand, in Patent Document 5, out of the resin provided on both the front surface and the back surface of the semiconductor element, the resin thickness on the back surface is reduced to 0.2-1.0 times the resin thickness on the front surface. Proposed. Patent Document 6 proposes that the resin on the back surface of the resin provided on both the front surface and the back surface of the semiconductor element has a larger thermal expansion coefficient, a smaller thickness, and a smaller elastic modulus than the resin on the front surface. ing. In either case, by providing resin on both the front surface and the back surface, the warping moment due to thermal expansion of the resin on the front surface is reduced by changing the dimensions and physical properties of the resin on the back surface.
Japanese Patent No. 3756689 JP 2003-60130 A JP 2000-228465 A Japanese Patent No. 3449796 JP 2005-142593 A JP 2007-12755 A

  However, the wafer-level chip size package has been further reduced in thickness, and it is more difficult to bend or damage due to impact when falling in the mounted state after soldering to the mounting substrate than surface damage or vibration damage in the manufacturing process. In recent years, breakage and defects that occur without being able to withstand a large "tensile stress" due to substrate deformation have become a major problem.

  In particular, in order to further improve the mounting reliability, that is, to suppress the peeling of the soldering part and the chip diffusion process layer, underfill is used at present, and the rigidity of the solder connection part is increased, resulting in the chip back surface. The stress of this is further increased, and the risk of destruction is increasing.

  SUMMARY OF THE INVENTION The present invention solves the above problems, and an object of the present invention is to provide a thin semiconductor device that can withstand a drop impact in a mounted state and deformation of a mounting substrate.

  In order to solve the above-described problems, the present invention provides a semiconductor device having a chip size package structure in which a reinforcing layer having a Young's modulus larger than the sealing resin for the circuit surface is disposed on the back surface of the semiconductor element whose circuit surface is resin-sealed. As a result, even when bending or tensile stress is applied to the back side of the semiconductor element due to a drop impact in the mounted state or deformation of the mounting substrate, the back side can be prevented from being deformed or broken. it can.

  That is, the semiconductor device of the present invention includes a semiconductor element having a circuit formed on a main surface thereof, an electrode part formed on the circuit surface of the semiconductor element, a wiring connected to the electrode part, and the electrode part excluding the electrode part. In a semiconductor device having a first resin layer that covers and seals the main surface of the semiconductor element and has an outer size defined by the side surface of the semiconductor element, on the back surface opposite to the main surface of the semiconductor element, A reinforcing layer having a Young's modulus larger than that of the first resin layer is provided.

  The reinforcing layer is formed separately, and is bonded to the back surface of the semiconductor element through the second resin layer. By adopting such a two-layer structure, the selection range of the material for the reinforcing layer is widened and it can withstand a drop impact.

  The reinforcing layer may be formed of any one of resin, metal, and ceramic. The reinforcing layer is made of a material having a Young's modulus of 130 GPa or more. This is because it is desirable for reinforcing the semiconductor element to have a Young's modulus equal to or higher than the Young's modulus of 130 GPa of silicon which is the base material of the semiconductor element.

  The reinforcing layer may be a metal layer formed by plating or molten metal. The reinforcing layer may be a ceramic layer formed by thermal spraying.

  In the semiconductor device according to the present invention, the semiconductor element is an ultra-thin chip by disposing a reinforcing layer having a Young's modulus larger than the resin layer on the circuit forming surface on the back surface of the semiconductor element having the circuit forming surface sealed with resin. In other words, while realizing a thin chip size package, it can not only prevent chipping of the back surface during the manufacturing process, but it can also cause extremely large usage stresses such as drop impact after mounting on electronic devices and bending stress of electronic devices. Can withstand.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. The same members as those of the conventional semiconductor device described above with reference to FIG.

  The semiconductor device shown in FIG. 1 is called a wafer level chip size package. A circuit is formed on one main surface of a semiconductor element (semiconductor chip) 1, and an electrode pad 2 is formed on the circuit surface. The reinforcing film 3 covered except for the connection portion of the electrode pad 2, the copper wiring 4 connected to the electrode pad 2, and the copper post 5 protruding from the copper wiring 4 by a predetermined height in the surface normal direction are the same 1 It is formed on the main surface. The copper wiring 4 is a rewiring in which the electrode pads 2 are rearranged with the pad pitch widened to an arrangement interval that enables soldering to a mounting board (not shown) such as a printed circuit board.

  A first resin layer 6 that covers and seals the main surface around the copper post 5 with a thickness comparable to the height of the copper post 5 is formed on one main surface of the semiconductor element 1. At the end of the copper post 5, a spherical crown-shaped solder ball 7 for external connection is formed. The diameter of the solder ball 7 is about 300 to 500 μm. The copper post 5 and the first resin layer 6 have functions of improving mountability and improving the life of the soldered portion.

  The above structure is formed in a wafer state, and the wafer is diced to form individual semiconductor devices. Therefore, the semiconductor element size is the same as the outer size of the semiconductor device, and the side surface of the semiconductor device is a cut surface.

  The semiconductor device of the first embodiment is different from the conventional semiconductor device in that a back surface reinforcing layer 10 having a Young's modulus larger than that of the first resin layer 6 is provided on the back surface of the semiconductor element 1. The back reinforcing layer 10 is formed separately and joined by the second resin layer 11. That is, on the back surface of the semiconductor element 1, a two-layer structure including the rigid back surface reinforcing layer 10 and the second resin layer 11 is formed.

  FIG. 2 is a sectional view of a semiconductor device according to the second embodiment of the present invention. The semiconductor device of the second embodiment is different from the semiconductor device of the first embodiment in that only the back surface reinforcing layer 10 is provided on the back surface of the semiconductor element 1. The back reinforcing layer 10 has a Young's modulus larger than that of the first resin layer 6.

  In the semiconductor device of the first or second embodiment, the back surface reinforcing layer 10 is installed on the individual semiconductor device (see FIG. 4) by individually attaching it before or after mounting on the mounting substrate. Alternatively, as shown in FIGS. 3A and 3B, the wafer 20 before dicing may be formed. The latter method, in which the back surface reinforcing layer 10 is formed before separation, is more cost effective than the former method, which is applied to a single semiconductor device.

  Each of the semiconductor devices of the first and second embodiments has the back surface reinforcing layer 10, so that when a bending impact or tensile stress is applied to the back surface side due to a drop impact in the mounted state or deformation of the mounting substrate, Deformation and destruction of the back side are difficult to occur.

  As in the semiconductor device of the second embodiment, when the back surface reinforcing layer 10 and the second resin layer 11 are used as a two-layer structure, the selection range of the material of the back surface reinforcing layer 10 is widened. Can also withstand.

  This back surface reinforcing layer 10 does not simply cover the back surface of the semiconductor element to prevent scratching or crack progression starting from this, but also serves as a structure for improving the rigidity of the semiconductor element. It is desired that the rigidity is high so that it can withstand the tensile force applied to the entire structure portion, and therefore, it is desired that the Young's modulus be higher, and at least one having a Young's modulus greater than that of the first resin layer is provided. High fracture strength and fracture toughness (ductility) are also required.

  To deal with scratches, chipping, etc., it is effective to form a soft resin film as in the conventional example with a film thickness of the order of 1 μm. However, the impact of the electronic circuit board itself undergoing significant bending deformation such as severe drops. On the other hand, the resin film does not contribute to rigidity at all. In order to ensure rigidity with a soft resin, that is, a resin with low rigidity, the only way to ensure rigidity is to increase the film thickness. However, if it is increased to a sufficient rigidity, the total thickness of the semiconductor device will increase, and thin electronic devices Can no longer be embedded. Therefore, as described above, the back surface reinforcing layer 10 is formed on the back surface of the element where stress is highest due to the material having high rigidity, that is, the outermost portion in the mounted state, thereby increasing the total thickness of the semiconductor device. Without increasing the rigidity / strength.

  The back reinforcing layer 10 can be formed of, for example, resin, metal, ceramics, or the like. In order to reduce the thickness of the semiconductor device, it is desirable that the back reinforcing layer 10 be made of a material having a Young's modulus equal to or higher than the Young's modulus of 130 GPa of silicon that is the base material of the semiconductor element. For that, metal is a preferred material. Ceramics are also a preferred material. In order to withstand impact fracture, a tough ceramic material is desirable.

When an epoxy resin (filler-containing Young's modulus of about 1 to 25 Gpa) is used for the first resin layer 6, the back surface reinforcing layer 10 includes an epoxy resin (30 GPa) as the resin, and a copper alloy (130 GPa as the metal). ), Tungsten (350 GPa), molybdenum (400 GPa), and the like, AL ₂ O ₃ (250 GPa) or the like can be used as the ceramic.

  The back reinforcing layer 10 can be used in the form of a sheet or film. In this case, the back reinforcing layer 10 is joined by the second resin layer 11 as shown in the second embodiment. The thickness of the back surface reinforcing layer 10 is at least equivalent to that of the semiconductor element 1 in order to give strength as a structural member because the thickness of the target semiconductor element 1 is about several hundreds to 10 μm, that is, about 10 μm to 300 μm. Scope. The strength F and thickness t required vary depending on the circuit board support structure after mounting. However, when it has a high rigidity of 200 GPa or more, it should be molded and used relatively thinly, such as about 10 μm to several tens of μm. Can do. As the second resin layer 11, for example, an epoxy resin (Young's modulus of about 1 to 25 Gpa) can be used. When the back surface reinforcing layer 10 is a resin, the back surface reinforcing layer 10 and the second resin layer 11 may be made of the same resin as a main material, but the back surface reinforcing layer 10 may have higher rigidity. It is effective.

Alternatively, the back surface reinforcing layer 10 may be a metal layer made of plated or molten metal, such as a copper alloy layer (Young's modulus is 130 GPa), or a ceramic layer formed by thermal spraying, such as an AL ₂ O ₃ layer (250 GPa). For the formation of the ceramic layer, a method called powder flame spraying or a method called cold spray can be used.

  In addition to the above materials, the back surface reinforcing layer 10 may be a material having a high tensile elastic modulus such as glass or carbon fiber, or may be a highly rigid material such as diamond. By adopting these, the tensile deformation applied to the back surface layer of the semiconductor element 1 due to the deformation of the mounting substrate can be prevented, and the stress generated on the back surface of the semiconductor element 1 can be kept low.

  In the above embodiment, the copper post 5 is provided as an example for mechanically and electrically connecting the circuit of the semiconductor element 1 and the solder ball 7 as the external connection electrode on the package surface. A copper foil pattern layer may be used instead of the copper post 5.

  Further, the external connection electrodes on the package surface are not limited to the solder balls 7 described above, and may be a solder supply method in which a solder paste containing powdered solder is applied. The effect obtained by the reinforcing layer 10 is not changed.

  The semiconductor device of the present invention can withstand a very large use stress such as a drop impact in a mounted state even if the semiconductor element is an ultra-thin chip, that is, a thin chip size package, so that a mobile phone or the like It is particularly useful for electronic devices that are required to be small and thin.

Sectional drawing of the semiconductor device of the 1st Embodiment of this invention Sectional drawing of the semiconductor device of the 2nd Embodiment of this invention The figure which shows the state which provides a reinforcement layer in the semiconductor device of FIG. 1 or FIG. Sectional view of a conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Electrode pad 3 Reinforcing film 4 Copper wiring 5 Copper post 6 First resin layer 7 Solder ball
10 Back reinforcement layer
11 Second resin layer
20 wafers

Claims (6)

A semiconductor element having a circuit formed on the main surface, an electrode portion formed on the circuit surface of the semiconductor element, a wiring connected to the electrode portion, and a main surface of the semiconductor element excluding the electrode portion In a semiconductor device having a sealed first resin layer and having an outer size defined by a side surface of the semiconductor element,
A semiconductor device comprising: a reinforcing layer having a Young's modulus larger than that of the first resin layer on a back surface opposite to a main surface of the semiconductor element. The semiconductor device according to claim 1, wherein the reinforcing layer is formed separately and joined to the back surface of the semiconductor element via the second resin layer.   The semiconductor device according to claim 1, wherein the reinforcing layer is formed of any one of resin, metal, and ceramics.   2. The semiconductor device according to claim 1, wherein the reinforcing layer is made of a material having a Young's modulus of 130 GPa or more.   4. The semiconductor device according to claim 3, wherein the reinforcing layer is a metal layer formed by plating or molten metal.   4. The semiconductor device according to claim 3, wherein the reinforcing layer is a ceramic layer formed by thermal spraying.

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