JP2008521157A5 - - Google Patents

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JP2008521157A5
JP2008521157A5 JP2007543071A JP2007543071A JP2008521157A5 JP 2008521157 A5 JP2008521157 A5 JP 2008521157A5 JP 2007543071 A JP2007543071 A JP 2007543071A JP 2007543071 A JP2007543071 A JP 2007543071A JP 2008521157 A5 JP2008521157 A5 JP 2008521157A5
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power supply
voltage
supply node
word line
operation mode
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JP2007543071A
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JP4988588B2 (en
JP2008521157A (en
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Priority claimed from US10/991,910 external-priority patent/US7085175B2/en
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電源電圧を受け取るための第１の電源ノード並びにワード線及びビット線へ接続されているメモリセルを含むメモリアレイと、
ワード線及び第２の電源ノードへ接続されている複数のワード線ドライバと、
電源電圧の低下を示す低供給電圧信号に応答して入力に対する電圧に関連して出力に対する電圧を低下させるために、第１の電源ノードへ接続されている入力及び第２の電源ノードへ接続されている出力を有する電圧低下回路と、からなる回路。 A memory array including a first power supply node for receiving a power supply voltage and memory cells connected to the word lines and bit lines;
A plurality of word line drivers connected to the word line and the second power supply node;
An input connected to the first power supply node and a second power supply node connected to reduce the voltage on the output in relation to the voltage on the input in response to a low supply voltage signal indicative of a power supply voltage drop. And a voltage drop circuit having an output. 通常動作モードと、低供給電圧信号によって示される、電源電圧の低下した低電力動作モードとを有する回路であって、
電源電圧を受け取るための第１の電源ノード並びにワード線及びビット線へ接続されているメモリセルを有するメモリアレイと、
ワード線へ接続されており、通常動作モード中、第１の電源ノードに対し印加される電圧を提供し、かつ、低電力動作モード中、第１の電源ノードに対し印加される電圧未満に低下した電圧を提供するためのワード線ドライバ手段と、を含む回路。 A circuit having a normal operating mode and a low power operating mode with a reduced power supply voltage indicated by a low supply voltage signal,
A memory array having a first power supply node for receiving a power supply voltage and memory cells connected to the word lines and bit lines;
Connected to the word line and provides a voltage applied to the first power supply node during normal operation mode and drops below the voltage applied to the first power supply node during low power operation mode Circuit comprising: a word line driver means for providing the selected voltage. 電源電圧を受け取るための第１の電源ノード並びにワード線及びビット線へ接続されているメモリセルを有するメモリアレイと、
ワード線及び第２の電源ノードへ接続されている複数のワード線ドライバと、
第１の電源ノード及び第２の電源ノードへ接続されており、通常動作モードにおいて第２の電源ノードに対し第１の供給電圧を提供し、かつ、電源電圧が低下される第２の動作モードに入ることに応答して、第２の動作モード中、第１電源ノードに対し提供される電圧未満の電圧を第２の電源ノードに対し提供するための電圧制御手段と、からなる回路。 A memory array having a first power supply node for receiving a power supply voltage and memory cells connected to the word lines and bit lines;
A plurality of word line drivers connected to the word line and the second power supply node;
A second operation mode connected to the first power supply node and the second power supply node, providing a first supply voltage to the second power supply node in the normal operation mode, and reducing the power supply voltage And a voltage control means for providing, to the second power supply node, a voltage that is less than the voltage provided to the first power supply node during the second mode of operation. 電源電圧を受け取るための第１の電源ノード並びにワード線及びビット線へ接続されているメモリセルを有するメモリアレイと、ワード線及び第２の電源ノードへ接続されている複数のワード線ドライバと、からなるメモリの動作方法であって、
第１の動作モード中、第１の電源ノード及び第２の電源ノードに対しほぼ等しい第１のレベルの電圧を印加する第１電圧印加工程と、
第１の電源ノードに対し第１のレベル未満の第２のレベルの電圧が印加される第２の動作モード中、第２の電源ノードに対し第２のレベル未満の電圧を印加する第２電圧印加工程と、からなる方法。 A memory array having a first power supply node for receiving a power supply voltage and memory cells connected to the word line and the bit line; and a plurality of word line drivers connected to the word line and the second power supply node; A memory operating method comprising:
A first voltage applying step of applying a substantially equal first level voltage to the first power supply node and the second power supply node during the first operation mode;
A second voltage for applying a voltage lower than the second level to the second power supply node during the second operation mode in which a second level voltage lower than the first level is applied to the first power supply node. And an applying step.
JP2007543071A 2004-11-18 2005-10-25 Word line driver circuit for static random access memory Active JP4988588B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/991,910 2004-11-18
US10/991,910 US7085175B2 (en) 2004-11-18 2004-11-18 Word line driver circuit for a static random access memory and method therefor
PCT/US2005/038468 WO2006055190A1 (en) 2004-11-18 2005-10-25 Word line driver circuit for a static random access memory and method therefor

Publications (3)

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JP2008521157A JP2008521157A (en) 2008-06-19
JP2008521157A5 true JP2008521157A5 (en) 2008-12-11
JP4988588B2 JP4988588B2 (en) 2012-08-01

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JP2007543071A Active JP4988588B2 (en) 2004-11-18 2005-10-25 Word line driver circuit for static random access memory

Country Status (5)

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US (1) US7085175B2 (en)
JP (1) JP4988588B2 (en)
KR (1) KR101227291B1 (en)
CN (1) CN101040343B (en)
WO (1) WO2006055190A1 (en)

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