JPH09326194A - Step-down circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a low threshold value to be set and to reduce power consumption in SRAM by diode-connecting a thin-film transistor, N-TFT, between ext. Vcc and int. Vcc. SOLUTION: A step-down circuit 100 includes an N-channel thin-film MOS transistor 101. This N-TFT connects its drain electrode and gate electrode to ext. Vcc and its source electrode to the int. Vcc output node N1 to make diode-connection between ext. Vcc and int. Vcc. Since a thick oxide film exists between thin-polysilicon and the Si substrate, only impressing the substrate bias on the lower section of the channel in this thin-film polysilicon through capacity coupling enables a low threshold value. Then, the ext. Vcc is fully stepped down to allow to obtain a specified int. Vcc an realize high-speed action.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a step-down circuit,
In particular, it relates to a step-down circuit for stepping down an external power supply voltage to generate an internal power supply voltage in an SRAM.

[0002]

2. Description of the Related Art In a conventional semiconductor device, it is necessary to reduce the transistor size, particularly the gate length of a MOS transistor, in order to further improve the degree of integration and performance. Also in the SRAM, the occupied area of the memory cell is reduced by reducing the gate length, and high integration is possible. However, as the gate length is reduced, the channel length is shortened, but unless the power supply voltage is reduced proportionally, the deterioration of the MOS transistor characteristics due to the hot carrier effect becomes a problem. Therefore, usually, a down converter (VDC)
The voltage of the external power supply system is stepped down using the circuit, and the voltage lower than the external power supply system is used as the internal power supply system, and the power supply line of the memory cell,
Supply has been made to each of the word lines, bit lines, and peripheral circuits.

FIG. 28 is a circuit diagram showing a step-down circuit 2800 which is an example of a conventional step-down circuit.

Referring to FIG. 28, step-down circuit 2800 is
Power supply voltage ext. Vcc (hereinafter abbreviated as ext.Vcc) and internal power supply voltage int. Vcc (hereinafter, int.V
and an N-channel MOS transistor (hereinafter abbreviated as NMOS transistor) 2801 that is diode-connected between the N channel MOS transistor 2801 and cc.

In FIG. 28, the NM formed on the substrate
Since the potential on the source side of the OS transistor is higher than that of the P well, the threshold voltage Vth is not the threshold voltage Vthn0 without the back gate effect but the threshold voltage Vthn affected by the back gate effect. (At V
It is stepped down by bb). Here, Vbb represents a back bias.

In Japanese Patent Laid-Open No. 2-199518, an external power supply voltage ext. Vcc and int. It is disclosed that it is possible to configure a circuit for stepping down the voltage to a desired internal power supply voltage by diode-connecting a PMOS transistor and an NMOS transistor in series between the Vcc output node and the Vcc output node. FIG. 29 shows a step-down circuit considered by Japanese Patent Laid-Open No. 1995-1995.

FIG. 29 is a circuit diagram showing another conventional step-down circuit 2900. Referring to FIG. 29, step-down circuit 290
0, the PMOS transistor 2901 and the NMOS transistor 2903 are ext. Vcc and int. The source electrode of the PMOS transistor is connected in series with Vcc. Since it is directly connected to Vcc,
There is no back gate effect, and int. Vcc = ext. V
It becomes cc-Vthn0-Vthn (at Vbb).

[0008]

However, when it is necessary to keep the power consumption low, for example, in a low power consumption SRAM, the threshold voltage Vth is set to about 0.7 to 0.8 [V]. However, it is necessary to set the ext. V
cc = 5 [V] is stepped down and the desired int. It was difficult to obtain Vcc.

[0009] That is, to explain more concretely using numerical values,

[0010]

[Equation 1]

In ext. Vcc = 5 [V], 2
φF = 0.6 [V], Vthn0 = 0.7 to 0.8
[V], K = 0.7 to 0.8, the threshold voltage Vthn (a affected by the back gate effect at this time
t Vbb) is 1.56 to 1.75 [V], and i
nt. Vcc is 3.25 to 3.44 [V].

If the substrate concentration of the NMOS transistor 2801 is intentionally increased to increase the value of K, the step-down width is further increased, but the threshold voltage Vthn0 without the back gate effect is also increased and the NMOS Since the source-drain current Ids itself of the transistor 2801 decreases, the NMO used as the step-down transistor
N of the same structure made similarly to the S transistor 2801
When the MOS transistor is used in another circuit in the semiconductor device, there are problems such as a decrease in operating speed. On the contrary, if the substrate concentration of the NMOS transistor 2801 is reduced and the value of K is further reduced, the step-down width is reduced, but the threshold voltage Vthn without the back gate effect is obtained.
0 also drops, and the current consumption in the standby state increases. Therefore, the step-down circuit 2800 of FIG.
In such a conventional step-down circuit, it is difficult to simultaneously satisfy the reliability, low power consumption, and high speed of the internal circuit in the semiconductor device without increasing the number of process steps.

The present invention has been made to solve the above problems, and in the SRAM, while ensuring the reliability of internal circuits such as memory cells miniaturized for high integration, A step-down circuit capable of stepping down an external power supply voltage to obtain a desired internal power supply voltage, and at the same time having both low power consumption and high speed, and occupying a smaller area on the layout to enable higher integration. The purpose is to provide.

[0014]

A step-down circuit according to a first aspect of the present invention includes a diode-connected thin film transistor that receives an external power supply voltage and steps down the external power supply voltage to generate an internal power supply voltage. It is a thing.

A step-down circuit according to claim 2 of the present invention is the first step-down circuit.
A first conductivity type transistor and a second conductivity type transistor different from the first diode-connected transistor connected between one electrode of the first conductivity type transistor and the internal power supply voltage. Transistor is diode-connected between the external power supply voltage and the second conductivity type transistor,
At least one of the first or second conductivity type transistors is a thin film transistor.

According to a third aspect of the present invention, in a step-down circuit, a resistance element connected between an external power supply voltage and an internal power supply voltage, a first conductivity type transistor, and a first conductivity type transistor are provided. A transistor of a second conductivity type different from the first, which is diode-connected between the one electrode and the ground voltage;
And the first conductivity type transistor is diode-connected between the internal power supply voltage and the second conductivity type transistor, and at least one of the first or second conductivity type transistor is a thin film transistor. .

According to a fourth aspect of the present invention, in a step-down circuit, a diode-connected first transistor, a first connecting means for connecting one electrode of the first transistor and a first node, and a diode connection are provided. And a second connecting means different from the first connecting the one electrode of the second transistor and the first node.
The other electrode of the transistor and the other electrode of the second transistor are connected to a second node different from the first,
Is connected to either the external power supply voltage or the internal power supply voltage, and the second node is connected to the other of the external power supply voltage or the internal power supply voltage to which the first node is connected. There is.

A step-down circuit according to a fifth aspect of the present invention is a diode-connected first conductivity type first transistor,
First connecting means for connecting one electrode of the first transistor and the first node, a second transistor of the first conductivity type diode-connected, and one electrode of the second transistor and the first node are connected. The first different second connecting means to be connected, the diode-connected second conductive third transistor different from the first, and the one electrode of the third transistor and the second node different from the first are connected. First connecting means for connecting, a diode-connected fourth transistor of the second conductivity type, and a fourth connecting means for connecting one electrode of the fourth transistor and the second node, The other electrode of the transistor and the other electrode of the second transistor are second
Of the third transistor and the other electrode of the fourth transistor are connected to a third node different from the first and second transistors, and the first node is connected to the external power supply voltage or the internal power supply. The third node is connected to one of the voltages, and the third node is connected to the other of the external power supply voltage and the internal power supply voltage connected to the first node.

A step-down circuit according to claim 6 of the present invention is the step-down circuit according to claim 5, wherein the first conductivity type first transistor, the first conductivity type second transistor, and the second conductivity type are included. At least one of the third transistor and the fourth transistor of the second conductivity type is a thin film transistor.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

(1) First Embodiment FIG. 1 is a step-down circuit 1 according to a first embodiment of a step-down circuit of the present invention.
It is a circuit diagram of 00.

Referring to FIG. 1, a step-down circuit 100 includes an N-channel type thin film MOS transistor (hereinafter referred to as N-TFT).
101).

In the N-TFT 101, the drain electrode and the gate electrode are ext. Connected to Vcc and the source electrode is i
nt. It is connected to the Vcc output node N1. That is, ext. Vcc and int. It is diode-connected to Vcc.

Generally, a thin film transistor (TFT)
In the film transistor, a thick oxide film exists between the thin film polysilicon and the Si substrate. Therefore, the substrate bias is only applied to the bottom of the channel in this thin film polysilicon by capacitive coupling through this thick oxide,
The back gate effect has almost no influence on the threshold voltage Vth. Therefore, the threshold voltage can be set low, and the ext. Vcc is sufficiently reduced to a predetermined int. Vcc can be obtained, and it is possible to reduce power consumption and speed up the operation.

For example, referring to FIG. 1, N-TFT 101
Is less susceptible to the back gate effect of the substrate, the threshold voltage Vth of the N-TFT 101 is about 0.7.
.About.0.8 [V], int. Vcc can be set to about 4.2 to 4.3 [V].

If a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) formed on a substrate is conventionally used as a step-down transistor, int. V
Although it was possible to set cc to about 4.2 [V], since the N-TFT 101 can be formed on other elements, the area occupied by the layout can be reduced. Therefore, higher integration is possible.

(2) Second Embodiment FIG. 2 is a step-down circuit 2 according to a second embodiment of the step-down circuit of the present invention.
It is a circuit diagram which shows 00.

Referring to FIG. 2, a step-down circuit 200 includes a P-channel type thin film MOS transistor (hereinafter referred to as P-TFT).
201) and an NMOS transistor.

The source electrode of the P-TFT 201 is ex
t. The drain electrode and the gate electrode are connected to Vcc, and are connected to the drain electrode and the gate electrode of the NMOS transistor 203. The source electrode of the NMOS transistor 203 is int. It is connected to the Vcc output node N1. That is, the P-TFT 201 and the NMOS transistor 203 have the ext. Vcc and int. Vcc
And are connected in series with a diode.

FIG. 3 is a plan view and a sectional view showing the structure of the P-TFT 200 of FIG. As shown in FIG.
When the FT is used, the P-TFT can be formed on another element, for example, the NMOS transistor 203.

Referring to FIG. 3, (a) shows a step-down circuit 20.
FIG. 10B is a plan view of No. 0, and FIG. 10B is a cross-sectional view taken along the line AA ′ of the plan view 10 of FIG.

In the NMOS transistor 203, P
A thin film polysilicon 325 is formed on the well 301,
An N ₊ source electrode 303 and an N ₊ drain electrode 305 are formed. Furthermore, a thick oxide film 30 is formed on top of it.
7 are formed. The oxide film 307 has a source electrode 303 and a drain electrode 30 of the NMOS transistor 203.
The gate electrode 309 is formed between the gate electrode 309 and the gate electrode. P well 301 and oxide film 307 except under the gate electrode 309
Field insulating films 311 and 313 are formed in a boundary portion between and. Thin-film polysilicon is formed on the oxide film 307, and the P ₊ source electrode 3 of the P-TFT 201 is formed.
15 and a P ₊ drain electrode 317 are formed. The source electrode 315 has an ext. An aluminum wiring 319 supplied with Vcc is connected. Aluminum wiring 31
9 is stopped by the stopper 323 in the oxide film 307. The drain electrode 305 of the NMOS transistor 203 and the drain electrode 317 of the P-TFT are connected by the aluminum wiring 321. Aluminum wiring 321
Furthermore, the NMOS transistor 203 and the P-TFT
201 common gate electrode 309 and each drain electrode 30
5, 317 are connected. NMOS transistor 2
03 source electrode 303 is connected to the aluminum wiring 323, and the stepped down int. Vcc
Is output.

Therefore, as compared with the case where the PMOS transistor is formed on the substrate, the source / drain region of P ₊ and the well isolation region are unnecessary, and the layout area is reduced as in the case of the step-down circuit of the first embodiment. The cost can be reduced. The source electrode of the P-TFT is ext. Since it is directly connected to Vcc, it is not affected by the back gate effect. Therefore, the voltage can be stepped down by the amount corresponding to the threshold voltage of the PMOS transistor without the back gate effect, as compared with the conventional step-down circuit of FIG.

Therefore, even if the threshold voltage Vth is set low in order to keep the power consumption low, int. Vcc
It is possible to provide a step-down circuit capable of high-speed operation and high integration capable of sufficiently stepping down the voltage.

(3) Third Embodiment FIG. 4 shows a step-down circuit 4 according to a third embodiment of the step-down circuit of the present invention.
It is a circuit diagram which shows 00.

Referring to FIG. 4, the step-down circuit 400 has a PM
It includes an OS transistor 401 and an N-TFT 403.

The source electrode of the PMOS transistor 401 is ext. It is connected to Vcc, and the drain electrode and the gate electrode are connected to the drain electrode and the gate electrode of the N-TFT 403. The source electrode of the N-TFT is i
nt. It is connected to the Vcc output node N1. That is, the PMOS transistor 401 and the N-TFT 403 have the ext. Vcc and int. It is diode-connected in series with Vcc.

The N-TFT 403 is less susceptible to the back gate effect of the substrate, and the source electrode of the PMOS transistor 401 is ext. Since it is directly connected to Vcc and is not affected by the back gate effect, the threshold value can be set low. Therefore, ext. Vcc is stepped down and a predetermined int. It is possible to obtain Vcc, reduce power consumption at the same time, and enable high speed operation.

For example, the threshold voltage Vth of the PMOS transistor is set to -0.7 to -0.8 [V] and the threshold voltage Vth of the N-TFT is set to 0.7 to 0.8 [V]. , Int. Vcc can be set to about 3.4 to 3.6 [V].

Further, since the N-TFT 403 can be formed on the PMOS transistor 401, the layout occupying area can be reduced and further high integration can be achieved.

(4) Fourth Embodiment FIG. 5 shows a step-down circuit 5 according to a fourth embodiment of the present invention.
It is a circuit diagram which shows 00.

Referring to FIG. 5, step-down circuit 500 has a P-T
It includes an FT 501 and an N-TFT 503.

The source electrode of the P-TFT 501 is ex
t. The drain electrode and the gate electrode are connected to Vcc, and are connected to the drain electrode and the gate electrode of the N-TFT 503. The source electrode of the N-TFT 503 is int.
It is connected to the Vcc output node N1. That is, P
-TFT 501 and N-TFT 503 are ext. Vc
c and int. It is diode-connected in series with Vcc.

The step-down circuit 500 is the step-down circuit 200 of FIG.
In the above, the NMOS transistor 203 is replaced with an N-TFT 503 which is a thin film transistor.

P-TFT 501 which is a thin film transistor
And the N-TFT 503 is not easily affected by the back gate effect, and the P-TFT 501 has the source electrode e.
xt. Since it is directly connected to Vcc, it is not affected by the back gate effect. Therefore, the threshold voltage can be set low.

For example, in order to keep the power consumption low,
The threshold voltage Vth of the P-TFT 501 is -0.7 to-
0.8 [V], threshold voltage Vth of N-TFT 503
Is set to a low value such as 0.7 to 0.8 [V], the int. Vcc can be set to about 3.4 to 3.6 [V].

Therefore, ext. Vcc is stepped down and a predetermined int. Vcc can be obtained, and it is possible to reduce power consumption and speed up the operation.

Further, the P-TFT 501 and the N-TFT 50
Since 3 and 3 can be formed on other elements in the semiconductor device, the layout occupying area can be reduced, and higher integration can be achieved.

(5) Fifth Embodiment FIG. 6 shows a step-down circuit 6 according to a fifth embodiment of the step-down circuit of the present invention.
It is a circuit diagram which shows 00.

Referring to FIG. 6, step-down circuit 600 includes NM
It includes an OS transistor 601 and a P-TFT 603.

The drain and gate electrodes of the NMOS transistor are ext. Connected to Vcc and the source electrode is P
-It is connected to the source electrode of the TFT 603. P-T
The drain electrode and the gate electrode of FT603 are int. V
It is connected to the cc output node N1.

That is, the NMOS transistor 601 and the P-TFT 603 are connected to the ext. Vcc and int. Vc
A diode connection is made in series with c.

The step-down circuit 600 is the same as the step-down circuit 200 of the second embodiment of the present invention shown in FIG.
The insertion position of the S transistor is reversed. The P-TFT 603, which is a thin film transistor, is hardly affected by the back gate effect on the threshold voltage Vth. Therefore, the NMOS transistors 601 and P-T
By setting the threshold voltage Vth of each FT 603 to be low, int. Vcc can be set to about 2.5 [V].

Therefore, ext. Vcc is sufficiently reduced to a predetermined int. Vcc can be obtained, and at the same time, power consumption can be reduced and operation speed can be increased.

Further, P is provided on the NMOS transistor 601.
-It is possible to form the TFT 603.

Therefore, the layout occupying area can be reduced and higher integration can be achieved.

(6) Sixth Embodiment FIG. 7 shows a step-down circuit 7 according to a sixth embodiment of the step-down circuit of the present invention.
It is a circuit diagram which shows 00.

Referring to FIG. 7, step-down circuit 700 has N-
It includes a TFT 701 and a PMOS transistor 703.

The drain electrode and the gate electrode of the N-TFT 701 are ext. Connected to Vcc and source electrode is PM
It is connected to the source electrode of the OS transistor 703. The drain electrode and the gate electrode of the PMOS transistor 703 are int. It is connected to the Vcc output node N1. That is, the N-TFT 701 and the PMOS transistor 703 have the ext. Vcc and int. It is diode-connected in series with Vcc.

N-TFT 701 which is a thin film transistor
Is hardly affected by the back gate effect on the threshold voltage. Therefore, by setting the threshold voltage of each of the N-TFT 701 and the PMOS transistor 703 to be low, int. Vcc can be set to around [V].

Therefore, ext. Vcc is stepped down and the desired int. Vcc can be obtained, and at the same time, power consumption can be reduced and operation can be speeded up.

Further, N is formed on the PMOS transistor 703.
-It is possible to form the TFT 701.

Therefore, the layout occupying area can be reduced and higher integration can be achieved.

(7) Seventh Embodiment FIG. 8 shows a step-down circuit 8 according to a seventh embodiment of the step-down circuit of the present invention.
It is a circuit diagram which shows 00.

Referring to FIG. 8, step-down circuit 800 has N-
It includes a TFT 801 and a P-TFT 802.

The drain electrode and the source electrode of the N-TFT 801 are ext. It is connected to Vcc and the source electrode is P-
It is connected to the source electrode of the TFT 802. P-TF
The drain electrode and the source electrode of T802 are int. Vc
It is connected to the c output node N1. That is, N-T
FT801 and P-TFT802 are ext. Vcc and int. It is diode-connected in series with Vcc.

N-TFT 801 which is a thin film transistor
Therefore, the P-TFT 802 is hardly affected by the back gate effect on the threshold voltage Vth. Therefore,
For example, in order to keep power consumption low, N-TFT8
The threshold voltage of 01 is 0.7 to 0.8 [V], P-TF
The threshold voltage Vth of T803 is -0.7 to -0.8.
Even if it is set to a low value such as [V], int. V
cc can be set to about 3.4 to 3.6 [V].

Therefore, ext. Vcc is stepped down and the desired int. It is possible to obtain Vcc, reduce power consumption at the same time, and speed up the operation.

In addition, N-TFT 801 and P-TFT 80
3 and 3 can be formed on another element in the semiconductor device.

Therefore, it is possible to provide a step-down circuit which reduces the layout occupying area and enables higher integration.

(8) Eighth Embodiment FIG. 9 shows a step-down circuit 9 according to the eighth embodiment of the present invention.
It is a circuit diagram which shows 00.

Referring to FIG. 9, step-down circuit 900 includes NM
A P-TFT 9 in which a wiring layer including an OS transistor 901 and a conductive film 929 such as polysilicon connected to the source electrode side is inserted between the channel polysilicon and the substrate.
03 is included.

The drain electrode and the gate electrode of the NMOS transistor are ext. The source electrode is connected to Vcc and the source electrode is connected to the source electrode of the P-TFT 903. P-
The drain electrode and the source electrode of the TFT 903 are int.
It is connected to the Vcc output node N1. That is, N
The MOS transistor 901 and the P-TFT 903 are
xt. Vcc and int. It is diode-connected in series with Vcc.

FIG. 10 is a diagram showing the structure of the step-down circuit 900 of FIG. 9, (a) is a plan view of the step-down circuit 900, and (b) is a step-down circuit 900 in the plan view of (a).
It is sectional drawing when it cut | disconnects by cutting plane BB '.

Referring to FIGS. 10A and 10B, the NMO
The S transistor 901 has an N ₊
Drain electrode 904 and N ₊ source electrode 905 are formed. Furthermore, an oxide film 907 of the P-TFT 903 is formed thereon. A gate electrode 909 is formed in the oxide film 907 between the drain electrode 904 and the source electrode 905. In addition, the gate electrode 909
Field insulating films 911 and 913 are formed in the boundary portion between the P well 901 and the oxide film 907 except the lower part of the field insulating film.

On the oxide film 907, thin-film polysilicon is formed, and a P ₊ drain electrode 915 and a P P ₊ source electrode 917 are formed (this is referred to as channel polysilicon). The source electrode 915 has an ext. V
The aluminum wiring 919 given with cc is connected.
The aluminum wiring 919 has a stopper 923 in the oxide film 907.
Has been stopped by. NMOS transistor 90
The source electrode 905 and the gate electrode 909 of No. 1 are ex
t. It is connected by an aluminum wiring 921 to which Vcc is applied. In the P-TFT 903, the drain electrode 915
A gate electrode 927 is formed on the upper part between the source electrode 917 and the source electrode 917. Then, a wiring layer made of a conductive film 929 such as polysilicon is inserted in the oxide film 907 between the NMOS transistor 901 and the P-TFT 903. The conductive film 929 is the source electrode 9 of the P-TFT 903.
17 and aluminum wiring 931. P-TFT
In 903, the source electrode 90 is connected to the aluminum wiring 919.
5 and the source electrode 917 are connected.

By forming a wiring layer such as the conductive film 929 in the step-down circuit 900, the influence of the substrate potential can be completely cut off.

Further, a P-TFT which is a thin film transistor
Since 903 is not affected by the back gate effect, the threshold voltage Vth can be set low. Therefore, power consumption can be reduced. further,
Since the P-TFT 903 can be formed on the NMOS transistor 901, the layout occupying area can be reduced and higher integration can be achieved.

(9) Ninth Embodiment FIG. 11 is a circuit diagram showing a step-down circuit 1100 according to a ninth embodiment of the step-down circuit of the present invention.

Referring to FIG. 11, step-down circuit 1100 has
N-TFT 1101 and PMOS transistor 1103
And a conductive film 1125 such as polysilicon.

The drain electrode and the gate electrode of the N-TFT 1101 are ext. The source electrode is connected to Vcc and the source electrode is connected to the source electrode of the PMOS transistor 1103. The drain electrode and the source electrode of the PMOS transistor 1103 are int. It is connected to the Vcc output node N1. The wiring layer formed of the conductive film 1125 is N−
It is inserted between a source electrode and a drain electrode formed on the thin film polysilicon of the TFT and a Si substrate formed between the N-TFT 1101 and the PMOS transistor 1103, and is connected to the source electrode of the N-TFT 1101. .

As in the case of the step-down circuit 900 of the eighth embodiment, the influence of the substrate potential can be completely cut off by forming the conductive film 1125.

Further, an N-TFT which is a thin film transistor
Since there is no influence due to the back gate effect, it is possible to set the threshold voltage Vth low, so that power consumption can be reduced. Furthermore, the N-TFT 11
Since 01 can be formed on the PMOS transistor 1103, the layout occupying area can be reduced and higher integration can be achieved.

(10) Tenth Embodiment FIG. 12 is a circuit diagram showing a step-down circuit 1200 according to a tenth embodiment of the step-down circuit of the present invention.

Referring to FIG. 12, step-down circuit 1200 includes
It includes an N-TFT 1201, a P-TFT 1203, and a conductive film 1235 such as polysilicon.

FIG. 13 is a diagram showing the structure of the step-down circuit 1200 of FIG. 12, (a) is a plan view of the step-down circuit 1200, and (b) is a plan view of the step-down circuit 1200 of (a). FIG. 9 is a cross-sectional view taken along the line C-C ′ in FIG.

Referring to FIGS. 12 and 13A and 13B, field insulating film 1211 is formed on P well 1201.
Are formed. An oxide film 1207 is formed on the field insulating film 1211. A thin film polysilicon 1235 is formed on the oxide film 1207, and the thin film polysilicon 1235 is formed.
235, the N ₊ source electrode 12 of the N-TFT 1201
04 and N ₊ drain electrode 1205 and P-TFT 12
A P ₊ drain electrode 1208 and a P ₊ source electrode 1209 of No. 03 are formed. A gate electrode 1206 is formed between the source electrode 1204 and the drain electrode 1205 of the N-TFT 1201. P-TFT12
A gate electrode 1210 is formed between the drain electrode 1208 and the source electrode 1209 of No. 03.

In the N-TFT 1201, the drain electrode 1205 and the gate electrode 1206 are ext. Vcc
Are formed by aluminum wiring 1219. P
-In the TFT 1203, the drain electrode 1208 and the gate electrode 1210 are int. Vcc output node N1
To the aluminum wiring 1221. The stopper 1223 in the oxide film is a stopper for the aluminum wirings 1219 and 1221. In the oxide film 1207, a wiring layer made of a conductive film 1235 is inserted between the field insulating film 1211 and the thin film polysilicon 1235. The conductive film 1235 is a source electrode 1204 of the N-TFT 1201.
And a source electrode 1209 of the P-TFT 1203 by an aluminum wiring 1240.

Further, an N-TFT which is a thin film transistor
Although the 1201 and the P-TFT 1203 are not easily affected by the back gate effect, the conductive film 1235 is not affected by the N
-N-TFT 1201 and P-TFT 1203 by extending and inserting between the source electrode and drain electrode of the TFT 1201 and P-TFT 1203 and the substrate.
In both cases, the effect of completely blocking the influence of the back gate effect by the substrate can be obtained.

Therefore, the N-TFTs 1201 and P
Since the threshold voltage Vth of each of the TFTs 1203 can be set low, the power consumption can be reduced.

Furthermore, N-TFT 1201 and P-TFT
Since 1203 can be formed on another element in the semiconductor device, the layout occupying area can be reduced,
Higher integration is possible.

(11) Eleventh Embodiment FIG. 14 is a circuit diagram showing a step-down circuit 1400 according to the eleventh embodiment of the high voltage circuit of the present invention.

Referring to FIG. 14, step-down circuit 1400 includes
It includes an N-TFT 1401 and a resistor R.

Ext. Vcc and int. A high resistance element R is connected between the output node N1 of Vcc and the output node N1. N-
The drain electrode and the gate electrode of the TFT 1401 are in
t. It is connected to the Vcc output node N1 and the source electrode is grounded.

As shown in FIG. 14, ext. Vcc and i
nt. By providing the high resistance element R between the Vcc output node N1 and the N-TFT 1401 having a larger conductance (reciprocal of resistance) than the high resistance element R on the ground side, int. Vcc can be set to the value of the threshold voltage Vth of the N-TFT. Therefore,
The N-TFT, which is a thin film transistor, is not easily affected by the back gate effect. Therefore, by setting the threshold voltage Vth low, a low int. It can be adjusted to output Vcc.

For example, when the threshold voltage Vth of the N-TFT 1401 is set to 0.7 to 0.8 [V], i
nt. Vcc can be set to about 0.7 to 0.8 [V].

Further, since the N-TFT 1401 can be formed on other elements of the semiconductor device, the layout occupying area can be reduced and higher integration can be achieved.

(12) Twelfth Embodiment FIG. 15 is a circuit diagram showing a step-down circuit 1500 according to a twelfth embodiment of the step-down circuit of the present invention.

Referring to FIG. 15, step-down circuit 1500 includes
P-TFT 1501 and NMOS transistor 1503
And a high resistance element R.

Ext. Vcc and int. High resistance element R is connected between Vcc output node N1. P-T
The source electrode of FT1501 is int. The drain electrode and the gate electrode, which are connected to the Vcc output node N1, have NM
The drain electrode and the gate electrode of the OS transistor 1503 are connected. The source electrode of the NMOS transistor 1503 is grounded. That is, P-TFT1
501 and NMOS transistor 1503 are int.
A diode is connected in series between the Vcc output node N1 and the ground voltage.

Since the N-TFT, which is a thin film transistor, is not easily affected by the back gate effect of the substrate, the threshold voltage can be set low. Therefore, FIG.
As shown in FIG. Vcc and int. A high-resistance element is provided between the high-resistance element R and the Vcc output node N1, and a P-TFT 1501 having a larger conductance (reciprocal of resistance) than the high-resistance element R is set to int. It is provided between the Vcc output node N1 and the grounded NMOS transistor 1503, and the threshold voltage Vth of the P-TFT 1501 is set to a low value to set the int. It is possible to adjust Vcc low.

For example, the threshold voltage Vth of the P-TFT 1501 is -0.7 to -0.8 [V], and the threshold voltage Vth of the NMOS transistor 1503 is 0.7 to 0.
When set to 8 [V], int. Vcc is about 1.4 ~
It can be set to around 1.6 [V].

Further, since the P-TFT 1501 can be formed on the NMOS transistor 1503 or another element in the semiconductor device, the layout occupying area can be reduced to achieve high integration.

(13) Thirteenth Embodiment FIG. 16 is a circuit diagram showing a step-down circuit 1600 according to a thirteenth embodiment of the step-down circuit of the present invention.

Referring to FIG. 16, step-down circuit 1600 includes
PMOS transistor 1601 and N-TFT 1603
And a high resistance element R.

Ext. Vcc and int. High resistance element R is connected between Vcc output node N1. PMO
The source electrode of the S transistor 1601 is int. Vc
The drain electrode and the gate electrode are connected to the c output node N1 and are connected to the drain electrode and the gate electrode of the N-TFT 1603. The source electrode of the N-TFT is grounded. That is, int. The PMOS transistor 1601 and the N-TFT 16 are connected between Vcc and the ground voltage.
And 03 are diode-connected in series.

N-TFT 160 which is a thin film transistor
No. 3 is less affected by the back gate effect of the substrate, so the threshold voltage Vth can be set low. Therefore, ext. Vcc and int. A high resistance element R is provided between the resistance element R and the Vcc output node N1, and the conductance (the reciprocal of the resistance value) N is larger than the resistance element R.
-TFT, int. By providing between the PMOS transistor 1601 connected to Vcc and the ground voltage, int. It is possible to set Vcc to a desired low value.

Further, the N-TFT 1603 is connected to the PMOS.
Since it can be formed over the transistor 1601 or another element of the semiconductor device, high integration can be achieved by reducing a layout area.

(14) Fourteenth Embodiment FIG. 17 is a circuit diagram showing a step-down circuit 1700 according to a fourteenth embodiment of the step-down circuit of the present invention.

Referring to FIG. 17, step-down circuit 1700 includes
It includes a P-TFT 1701, an N-TFT 1703, and a high resistance element R.

Ext. Vcc and int. High resistance element R is connected between Vcc output node N1. P-T
The source electrode of FT1701 is int. The drain electrode and the gate electrode are connected to the Vcc output node N1
-It is connected to the drain electrode and the gate electrode of the TFT 1703. The source electrode of the N-TFT 1703 is grounded. That is, int. A P-TFT 1701 and an N-TFT 1703 are diode-connected in series between Vcc and the ground voltage.

P-TFT 170 which is a thin film transistor
1 and the N-TFT 1703 are not easily affected by the back gate effect of the substrate, so that the threshold voltage Vth can be set low. Therefore, ext. Vcc and int. A high resistance element R is provided between Vcc output node N1 and int. Between the Vcc output node N1 and the ground voltage, the P-TFT 1701 and the N-TFT 17 having a larger conductance (reciprocal of resistance) than the high resistance element R.
03 and by providing int. Vcc can be set to a desired low value. Furthermore, P-TFT17
01 and the N-TFT 1703 can be formed on other elements of the semiconductor device, so that the area occupied by the layout can be reduced to achieve high integration.

(15) Fifteenth Embodiment FIG. 18 is a circuit diagram showing a step-down circuit 1800 according to a fifteenth embodiment of the step-down circuit of the present invention.

Referring to FIG. 18, step-down circuit 1800 is
NMOS transistor 1801 and P-TFT 1803
And a high resistance element R.

Ext. Vcc and int. High resistance element R is connected between Vcc output node N1. NMO
The drain electrode and the gate electrode of the S transistor 1801 are int. The source electrode is connected to the Vcc output node N1 and the source electrode is connected to the source electrode of the P-TFT 1803. The drain electrode and the gate electrode of the P-TFT 1803 are grounded. That is, int. NMOS transistor 1801 and P-TF are connected between Vcc and ground voltage.
T1803 is diode-connected in series.

P-TFT 180 which is a thin film transistor
In No. 3, the substrate is not easily affected by the back gate effect, so that the threshold voltage Vth can be set low. Therefore, ext. Vcc and int. A high resistance element R is provided between the output node and the Vcc output node, and int. Vc
NMOS transistor 1 connected to the output node N1
By providing a P-TFT 1803 having a large conductance (reciprocal of resistance) between the 801 and the ground voltage, int. Vcc can be set to a desired low value.

For example, NMOS transistor 1801
Threshold voltage Vth of 0.7 to 0.8 [V], P-T
The threshold voltage Vth of the FT1803 is -0.7 to -0.
When set to 8 [V], the NMOS transistor 180
The threshold voltage Vth of 1 becomes 1.56 to 1.75 [V] due to the back gate effect, and int. Vcc can be set to around 2.5 [V].

Further, the P-TFT 1803 is an NMOS.
Since it can be formed over the transistor 1801 or another element of the semiconductor device, high integration can be achieved by reducing a layout occupation area.

(16) Sixteenth Embodiment FIG. 19 is a circuit diagram showing a step-down circuit 1900 according to a sixteenth embodiment of the step-down circuit of the present invention.

Referring to FIG. 19, step-down circuit 1900 includes
N-TFT 1901 and PMOS transistor 1903
And a high resistance element R.

Ext. Vcc and int. High resistance element R is connected between Vcc output node N1. NT
The drain electrode and gate electrode of FT1901 are in
t. The source electrode is connected to the Vcc output node N1.
It is connected to the source electrode of the PMOS transistor 1903. The drain electrode and the gate electrode of the PMOS transistor 1903 are grounded. That is, int.
An N-TFT is provided between the Vcc output node N1 and the ground voltage.
The 1908 and the PMOS transistor 1903 are diode-connected in series.

N-TFT 190 which is a thin film transistor
No. 1 is less susceptible to the back gate effect of the substrate, so that the threshold voltage Vth can be set low. Therefore, ext. Vcc and int. A high resistance element R is provided between Vcc output node N1 and int.
By providing an N-TFT 1901 having a conductance (reciprocal of resistance) larger than that of the high resistance element R between the Vcc output node N1 and the grounded PMOS transistor 1903, int. It is possible to set Vcc to a desired low value.

Further, since the N-TFT can be formed on the PMOS transistor 1903 or another element of the semiconductor element, the layout occupying area can be reduced and high integration can be achieved. .

(17) Seventeenth Embodiment FIG. 20 is a circuit diagram showing a step-down circuit 2000 according to a seventeenth embodiment of the step-down circuit of the present invention.

Referring to FIG. 20, step-down circuit 2000 includes
It includes an N-TFT 2001, a P-TFT 2003, and a high resistance element R.

Ext. Vcc and int. High resistance element R is connected between Vcc output node N1. NT
The drain electrode and the gate electrode of FT2001 are in
t. The source electrode is connected to the Vcc output node N1.
It is connected to the source electrode of the P-TFT2003. P
-The drain electrode and the gate electrode of the TFT 2003 are grounded. That is, int. Vcc output node N1
Between the N-TFT 2001 and the P-TFT
2003 are diode-connected in series.

N-TFT200 which is a thin film transistor
1 and the P-TFT 2003 are not easily affected by the back gate effect of the substrate, the threshold voltage Vth can be set low. Therefore, ext. Vcc
And int. High resistance element R between Vcc output node N1
And int. By providing an N-TFT 2001 and a P-TFT 2003 having a larger conductance than that of the high resistance element R between the Vcc output node N1 and the ground voltage, int. It is possible to set Vcc to a predetermined low value.

For example, the threshold voltage Vth of the N-TFT 2001 is 0.7 to 0.8 [V], and the P-TFT 200 is
3 is set to -0.7 to -0.8 [V], int. Vcc can be set to about 1.4 to 1.6 [V].

Furthermore, N-TFT 2001 and P-T
Since the FT 2003 can be formed on another element of the semiconductor device, the layout occupying area can be reduced and high integration can be achieved.

(18) Eighteenth Embodiment FIG. 21 is a circuit diagram showing a step-down circuit 2100 according to an eighteenth embodiment of the step-down circuit of the present invention.

Referring to FIG. 21, step-down circuit 2100 has
NMOS transistor 2101 and P-TFT 2103
And a wiring layer 2125 such as polysilicon and a high resistance element R. That is, int. The NMOS transistor 2101 and the P-TFT 21 are connected between Vcc and the ground voltage.
And 03 are diode-connected in series. The wiring layer 2125 is inserted between the substrate and the source and drain electrodes of the P-TFT 2103.

By inserting a wiring layer made of the conductive film 2125 connected to the source electrode side of the P-TFT 2103 between the channel polysilicon and the substrate, the influence of the substrate potential can be completely shielded.

Furthermore, the P-TFT 2103 is an NMOS.
Since it can be formed over the transistor 2101 or another element of the semiconductor device, the layout occupying area can be reduced and high integration can be achieved.

(19) Nineteenth Embodiment FIG. 22 is a circuit diagram showing a step-down circuit 2200 according to a nineteenth embodiment of the step-down circuit of the present invention.

Referring to FIG. 22, step-down circuit 2200 includes
N-TFT 2201 and PMOS transistor 2203
And a conductive film 2225 and a high resistance element R.

Ext. Vcc and int. High resistance element R is connected between Vcc output node N1. NT
The drain electrode and the gate electrode of FT2201 are in
t. It is connected to the Vcc output node N1 and the source electrode is P
It is connected to the source electrode of the MOS transistor 2203. The drain electrode and the gate electrode of the PMOS transistor 2203 are grounded. That is, int. V
N-TFT22 is connected between the cc output node N1 and the ground voltage.
01 and the PMOS transistor 2203 are diode-connected in series. A wiring layer made of the conductive film 2225 is inserted between the substrate and the source and drain electrodes of the N-TFT.

By inserting the conductive film 2225 such as polysilicon connected to the drain side of the N-TFT, the influence of the substrate potential can be completely shielded.
The threshold voltage of 2201 can be set low. Therefore, ext. Vcc and int. A high resistance element R is provided between the output node N1 of Vcc and int.
Between the Vcc output node N1 and the ground voltage, an N-TFT 2201 having a larger conductance than the high resistance element,
By providing the PMOS transistor 2203,
int. Vcc can be set to a predetermined low value.

Further, the N-TFT 2201 is a PMOS
Since it can be formed over the transistor 2203 or another element of the semiconductor device, the layout occupying area can be reduced and high integration can be achieved.

(20) Twentieth Embodiment FIG. 23 is a circuit diagram showing a step-down circuit 2300 according to a twentieth embodiment of the step-down circuit of the present invention.

Referring to FIG. 23, step-down circuit 2300 is
It includes an N-TFT 2301, a P-TFT 2303, a conductive film 2335, and a high resistance element R.

Ext. Vcc and int. High resistance element R is connected between Vcc output node N1. NT
The drain electrode and gate electrode of FT2301 are in
t. It is connected to the Vcc output node N1 and the source electrode is P
-It is connected to the source electrode of the TFT 2303. P-
The drain electrode and the gate electrode of the TFT 2303 are grounded. Source electrode of N-TFT 2301 and P-
The wiring layer made of a conductive film 2335 such as polysilicon connected to the source electrode of the TFT 2303 is the N-TFT 2
301 source and drain electrodes and P-TFT2
It is inserted between the source electrode and the gate electrode of 303 and the substrate.

By inserting the conductive film 2335 between the channel polysilicon of the N-TFT 2301 and the P-TFT 2303 and the substrate, the influence of the substrate potential can be completely shielded.
The threshold voltage Vth of the TFT 2303 can be set low. Therefore, ext. Vcc and int. Vc
The high resistance element R is provided between the output node N1 and the
t. An N-TFT 2301 having a conductance larger than that of the high resistance element R between the Vcc output node N1 and the ground voltage.
And by providing the P-TFT 2303,
t. It is possible to set Vcc to a predetermined low value.

Furthermore, N-TFT 2301 and P-T
Since the FT 2303 can be formed on another element of the semiconductor device, the layout occupying area can be reduced and high integration can be achieved.

(21) Twenty-first Embodiment FIG. 24 is a circuit diagram showing a step-down circuit 2400 according to a twenty-first embodiment of the step-down circuit of the present invention.

Referring to FIG. 24, step-down circuit 2400 includes
NMOS transistors 241, 242, ..., 24n (n
Is a natural number) and fuses H1, H2, ..., Hn.

The fuses H1, H2, ..., Hn are NMO.
, 24n respectively corresponding to the S transistors 241, 242 ,. Vcc and int. Vcc output node N
, And NMOS transistors 241, 242, ...
24n are diode-connected in parallel via fuses H1, H2, ..., Hn, respectively. That is, the step-down circuit 2400 is a trimming circuit using the conventional step-down circuit 2800 of FIG. By utilizing the gate length dependency of the threshold voltage Vth of the transistor, the step-down width is changed by changing the gate length of each of the NMOS transistors 241, 242, ..., 24n.
By selectively leaving any one (or more) of H2, ..., Hn and cutting the rest, int. It becomes possible to set Vcc to a desired value.

In FIG. 24, the NMOS transistor 2
, 24n are provided with Ps having different gate lengths.
The same effect can be obtained even if the MOS transistor is replaced. Also, NMOS transistors 241 and 24
2, ..., 24n are N-type or P-type thin film transistors (N-TFTs or P-TFs) having different gate lengths.
Even if it is replaced with T), the same effect can be obtained, and further, since the thin film transistor can be formed on another element of the semiconductor device, the layout occupying area can be reduced and compared to the case where the MOS transistor is used. High integration is possible.

(22) Twenty-second Embodiment FIG. 25 is a circuit diagram showing a step-down circuit 2500 according to a twenty-second embodiment of the step-down circuit of the present invention.

Referring to FIG. 25, step-down circuit 2500 includes
, 25n, and PMOS transistors 251, 252, ...
NMOS transistors 251 ', 252', ..., 25
m'and fuses H1, H2, ..., Hn, H1 ', H
2 ′, ..., Hm ′ (n and m are natural numbers).

The fuses H1, H2, ..., Hn are PMOS.
, 25n provided to correspond to each of the transistors 251, 252 ,.
..., 25n is ext. Diodes are connected in parallel between Vcc and the node N2 via fuses H1, H2, ..., Hn. Further, the fuses H1 ', H2', ...,
Each of Hm 'is an NMOS transistor 251', 25
2 ', ..., 25 m'corresponding to each of the NMO
The S transistors 251 ', 252', ..., 25m 'are
Node N2 and int. Between Vcc output node N1 and
Diodes are connected in parallel via fuses H1 ', H2', ..., Hm '.

As in the case of the step-down circuit 2400 of the twenty-first embodiment, the gate length dependency of the threshold voltage Vth of the transistor is utilized to make use of the PMOS transistors 251, 252, ..., 25n and the NMOS transistors having different gate lengths. , 25m 'are provided, and fuses H1, H2, ..., Hn and fuses H1', H are provided.
By selectively leaving one (or more) of 2 ', ..., Hm' and cutting the rest, the step-down width is changed,
int. Vcc can be set to a desired value.

Here, the PMOS transistors 251 and 251 are used.
, 25n to the thin film transistor P-TFT,
MOS transistors 251 ', 252', ..., 25m '
Is replaced with a thin film transistor N-TFT, the step-down circuit 200 of the second embodiment of FIG. 2 or the third embodiment of FIG.
Either the step-down circuit 400 of FIG. 5 or the step-down circuit 500 of the fourth embodiment shown in FIG. 5 is obtained, and the same effect as that described in each of the embodiments can be obtained.

Here, if necessary, the fuses H1, H
, ..., Hn and H1 ', H2', ..., Hm 'are selectively left at least two, and int. It is also possible to adjust Vcc.

PMOS transistors 251, 252,
, 25n are connected to the node N2 and int. Vcc output node N1 is diode-connected and NMOS transistors 251 ', 252', ..., 25m 'are connected to ext. Even if a diode is connected between Vcc and the node N1, the step-down circuit 25
The same effect as 00 can be obtained.

FIG. 26 shows PMOS transistors 251, 252, ..., 25 in the step-down circuit 2500 of FIG.
n is a P-type thin film transistor P-TFT 271, 272,
..., 27n with NMOS transistors 251 ', 25
25 'is an N-type thin film transistor N-TF.
It is the circuit diagram replaced by T271 ', 272', ..., 27m '.

The step-down circuit 2700 is the step-down circuit 2 of FIG.
Since it is possible to set the threshold voltage of each of the P-TFT and the N-TFT lower than that of 500,
t. Vcc can be set to a predetermined lower value.

Further, P-TFTs 271, 272, ...
27n and N-TFTs 271 ', 272', ..., 27
Since m'can be formed on other elements in the semiconductor device, respectively, the layout occupying area can be reduced and high integration can be achieved.

Further, the step-down circuit 90 of FIG. 9 is provided between the channel polysilicon of the N-TFT and P-TFT and the substrate.
0, step-down circuit 1100 of FIG. 11, step-down circuit 12 of FIG.
As in the case of No. 00, if a conductive film is inserted, the influence of the substrate potential can be completely shielded.
-The threshold voltage of the TFT can be set lower. Therefore, int. It is possible to set Vcc to a predetermined lower value.

(23) Twenty-third Embodiment FIG. 27 is a circuit diagram showing a step-down circuit 2600 according to a twenty-third embodiment of the step-down circuit of the present invention.

Referring to FIG. 27, step-down circuit 2600 includes
, 26n, and PMOS transistors 261, 262 ,.
NMOS transistors 261 ', 262', ..., 26
m'and fuses H1, H2, ..., Hn, H1 ', H
2 ′, ..., Hm ′ (n and m are natural numbers) and a high resistance element R
And

Ext. Vcc and int. High resistance element R is connected between Vcc output node N1. The fuses H1, H2, ..., Hn are PMOS transistors 26.
, 26n corresponding to the int. Diodes are connected in parallel between Vcc output node N1 and node N2 via corresponding fuses. The fuses H1 ', H2', ..., Hm 'are NMOSs.
, 26m 'corresponding to the NMOS transistors 261', 262 ',
, 26m 'are connected in parallel via a fuse between the node N2 and the ground voltage.

, Hn and each of the fuses H1 ', H2', ..., Hm 'are selectively left and blown to disconnect the remaining portions. The same effects as those of the step-down circuit 1500 of the twelfth embodiment, the step-down circuit 1600 of the thirteenth embodiment of FIG. 16 or the step-down circuit 1700 of the fourteenth embodiment of FIG. 17 can be obtained.

PMOS transistors 261, 262,
, 26n are diode-connected between the node N2 and the ground voltage, and NMOS transistors 261 ', 262',
..., 26m 'int. Even if a diode is connected between Vcc output node N1 and node N2, the same effect as in the case of step-down circuit 2600 can be obtained.

Here, the PMOS transistors 261 and 2 are
62, ..., 26n to the thin film transistor P-TFT, N
MOS transistors 261 ', 262', ..., 26m '
Is replaced with a thin film transistor N-TFT, either the step-down circuit 1500 of the twelfth embodiment shown in FIG. 15, the step-down circuit 1600 of the thirteenth embodiment shown in FIG. 16, or the step-down circuit 1700 shown in the fourteenth embodiment of FIG. The same effect as the case can be obtained.

Further, between the channel polysilicon in the N-TFT and P-TFT and the substrate, in the same manner as in the step-down circuit 2100 of FIG. 21, the step-down circuit 2200 of FIG. 22, and the step-down circuit 2300 of FIG. 23, Since the influence of the substrate potential can be completely shielded by inserting the conductive film, the threshold voltage of the N-TFT or P-TFT can be set lower. Therefore, int. It is possible to set Vcc to a predetermined lower value.

[0166]

As described above, the step-down circuit of the present invention is
In the RAM, it is possible to provide a step-down circuit that reduces power consumption and also reduces the layout occupying area and enables higher integration.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a step-down circuit according to a first embodiment of a step-down circuit of the present invention.

FIG. 2 is a circuit diagram showing a step-down circuit according to a second embodiment of the step-down circuit of the present invention.

3A and 3B are a plan view and a cross-sectional view showing the structure of the step-down circuit of FIG.

FIG. 4 is a circuit diagram showing a step-down circuit according to a third embodiment of the step-down circuit of the present invention.

FIG. 5 is a circuit diagram showing a step-down circuit according to a fourth embodiment of the step-down circuit of the present invention.

FIG. 6 is a circuit diagram showing a step-down circuit according to a fifth embodiment of the step-down circuit of the present invention.

FIG. 7 is a circuit diagram showing a step-down circuit according to a sixth embodiment of the step-down circuit of the present invention.

FIG. 8 is a circuit diagram showing a step-down circuit according to a seventh embodiment of the step-down circuit of the present invention.

FIG. 9 is a circuit diagram showing a step-down circuit according to an eighth embodiment of the step-down circuit of the present invention.

10A and 10B are a plan view and a cross-sectional view showing the structure of the step-down circuit of FIG.

FIG. 11 is a circuit diagram showing a step-down circuit according to a ninth embodiment of the step-down circuit of the present invention.

FIG. 12 is a circuit diagram showing a step-down circuit according to a tenth embodiment of the step-down circuit of the present invention.

13A and 13B are a plan view and a cross-sectional view showing the structure of the step-down circuit of FIG.

FIG. 14 is a circuit diagram showing a step-down circuit according to an eleventh embodiment of the step-down circuit of the present invention.

FIG. 15 is a circuit diagram showing a step-down circuit according to a twelfth embodiment of the step-down circuit of the present invention.

FIG. 16 is a circuit diagram showing a step-down circuit according to a thirteenth embodiment of the step-down circuit of the present invention.

FIG. 17 is a circuit diagram showing a step-down circuit according to a fourteenth embodiment of the step-down circuit of the present invention.

FIG. 18 is a circuit diagram showing a step-down circuit according to a fifteenth embodiment of the step-down circuit of the present invention.

FIG. 19 is a circuit diagram showing a step-down circuit according to a sixteenth embodiment of the step-down circuit of the present invention.

FIG. 20 is a circuit diagram showing a step-down circuit according to a seventeenth step of the step-down circuit of the present invention.

FIG. 21 is a circuit diagram showing a step-down circuit according to an eighteenth embodiment of the step-down circuit of the present invention.

FIG. 22 is a circuit diagram showing a step-down circuit according to Embodiment 19 of the step-down circuit of the present invention.

FIG. 23 is a circuit diagram showing a step-down circuit according to a twentieth embodiment of the step-down circuit of the present invention.

FIG. 24 is a circuit diagram showing a step-down circuit according to a twenty-first embodiment of the step-down circuit of the present invention.

FIG. 25 is a circuit diagram showing a step-down circuit according to a twenty-second embodiment of the step-down circuit of the present invention.

FIG. 26 is a circuit diagram in which an NMOS transistor in the step-down circuit of FIG. 25 is replaced with a thin film transistor.

FIG. 27 is a circuit diagram showing a step-down circuit according to a twenty-third embodiment of the step-down circuit of the present invention.

FIG. 28 is a circuit diagram showing a conventional step-down circuit.

FIG. 29 is a circuit diagram showing a conventional step-down circuit.

[Explanation of symbols]

100, 200, 400, 500, 600, 700, 8
00,900,1100,1200,1400,150
0, 1600, 1700, 1800, 1900, 200
0, 2100, 2200, 2300, 2400, 250
0, 2600, 2700 step-down circuit, 101, 403,
503, 701, 801, 1101, 1201, 140
1,1603,1703,1901,2001,220
1,2301,271 ', 272', ..., 27m 'N
-TFT, 201, 501, 603, 803, 903
1203, 1501, 1701, 1803, 2003,
2103, 2303, 271, 272, ..., 27n P
-TFT, 929, 1125, 1235, 2125, 2
225, 2335 Conductive film.

Claims (6)

[Claims] 1. A step-down circuit including a diode-connected thin film transistor that receives an external power supply voltage and steps down the external power supply voltage to generate an internal power supply voltage. 2. A step-down circuit for receiving an external power supply voltage and stepping down the external power supply voltage to generate an internal power supply voltage, the transistor having a first conductivity type and the transistor of the first conductivity type. A second conductivity type transistor different from the first conductivity type, which is diode-connected between the one electrode and the internal power supply voltage, wherein the first conductivity type transistor is connected to the external power supply voltage and the first power supply voltage. A step-down circuit diode-connected between two conductivity type transistors, wherein at least one of the first or second conductivity type transistors is a thin film transistor. 3. A step-down circuit that receives an external power supply voltage and steps down the external power supply voltage to generate an internal power supply voltage, the resistor being connected between the external power supply voltage and the internal power supply voltage. An element, a first conductivity type transistor, and a second conductivity type transistor different from the first conductivity type diode-connected between one electrode of the first conductivity type transistor and a ground voltage. The first conductivity type transistor is diode-connected between the internal power supply voltage and the second conductivity type transistor, and at least one of the first or second conductivity type transistors is a thin film transistor. Is a step-down circuit. 4. A step-down circuit that receives an external power supply voltage and steps down the external power supply voltage to generate an internal power supply voltage, comprising a diode-connected first conductivity type first transistor, First connecting means for connecting one electrode of the first transistor and the first node; second diode-connected transistor; connecting one electrode of the second transistor and the first node; A second connection means, wherein the other electrode of the first transistor and the other electrode of the second transistor are connected to a second node different from the first node, and the first node is the external node. One of a power supply voltage and the internal power supply voltage, wherein the second node is one of the external power supply voltage and the internal power supply voltage to which the first node is connected. Connected to the step-down circuit to said other. 5. A step-down circuit that receives an external power supply voltage and steps down the external power supply voltage to generate an internal power supply voltage, comprising: a diode-connected first conductivity type first transistor; First connecting means for connecting one electrode of one transistor to a first node; second transistor of the first conductivity type diode-connected; one electrode of the second transistor and the first node And a second connection means for connecting the diode, a diode-connected third transistor of a second conductivity type different from the first, a first electrode of the third transistor and a second node different from the first Third connecting means for connecting, the diode-connected fourth transistor of the second conductivity type, and a fourth contact connecting the one electrode of the fourth transistor and the second node. The other electrode of the first transistor and the other electrode of the second transistor are connected to the second node, and the other electrode of the third transistor and the other electrode of the fourth transistor are , A third node different from the first and second, the first node is connected to either one of the external power supply voltage or the power supply internal voltage, the third node, A step-down circuit connected to the other of the external power supply or the voltage and the internal power supply voltage to which the first node is connected. 6. The step-down circuit according to claim 5, wherein at least one of the first transistor, the second transistor, the third transistor, and the fourth transistor is a thin film transistor.