CN103531229A - Static random access memory - Google Patents
Static random access memory Download PDFInfo
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- CN103531229A CN103531229A CN201310493442.XA CN201310493442A CN103531229A CN 103531229 A CN103531229 A CN 103531229A CN 201310493442 A CN201310493442 A CN 201310493442A CN 103531229 A CN103531229 A CN 103531229A
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Abstract
The invention discloses a static random access memory which comprises a memory array and a circuit of the memory array. The static random access memory is characterized by further comprising a plurality of self-bias circuits, wherein each self-bias circuit consists of a P-type transistor controlled by a word line and an N-type transistor formed by connecting a grid with a drain. Therefore, the static random access memory disclosed by the invention is provided with the plurality of self-bias circuits, and because of the plurality of self-bias circuits, the voltage in the static working state is effectively reduced under the condition that the reading and writing operation voltage is not affected; as the power supply voltage does not need to be specially regulated, the memory is easy to integrate, can be used for effectively reducing the drain current of the memory array, has high practical values and is convenient to widely popularize and apply.
Description
Technical field
The present invention relates to a kind of static RAM, specifically, relate to a kind of static RAM with self-bias, belong to memory technology field.
Background technology
Static RAM (English is Static Random Access Memory, is called for short SRAM), as a kind of memory cell of standard, is widely used in the fields such as palm PC, wireless telecommunications and digital entertainment equipment.Along with the raising of integrated circuit integrated level and speed, the power consumption of chip is increasing, and the levels of leakage of SRAM is also rising rapidly.The static RAM that how to design low-power consumption has become an important topic of current integrated circuit fields.
Conventionally the normal working voltage of SRAM should be higher than 90% of design voltage, but in fact when SRAM storage unit is not when reading and writing store status, only need just normal save data of 70% design voltage, SRAM storage unit is in data preservation mode (data retention mode) state.In design in the past, only have when whole SRAM storage array is during all in non-read-write state, system just can enter data preservation mode, and in fact when chip works, SRAM can frequently be read and write, how the chance that data preservation mode is used seldom, therefore, effectively utilizes the low-voltage state of data preservation mode to reduce power consumption necessary in SRAM design.
Summary of the invention
For prior art above shortcomings, the object of this invention is to provide a kind of static RAM with self-bias, realization, in chip normal operation, makes the memory cell that has neither part nor lot in read-write operation in relatively low voltage, effectively to solve the technical matters of leakage current.
For achieving the above object, the present invention adopts following technical scheme to realize:
, comprise memory array and circuit thereof, it is characterized in that: also comprise several auto bias circuits, each auto bias circuit forms with the N-type transistor that a grid is connected with drain electrode by the P transistor npn npn of a word line traffic control.
As a kind of optimal way, also comprise power lead, described power lead is connected with memory array by auto bias circuit.
As a kind of optimal way, external power source is connected to internal electric source by auto bias circuit, and this internal electric source is connected with the unit of memory array.
The principle of work of static RAM provided by the invention is as follows:
In real work, when the storage unit of SRAM is during in read-write state, its word line (WLx) is in noble potential, P transistor npn npn (MPx) conducting of controlling by reverser, and now the voltage of internal electric source (Virtual VDD) equals external power source (VDD); For the storage unit in read-write state not, its word line is in electronegative potential, and the P transistor npn npn of controlling by reverser is closed, and N-type transistor (MNx) conducting; Due to the design that the transistorized operating characteristic of N-type is extremely connected with grid leak, drain electrode is greater than threshold voltage with the potential difference (PD) of source electrode, and N-type transistor has produced the voltage drop of Δ V, and the voltage of internal electric source is only VDD-Δ V like this, thereby effectively reduces leakage current.
Compared with prior art, static RAM provided by the invention, its auto bias circuit can not affect under the condition of read-write operation mode voltage, can effectively reduce the voltage under quiescent operation state; Owing to not needing special regulating power source voltage, therefore, this storer is convenient to integrated, can effectively reduce the leakage current of memory array simultaneously, has extremely strong practical value, is convenient to wide popularization and application.
Accompanying drawing explanation
Fig. 1 is the structural representation of the static RAM described in embodiment 1;
Fig. 2 is the inner structure schematic diagram of the memory array described in embodiment 1;
Fig. 3 is the circuit diagram of the static RAM (6T cellular construction) described in embodiment 1;
Fig. 4 is static RAM described in embodiment 1 voltage waveform view when work;
Fig. 5 is the structural representation of the static RAM described in embodiment 2;
The structural representation of the static RAM described in Fig. 6 embodiment 3;
Fig. 7 is the circuit diagram of the static RAM (8T cellular construction) described in embodiment 3.
Embodiment
Below in conjunction with the drawings and specific embodiments, technical scheme of the present invention is elaborated further.
As shown in Figure 1 to Figure 3, the static RAM that the present embodiment provides, comprise memory array and circuit thereof, and several auto bias circuits and power lead, each auto bias circuit forms with the N-type transistor that a grid is connected with drain electrode by the P transistor npn npn of a word line traffic control, described power lead is connected with memory array by auto bias circuit, and power lead is powered to memory array by auto bias circuit; External power source (VDD) is connected to internal electric source by auto bias circuit, and this internal electric source is connected with the unit of memory array, is directly used in to memory cell and powers; Every word line (WLx) is controlled separately an auto bias circuit.
When storer carries out normal read-write operation, conventionally only have one word line is selected and in noble potential, other word line of this storer is all in electronegative potential.For the word line (WLx) in noble potential, its P transistor npn npn (MPx) of controlling by reverser is opened, and internal electric source (Virtual VDD) is pulled to external power source current potential, and read-write operation speed can not be affected.And other word lines in electronegative potential, its P transistor npn npn (MPx) of controlling by reverser is all closed, the N-type transistor (MNx) itself extremely connected due to grid leak can produce a voltage drop (Δ V), internal electric source (Virtual VDD) is all positioned at relative low-voltage (VDD-Δ V), memory cell by its power supply is also all under relative low-voltage (VDD-Δ V), therefore can reach the object that reduces electric leakage.The voltage waveform view of static RAM described in the present embodiment when work as shown in Figure 4.
Fig. 5 is the structural representation of the static RAM described in the present embodiment, comparison diagram 5 and Fig. 1 are visible, the difference of the static RAM that the present embodiment provides and embodiment 1 is: when control signal (RE) is during in noble potential, no matter whether selected word line is, the P transistor npn npn (MPx) of its control is all opened; And when control signal (RE) is during in electronegative potential, can just control the switch of P transistor npn npn (MPx) by controlling word line potential, thereby reduce quiescent operation voltage by auto bias circuit.
Fig. 6 is the structural representation of the static RAM described in the present embodiment, Fig. 7 is the circuit diagram of the static RAM (8T cellular construction) described in the present embodiment, from Fig. 6 and 7: for the static random access memory cell of this 8T structure, it has two control word lines (WLa/WLb); Selected during in noble potential when any control word line, P transistor npn npn (MPx) is all in open mode; And when two control word lines are during simultaneously in electronegative potential, the P transistor npn npn (MPx) of its control is in closed condition, N-type transistor (MNx) conducting, reduces internal power source voltage, thereby can effectively reduce leakage current.
In sum, static RAM provided by the invention, its auto bias circuit can not affect under the condition of read-write operation mode voltage, can effectively reduce the voltage under quiescent operation state; Owing to not needing special regulating power source voltage, therefore, this storer is convenient to integrated, can effectively reduce the leakage current of memory array simultaneously, has extremely strong practical value, is convenient to wide popularization and application.
Finally be necessary to be pointed out that at this; above-mentioned explanation is only for being described in further detail technical scheme of the present invention; can not be interpreted as limiting the scope of the invention, some nonessential improvement that those skilled in the art's foregoing according to the present invention is made and adjustment all belong to protection scope of the present invention.
Claims (3)
1. a static RAM, comprises memory array and circuit thereof, it is characterized in that: also comprise several auto bias circuits, each auto bias circuit forms with the N-type transistor that a grid is connected with drain electrode by the P transistor npn npn of a word line traffic control.
2. static RAM as claimed in claim 1, is characterized in that: also comprise power lead, described power lead is connected with memory array by auto bias circuit.
3. static RAM as claimed in claim 1 or 2, is characterized in that: external power source is connected to internal electric source by auto bias circuit, and this internal electric source is connected with the unit of memory array.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310493442.XA CN103531229A (en) | 2013-10-18 | 2013-10-18 | Static random access memory |
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| CN201310493442.XA CN103531229A (en) | 2013-10-18 | 2013-10-18 | Static random access memory |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107408409A (en) * | 2015-06-05 | 2017-11-28 | 思科技术公司 | Low-power, towards capable memory write auxiliary circuit |
| WO2021212393A1 (en) * | 2020-04-23 | 2021-10-28 | 华为技术有限公司 | Low-leakage memory array |
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| CN1898744A (en) * | 2003-09-05 | 2007-01-17 | 兹摩斯科技股份有限公司 | Low voltage operation dram control circuits |
| US20070121370A1 (en) * | 2005-11-29 | 2007-05-31 | International Business Machines Corporation | Sram voltage control for improved operational margins |
| CN101040343A (en) * | 2004-11-18 | 2007-09-19 | 飞思卡尔半导体公司 | Word line driver circuit for a static random access memory and method therefor |
| CN101930795A (en) * | 2009-06-25 | 2010-12-29 | 上海华虹Nec电子有限公司 | Bit line pretreatment and storage device and method |
| CN203573659U (en) * | 2013-10-18 | 2014-04-30 | 上海工程技术大学 | Static random access memory with automatic bias |
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| CN1898744A (en) * | 2003-09-05 | 2007-01-17 | 兹摩斯科技股份有限公司 | Low voltage operation dram control circuits |
| CN1694182A (en) * | 2004-04-30 | 2005-11-09 | 台湾积体电路制造股份有限公司 | Static dasd and control circuit and control method |
| CN101040343A (en) * | 2004-11-18 | 2007-09-19 | 飞思卡尔半导体公司 | Word line driver circuit for a static random access memory and method therefor |
| US20070121370A1 (en) * | 2005-11-29 | 2007-05-31 | International Business Machines Corporation | Sram voltage control for improved operational margins |
| CN101930795A (en) * | 2009-06-25 | 2010-12-29 | 上海华虹Nec电子有限公司 | Bit line pretreatment and storage device and method |
| CN203573659U (en) * | 2013-10-18 | 2014-04-30 | 上海工程技术大学 | Static random access memory with automatic bias |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107408409A (en) * | 2015-06-05 | 2017-11-28 | 思科技术公司 | Low-power, towards capable memory write auxiliary circuit |
| CN107408409B (en) * | 2015-06-05 | 2021-01-12 | 思科技术公司 | Low power, line-oriented memory write assist circuit |
| WO2021212393A1 (en) * | 2020-04-23 | 2021-10-28 | 华为技术有限公司 | Low-leakage memory array |
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Application publication date: 20140122 |