JP5224040B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor memory integrated circuit that stores information used by a processor that performs frequency / voltage control. More specifically, the present invention relates to a semiconductor integrated circuit device in which a processor and a semiconductor memory are integrated on the same semiconductor chip to constitute a system on chip (SoC).

  Miniaturization of LSIs (Large Scale Integrated Circuits) has been promoted for the purpose of reducing power consumption, speeding up processing operations, and reducing the size of the entire apparatus. As such miniaturization progresses, the influence of variations in manufacturing parameters on transistor characteristics has increased. For this reason, due to the influence of parameter variations such as impurity fluctuations in the manufacturing process, it is necessary to design an LSI in consideration of local variations in addition to global variations in transistor characteristics.

  In particular, in a system LSI (SoC: system on chip) whose size is most advanced, logic (processor) and SRAM (static random access memory) are integrated on the same semiconductor chip. The transistor element is miniaturized according to the scaling law. Therefore, the SRAM cell transistor is most sensitive to the influence of the variation in threshold voltage due to the miniaturization, and the so-called “static noise margin (SNM)” is sufficiently secured. It is becoming difficult. That is, it is necessary to secure a threshold voltage range that operates stably even with respect to variations in threshold voltage, and this causes one limit to miniaturization. Patent Document 1 (Japanese Patent Laid-Open No. 2005-260260) is a configuration that ensures a static noise margin and stably performs data writing / reading even if the threshold voltage varies when the memory cell is miniaturized. 2005-38557), Patent Document 2 (Japanese Patent Laid-Open No. 2005-129109), and Patent Document 3 (Japanese Patent Laid-Open No. 2007-66493).

  In Patent Document 1, an SRAM cell is configured with thin film transistors, and the voltage amplitude of the word line is driven with an amplitude different from the logic amplitude of the memory cell. Even when the threshold voltage variation of the thin film transistor is large, the word line voltage is set to a voltage level different from the memory cell power supply voltage to increase the write or read margin.

  In the configuration of the SRAM shown in Patent Document 2, the voltage level of the selected word line is set higher than the power supply voltage of the memory cell during data writing. Even under a low power supply voltage, the write margin is expanded to stably write data.

  In the SRAM configuration disclosed in Patent Document 3, the voltage level of the selected word line is adjusted in conjunction with the fluctuation of the threshold voltage of the transistor of the memory cell, and data can be stably written even under a low power supply voltage. Try to read / write.

Further, in order to reduce power consumption in SoC, a configuration that performs frequency / voltage control (FV control) for controlling frequency and voltage according to processing contents is described in Non-Patent Document 1 (Toyama et al., “CPU power consumption reduction”). Application of Frequency-Voltage Coordinated Power Control Method for Power Supply by Design Rule and Feedback Prediction Method ”, IEICE Transactions, DI, Vol. J87-D-I, No. 4, pp 452-461, 2004 April). In the configuration shown in Non-Patent Document 1, a moving picture decoder is used as a processor, and the operating frequency and power supply voltage of the decoder are adjusted according to the amount of moving picture motion.
JP 2005-38557 A JP 2005-129109 A JP 2007-66493 A Toyama et al., “Application of Frequency-Voltage Coordinated Power Control Method for CPU Power Consumption Reduction Using Design Rules and Feedback Prediction Method”, IEICE Transactions, DI, Vol. J87-DI, No. 4, pp452-461 April 2004

  In the configuration disclosed in Patent Document 1, the read margin (static noise margin) and the write margin are improved by switching the voltage amplitude of the word line in the read mode and the write mode for reading and writing data. I will try. Specifically, in order to improve the write margin of the SRAM cell, the selected word line voltage is set higher than the internal cell power supply voltage. In order to improve the margin at the time of reading, the voltage of the selected word line is set to a level lower than the cell power supply voltage.

  In the configuration shown in Patent Document 1, a level shift circuit is provided for each word line driver provided for a word line. The voltage of the selected word line is changed by adjusting the voltage of the word line by the level shift circuit for each word line. Therefore, although the amplitude of the voltage of the selected word line is changed and the write / read margin of the memory cell is improved, the memory cell power supply voltage is consumed, so that the power consumption cannot be reduced. In addition, a level shift circuit is provided for each word line driver, which increases the layout area of the word line driver section and becomes an obstacle to chip size reduction. The power supply voltage of the memory is constant regardless of the operation mode.

  In the configuration disclosed in Patent Document 2, the voltage of the selected word line is set higher than the memory cell power supply voltage during the write operation, thereby increasing the write margin. However, in this case, the read margin (static noise margin) deteriorates. When the miniaturization of a memory transistor advances and the variation in threshold voltage becomes large, there arises a problem that data cannot be stably held under a low power supply voltage. In Patent Document 2, a configuration that stably maintains the data retention characteristic even when a miniaturized transistor is used is not considered.

  Patent Document 3 uses a transistor having the same structure as a memory cell as a voltage drop element to adjust the voltage level of a selected word line. In this configuration, even if the threshold voltage of the memory cell transistor varies, the voltage level of the selected word line is also adjusted in accordance with the variation in the threshold voltage. A read margin (static noise margin) is ensured by making the voltage of the selected word line lower than the memory cell power supply voltage. That is, the voltage level of the selected word line is pulled down using a transistor having the same characteristics as the memory cell transistor, and the voltage amplitude of the selected word line is made smaller than the cell power supply voltage. Therefore, in the memory cell, the power supply voltage of the memory cell is consumed, resulting in a problem that the power consumption cannot be sufficiently reduced. Further, the memory power supply voltage is maintained at a constant voltage level regardless of the operation mode.

  In Non-Patent Document 1, a moving picture processing time is monitored for an MPEG (Motion Picture Experts Group) decoder, and FV control is performed according to the monitoring result. That is, when there is a margin in the processing time, the frequency and the power supply voltage are reduced, and when the margin for the processing time is small, the frequency and the power supply voltage are increased. However, in the case of the configuration of Non-Patent Document 1, when an SRAM is used as a working memory, when the system power supply voltage level is adjusted according to the processing content, the level change of the memory power supply voltage applied to the SRAM changes. No consideration is given to the influence on the data retention characteristics of the SRAM cell.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory suitable for mounting on a SoC (system on chip) capable of stably writing / reading data with low power consumption, and the semiconductor memory. An object of the present invention is to provide a built-in semiconductor integrated circuit device.

  In one aspect, the semiconductor integrated circuit device according to the present invention adjusts the voltage level of a selected word line of a static memory cell in accordance with a control signal supplied from a processor that performs frequency / voltage control.

  In another aspect, the semiconductor integrated circuit device according to the present invention changes the level of the power supply voltage according to the operation mode, and adjusts the level of the voltage transmitted to the selected word line according to the level of the power supply voltage.

  In one embodiment, a semiconductor integrated circuit device according to the present invention has a processor in which an operation cycle is defined by a clock signal and the frequency of the clock signal and the level of the power supply voltage are adjusted according to the processing situation, and at least the processor And a semiconductor memory for storing information used by the computer. The semiconductor memory includes a plurality of static memory cells arranged in a matrix, a plurality of word lines arranged corresponding to each memory cell row, each of which is connected to a memory cell in a corresponding row, and an address signal And a row selection drive circuit for driving a word line arranged corresponding to the addressed row to a selected state. The row selection drive circuit includes a word line voltage adjustment circuit that adjusts the level of the selection voltage transmitted to the selected row in accordance with the frequency of the clock signal of the processor and the level of the power supply voltage.

  FV control is performed in the processor, and the power consumption of the semiconductor memory (SRAM in one embodiment) is reduced according to the FV control. In this case, if the read margin (static noise margin) deteriorates due to the memory power supply voltage level due to variations in the threshold voltage of the memory cell, the voltage level of the word line is adjusted. As a result, deterioration of the static noise margin due to variations in the threshold voltage of the memory cell can be suppressed, and data can be stably retained, written and read.

[Embodiment 1]
FIG. 1 schematically shows an entire configuration of a system LSI according to the present invention. 1, a system LSI including a semiconductor integrated circuit device (semiconductor memory) according to the present invention includes a processor 1 and a semiconductor memory 2 for storing information (data and instructions) used by the processor 1. The processor 1 receives the logic power supply voltage VDDL from the power supply node 3 as an operation power supply voltage, and executes various processes. The processor 1 also has an FV control (frequency / voltage control) function, and controls the operating frequency and the level of the operating power supply voltage VDDL according to the processing content / processing status. The processor 1 and the semiconductor memory 2 are preferably integrated on the same semiconductor chip to constitute the SoC, but they may be formed on separate semiconductor chips.

  Semiconductor memory (semiconductor integrated circuit device) 2 is an SRAM (Static Random Access Memory), and receives memory power supply voltage VDDM from power supply node 4 as an operation power supply voltage. Power supply voltages VDDL and VDDM respectively applied to power supply nodes 3 and 4 may be voltages supplied from a common power supply node, or may be voltages supplied via different power supply nodes. The logic power supply voltage VDDL and the memory power supply voltage VDDM may be the same voltage level, or the voltage levels may be different.

  The processor 1 supplies a control signal group CTL and an address signal ADD to the semiconductor memory 2 at the time of processing execution, and information (data or instruction: hereinafter simply referred to as data) with the addressed memory cell of the semiconductor memory 2. Access DATA.

  The processor 1 also adjusts the logic level of the word line voltage control signal WVCON of the semiconductor memory 2 according to the execution status of the FV control. In accordance with word line voltage control signal WVCON, in semiconductor memory 2, the voltage level transmitted to the selected word line is adjusted, as will be described later. In this system LSI, current consumption is reduced by performing FV control. Further, by adjusting the selected word line voltage level in the semiconductor memory 2 in accordance with the memory power supply voltage level at the time of execution of the FV control, data is accessed in the semiconductor memory 2 without deteriorating data retention characteristics.

  FIG. 2 schematically shows a configuration of a main part of semiconductor memory 2 shown in FIG. 2, semiconductor memory 2 includes a memory array 10 in which memory cells MC are arranged in a matrix, and a word line decoder 11 and a word line drive circuit 12 for selecting a memory cell row of the memory array 10.

  In memory array 10, word lines WL are arranged corresponding to the respective rows of memory cells MC, and bit lines BL and / BL are arranged corresponding to the respective columns of memory cells MC. FIG. 2 representatively shows one memory cell MC. The memory cell MC is an SRAM cell as will be described in detail later.

  The word line decoder 11 decodes the word line address ADX included in the address signal ADD from the processor 1 and generates a row selection signal for designating the addressed row of the memory array 10. Word line drive circuit 12 includes a word line driver provided corresponding to each word line, and drives word line WL corresponding to the addressed row to a selected state in accordance with a word line selection signal from word line decoder 11. To do.

  The word line drive circuit 12 is provided with a word line power supply control circuit 13 and a word line power supply circuit 14 for adjusting the voltage level transmitted to the selected word line. The word line power supply control circuit 13 adjusts the voltage level of the word line voltage WVCC supplied by the word line power supply circuit 14 in accordance with the word line voltage control signal WVCON including the chip mode instruction signal CS from the processor 1. When the FV control is executed, the processor 1 increases the frequency F and the voltage V and executes high-speed processing when the amount of processing is large. In this case, the word line power supply control circuit 13 generates a control signal for lowering the voltage level of the word line selection voltage WVCC generated by the word line circuit 14 in accordance with the word line voltage control signal WVCON.

  Semiconductor memory 2 further selects a bit line decoder 15 that decodes bit line address ADY included in address signal ADD from processor 1, and selects a memory cell column of memory array 10 in accordance with a column selection signal from bit line decoder 15. Column selection circuit 16 and a write / read circuit 17 for writing / reading data to / from the memory cell column selected by column selection circuit 16 are included.

  Bit line decoder 15 decodes bit line address ADY, and generates a column selection signal designating a bit line corresponding to the selected column according to the decoding result.

  Column selection circuit 16 includes a bit line selection gate provided corresponding to each pair of bit lines BL and / BL, and bit lines BL and / BL corresponding to the selected column according to a column selection signal from bit line decoder 15. Are coupled to write / read circuit 17 through a corresponding bit line select gate.

  Write / read circuit 17 generates internal write data in accordance with external write data DQ at the time of data writing, and sets the voltage levels of bit lines BL and / BL of the selected column via column select circuit 16. Then, it is driven to a voltage level corresponding to the write data. Write / read circuit 17 also differentially amplifies the potentials of bit lines BL and / BL in the selected column to detect stored data in the memory cell and generate internal read data at the time of data reading. External read data DQ is generated and output according to the data.

  In order to control the internal operation of the semiconductor memory 2, a main control circuit 18 is provided. The main control circuit 18 generates control signals necessary for internal operations in accordance with the control signal group CTL from the processor 1. This control signal group CTL includes a chip enable signal CE and a write enable signal WE as an example. The chip enable signal CE indicates that the semiconductor memory is selected and data access is performed. A chip mode instruction signal CS included in the word line voltage control signal indicates whether the operation mode of the semiconductor memory 2 is a low-speed normal operation mode or a higher-speed operation mode than the normal mode.

  FIG. 3 is a diagram showing an example of the configuration of the memory cell MC included in the memory array 10 shown in FIG. In FIG. 3, memory cell MC includes two P-channel MOS transistors (insulated gate field effect transistors) PQ1 and PQ2, and four N-channel MOS transistors NQ1-NQ4. MOS transistors PQ1 and NQ1 constitute one CMOS (complementary MOS) inverter, and MOS transistors PQ2 and NQ2 constitute another CMOS inverter. These MOS transistors PQ1, PQ2, NQ1, and NQ2 constitute an inverter latch, and complementary data is held in storage nodes SN and / SN. Memory power supply voltage VDDM is supplied to the source nodes (cell power supply nodes) of load MOS transistors PQ1 and PQ2.

  MOS transistors NQ3 and NQ4 are selectively turned on in response to the signal potential on word line WL, respectively, and when turned on, couple storage nodes SN and / SN to bit lines BL and / BL, respectively.

  The memory cell MC shown in FIG. 3 is an SRAM cell composed of six transistors. In this SRAM cell, an index called a static noise margin SNM representing data retention characteristics (data reading stability) is defined. This static noise margin SNM is the size of a region surrounded by the input / output transfer characteristic curves of two inverters composed of MOS transistors PQ1, PQ2, NQ1, and NQ2 (inscribed circle diameter or inscribed square one side or diagonal line) Length). When the static noise margin SNM is large, the memory cell MC stably retains data, and when the static noise margin SNM becomes small, the retained data is easily inverted and destroyed. Therefore, it is necessary to secure a static noise margin in order to stably hold data.

  Normally, in memory cell MC, the operable range of memory cell MC is determined by threshold voltage Vthn of the N-channel MOS transistor and absolute value Vthp of the threshold voltage of the P-channel MOS transistor.

  FIG. 4 is a diagram showing the relationship between the threshold voltage of the SRAM cell transistor and the operable range. In FIG. 4, the horizontal axis represents the threshold voltage Vthn of the N channel MOS transistor, and the vertical axis represents the absolute value Vthp of the threshold voltage of the P channel MOS transistor of the memory cell. Hereinafter, for the sake of simplicity, the absolute value Vthp of the threshold voltage is simply referred to as the threshold voltage Vthp, unless there is a possibility of misunderstanding.

  In the operating characteristics of the memory cell, the upper limit values VThnh and Vthph of the threshold voltages Vthn and Vthp are determined from the target operating speed. Therefore, the point A indicates a target operating speed limit point. In a region having a threshold voltage higher than this point A, the on-current of the memory cell transistor becomes small, and data cannot be written at high speed.

  Further, in order to determine the upper limit value of the leakage current of the memory cell, lower limit values Vthnl and Vthpl of threshold voltages Vthn and Vthp are determined. Therefore, the point B indicates a leak current limit point. In the region of the threshold voltage lower than point B, the leakage current of the memory cell transistor becomes large, and the current consumption requirement in the standby state is not satisfied.

  Further, a static noise margin limit line L1 is determined in order to secure the static noise margin SNM during data reading. In the region above the static noise margin limit line L1, the static noise margin SNM is not held, data inversion occurs, and nondestructive reading cannot be performed.

  Further, a write limit line L2 for inverting the storage data of the memory cell MC is determined. In the region below the write limit line L2, the data held in the memory cell MC is not inverted, and data cannot be written. A region between the limit lines L1 and L2 and within the range of the limit points A and B is an operable range (indicated by a one-point diagonal line in FIG. 4).

  In this region, the manufacturing control region II is usually set in order to operate stably over the entire level of the power supply voltage used (the threshold voltage range of the memory cell transistor takes into account variations in the threshold voltage). Designed).

  In the memory cell MC, when the power supply voltage VDDM increases, the transfer characteristic curve of the inverter of the memory cell becomes steep, the static noise margin decreases, and the static noise margin limit line L1 moves downward in FIG. The processor 1 (see FIG. 1) performs FV control, and when the amount of processing information is large and it is necessary to perform processing at high speed, the frequency F and the power supply voltage V are increased. Therefore, when the manufacturing management area II is set according to the power supply voltage level in the normal operation mode, when the power supply voltage is increased in the FV control mode in the high-speed operation in FIG. 4, as shown by the straight line L3, The static noise margin limit line crosses the manufacturing management area II, and data cannot be held stably. In this case, it is conceivable to set the manufacturing control region II from the beginning so that the power supply voltage during high-speed operation can be stably operated. However, in this case, the area of the manufacturing management region II is reduced, and it is impossible to cope with threshold voltage variations, the manufacturing process management becomes complicated, and the manufacturing margin decreases.

  Therefore, in the first embodiment of the present invention, even when the processor 1 operates at high speed and the power supply voltages VDDL and VDDM are increased in level, the processor 1 is transmitted to the selected word line for stable operation. Reduce the voltage level.

  When the memory power supply voltage VDDM is increased in the high-speed operation mode, the selection voltage level of the word line WL is lowered with respect to the memory power supply voltage VDDM. In this case, the conductances of N channel MOS transistors NQ3 and NQ4 for accessing memory cell MC shown in FIG. 3 are lowered, and become smaller than the conductances of driver N channel MOS transistors NQ1 and NQ2. Therefore, the β ratio normally defined in the SRAM cell can be increased equivalently, and the static noise margin SNM can be improved. Thus, even when the memory power supply voltage VDDM is set higher than the power supply voltage level during normal processing during high-speed operation, the static noise margin SNM is improved and data retention is performed stably.

  FIG. 5 shows an example of the configuration of the word line power supply circuit and word line drive circuit 12 shown in FIG. FIG. 5 also shows the configuration of the memory cell MC.

  5, word line drive circuit 12 includes word line drivers WD0-WDn provided corresponding to word lines WL0-WLn, respectively. Each of these word line drivers WD0 to WDn has the same CMOS inverter configuration, and includes P channel MOS transistor PT and N channel MOS transistor NT. In each of word line drivers WD0 to WDn, P channel MOS transistor PT and N channel MOS transistor NT are complementarily conducted in accordance with a decode signal from word line decoder 11 shown in FIG. P channel MOS transistor PT transmits word line selection voltage WVDD on driver power supply line 20 to corresponding word line WLi (i = 0-n) when conductive, and N channel MOS transistor NT responds when conductive. The ground voltage is transmitted to the word line WLi.

  Word line power supply circuit 14 includes P channel MOS transistor PQ10 connected between the power supply node and driver power supply line 24, and P channel MOS transistors PQ11 and PQ12 connected in parallel between driver power supply line 20 and the ground node. Including. These MOS transistors PQ10 to PQ12 conduct when control signals EN1, EN2 and EN3 are activated (at L level), respectively.

  MOS transistors PQ11 and PQ12 have the same threshold voltage (Vth) characteristics as load MOS transistors PQ1 and PQ2 included in memory cell MC, and the threshold voltages of load transistors PQ1 and PQ2 in memory cell MC The variation is reflected in the threshold voltages of the MOS transistors PQ11 and PQ12 in the word line power supply circuit 14. Accordingly, the voltage level of word line selection voltage WVDD is adjusted according to the variation in threshold voltage of load transistors PQ1 and PQ2 of memory cell MC. For example, MOS transistors PQ11 and PQ12 are formed in the same manufacturing process as load MOS transistors PQ1 and PQ2 of memory cell MC.

  That is, when threshold voltages Vthp of P channel MOS transistors PQ1 and PQ2 of the memory cell are increased, the threshold voltages of MOS transistors PQ11 and PQ12 are also increased. Accordingly, the voltage level of the word line selection voltage WVDD increases (the amount of voltage drop decreases). On the other hand, when the threshold voltages of MOS transistors PQ1 and PQ2 of the memory cell are lowered, the threshold voltages of MOS transistors PQ11 and PQ12 are also lowered, and the voltage level of word line selection voltage WVDD is lowered (dropped). The amount increases). As a result, it is not necessary to change the word line voltage more than necessary, it is possible to prevent the field where the word line voltage drop amount becomes too large and the write margin is lowered, and the deterioration of the write margin is suppressed and static. A noise margin can be secured.

  Since word line power supply circuit 14 supplies word line selection voltage WVDD to word line drivers WD0 to WDn, the current supply capability of MOS transistor PQ10 is made sufficiently larger than MOS transistors PQ1 and PQ2 of memory cell MC. . Similarly, the current driving capabilities of MOS transistors PT and NT of word line drivers WD0 to WDn are sufficiently increased to charge and discharge the word lines at high speed.

  FIG. 6 is a timing chart showing operations of word line power supply circuit 14 and word line drive circuit 12 shown in FIG. The operation of the configuration shown in FIG. 5 will be described below with reference to FIG.

  In the normal mode, that is, when the memory power supply voltage VDD is set to the voltage level of the voltage V1 and is operating in the entire manufacturing management region II below the SNM limit line L1 shown in FIG. 4, the control signals EN1 and EN2 are at the L level. The control signal EN3 is set to H level. When accessing the semiconductor memory, the word line voltage enable signal VDDEN is at the H level, and the word line power supply circuit 14 is in the enabled state (the MOS transistor NQ10 is in the on state).

  In this state, MOS transistors PQ10 and PQ11 are turned on and MOS transistor PQ12 is turned off by control signals EN1 and EN2. Therefore, the voltage level of word line selection voltage WVDD on driver power supply line 20 is set to a voltage level determined by the ON resistances of MOS transistors PQ10 and PQ11. The current driving capability (conductance) of the current supply MOS transistor PQ10 is set sufficiently larger than the current driving capability of the MOS transistor PQ11, and the voltage level of the word line selection voltage WVDD is substantially the same as the voltage V1 of the memory power supply voltage VDDM. Voltage level.

  On the other hand, when the amount of processing information is large and data processing is performed at high speed, the high-performance mode is set as the special mode. In this high-performance mode, control signals EN1, EN2, and EN3 are all set to L level, and in MOS transistor PQ10-PQ12 are all turned on in word line power supply circuit 14.

  In this state, MOS transistors PQ11 and PQ12 are connected in parallel to driver power supply line 20, driver power supply line 20 is discharged via MOS transistor NQ10, and the voltage level of word line selection voltage WVDD on driver power supply line 20 However, it is lower than that in the normal mode. In this case, a resistance voltage dividing circuit is constituted by the on-resistance of MOS transistor PQ10 and the parallel on-resistances of MOS transistors PQ11 and PQ12. Therefore, the voltage drop amount ΔV of the word line selection voltage WVDD of the driver power supply line 20 becomes larger than when one MOS transistor PQ11 is connected to the driver power supply line 20. In FIG. 6, two types of voltage drop amounts ΔV1 and ΔV2 are representatively shown as the voltage drop amount ΔV. ΔV1 or ΔV2 is used depending on the voltage level of the memory power supply voltage VDDM.

  The drop amount ΔV1 or ΔV2 of the word line selection voltage in the high-performance mode with respect to the memory power supply voltage VDDM is set to an appropriate value according to the operating characteristics of the memory cell. For example, when the voltage V1 in the normal mode of the memory power supply voltage VDDM is about 1.2V, the word line selection voltage WVDD is set to about 1.1V. On the other hand, in the high-performance mode, when the voltage level V2 of the memory power supply voltage VDDM is set to about 1.5V, the word line selection voltage WVDD is set to a voltage level of about 1.3V.

  In the high performance mode, the voltage level of the selected word line WL is further lower than the memory power supply voltage VDDM. In memory cell MC, the conductances of access transistors NQ3 and NQ4 are smaller than the conductances of load MOS transistors PQ1 and PQ2 and driver MOS transistors NQ1 and NQ2 as compared with those in the normal mode. Correspondingly, the β ratio becomes equivalently small, data inversion hardly occurs, and the static noise margin SNM is improved.

  In this way, even if the memory power supply voltage VDDM is increased and the state of the SNM limit line L3 shown in FIG. 4 occurs, the limit line can be equivalently shifted in the direction of the SNM limit line L1. Become. As a result, data can be stably read from and written to the memory cells in manufacturing management region II.

  In a low power consumption mode such as a standby mode (sleep mode), the control signal EN1 is set to H level. At this time, the word line voltage enable signal WVDDEN is also set to the L level. In response, the word line power supply circuit 14 enters an output high impedance state. In word line drivers WD0 to WDn, MOS transistor PT is set to an off state. Therefore, the driver power supply line 20 is in a high impedance state, and the voltage level is discharged by the leak current, and the voltage level is lowered to a voltage level substantially close to the ground voltage level.

  As described above, the word line power supply circuit 14 is used to adjust the level of the word line selection voltage in accordance with the voltage levels of the power supply voltages VDDL and VDDM during the FV control of the processor. Therefore, it is possible to construct a processing system that operates with low power consumption by FV control. Further, the semiconductor memory (SRAM) has the word line voltage level lower than the memory power supply voltage even in the high-performance mode. Accordingly, the influence of threshold voltage variation is suppressed, the static noise margin SNM is improved, and data can be held stably. As a result, it is possible to realize an SRAM that operates stably even during FV control using a miniaturized memory cell.

  By adjusting the voltage level of the word line selection voltage WVDD output from the word line power supply circuit 14, it is not necessary to provide a voltage adjusting element for each word line driver, and an increase in the memory layout area is suppressed.

  FIG. 7 is a diagram showing an example of the configuration of the word line power supply control circuit 13 shown in FIG. In FIG. 7, an external chip enable signal CEEX #, an external resume standby instruction signal RSEX, and an external chip mode instruction signal CSEX are externally applied to the word line power supply control circuit 13 as a word line voltage control signal WVCON.

  Word line power supply control circuit 13 includes an inverter IV1 receiving external chip enable signal CEEX #, a buffer circuit BF1 receiving external resume standby instruction signal RSEX, and a NAND gate NG1- selectively enabled according to the output signal of inverter IV1. Includes NG3.

  The buffer circuit BF1 is composed of two stages of cascaded inverters. Resume standby instruction signal RSEX is set to H level when activated, and interrupts the processing of this semiconductor memory (SRAM). For example, when a moving picture application is executed on a mobile phone, the external resume standby instruction signal RSEX is activated when the application is interrupted to make a call. Alternatively, when an operation such as folding the mobile phone (or closing the lid in the laptop computer) is performed after the video application is completed, the button is pressed and the resume standby instruction signal RSEX is activated. .

  External chip enable signal CEEX # is activated when this semiconductor memory is accessed, and is set to the L level.

  NAND gate NG1 receives the output signal of inverter IV1 and the output signal of buffer BF1, and generates control signal EN1. NAND gate NG2 receives memory power supply voltage VDDM and the output signal of inverter IV1, and generates control signal EN2. NAND gate NG3 receives external chip mode instruction signal CSEX and the output signal of inverter IV1, and generates control signal EN3.

  The word line power supply control circuit 13 further receives the internal clock signal CLKIN from the internal clock generation circuit 22 included in the main control circuit 18 and the output signal of the inverter IV1, and receives a word line voltage enable signal having a predetermined time width. A pulse generation circuit 21 for generating VDDEN is included.

  An internal clock generation circuit 22 included in the main control circuit 18 generates an internal clock signal CLKIN having a predetermined pulse width in accordance with an external clock signal CLKEX. The internal operation cycle and internal operation timing of the semiconductor memory are defined according to the internal clock signal CLKIN.

  FIG. 8 is a timing chart showing the operation of the word line power supply control circuit 13 shown in FIG. The operation of the word line power supply control circuit 13 shown in FIG. 7 will be described below with reference to FIG.

  The external clock signal CLKEX defines the operation cycle of the processor and the semiconductor memory. Internal clock generation circuit 22 generates internal clock signal CLKIN having a predetermined pulse width in accordance with external clock signal CLKEX from the outside. The internal clock signal CLKIN from the internal clock generation circuit 22 is a clock signal synchronized with the external clock signal, but its pulse width is constant. Thereby, the influence of the jitter of the external clock signal CLKEX is suppressed, a stable internal operation cycle defining signal is generated, and the internal operation cycle and the internal operation timing are stabilized.

  When the semiconductor memory (SRAM) is accessed, external chip enable signal CEEX # is at the active L level, and NAND gates NG1-NG3 and pulse generation circuit 21 are enabled. At the time of accessing the semiconductor memory, the resume standby instruction signal RSEX is at the inactive state of H level. Since resume resume instruction signal RSEX from the outside is at the H level, when external chip enable signal CEEX # is set at the L level, control signal EN1 from NAND gate NG1 is set at the L level. In response, the word line power supply circuit 14 is enabled to supply current to the driver power supply line 20.

  NAND gate NG2 maintains control signal EN2 at the L level according to memory power supply voltage VDDM in both the normal mode and the high performance mode.

  When the operation mode of the semiconductor memory is the high-performance mode, the external chip mode instruction signal CSEX is at the H level, and when in the normal mode, the external chip mode instruction signal CSEX is at the L level. Therefore, when accessing the semiconductor memory, the control signal EN3 is at the H level in the normal mode and at the L level in the high performance mode.

  Pulse generation circuit 21 generates, as word line voltage enable signal VDDEN, a one-shot pulse signal that rises in synchronization with the rise of internal clock signal CLKIN and falls slightly later than the fall. When the clock signal CLKIN is generated, when the chip enable signal CEEX # is activated, a word line activation signal (not shown) is activated in the main control circuit 18 in accordance with the external address signal ADD and the internal clock signal CLKIN. The designated word line WL is driven to the selected state. Before the word line WL is selected, the word line voltage enable signal VDDEN is activated. As described above, the word line power supply circuit (14) operates the word line selection voltage WVDD according to the high performance mode and the normal mode. The word line selection voltage WVDD having a voltage level corresponding to the operation mode is generated from the memory power supply voltage VDDM.

  When a word line activation signal (not shown) is deactivated, the word line WL is driven to a non-selected state. After the word line WL is deactivated, the word line voltage enable signal VDDEN from the pulse generation circuit 21 is driven to an inactive state. Accordingly, the discharge path of the word line power supply circuit (14) is cut off, and the word line selection voltage WVDD on the driver power supply line (20) is restored to the memory power supply voltage VDDM level by the MOS transistor PQ10 shown in FIG.

  Thereafter, the internal clock signal CLKIN is generated in synchronization with the rising edge of the external clock signal CLKEX, and the following operation is executed within a cycle defined by the internal clock signal CLKIN. The word line voltage enable signal VDDEN is activated. In accordance with the activation of the word line voltage enable signal VDDEN, the voltage level of the word line selection voltage WVDD is set to a voltage level corresponding to the operation mode. When the word line selection voltage WVDD is stabilized, a word line activation signal (not shown) is driven to a selected state at a predetermined timing, and the word line WL is driven to the selected state. When the word line WL is driven to a non-selected state after a predetermined period of time, the word line voltage enable signal VDDEN from the pulse generation circuit 21 is deactivated, and the word line selection voltage WVDD is changed to the original memory power supply. Return to voltage VDDM level. This operation is repeated every clock cycle (during the active state of external chip enable signal CEEX #).

  When external chip enable signal CEEX # is deactivated and becomes H level, the output signal of inverter IV1 becomes L level, and all of control signals EN1-EN3 become H level. Further, the word line voltage enable signal VDDEN from the pulse generation circuit 21 is maintained at the inactive L level. Thereby, the word line power supply circuit (14) is maintained in the output high impedance state.

  If the resume standby instruction signal RSEX is activated and the low power consumption mode is designated when the chip enable signal CEEX # is at the H level, the control signal EN1 is driven to the H level. At this time, the operation of generating the internal clock signal CLKIN of the internal clock generation circuit 22 is stopped, and the word line voltage enable signal VDDEN from the pulse generation circuit 21 is also maintained in the inactive state (L level). Therefore, the word line power supply circuit (14) is maintained in the output high impedance state regardless of the states of the control signals EN2 and EN3. In this state, the so-called sleep mode is designated, and the internal operation of the semiconductor memory is stopped, and the power consumption of the semiconductor memory is reduced.

  In the configuration shown in FIG. 7, a resume standby instruction signal RSEX is given to the internal clock generation circuit 22. However, instead of supplying the resume standby instruction signal to the internal clock generation circuit 22, the following configuration may be used. That is, when the resume standby instruction signal RSEX is activated, the processor stops supplying the external clock signal CLKEX to the semiconductor memory, and accordingly the generation of the internal clock signal CLKIN from the internal clock generation circuit 22 is stopped.

  The pulse generation circuit 21 is configured to generate a one-shot pulse signal that is maintained at the H level during the word selection period according to the internal clock signal CLKIN when the output signal of the inverter IV1 is at the H level. I just need it.

  FIG. 9 is a flowchart showing a sequence for performing voltage control on the semiconductor memory of the processor shown in FIG. Hereinafter, the word line voltage control sequence for the semiconductor memory from the processor will be described with reference to FIG.

  The processor 1 does not show its internal configuration, but an instruction / data memory (cache memory) and a controller (access to the instruction / data memory to exchange necessary information and execute predetermined processing ( CPU core). The controller executes various designated processes in accordance with external instructions.

  First, the processor (1) determines whether an instruction to start processing is given (step S1). This process start determination is performed by checking whether a process start instruction from an external operator is given (for example, by pressing an operation button).

  When the process start is designated, it is next determined whether or not the process content can be processed in the normal mode (step S2). The determination as to whether or not the processing is performed in the normal mode is performed as follows as an example. When a processing start instruction is given, it is performed by taking a program (or application) to be processed and looking at the contents (header information etc.) of the application, or at the time of processing start instruction, the type of processing ( Moving image processing or audio processing) is performed by pressing an operation button, and the type of the operation button is identified to identify the processing content. For example, when the processing target is audio processing, the normal mode is designated, and when performing moving image (game etc.) processing, the high performance mode is designated.

  When the normal mode is designated, the processor sets the chip mode instruction signal CSEX for the semiconductor memory to the L level (step S3). On the other hand, if the processing content is the content for high-performance mode de-processing, the processor sets the chip mode instruction signal CSEX for the semiconductor memory to the H level (step S4).

  When the logic level of the chip mode instruction signal CSEX is set and the word line selection voltage of the semiconductor memory is set, the processor executes the designated processing and executes the access to the semiconductor memory in parallel. (Step S5).

  During execution of this process, it is determined whether an instruction to interrupt the process has been given (step S6) or an instruction to end this process has been given (step S11). The process interruption instruction is given, for example, by an operation such as an interruption operation button from the operator or when a predetermined interrupt instruction is generated.

  In step S6, when a processing interruption instruction is given, the processor asserts the resume standby instruction signal RSEX and sets it to the H level (step S7). After the resume standby instruction signal RSEX is asserted, it is next determined whether or not the processor is instructed to resume processing (step S8). Whether or not the process can be resumed is determined by monitoring whether or not the operation giving the process interruption instruction is avoided (step S8).

  On the other hand, when the process resumption instruction has not been given yet in step S8, it is next determined whether or not the operator has given an instruction to end the suspended process (step S9).

  If this process end instruction is not given, the process returns to the process resuming step S8 and waits for the resumption instruction to be given. On the other hand, if a process end instruction is given by an operator's operation in step S9, the process proceeds to step S12, a predetermined end process is executed, and this process ends.

  On the other hand, when a process restart instruction is given in step S8, the interrupted process is restarted (step S10). After the necessary restart process is performed, the process from step S5 is executed again.

  In step S11, when the end of the process is instructed by an operation such as pressing an operator's button during the execution of the process, the process moves to step S12, the necessary end process is executed, and the series of processes is completed.

  Therefore, when the processor gives a processing instruction from the operator, FV control is executed in accordance with the processing content. In accordance with the FV control, a control signal for controlling the word line voltage for the semiconductor memory is generated. Thereby, the processor operates with power consumption corresponding to the processing, and the semiconductor memory can hold data stably. Thereby, a processing system with low power consumption can be realized.

[Example of change]
FIG. 10 shows a structure of a modification of word line power supply circuit 14 of the semiconductor memory according to the first embodiment of the present invention. In word line power supply circuit 14, N channel MOS transistors NQ11 and NQ12 are connected in parallel with each other between driver power supply line 20 and MOS transistor NQ10. These MOS transistors NQ11 and NQ12 receive control signals EN2Z and EN3Z complementary to the previous control signals EN2 and EN3, respectively, and selectively conduct.

  N channel MOS transistors NQ11 and NQ12 have the same threshold voltage characteristics (Vth characteristics) as N channel MOS transistors (NQ1-NQ4) included in the memory cell. These MOS transistors NQ11 and NQ12 can have the same threshold voltage Vth characteristics by being formed in the same manufacturing process as the N channel MOS transistors (NQ1-NQ4) of the memory cell. As a result, as in the case where the PMOS transistors PQ11 and PQ12 are used and sold, the influence of the variation in the threshold voltage of the memory cell transistors (NQ1-NQ4) can be reflected on the voltage level of the word line selection voltage WVDD.

  That is, when the threshold voltage of N channel MOS transistors NQ1-NQ4 of the memory cell increases, similarly, in this word line power supply circuit 14, the threshold voltages of MOS transistors NQ11 and NQ12 also increase. The voltage level of the selection voltage WVDD is increased. Conversely, when the threshold voltages of the MOS transistors NQ1-NQ4 of the memory cell are lowered, the threshold voltages of these MOS transistors NQ11 and NQ12 are also lowered, and the voltage level of the word line selection voltage WVDD is lowered. Let Thereby, it is not necessary to excessively lower the word line selection voltage WVDD even for threshold voltage variations of the memory cells, and a read margin (static noise margin SNM) is ensured without deteriorating the write margin. be able to.

  In the configuration of word line power supply circuit 14 shown in FIG. 10, control signals EN2Z and EN3Z are complementary to previous control signals EN2 and EN3, MOS transistor NQ11 is always on, and MOS transistor NQ12 is in normal operation. It is turned on in the mode and resume standby mode, and turned on in the high performance mode. Therefore, the same voltage control as that of the word line power supply circuit 14 shown in FIG. 5 can be realized.

  FIG. 11 is a diagram showing an example of a configuration of a processing system constituting the SoC incorporating the semiconductor memory according to the present invention. That is, FIG. 11 is a diagram showing a configuration of a specific application example of the semiconductor integrated circuit device shown in FIG.

  11, a semiconductor integrated circuit device 30 according to the present invention includes an application block 32 for processing an application program and a communication block 34 for voice / data communication. The application block 32 includes an application processor 40 that processes an application program, a local memory (semiconductor memory) 42 that stores a program and data output from the application processor 40, and a power supply voltage for the application processor 40 and the local memory 42. And a power supply controller 44 for supplying VDDL and VDDM, respectively.

  The power supply controller 44 adjusts the voltage level of the power supply voltage VDD supplied from the power supply unit 46 provided outside the device 30 to generate the logic power supply voltage VDDL and the memory power supply voltage VDDM. The application processor 40 and the local memory 42 correspond to the processor 1 and the semiconductor memory 2 shown in FIG. The application processor 40 has an FV control function, and sets the logic level of the word line voltage control signal WVCON for the local memory 42 according to the processing contents (for example, sound processing and image processing). The power supply controller 44 adjusts the voltage level of the power supply voltage VDD supplied from the power supply unit 46 in accordance with the power supply control signal VCON from the application processor 40. The power supply unit 46 generates a power supply voltage VDD from an external power supply voltage EXVDD and supplies it to the power supply controller 44. The power supply controller 44 or the power supply unit 46 may also include a block that generates various intermediate voltages (reference voltage or the like). A control signal is transmitted bi-directionally between the power supply unit 46 and the power supply controller 44, and a determination of the operation state (stabilization of the power supply voltage) in the power supply unit 46 and a voltage generation operation stop instruction from the power supply controller 44 are transmitted and received. Is done.

  The communication block 34 includes a baseband processor 50 that performs communication, and a local memory 52 that stores information (such as voice data / packet data) used by the baseband processor 50. Since the baseband processor 50 is not required to perform high-speed operation processing as much as the application processor 40, an FV control function is not particularly provided.

  By providing the local memories 42 and 52 for the application processor 40 and the baseband processor 50, the processing can be executed individually according to the processing. A large-capacity memory may be provided in common for these processors 40 and 50 as an external memory for storing application programs and mail data.

  In the power supply controller 44, a configuration in which the voltage level of the power supply voltage VDD supplied from the power supply unit 46 is adjusted according to the voltage control signal VCON according to each mode, for example, analog / This can be easily realized by using a resistor voltage divider such as a digital conversion circuit. The power supply controller 44 has a configuration of a feedback loop type step-down circuit (VDC) that compares the reference voltage and the internal power supply voltage and adjusts the internal power supply voltage level to the reference voltage level according to the comparison result. Also good. The voltage level of the reference voltage is updated according to the voltage control signal VCON, or the voltage level of the internal power supply voltage is changed and compared with the fixed reference voltage. The amount of change in the internal power supply voltage is adjusted according to the voltage control signal VCON. By utilizing these configurations, the power supply controller 44 can supply the power supply voltages VDDL and VDDM at the required voltage level according to the voltage control signal VCON from the application processor 40.

  The power supply control signal VCON is output from the application processor 40 in order to adjust the voltage level when executing the FV control.

  In the configuration shown in FIG. 11, the power supply controller 44 supplies the power supply voltage VDDL for the application processor 40 and the power supply voltage VDDM corresponding to the local memory 42 through different paths. However, the power supply controller 44 may supply the power supply voltages VDDL and VDDM to the application processor 40 and the local memory 42 via a common power supply line.

  In this semiconductor integrated circuit device 30, one application block 32 is arranged as a macro on the semiconductor chip, and a communication block 34 is arranged as one macro on the semiconductor chip, and as a whole, on one semiconductor chip. These application block 32 and communication block 34 are integrated. However, these application block 32 and communication block 34 may be formed on separate semiconductor chips.

  As described above, according to the first embodiment of the present invention, the voltage level transmitted to the word line of the semiconductor memory (SRAM) according to the operating speed of the processor having the FV control function and the voltage level of the operating power supply voltage. Is adjusting. Therefore, a static noise margin SNM can be sufficiently secured even during high-speed operation, and a processing system that operates stably with low current consumption power can be constructed using a miniaturized SRAM cell.

  In the above-described configuration, the voltage level of word line selection voltage WVDD is lower than the voltage level of memory power supply voltage VDDM in both the normal operation mode and the high performance mode. However, in the normal operation mode, only the MOS transistor PQ10 is turned on, the remaining transistors PQ11 and PQ12 or NQ11 and NQ12 are turned off, and the word line selection voltage WVDD is set to the voltage level of the memory power supply voltage VDDM. May be.

[Embodiment 2]
FIG. 12 schematically shows SNM limit lines of the memory cells of the semiconductor memory according to the second embodiment of the present invention. In the characteristics of the memory cell shown in FIG. 12, when the memory power supply voltage VDDM in the normal mode is the voltage V1, the SNM limit line L4 crosses the manufacturing management area II. Even when the memory power supply voltage VDDM in the high-performance mode is the voltage V2, the SNM limit line L5 crosses the manufacturing management area II. Even in such a case, the mobile phone 2 of the embodiment improves the manufacturing yield by ensuring a sufficient SNM in the normal and high-performance modes.

  FIG. 13 schematically shows the relationship between the word line selection voltage and the memory power supply voltage in the second embodiment of the present invention. In the normal mode, when the memory power supply voltage VDDM is the voltage V1, the word line selection voltage WVDD is lowered by the voltage ΔV1 and set to the voltage level of the voltage V1-ΔV1. On the other hand, in the high-performance mode, when the memory power supply voltage VDDM is the voltage V2, the word line selection voltage WVDD is lowered by the voltage ΔV2 and set to the voltage level of the voltage V2-ΔV2. In this case, V1-ΔV1 is at a higher voltage level than voltage V2-ΔV2. Further, ΔV1 <ΔV2. The voltage drop amounts ΔV1 and ΔV2 may be the same voltage level as the voltage drop amount in the high-performance mode shown in the first embodiment, or may be different voltage levels. Therefore, by securing the static noise margin SNM in the normal mode, the static noise margin SNM can be sufficiently secured even in the high-performance mode, and can be operated stably.

  FIG. 14 shows an exemplary configuration of word line power supply circuit 14 of the semiconductor memory according to the second embodiment of the present invention. The configuration of the word line power supply circuit shown in FIG. 14 differs from the configuration of the word line power supply circuit 14 shown in FIG. 5 in the following points. More specifically, a P channel MOS transistor PQ13 that is selectively turned on in response to control signal EN2 is provided between driver power supply line 20 and MOS transistor NQ10. MOS transistor PQ13 has the same threshold voltage (Vth) characteristics as load MOS transistors PQ1 and PQ2 included in the memory cell. The other configuration of the word line power supply circuit 14 shown in FIG. 14 is the same as that of the word line power supply circuit shown in FIG. 5, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the configuration of word line power supply circuit 14 shown in FIG. 14, in the normal mode, MOS transistors PQ11 and PQPQ13 are on, and MOS transistor PQ12 is off. Therefore, compared with the configuration of the first embodiment, the voltage level of driver power supply line 20 is lowered by two MOS transistors PQ11 and PQ13, so that word line selection voltage WVDD on power supply line 20 is equal to the memory power supply voltage. The voltage further drops below VDDM and becomes voltage V1-ΔV1. These voltages satisfy the relationship of V1-ΔV1> V2-ΔV2. The static noise margin SNM is improved by moving the SNM limit line L5 that has deeply entered the manufacturing management area II in the high-performance mode to a larger value in the upper left direction in FIG. 12 than in the normal mode.

  Since the control signal EN3 is set to the L level in the high performance mode, the driver power supply line 20 is discharged by these MOS transistors PQ11 to PQ13, and the voltage level of the word line selection voltage WVDD is further lowered. Therefore, compared with the configuration of the first embodiment, the voltage level of the word line selection voltage WVDD can be further lowered to be the voltage V2-ΔV2. Therefore, in both the normal mode and the high-performance mode, even when the SNM limit line crosses the manufacturing control region II, the static noise margin of the memory cell can be improved, and the influence of the variation of the threshold voltage is suppressed. A semiconductor memory capable of performing stable data access can be realized.

  The ratio of the number of MOS transistors that are turned on according to control signals EN2 and EN3 is not limited to 2: 1 as shown in FIG. Depending on the relationship between the voltage level of the word line selection voltage WVDD and the voltage level of the memory power supply voltage VDDM, the voltage levels of the voltage drop amounts ΔV1 and ΔV2 become appropriate values, and the word line selection voltage WVDD becomes an appropriate voltage level. In this way, the number of transistors for discharging (for voltage drop) may be adjusted.

  In the configuration of word line power supply circuit 14 shown in FIG. 14, N channel MOS transistors having the same threshold voltage characteristics as N channel MOS transistors NT1-NT4 of memory cells MC are used instead of MOS transistors PQ11-PQ13. May be used.

  As the configuration of the word line power supply control circuit for generating control signals EN1-EN3 and VDDEN, the same configuration as that of the word line transmission control circuit of the first embodiment can be used.

[Example of change]
FIG. 15 schematically shows a structure of a modification of word line power supply circuit 14 of the semiconductor memory according to the second embodiment of the present invention. In FIG. 15, P channel MOS transistors PQ11a-PQ11m and PQ12a-PQ12n are provided in parallel between driver power supply line 20 and MOS transistor NQ10. Control signals EN2a-EN2m are applied to the gates of MOS transistors PQ11a-PQ11m, respectively, and MOS transistors PQ12a-PQ12n receive control signals EN3a-EN3n at the gates, respectively. MOS transistors PQ10 and NQ10 are the same as those described in the first and second embodiments.

  In the configuration of the word line power supply circuit 14 shown in FIG. 15, the control signal EN2a-EN2m and EN3a-EN3n are appropriately set to the utilization state (L level) in the normal mode and the high-performance mode, thereby The voltage level of the word line selection voltage WVDD on 20 can be set to an appropriate voltage level according to the use environment.

  In the configuration of word line power supply circuit 14 shown in FIG. 15, as an example, MOS transistors PQ11a-PQ11m are always kept on in the normal mode and the high performance mode, and MOS transistors PQ12a-PQ12n are maintained in the high performance mode. May be selectively set to an on state. Instead, in the normal mode, the MOS transistors PQ11a to PQ11m are selectively turned on, and the MOS transistors PQ12a to PQ12n are selectively turned on according to the control signals EN3a to EN3n in the high performance mode. The state may be set.

  Also in the configuration of word line power supply circuit 14 shown in FIG. 15, MOS transistors PQ11a-PQ11m and PQ12a-PQ12n have the same threshold voltage characteristics as MOS transistors PQ1, PQ2 at the load of the memory cell. Instead of MOS transistors PQ11a-PQ11m and PQ12a-PQ12n, N channel MOS transistors having the same threshold voltage characteristics as N channel MOS transistors NQ1-NQ4 of the memory cell may be used. For example, MOS transistors having the same threshold voltage characteristics can be easily realized by forming these transistors in the same manufacturing process.

  FIG. 16 is a diagram showing an example of the configuration of the word line power supply control circuit for the word line power supply circuit shown in FIG. FIG. 16 shows a configuration of a part that generates control signals EN2a-EN2m and EN3a-EN3n.

  In FIG. 16, the word line power supply control circuit 13 has a fuse program circuit 60 that stores information in a fixed manner by a fuse program, and control signals EN2a-EN2m and EN3a according to the stored information of the fuse program circuit 60 and the chip mode instruction signal CS. Includes a decoder 62 that generates EN3n.

  The fuse program circuit 60 stores information indicating the active / specific active states of the control signals EN2a-EN2m and EN3a-EN3n depending on whether the fuse element is blown or not blown. Decoder 62 selectively drives control signals EN2a-EN2m and EN3a-EN3n to the active state (L level) in the normal mode and the high-performance mode in accordance with the program information of fuse program circuit 60 and chip mode instruction signal CS. .

  The number of bits of data stored in fuse program circuit 60 is appropriately determined according to the number of MOS transistors PQ11a-PQ11m and PQ12a-PQ12n included in word line power supply circuit 14.

  The fuse program circuit 60 is used to set the MOS transistor that is turned on in the normal mode and the high-performance mode, so that the word line selection voltage WVDD is set to the memory power supply voltage VDDM in the normal mode and the high-performance mode. An appropriate level can be set according to the voltage level in the mode and according to the characteristics of the memory.

  In the word line power supply circuit 14 shown in FIG. 15, when N-channel MOS transistors are used instead of MOS transistors PQ11a-PQ11m and PQ12a-PQ12n, decoder 62 receives control signals EN2a-EN2m and EN3a- A complementary control signal of EN3n is generated.

  As described above, according to the second embodiment of the present invention, the memory power supply voltage decreases the word line selection voltage level regardless of the normal mode and the high performance mode, and the amount of decrease depends on the operation mode. It is adjusted. As a result, it is possible to realize a semiconductor memory capable of accurately writing / reading data even if the threshold voltage varies when the memory cell is miniaturized, and correspondingly low power consumption. Thus, a processing system that operates stably and at high speed can be realized.

  Also in the second embodiment, the processing system using the semiconductor memory is the same as the system shown in the first embodiment.

  In the first and second embodiments, two access operation modes, the normal mode and the high performance mode, are shown during FV control, and the level of the power supply voltage is adjusted according to each operation mode. However, the level of the power supply voltage is not limited to 2, and may be adjusted according to a larger number of operation modes.

  A semiconductor integrated circuit device (semiconductor memory) according to the present invention is applied to an SRAM that is used together with a processor that performs FV control, so that a semiconductor integrated circuit device (system LSI) that has a low occupation area, low power consumption, and operates at high speed. Can be realized.

  Note that the target information for FV control performed by the processor is not limited to moving image and audio data. The semiconductor integrated circuit device according to the present invention can be applied to any processor in which the operating frequency and operating power supply voltage level of the processor are changed according to the processing status.

  In particular, by applying a semiconductor integrated circuit device (semiconductor memory) according to the present invention to an SoC (system on chip) SRAM, even when the transistor size is miniaturized, the threshold voltage of the memory cell varies. Thus, an SRAM core that operates stably with a low occupation area can be realized.

1 is a diagram schematically showing a configuration of a processing system including a semiconductor memory according to the present invention. FIG. FIG. 2 is a diagram schematically showing an overall configuration of the semiconductor memory shown in FIG. 1. FIG. 3 is a diagram showing an example of a configuration of a memory cell of the semiconductor memory shown in FIG. 2. FIG. 4 schematically shows operating characteristics of the memory cell shown in FIG. 3. FIG. 3 is a diagram showing an example of a configuration of a word line power supply circuit and a word line power supply control circuit shown in FIG. 2. FIG. 6 is a timing chart showing the operation of the circuit shown in FIG. 5. FIG. 5 is a diagram showing an example of a configuration of a word line power supply control circuit shown in FIG. 4. FIG. 8 is a timing chart showing an operation of the word line power supply control circuit shown in FIG. 7. FIG. 7 is a flowchart showing a main operation of the processor of the semiconductor integrated circuit device according to the first embodiment of the present invention. It is a figure which shows an example of a structure of the word line power supply circuit of the example of a change of Embodiment 1 of this invention. It is a figure which shows an example of a structure of the system on chip | tip to which the semiconductor memory according to Embodiment 1 of this invention is applied. It is a figure which shows roughly the operating characteristic of the memory cell of the semiconductor memory according to Embodiment 2 of this invention. It is a figure which shows roughly the adjustment aspect of the word line selection voltage in Embodiment 2 of this invention. It is a figure which shows an example of a structure of the word line power supply circuit of the semiconductor memory according to Embodiment 2 of this invention. It is a figure which shows schematically the structure of the example of a change of the word line power supply circuit of the semiconductor memory according to Embodiment 2 of this invention. FIG. 16 is a diagram schematically showing an example of a configuration of a part that generates a control signal shown in FIG. 15.

Explanation of symbols

  1 processor, 2 semiconductor memory, 10 memory array, 11 word line decoder, 12 word line drive circuit, 13 word line power supply control circuit, 14 word line power supply circuit, PQ1, PQ2, PQ10-PQ12, PQ11a-PQ11m, PQ12a-PQ12n P channel MOS transistor, NQ1-NQ4, NQ10, NQ12 N channel MOS transistor, 30 Semiconductor integrated circuit device (system LSI), 32 application block, 34 communication block, 40 application processor, 42 local memory, 50 baseband processor, 52 local Memory, 60 fuse program circuit, 62 decoder.

Claims (4)

An operation cycle is defined by a clock signal, and includes a processor in which the frequency of the clock signal and the level of a power supply voltage are adjusted according to a processing situation, and a semiconductor memory storing at least information used by the processor, A plurality of static memory cells arranged in a matrix, a plurality of word lines arranged corresponding to each memory cell row, each of which is connected to a corresponding row of memory cells, and addressed according to an address signal A row selection drive circuit for driving a word line arranged corresponding to the selected row to a selected state, wherein the row selection drive circuit selects a selected row according to a frequency of a clock signal of the processor and a level of a power supply voltage. look including a word line voltage adjustment circuit for adjusting the level of the selection voltage transferred to,
The word line voltage adjustment circuit transmits a voltage corresponding to the power supply voltage as the selection voltage when the power supply voltage is at a first voltage level, and the second voltage is higher than the first level. A semiconductor integrated circuit device that transmits a voltage obtained by stepping down the power supply voltage as the selection voltage when the level is low . A processor in which an operation cycle is defined by a clock signal, and a frequency of the clock signal and a level of a power supply voltage are adjusted according to a processing situation; and
A semiconductor memory for storing at least information used by the processor, the semiconductor memory being arranged corresponding to each of the memory cell rows and a plurality of static memory cells arranged in a matrix; A plurality of word lines to which the memory cells are connected, and a row selection driving circuit for driving a word line arranged corresponding to a row addressed in accordance with an address signal to a selected state. A word line voltage adjustment circuit for adjusting a level of a selection voltage transmitted to a selected row according to a frequency of a clock signal of the processor and a level of a power supply voltage;
The word line voltage adjustment circuit transmits, as the selection voltage, a voltage obtained by lowering the power supply voltage by a first amount when the power supply voltage is at a first voltage level, and the power supply voltage is less than the first voltage level. It is high when the second voltage level to transmit a second quantity stepped-down voltage the power supply voltage is greater than the first amount as the selection voltage, the semi-conductor integrated circuit device. A semiconductor memory in which the level of a power supply voltage is changed according to an operation mode,
A plurality of static memory cells arranged in a matrix;
A plurality of word lines arranged corresponding to each memory cell row and connected to the memory cells in the corresponding row, and a word line arranged corresponding to the row addressed according to the address signal are selected. and a row select driver circuit for driving the row select driver circuit in accordance with the operation mode, see contains the word line voltage adjustment circuit for adjusting the level of the word line selection voltage transmitted to the selected row,
The word line voltage adjustment circuit transmits a voltage corresponding to the power supply voltage as the selection voltage when the power supply voltage is at a first voltage level, and the second voltage is higher than the first level. A semiconductor integrated circuit device that transmits a voltage obtained by stepping down the power supply voltage as the selection voltage when the level is low . A semiconductor memory in which the level of a power supply voltage is changed according to an operation mode,
A plurality of static memory cells arranged in a matrix;
A plurality of word lines arranged corresponding to each memory cell row and connected to the memory cells in the corresponding row, and a word line arranged corresponding to the row addressed according to the address signal are selected. A row selection driving circuit for driving, the row selection driving circuit including a word line voltage adjustment circuit for adjusting a level of a word line selection voltage transmitted to the selected row according to an operation mode,
The word line voltage adjustment circuit transmits, as the selection voltage, a voltage obtained by lowering the power supply voltage by a first amount when the power supply voltage is at a first voltage level, and the power supply voltage is less than the first voltage level. It is high when the second voltage level to transmit a second quantity stepped-down voltage the power supply voltage is greater than the first amount as the selection voltage, the semi-conductor integrated circuit device.

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