TWI726775B - Memory apparatus and method of input and output buffer control thereof - Google Patents

Abstract

A memory apparatus includes a pseudo static random access memory and a controller. The pseudo static random access memory includes an input and output circuit having a fast mode circuit and a slow mode circuit. The controller adjusts a power supply voltage and a clock frequency according to the operation mode of the memory apparatus, and generates a register setting code based on an adjusted power supply voltage and an adjusted clock frequency. The pseudo static random access memory enables one of the fast mode circuit and the slow mode circuit according to the register setting code, and disables the other of the normal mode circuit and the fast mode circuit.

Description

Memory device and its input and output buffer control method

The present invention relates to a semiconductor circuit, and more particularly to a memory device and its input and output buffer control method.

In recent years, low pin count memory (LPC memory) has been widely used in Internet of Things (IOT) and wearable devices. However, due to the need to operate at a higher clock frequency, the input-output circuit (IO circuit) of the low-pin-number memory needs to consume a large amount of current. In addition, in the prior art, the access time has nothing to do with the clock frequency, and the current driving force control does not depend on the operation mode and the clock frequency, resulting in shortened battery life.

In view of this, the present invention provides a memory device and its input/output buffer control method, which is used to generate a register setting code according to the power supply voltage and clock frequency, and to enable high speed in the input/output circuit according to the register setting code. Mode circuit or slow mode circuit to dynamically adjust the access time of the input and output circuits to provide power saving control and extend battery life.

The embodiment of the present invention provides a memory device. The memory device includes Virtual static random access memory and controller. The virtual static random access memory includes an input and output circuit with a high-speed mode circuit and a slow-mode circuit. The controller is coupled to the virtual static random access memory. The controller adjusts the power supply voltage and the clock frequency according to the operation mode of the memory device, and generates a register setting code based on the adjusted power supply voltage and the adjusted clock frequency. The virtual static random access memory enables one of the high-speed mode circuit and the slow mode circuit according to the register setting code, and disables the other of the high-speed mode circuit and the slow mode circuit.

The embodiment of the present invention provides an input and output buffer control method, which is suitable for a memory device, and the memory device includes a virtual static random access memory and a controller. The virtual static random access memory includes an input and output circuit with a high-speed mode circuit and a slow-mode circuit. The input and output buffer control method includes adjusting the power supply voltage and the clock frequency according to the operation mode of the memory device. The register setting code is generated based on the adjusted power supply voltage and the adjusted clock frequency. According to the register setting code, one of the high-speed mode circuit and the slow mode circuit is enabled, and the other of the high-speed mode circuit and the slow mode circuit is disabled.

Based on the above, in an embodiment of the present invention, the memory device and its input/output buffer control method are used to adjust the power supply voltage and clock frequency according to the operation mode, and generate temporary storage by the adjusted power supply voltage and clock frequency And enable the high-speed mode circuit or the slow mode circuit in the input/output circuit according to the register setting code to dynamically adjust the access time of the input/output circuit, thereby providing power saving control and extending battery life.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

10: Memory device

110: Virtual Static Random Access Memory

120: Controller

130: Input and output circuit

140: High-speed mode circuit

150: Slow mode circuit

160: input receiver

170: Microprocessor

180: power management circuit

190: Power supply circuit

210: Command decoder

220: memory array

230: Address latch and decoding circuit

240: data path

250_1, 250_N: array

260_1, 260_N-1: sense amplifier

270: X decoder

280: Y decoder/second sense amplifier

500, 510, 520: off-chip drivers

530, 550: off-chip driver control circuit

540, 560: output stage

NOT1, NOT2, NOT3: inverter

DA: Differential amplifier

RS: series resistance

NAND1: reverse and gate

AS: address space bit

CK, CK#: differential clock signal

CR[15]: Operation mode

CR[7:4]: Delay count

CS#: Chip selection signal

CTLPWR: power management control signal

CTLVDDQ: power control signal

CTLRX: Input control signal

CTLRXB: Inverting input control signal

CTLTX: Transmission control signal

DQ: data bus

DATA_IN: input data

DATA_OUT: output data

RWDS: select communication number for reading and writing data

GND: Ground voltage

N1, N2, N3: node voltage

VDDQ: power supply voltage

VIN: Input signal

VN: High-speed mode voltage

VOUT: output signal

VREF: Reference voltage

VS: Slow mode voltage

MP1, MP2, MP3, MP4, MP5, MN1, MN2, MN3, MN4, MN5: Transistor

SW1, SW2, SW3, SW4, SW5: switch

S310, 311, S312, S313, S314, S315, S320, 321, S322, S323, S324, S325, S610, S620, S630, S640, S710, S720, S730: steps

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the invention.

FIG. 2 is a circuit block diagram of a virtual static random access memory according to an embodiment of the invention.

FIG. 3A is a flowchart of determining a command address bit according to an embodiment of the present invention.

FIG. 3B is a flow chart of judging command address bits according to an embodiment of the present invention.

4 is a circuit block diagram of an address latch decoding circuit according to an embodiment of the present invention.

FIG. 5 is a timing diagram of a page access sequence according to an embodiment of the invention.

Fig. 6 is a flowchart of a continuous reading and writing method according to an embodiment of the present invention.

Fig. 7 is a flowchart of an input/output buffer control method according to an embodiment of the present invention.

1, the memory device 10 may include a virtual static random access memory 110 and a controller 120. The virtual static random access memory 110 includes an input and output circuit 130. The input and output circuit 130 includes a high-speed mode circuit 140 and a slow-speed mode circuit 150. The controller 120 is coupled to the virtual static random access memory 110.

In different embodiments, the memory device 10 may be an octal flash memory (Octal Flash memory), a ferroelectric random access memory (Ferroelectric Random Access Memory, FRAM), an electronic erasable rewritable read-only Memory (Electrically-Erasable Programmable Read-Only Memory, EEPROM) or other memory.

2, the virtual static random access memory 110 includes an input/output circuit 130, a command decoder 210, and a memory array 220. Input and output circuit 130 It is connected to the command decoder 210 and is used as an input/output interface between the internal circuit of the virtual static random access memory 110 and the external circuit. Furthermore, the input/output circuit 130 includes an input receiver 160, and the input receiver 160 includes a high-speed mode circuit 140 and a slow-speed mode circuit 150. The command decoder 210 is coupled between the input/output circuit 130 and the memory array 220. The command decoder 210 is used to decode the register setting code CR received from the controller 120 and generate the input control signal CTLRX and transmission control Signal CTLTX. The memory array 220 is composed of a plurality of storage units, and performs data writing or reading control on the storage units designated by the microprocessor 170. In one embodiment, the virtual static random access memory 110 may have a dynamic random access memory (Dynamic Random Access Memory, DRAM) as the core and a static random access memory (Static Random Access Memory, SRAM) as the core The interface is composed. In an embodiment, the virtual static random access memory 110 may also include other devices, such as an address latch and decode circuit 230 and a data path 240, but it is not limited to this. . In an embodiment, the memory array 220 includes an array 250_1, a sense amplifier 260_1...sense amplifier 260_N-1 and an array 250_N, an X decoder 270, and a Y decoder/second sense amplifier 280.

2, the controller 120 includes a microprocessor 170, a power management circuit 180 and a power circuit 190.

The microprocessor 170 is coupled to the virtual static random access memory 110, and the microprocessor 170 provides a differential clock signal CK, a differential clock signal CK# and a chip selection signal CS# to the virtual static random access memory 110, The virtual static random access memory 110 and the microprocessor 170 also have a bidirectional data bus DQ and read and write data. Material selection communication number RWDS. Regarding the clock frequency adjustment of the differential clock signal CK and the differential clock signal CK#, specifically, the microprocessor 170 generates the power management control signal CTLPWR according to the operation mode of the memory device 10 and adjusts the clock frequency. For example, when pointing to low power consumption mode, the frequency is adjusted from 400MHz to 133MHz. And the microprocessor 170 generates the corresponding command address bit CA and register setting code CR according to the change of the clock frequency. According to the design requirements, the microprocessor 170 can be a central processing unit (Central Processing Unit, CPU), or other programmable microprocessor (Microprocessor), digital signal processor (Digital Signal Processor, DSP), programmable Controller, Application Specific Integrated Circuit (ASIC) or other similar components or a combination of the above components.

The power management circuit 180 is coupled to the microprocessor 170, and the power management circuit 180 generates a power control signal CTLVDDQ according to the power management control signal CTLPWR. For example, when the microprocessor 170 instructs to enter the low power consumption mode, the microprocessor 170 sends a high logic level power management control signal CTLPWR to the power management circuit 180. Then, the power management circuit 180 sends the power control signal CTLVDDQ of the low logic level to the power circuit 190 according to the power management control signal CTLPWR of the high logic level.

The power circuit 190 is coupled to the virtual static random access memory 110, the microprocessor 170 and the power management circuit 180. The power circuit 190 generates a power voltage VDDQ according to the power control signal CTLVDDQ and provides it to the microprocessor 170 and the virtual static random access memory 110. Following the above example, when the power supply circuit 190 receives the power control signal CTLVDDQ with a low logic level, the power supply circuit 190 increases the power supply voltage VDDQ It is provided to the microprocessor 170 and the virtual static random access memory 110, for example, to increase the power supply voltage VDDQ from 1.2V to 1.8V.

Conversely, when the microprocessor 170 instructs to enter the high-speed mode, the microprocessor 170 sends a low logic level power management control signal CTLPWR to the power management circuit 180. Then, the power management circuit 180 sends the power control signal CTLVDDQ of the high logic level to the power circuit 190 according to the power management control signal CTLPWR of the low logic level. When the power supply circuit 190 receives the high logic level power control signal CTLVDDQ, the power supply circuit 190 increases the power supply voltage VDDQ and provides it to the microprocessor 170 and the virtual static random access memory 110, for example, reduces the power supply voltage VDDQ from 1.8V to 1.2V.

3A, in step S310, the memory device 10 starts to access. Then, in step S311, the command decoder 210 in the virtual static random access memory 110 determines that the access is memory access (AS=0) or according to the address space bit AS in the command address bit CA For register access (AS=1), when it is a memory access (AS=0), go to step S312, and when it is a register access (AS=1), go to step S313. In step S312, the memory device 10 performs array access to the memory array 220. In step S313, the memory device 10 accesses the register of the command decoder 210, and judges the operation mode CR[15] in the register setting code CR stored in the command decoder 210. When the mode setting CR[15] is 0b, go to step S314. When the mode setting CR[15] is 1b, go to step S315. For details of the mode setting CR[15] in the register setting code CR, please refer to Table 1.

【Table I】

In step S314, it is judged that the input/output circuit 130 will operate in the slow mode, and the decoder 210 is instructed to output the low logic level input control signal CTLRX (ie CTLRX=L) and the low logic level transmission control signal CTLTX (ie CTLTX). =L). In step S315, it is judged that the input/output circuit 130 will operate in the high-speed mode, and the decoder 210 is instructed to output the high logic level input control signal CTLRX (ie CTLRX=H) and the high logic level transmission control signal CTLTX (ie CTLTX= H).

Referring to FIG. 3B, in step S320, the memory device 10 starts to access. Then, in step S321, the command in the virtual static random access memory 110 is decoded The encoder 210 determines whether the access is memory access (AS=0) or register access (AS=1) according to the address space bit AS in the command address bit CA. When it is a memory access (AS=0), go to step S322, when it is a register access (AS=1), go to step S323. In step S322, the memory device 10 performs array access to the memory array 220. In step S323, the memory device 10 performs register access to the command decoder 210, and judges the delay count CR[7:4] in the register setting code CR stored in the command decoder 210. When the delay count CR[7:4] is 5, 6, 7, 8 clocks, go to step S324. When the delay count CR[7:4] is 12, 14, 16 clocks, go to step S325. For the details of the delay count CR[7:4] in the register setting code CR, please refer to Table 1. In step S324, it is judged that the input/output circuit 130 will operate in the slow mode, and the decoder 210 is instructed to output the low logic level input control signal CTLRX (ie CTLRX=L) and the low logic level transmission control signal CTLTX (ie CTLTX). =L). In step S325, it is judged that the input/output circuit 130 will operate in the high-speed mode, and the decoder 210 is instructed to output the high logic level input control signal CTLRX (ie CTLRX=H) and the high logic level transmission control signal CTLTX (ie CTLTX= H).

Referring to FIG. 2, FIG. 3A, FIG. 3B and Table 1, when the microprocessor 170 instructs to enter the low power consumption mode, the microprocessor 170 reduces the clock frequency, for example, adjusts the frequency from 400 MHz to 133 MHz. Then the microprocessor 170 generates the command address bit CA and the register setting code CR according to the change of the frequency (as shown in Table 1). The command address bit CA includes at least the address space bit AS, and the register setting code CR includes at least the mode setting CR[15] and the delay count CR[7:4]. Virtual static random access memory 110 The command address bit CA is received, and the high speed mode circuit 140 or the slow mode circuit 150 is enabled according to the command address bit CA and the register setting code CR.

Therefore, referring to FIG. 1, FIG. 2, FIG. 3A, FIG. 3B, and Table 1, the controller 120 can adjust the power supply voltage VDDQ, the differential clock signal CK, and the differential clock signal CK# according to the operation mode of the memory device 10. And generate a register setting code CR corresponding to the adjusted power supply voltage VDDQ and the adjusted clock frequency. Then, the virtual static random access memory 110 can enable one of the high-speed mode circuit 140 and the slow mode circuit 150, and disable the high-speed mode circuit 140 and the slow mode circuit 150 according to the register setting code CR. The other one. Furthermore, the virtual static random access memory 110 enables one of the high-speed mode circuit 140 and the slow mode circuit 150, and disables the high-speed mode circuit 140 and the slow mode circuit according to the input control signal CTLRX The other of 150.

In detail, when the virtual static random access memory 110 determines that the input/output circuit 130 is set to the high-speed mode according to the register setting code CR (ie CTLRX=H), the high-speed mode circuit 140 is enabled and disabled The slow mode circuit 150 is described. When the virtual static random access memory 110 determines that the input/output circuit 130 is set to the slow mode according to the register setting code CR (ie, CTLRX=L), the slow mode circuit 150 is enabled and the high mode circuit 140 is disabled.

With respect to FIG. 4, the input receiver 160 includes an inverter NOT1, a high-speed mode circuit 140, a slow mode circuit 150, and an inverter NAND1. The inverter NOT1 receives and inverts the input control signal CTLRX to generate the inverted input control signal CTLRXB. The high-speed mode circuit 140 is coupled to the inverter NOT1, and the high-speed mode circuit 140 receives the inverted input control signal CTLRXB and the input signal VIN to generate the high-speed mode voltage VN. The slow mode circuit 150, coupled to the inverter NOT1, is configured to receive the inverted input control signal CTLRXB and the input signal VIN to generate the slow mode voltage VS. The inverter NAND1 is coupled to the high-speed mode circuit 140 and the slow mode circuit 150, and the inverter NAND1 performs an inverse operation on the high-speed mode voltage VN and the slow mode voltage VS to generate the output signal VOUT. When it is determined that the input/output circuit 130 will operate in the high-speed mode, the inverted input control signal CTLRXB enables the high-speed mode circuit 140 and disables the slow-speed mode circuit 150. When it is judged that the input/output circuit 130 will operate in the slow mode, the inverting input control signal CTLRXB disables the high-speed mode circuit 140 and enables the slow mode circuit 150.

The high-speed mode circuit 140 includes an inverter NOT2, a switch SW1, a differential amplifier DA, a series resistor RS, a switch SW2, and a switch SW3. The inverter NOT2 is coupled to the inverter NOT1, and the inverter NOT2 receives the inverting input control signal CTLRXB to generate the node voltage N1. The first terminal of the first switch SW1 is coupled to the power supply voltage VDDQ, the control terminal of the first switch SW1 is coupled to the node voltage N1, and the second terminal of the first switch SW1 is coupled to the high-speed mode voltage VN. The differential amplifier DA includes a transistor NM1, a transistor NM2, and a current mirror load. The current mirror load includes a transistor PM1 and a transistor PM2. The first end of the transistor NM1 is coupled to the high-speed mode voltage VN, the control end of the transistor NM1 is coupled to the input signal VIN, and the second end of the transistor NM1 is coupled to the node voltage N2. The first end of the transistor NM2 is coupled to the node voltage N3, and the control end of the transistor NM2 receives the voltage divided by the series resistor RS. The second terminal of the transistor NM2 is coupled to the node voltage N2. The first terminal of the transistor PM1 is coupled to the power supply voltage VDDQ, the control terminal of the transistor PM1 is coupled to the node voltage N3, and the second terminal of the transistor PM1 is coupled to the high-speed mode voltage VN. The first end of the transistor PM2 is coupled to the power supply voltage VDDQ, the control end of the transistor PM2 is coupled to the node voltage N3, and the second end of the transistor PM2 is coupled to the node voltage N3. The series resistor RS includes a first resistor R1 and a second resistor R2. The series resistor RS uses the first resistor R1 and the second resistor R2 to perform a voltage division operation to generate the reference voltage VREF. The first end of the series resistor RS is coupled to the power supply voltage VDDQ, the second end of the series resistor RS is coupled to the switch SW3, and the voltage dividing end of the series resistor RS is coupled to the control end of the transistor NM2. The first resistor R1 is coupled between the power supply voltage VDDQ and the reference voltage VREF, and the second resistor R2 is coupled between the reference voltage VREF and the switch SW3. The first end of the switch SW2 is coupled to the node voltage N2 in the differential amplifier DA, the control end of the switch SW2 is coupled to the node voltage N1, and the second end of the switch SW2 is coupled to the ground voltage GND. The first end of the switch SW3 is coupled to the second resistor R2, the control end of the switch SW3 is coupled to the node voltage N1, and the second end of the switch SW3 is coupled to the ground voltage GND.

Specifically, when the input control signal CTLRX is at a high logic level (ie CTLRX=H), since the inverting input control signal CTLRXB is at a low logic level (ie CTLRXB=L), the node voltage N1 in the high-speed mode circuit 140 Is a high logic level, so that the switch SW1 is not turned on, and the switches SW2 and SW3 are turned on to the ground voltage GND, so the series resistor RS can divide the power supply voltage VDDQ to generate the reference voltage VREF, and the differential amplifier DA compares Input signal VIN and parameters The voltage VREF is tested to generate the high-speed mode voltage VN. In contrast, since the input control signal CTLRX is at a high logic level (ie CTLRX=H) and the inverting input control signal CTLRXB is at a low logic level (ie CTLRXB=L), the switch SW4 in the slow mode circuit 150 is not turned on. The switch SW5 is turned on, so that the slow mode voltage VS is fixed at the high logic level. Therefore, when the input control signal CTLRX is at a high logic level (ie, CTLRX=H), the high-speed mode circuit 140 receives the input signal VIN to generate the high-speed mode voltage VN, and NAND1 is coupled to the high-speed mode voltage generated by the input signal VIN. The mode voltage VN and the slow mode voltage VS fixed to a high logic level perform a NAND operation to generate an output signal VOUT.

The slow mode circuit 150 includes an inverter NOT3, a switch SW4, and a switch SW5. The first terminal of the inverter NOT3 is coupled to the power supply voltage VDDQ, the input terminal of the inverter NOT3 is coupled to the input signal VIN, and the output terminal of the inverter NOT3 is coupled to the slow mode voltage VS. The inverter NOT3 is composed of a transistor PM3 and a transistor NM3. The first terminal of the switch SW4 is coupled to the second terminal of the inverter NOT3, the control terminal of the switch SW4 receives the inverted input control signal CTLRXB, and the second terminal of the switch SW4 is coupled to the ground voltage GND. The first terminal of the switch SW5 is coupled to the power supply voltage VDDQ, the control terminal of the switch SW5 receives the inverted input control signal CTLRXB, and the second terminal of the switch SW5 is coupled to the slow mode voltage VS.

Specifically, when the input control signal CTLRX is at a low logic level (ie CTLRX=L), since the inverting input control signal CTLRXB is at a high logic level (ie CTLRXB=H), the node voltage N1 in the high-speed mode circuit 140 Is a low logic level, so that the switch SW1 is turned on and the high-speed mode voltage VN is fixed to a high logic level, and The switch SW2 and the switch SW3 are not conductive, and the series resistor RS cannot divide the power supply voltage VDDQ to generate the reference voltage VREF. In contrast, since the input control signal CTLRX is at a low logic level (ie CTLRX=L), and the inverting input control signal CTLRXB is at a high logic level (ie CTLRXB=H), the switch SW4 in the slow mode circuit 150 is turned on to switch SW5 is not turned on, so that the inverter NOT3 inverts the input signal VIN and outputs the slow mode voltage VS. Therefore, when the input control signal CTLRX is at a low logic level (ie CTLRX=L), the slow mode circuit 150 receives the input signal VIN and generates a slow mode voltage VS, and the pair of NAND1 is fixed at a high logic level. The high-speed mode voltage VN and the slow-mode voltage VS generated by the input signal VIN perform a NAND operation to generate an output signal VOUT.

It must be noted that the slow mode circuit 150 is enabled in the slow mode (ie CTLRX=L), compared to the high-speed mode (ie CTLRX=H) when the high-speed mode circuit 140 is enabled, the slow mode is slow Compared with the high-speed mode circuit 140 in the high-speed mode, the input signal VIN in the high-speed mode circuit 150 has passed an inverter delay (that is, the inverter NOT3). It must be noted that this embodiment is only an example, and the present invention does not limit the number of inverters that generate a delay. Therefore, in the slow mode (ie, CTLRX=L), although the input and output response of the input receiver 160 is relatively slow, the current consumption is less than that in the high-speed mode circuit 140, so that the battery life can be prolonged.

5, the memory device 10 further includes an off-chip driver (Off-Chip Driver, OCD) 500, the off-chip driver 500 is at least configured in the input and output circuit 130, and includes the data selection communication number DQS (not shown) and data Bus DQ. The off-chip driver 500 includes a first off-chip driver 510 and a second off-chip driver 520, The off-chip driver 500 is used for buffering the input data DATA_IN according to the transmission control signal CTLTX to generate the output data DATA_OUT. The first off-chip driver 510 receives the input control signal CTLRX, and the first off-chip driver 510 is enabled or disabled according to the transmission control signal CTLTX. The second off-chip driver 520 is configured for constant operation. The off-chip driver 500 is used to dynamically adjust the current driving force buffered from the input data DATA_IN to the output data DATA_OUT according to the transmission control signal CTLTX, and then the output data after the current driving force is adjusted DATA_OUT is provided to the data bus DQ.

In detail, the first off-chip driver 510 includes an off-chip driver control circuit 530 and an output stage 540. The off-chip driver control circuit 530 receives the transmission control signal CTLTX and the input data DATA_IN, and the off-chip driver control circuit 530 is enabled or disabled according to the transmission control signal CTLTX to adjust the voltage provided to the output stage 540. The output stage 540 includes a transistor PM4 and a transistor NM4 for generating output data DATA_OUT according to the voltage provided by the off-chip driver control circuit 530. On the other hand, the second off-chip driver 520 includes an off-chip driver control circuit 550 and an output stage 560. The off-chip driver control circuit 550 receives the input data DATA_IN for adjusting the voltage provided to the output stage 540. The output stage 560 includes a transistor PM5 and a transistor NM5 for generating output data DATA_OUT according to the voltage provided by the off-chip driver control circuit 550.

Specifically, when the virtual static random access memory 110 determines that the input/output circuit 130 is set to the high-speed mode according to the register setting code CR, the first off-chip driver 510 is enabled according to the transmission control signal CTLTX. When virtual static random storage When the memory 110 determines that the input/output circuit 130 is set to the slow mode according to the register setting code CR, the first off-chip driver 510 is disabled according to the transmission control signal CTLTX. Since the second off-chip driver 520 is configured for constant operation, both the first off-chip driver 510 and the second off-chip driver 520 are enabled in the high-speed mode, and only the second off-chip driver 520 is enabled in the slow mode. The driver 520 is enabled. In other words, the off-chip driver 500 can adjust the current driving force of the data input and output through the register setting code CR, so as to provide the best DQ bus area dynamic ability according to the high-speed mode or the slow-speed mode.

Referring to FIGS. 2 and 6, the communication number RWDS is selected for reading and writing data to enable the microprocessor 170 to learn the state transition of the operation mode of the virtual static random access memory 110. Since it takes a transition time to update the power supply voltage VDDQ, while waiting for the transition time, the virtual static random access memory 110 can use the read and write data to select the communication number RWDS to inform the microprocessor 170 about the operation mode of the virtual static random access memory 110. Specifically, in step S610, the virtual static random access memory 110 starts to access. Next, in step S620, it is determined whether the power supply voltage VDDQ has been adjusted. If the power supply voltage VDDQ has not been adjusted, go to step S625. When the power supply voltage VDDQ has been adjusted, step S630 is entered. In step S630, the logic level of the communication number RWDS is controlled to read and write data. When the communication number RWDS selected for reading and writing data is at a low logic level (ie, RWDS=L), step S640 is entered. When the communication number RWDS selected for reading and writing data is at a high logic level (ie, RWDS=H), step S630 returns to step S650 to notify the microprocessor 170 that the power supply voltage VDDQ is being adjusted. In step S640, inform the microprocessor 170 that it is ready to receive a transaction (transaction) For array access. In step S650, the microprocessor 170 is notified that the current operating mode is being adjusted.

Referring to FIG. 7, in step S710, the controller 120 adjusts the power supply voltage VDDQ and the clock frequency according to the operation mode of the memory device 10. Next, in step S720, the controller 120 generates a register setting code CR based on the adjusted power supply voltage VDDQ and the adjusted clock frequency. In step S730, the virtual static random access memory 110 enables one of the high-speed mode circuit 140 and the slow mode circuit 150 according to the register setting code CR, and disables the high-speed mode circuit 140 and the slow mode circuit 150 The other one.

To sum up, in the embodiment of the present invention, the memory device and its input/output buffer control method are used to adjust the power supply voltage and clock frequency according to the operation mode, and the adjusted power supply voltage and clock frequency are used to generate The register setting code enables the high-speed mode circuit or the slow mode circuit in the input/output circuit according to the register setting code to dynamically adjust the access time of the input/output circuit. And adjust the current driving force of the off-chip driver data through the register setting code. In addition, the microprocessor can be notified of the state transition of the power supply voltage. The present invention optimizes the control of the input and output circuits through the operation mode, which can achieve faster speed and prolong battery life.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10: Memory device

110: Virtual Static Random Access Memory

120: Controller

130: Input and output circuit

140: High-speed mode circuit

150: Slow mode circuit

Claims (13)

A memory device includes: a virtual static random access memory, including an input and output circuit having a high-speed mode circuit and a slow mode circuit; and a controller, coupled to the virtual static random access memory, and configured according to The operating mode of the memory device adjusts the power supply voltage and the clock frequency, and generates a register setting code based on the adjusted power supply voltage and the adjusted clock frequency, wherein the virtual static random access memory is based on the The register setting code enables one of the high-speed mode circuit and the slow mode circuit, and disables the other of the high-speed mode circuit and the slow mode circuit. The memory device according to claim 1, wherein when the virtual static random access memory determines that the input/output circuit is set to the high-speed mode according to the register setting code, the high-speed mode circuit is enabled And disable the slow mode circuit; and enable the slow mode when the virtual static random access memory determines that the input/output circuit is set to the slow mode according to the register setting code The circuit also disables the high-speed mode circuit. The memory device according to claim 1, wherein the register setting code includes a mode setting or a delay count. The memory device according to claim 1, wherein the virtual static random access memory further includes a command decoder, and the command decoder is configured to receive and decode the register setting code to generate input control signals and transmit Control signal. The memory device according to claim 4, wherein the virtual static random access memory enables one of the high-speed mode circuit and the slow mode circuit according to the input control signal, and disables The other of the high speed mode circuit and the slow mode circuit. The memory device according to claim 1, wherein the controller further includes: a microprocessor coupled to the virtual static random access memory, the microprocessor according to the operation of the memory device Mode to generate a power management control signal and adjust the clock frequency, and the microprocessor generates the register setting code according to the change in the clock frequency, wherein the microprocessor and the virtual The static random access memory has a data bus and a communication number for reading and writing data; a power management circuit, coupled to the microprocessor, and the power management circuit generates a power control signal according to the power management control signal; and a power supply A circuit coupled to the virtual static random access memory, the microprocessor, and a power management circuit. The power circuit generates a power voltage according to the power control signal and supplies it to the microprocessor and the virtual static Random access memory. The memory device according to claim 4, wherein the input/output circuit further includes an input receiver, and the input receiver includes a first inverter configured to receive and invert the input control signal to generate an inverted signal Input control signal; A high-speed mode circuit, coupled to the first inverter, configured to receive the inverting input control signal and an input signal to generate a high-speed mode voltage; a slow mode circuit, coupled to the first inverter , Configured to receive the inverting input control signal and the input signal to generate a slow mode voltage; and an inverter, coupled to the high speed mode circuit and the slow mode circuit, and configured to receive the A high-speed mode voltage and the slow mode voltage, and an inverse logic operation is performed on the high-speed mode voltage and the slow mode voltage to generate the output signal. The memory device according to claim 7, wherein the high-speed mode circuit includes: a second inverter, coupled to the first inverter, configured to receive the inverting input control signal to generate a second inverter A node voltage; a first switch, the first terminal of the first switch is coupled to the power supply voltage, the control terminal of the first switch is coupled to the first node voltage, the second terminal of the first switch Coupled to the high-speed mode voltage; a differential amplifier having a current mirror load, configured to receive the input signal to generate the high-speed mode voltage; a series resistor, the first end of the series resistor is coupled to the A power supply voltage, the series electrical group includes a first resistor and a second resistor, the series resistor generates a reference voltage through a voltage dividing operation, and the first resistor is coupled between the power supply voltage and the reference voltage , A second switch, a first terminal of the second switch is coupled to the differential amplifier, a control terminal of the second switch is coupled to the first node voltage, and a second terminal of the second switch is coupled Connected to the ground voltage; and a third switch, the first end of the third switch is coupled to the second resistor, the control end of the third switch is coupled to the first node voltage, the third The second end of the switch is coupled to the ground voltage. The memory device according to claim 7, wherein the slow mode circuit includes a third inverter, a first terminal of the third inverter is coupled to the power supply voltage, and the third inverter The input terminal of the inverter is coupled to the input signal, the output terminal of the third inverter is coupled to the slow mode voltage; a fourth switch, the first terminal of the fourth switch is coupled to the first The second terminal of the three inverter, the control terminal of the fourth switch receives the inverting input control signal, the second terminal of the fourth switch is coupled to the ground voltage; and the fifth switch, the The first terminal of the fifth switch is coupled to the power supply voltage, the control terminal of the fifth switch receives the inverting input control signal, and the second terminal of the fifth switch is coupled to the slow mode voltage . The memory device according to claim 4, wherein the memory device further includes an off-chip driver, the off-chip driver includes: a first off-chip driver that receives the input control signal, the first off-chip driver Is enabled or disabled according to the transmission control signal; and the second off-chip driver is configured to be always activated, The off-chip driver is used for dynamically adjusting the current driving force of the off-chip driver according to the transmission control signal. The memory device according to claim 10, wherein when the virtual static random access memory determines that the input/output circuit is set to the high-speed mode according to the register setting code, it is triggered according to the transmission control signal Enabling the first off-chip driver; and when the virtual static random access memory determines that the input/output circuit is set to slow mode according to the register setting code, disable it according to the transmission control signal The first off-chip driver. The memory device according to claim 6, wherein the read and write data selection communication number is used to enable the microprocessor to learn the operation mode of the virtual static random access memory. An input and output buffer control method, suitable for a memory device, the memory device includes a virtual static random access memory and a controller, the virtual static random access memory includes a high-speed mode circuit and a slow mode circuit The input and output circuit, the input and output buffer control method includes: adjusting the power supply voltage and clock frequency according to the operation mode of the memory device; generating a register setting code based on the adjusted power supply voltage and the adjusted clock frequency; And enable one of the high-speed mode circuit and the slow mode circuit according to the register setting code, and disable the high-speed mode circuit and the slow mode The other one in the circuit.

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