JP2008502069A - メモリ・キャッシュ制御装置及びそのためのコヒーレンシ動作を実行する方法 - Google Patents

メモリ・キャッシュ制御装置及びそのためのコヒーレンシ動作を実行する方法 Download PDF

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JP2008502069A
JP2008502069A JP2007526629A JP2007526629A JP2008502069A JP 2008502069 A JP2008502069 A JP 2008502069A JP 2007526629 A JP2007526629 A JP 2007526629A JP 2007526629 A JP2007526629 A JP 2007526629A JP 2008502069 A JP2008502069 A JP 2008502069A
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Prior art keywords
cache
memory
coherency
address
main memory
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JP2007526629A
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English (en)
Japanese (ja)
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JP2008502069A5 (enExample
Inventor
ペレド，イタイ
アンシェル，モシェ
エフラト，ヤコブ
エルダー，アロン
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NXP USA Inc
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NXP USA Inc
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Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2008502069A publication Critical patent/JP2008502069A/ja
Publication of JP2008502069A5 publication Critical patent/JP2008502069A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
JP2007526629A 2004-06-08 2005-05-31 メモリ・キャッシュ制御装置及びそのためのコヒーレンシ動作を実行する方法 Pending JP2008502069A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04013507A EP1605360B1 (en) 2004-06-08 2004-06-08 Cache coherency maintenance for DMA, task termination and synchronisation operations
PCT/IB2005/051774 WO2005121966A2 (en) 2004-06-08 2005-05-31 Cache coherency maintenance for dma, task termination and synchronisation operations

Publications (2)

Publication Number Publication Date
JP2008502069A true JP2008502069A (ja) 2008-01-24
JP2008502069A5 JP2008502069A5 (enExample) 2008-07-10

Family

ID=34925293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007526629A Pending JP2008502069A (ja) 2004-06-08 2005-05-31 メモリ・キャッシュ制御装置及びそのためのコヒーレンシ動作を実行する方法

Country Status (7)

Country Link
US (1) US20080301371A1 (enExample)
EP (1) EP1605360B1 (enExample)
JP (1) JP2008502069A (enExample)
CN (1) CN101617298B (enExample)
AT (1) ATE458222T1 (enExample)
DE (1) DE602004025556D1 (enExample)
WO (1) WO2005121966A2 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8060915B2 (en) * 2003-12-30 2011-11-15 Entrust, Inc. Method and apparatus for providing electronic message authentication
US8230486B2 (en) * 2003-12-30 2012-07-24 Entrust, Inc. Method and apparatus for providing mutual authentication between a sending unit and a recipient
US9191215B2 (en) 2003-12-30 2015-11-17 Entrust, Inc. Method and apparatus for providing authentication using policy-controlled authentication articles and techniques
US9281945B2 (en) 2003-12-30 2016-03-08 Entrust, Inc. Offline methods for authentication in a client/server authentication system
US8966579B2 (en) * 2003-12-30 2015-02-24 Entrust, Inc. Method and apparatus for providing authentication between a sending unit and a recipient based on challenge usage data
US8612757B2 (en) * 2003-12-30 2013-12-17 Entrust, Inc. Method and apparatus for securely providing identification information using translucent identification member
US20090210629A1 (en) * 2008-02-15 2009-08-20 International Business Machines Corporation Method, system and computer program product for selectively purging cache entries
JP5728982B2 (ja) * 2010-02-26 2015-06-03 株式会社Ｊｖｃケンウッド 処理装置および書込方法
CN102035733B (zh) * 2010-11-29 2013-04-10 武汉微创光电股份有限公司 通过以太网建立串行数据透明传输通道的方法
US9026698B2 (en) * 2013-03-15 2015-05-05 Intel Corporation Apparatus, system and method for providing access to a device function
KR20150136045A (ko) * 2013-03-28 2015-12-04 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 리플렉티브 메모리를 이용한 일관성 구현
WO2015195076A1 (en) * 2014-06-16 2015-12-23 Hewlett-Packard Development Company, L.P. Cache coherency for direct memory access operations
CN106302374B (zh) * 2015-06-26 2019-08-16 深圳市中兴微电子技术有限公司 一种用于提高表项访问带宽和原子性操作的装置及方法
US20180054480A1 (en) * 2016-08-17 2018-02-22 Microsoft Technology Licensing, Llc Interrupt synchronization of content between client device and cloud-based storage service
US10157139B2 (en) * 2016-09-19 2018-12-18 Qualcomm Incorporated Asynchronous cache operations
CN109101439B (zh) * 2017-06-21 2024-01-09 深圳市中兴微电子技术有限公司 一种报文处理的方法及装置
CN114157621A (zh) * 2020-09-07 2022-03-08 华为技术有限公司 一种发送清除报文的方法及装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06309231A (ja) * 1993-04-27 1994-11-04 Agency Of Ind Science & Technol キャッシュメモリ制御方法
JPH0895861A (ja) * 1994-09-22 1996-04-12 Toshiba Corp キャッシュメモリを有する電子計算機
JPH08335189A (ja) * 1995-06-09 1996-12-17 Nec Corp キャッシュメモリ装置
JP2004102825A (ja) * 2002-09-11 2004-04-02 Renesas Technology Corp キャッシュメモリ制御装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4713755A (en) * 1985-06-28 1987-12-15 Hewlett-Packard Company Cache memory consistency control with explicit software instructions
US6378047B1 (en) * 1997-07-07 2002-04-23 Micron Technology, Inc. System and method for invalidating set-associative cache memory with simultaneous set validity determination
DE69903707T2 (de) * 1999-02-18 2003-07-10 Texas Instruments France, Villeneuve Loubet Optimierte Hardware-Reinigungsfunktion für einen Daten-Cache-Speicher mit virtuellen Indizes und Tags
ATE548695T1 (de) * 2000-08-21 2012-03-15 Texas Instruments France Softwaregesteuerte cache-speicherkonfiguration
DE60041444D1 (de) * 2000-08-21 2009-03-12 Texas Instruments Inc Mikroprozessor
EP1182563B1 (en) * 2000-08-21 2009-09-02 Texas Instruments France Cache with DMA and dirty bits
US8010682B2 (en) * 2004-12-28 2011-08-30 International Business Machines Corporation Early coherency indication for return data in shared memory architecture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06309231A (ja) * 1993-04-27 1994-11-04 Agency Of Ind Science & Technol キャッシュメモリ制御方法
JPH0895861A (ja) * 1994-09-22 1996-04-12 Toshiba Corp キャッシュメモリを有する電子計算機
JPH08335189A (ja) * 1995-06-09 1996-12-17 Nec Corp キャッシュメモリ装置
JP2004102825A (ja) * 2002-09-11 2004-04-02 Renesas Technology Corp キャッシュメモリ制御装置

Also Published As

Publication number Publication date
WO2005121966A2 (en) 2005-12-22
DE602004025556D1 (de) 2010-04-01
EP1605360A1 (en) 2005-12-14
WO2005121966A3 (en) 2006-06-22
ATE458222T1 (de) 2010-03-15
US20080301371A1 (en) 2008-12-04
CN101617298B (zh) 2012-03-21
CN101617298A (zh) 2009-12-30
EP1605360B1 (en) 2010-02-17

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