JP2008501119A - Semiconductor structure having stress sensitive elements and method for measuring stress in a semiconductor structure - Google Patents

Abstract

The semiconductor structure has a stress sensitive element. The characteristic of the stress sensitive element represents the stress of the semiconductor structure (100). Furthermore, the semiconductor structure may have an electrical element (110). The stress sensitive element and the electrical element have part of a common layer structure (107). The analyzer may be adapted to determine the characteristics of the stress sensitive element representing the stress in the semiconductor structure (100) and the characteristics of the electrical element (110). The stress sensitive element can be characterized and the manufacturing process can be modified based on the determined characteristics of the stress sensitive element. In order to investigate the effect of stress on the electrical element, the characteristics of the electrical element (110) can be related to the characteristics of the stress sensitive element.

Description

  The present invention relates to the field of semiconductor device manufacturing and, more particularly, to the measurement of stress in semiconductor structures.

  An integrated circuit has many individual circuit elements such as transistors, capacitors, and resistors. These elements are internally connected through conductive lines to form complex circuits such as memory devices, logic elements, and microprocessors. To improve integrated circuit performance, feature sizes need to be reduced. In addition to the increase in operation speed due to the shortened signal transmission time, the feature size can be reduced to increase the number of functional elements in the circuit in order to expand the function of the circuit. . Today, high performance semiconductor structures can have feature sizes of 0.1 μm or less.

  As the size of structural elements such as circuit elements and conductive lines becomes smaller, the influence of stress becomes more and more important. The conductive line is usually embedded in an interlayer insulating film. When stress is generated in the interlayer insulating film, mechanical connection between the conductive line and the interlayer insulating film and / or a structural element (such as another conductive line or a circuit element) to which the conductive line is connected may be weakened. This adversely affects the stability of the integrated circuit and causes an increase in contact resistance between the conductive lines. The increase in contact resistance adversely affects the function of the integrated circuit, and excessive heat generation may cause the circuit to deteriorate rapidly. Further, due to stress, the conductive line may be peeled off from the structural element to which the conductive line is connected, and as a result, a failure of the integrated circuit may occur.

  When the interlayer insulating film includes a low-k material used to reduce signal transmission delay due to parasitic capacitance, the stress of the interlayer insulating film can be particularly inconvenient. Since such a material has a relatively low bonding force, a stress may cause a crack or a conductive line may be peeled off from the interlayer insulating film.

  Conversely, stress can be used deliberately to improve the performance of circuit elements. The tensile or compressive stress of the semiconductor material can change the mobility of electrons and holes. When tensile stress is generated, the mobility of electrons increases, and depending on the magnitude of the tensile stress, an increase of up to 20% can be obtained, which directly leads to an increase in electrical conductivity. The stress-induced increase in electron mobility can be used to improve the performance of N-type field effect transistors by increasing the mobility of charge carriers in the channel region. In contrast, compressive stress in the channel region of a P-type field effect transistor increases hole mobility and can be used to improve transistor performance.

  In order to generate tensile or compressive stresses in the channel region of the transistor, it has been proposed, for example, to insert a silicon / germanium layer or a silicon / carbon layer below or in the channel region. Alternatively, stress can be generated in the channel region by depositing a strained spacer layer and etching the strained spacer layer to form a spacer element having tensile or compressive stress near the gate electrode. .

  For this reason, stresses in the integrated circuit can significantly affect the performance of the circuit. Thus, the measurement of stress in a semiconductor structure can be important in the design of an integrated circuit or its structural elements.

  The following describes a method for measuring stress in a semiconductor structure according to the state of the art. Usually, the curvature of a substrate is measured using a profiler (profile meter), which is a device suitable for scanning the surface of the substrate with a stylus. Thereafter, a layer of material is deposited on the substrate. When stress is generated by the deposition of a layer of material, the substrate bends. For this reason, the curvature of the substrate changes. After depositing the layer, the curvature of the substrate is measured again. Thereafter, the stress in the film is calculated from the curvature measured before and after the deposition of the layer, using an equation derived by elasticity theory.

  One of the problems associated with the measurement of stress in semiconductor structures by conventional methods is that the thickness of the substrate is included in the stress calculation. As the substrate becomes thicker, the change in curvature caused by receiving a predetermined stress becomes smaller, resulting in a decrease in measurement sensitivity. On the other hand, thin substrates are easily deformed by gravity, which can also adversely affect measurement accuracy.

  Another problem with the measurement of stresses in semiconductor structures by conventional methods is that the curvature of the substrate must be measured over a range of at most several centimeters, resulting in the substrate and / or the deposited layers. If there is non-uniformity, there is a point that an error in measurement results may occur.

  Yet another problem related to the measurement of stresses in semiconductor structures by conventional methods is to provide a substrate made of one of these materials to measure the stress between the first material and the second material. There is a point. This can significantly increase the cost of the measurement process, especially when the material is very expensive and / or difficult to process for measurement.

  Yet another problem with measuring stress in a semiconductor structure by conventional methods is that the measurement cannot be performed in-situ during processing of the semiconductor structure.

  In view of the above problems, there is a need for a system and method that allows for precise measurement of stress in a semiconductor structure.

  The following provides an overview of the invention so that the basics of some aspects of the invention can be understood. This summary is not an extensive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some of the concepts in a concise manner prior to the detailed description that follows.

  According to an illustrative embodiment of the invention, the semiconductor structure has a stress sensitive element. The characteristic of the stress sensitive element represents the stress state in the semiconductor structure. Furthermore, the semiconductor structure has electrical elements. The stress sensitive element and the electric element have a part of a common layer structure.

  According to another illustrative embodiment of the present invention, a system for measuring stress in a semiconductor structure includes a stress sensitive element formed in the semiconductor structure and an electrical element formed in the semiconductor structure. Have. The stress sensitive element and the electric element have a part of a common layer structure. The system includes a first analyzer adapted to determine a characteristic of a stress sensitive element representing a stress state in a semiconductor structure and a second analysis adapted to determine a characteristic of the electrical element. Part.

  According to yet another illustrative embodiment of the present invention, a system for measuring stress in a semiconductor structure includes a stress sensitive element formed in the semiconductor structure and an analyzer. The analysis unit has a light source and a photodetector. The analysis unit is adapted to determine a characteristic of the stress sensitive element representing a stress state in the semiconductor structure.

  According to yet another illustrative embodiment of the present invention, a method for adjusting a manufacturing process of a semiconductor structure includes forming a first semiconductor structure by the manufacturing process. The method further includes forming a stress sensitive element in the first semiconductor structure. The characteristics of the stress sensitive element are determined. This characteristic represents the stress state in the first semiconductor structure. The manufacturing process is changed based on the determined characteristics of the stress sensitive element. A second semiconductor structure is formed by the modified manufacturing process, and an electrical element is formed in the second semiconductor structure.

  According to yet another illustrative embodiment of the present invention, a method for investigating the effect of stress on an electrical element of a semiconductor structure includes the steps of forming a stress sensitive element in the semiconductor structure, and the electrical element in the semiconductor structure. Forming a step. The characteristics of the stress sensitive element are determined. This characteristic represents the stress state in the semiconductor structure. The characteristics of the electrical element are determined. The characteristics of the electrical element are related to the characteristics of the stress sensitive element.

  The invention will be understood from the following description in conjunction with the accompanying drawings, in which: In the accompanying drawings, the same reference signs refer to the same elements.

  While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and are herein described in detail. However, the detailed description of this particular embodiment is not intended to limit the invention to the particular form disclosed, but on the contrary, the spirit of the invention as defined by the appended claims and It should be understood that all variations, equivalents and alternatives included in the scope are included.

  Exemplary embodiments of the invention are described below. For the sake of brevity, not all features of an actual implementation are described herein. Of course, developing an actual embodiment requires a number of implementation specific decisions to achieve specific development goals, such as adapting to system and business constraints. It is understood that it varies depending on the implementation. Further, although this type of development work is complex and time consuming, it will be understood that it is a routine work for those skilled in the art who benefit from the present disclosure.

  The present invention will be described with reference to the accompanying drawings. For purposes of explanation only, various structures, systems and devices are schematically shown in the drawings so as not to obscure the present invention with details that are known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present invention. The terms used herein should be understood and interpreted to have the same meaning as understood by those of ordinary skill in the relevant art. When a phrase is used consistently in this specification, the phrase has a special definition, i.e. it is used normally and routinely and does not have a definition different from the meaning understood by those skilled in the art. When a word has a special meaning, i.e. used in a meaning that is different from the understanding of those skilled in the art, such special definition is explicitly stated herein and the special definition is directly and directly Show clearly.

  The present invention enables the measurement of mechanical stress in a semiconductor structure to determine the effect of mechanical stress on electrical elements (such as conductive lines or field effect transistors) and to adjust the manufacturing process of the semiconductor structure To do. Stress sensitive elements can be implemented during the wafer level manufacturing process, depending on the processing steps used in semiconductor manufacturing. Measurements can be performed in-situ during manufacturing of the semiconductor structure, or after completion of the semiconductor structure, to monitor the increase and / or relaxation of stress in the semiconductor structure. It may be done at both times. The present invention provides a semiconductor structure manufactured by monitoring stress characteristics in a semiconductor structure, such as a wafer having one or more integrated circuits, in-situ or in-line during a manufacturing process in a factory. It can be used to modify the manufacturing process to control the stress within.

  According to an illustrative embodiment, the semiconductor structure has a stress sensitive element, and the characteristic of the stress sensitive element represents the stress state in the semiconductor structure. Furthermore, the semiconductor structure may have electrical elements. The stress sensitive element and the electrical element may have a part of a common layer structure. By determining the characteristics of the stress sensitive element, the stress in the semiconductor structure that affects the electrical element can be measured. The characteristics of the electrical element can be determined and correlated with the characteristics of the stress sensitive element to examine the effect of stress on the performance of the electrical element.

  In another embodiment of the present invention, a stress sensitive element is formed in the first semiconductor structure and a characteristic of the stress sensitive element representing a stress state in the first semiconductor structure is determined. Thereafter, the manufacturing process used for manufacturing the first semiconductor structure is changed in consideration of the stress state in the first semiconductor structure estimated from the characteristics of the stress sensitive element. A second semiconductor structure is manufactured by the modified manufacturing process, and an electrical element is formed in the second semiconductor structure. For this reason, the electrical element of the second semiconductor structure can be placed in a clearly defined stress state.

  A system for measuring stress in a semiconductor structure may include a stress sensitive element formed in the semiconductor structure and an analyzer adapted to determine characteristics of the stress sensitive element. More specifically, the analysis unit can be configured to determine the characteristics by optical means. Furthermore, a second analysis unit adapted to determine the characteristics of the electrical elements formed in the semiconductor structure can be provided.

  FIG. 1 is a schematic diagram of a semiconductor structure 100 according to an illustrative embodiment of the invention. The semiconductor structure 100 has a substrate 101. A layer structure 107 is formed on the substrate 101. The layer structure 107 includes a first material layer 102, a second material layer 104, and a third material layer 105. Stress sensitive elements are provided in the layer 102 of the semiconductor structure 100 in the form of lines 103 of transmissive material extending in the longitudinal direction x. Layer 105 has electrical elements provided in the form of conductive lines 110. Conductive line 110 is separated from the rest of layer 105 by insulating portion 106.

The transmissive material of line 103 may include glass, polymer, ceramic material, or any other material that is highly transmissive to light. Here, it should be understood that the term “light” includes infrared light and ultraviolet light in addition to the visible wavelength region. The ceramic material may include aluminum oxide (Al ₂ O ₃ ). Layer 102 may include a first dielectric material such as silicon dioxide. Layer 103 may include a second dielectric material, such as a low-k material, such as hydrogenated silicon oxycarbide (SiCOH). The third material can include a metal such as copper. In another embodiment of the present invention, the first material and the second material may comprise substantially the same dielectric material (such as silicon dioxide).

  In yet another embodiment of the invention, the semiconductor structure 100 may have electrical elements other than conductive lines. More specifically, the electric element may include a field effect transistor.

  In such an embodiment, layers 102 and 105 can include silicon. Layer 104 is adapted to create a compressive or tensile stress in layer 105 and may include, for example, a silicon and germanium alloy or a silicon and carbon alloy. A channel region of a field effect transistor can be formed in layer 105. The substrate 101 can include an insulating material such as silicon dioxide. For this reason, the field effect transistor is formed with a silicon-on-insulator configuration. In another embodiment, the substrate 101 may include a semiconductor material (such as silicon).

  The characteristic of the stress sensitive element 103 represents the stress state in the semiconductor structure 100.

  This characteristic may be the optical path length of the light passing through the line 103 of transmissive material. When stress is present in the semiconductor structure 100, the line 103 of permeable material is deformed. The line 103 can be stretched in the longitudinal direction x (resulting in a lengthening of the line 103) or compressed in the longitudinal direction x (resulting in the line 103 as a result) depending on whether the layer structure 107 is subjected to tensile pressure or compressive stress. Becomes shorter).

  When the line 103 becomes longer, the optical path length of the line 103 made of a transmissive material becomes longer, and when the line 103 becomes shorter, the optical path length of the line 103 made of a transmissive material becomes shorter. For this reason, the optical path length of light passing through the line 103 of transmissive material is a characteristic representing the stress state in the semiconductor structure 100 of the line 103.

  In another embodiment of the present invention, the characteristic of the line 103 of transmissive material representing the stress state in the semiconductor structure 100 is the wavelength of light reflected by the line 103 of transmissive material.

  For this purpose, the line 103 may have a grating region whose refractive index changes periodically in the longitudinal direction x. This grating region has a zone where the refractive index of the transmissive material is higher than the rest of the line 103. The high refractive index zones are provided at predetermined intervals.

  Due to the change in refractive index, light is scattered by the Bragg effect. When light having a predetermined wavelength passes through a line 103 of transparent material in a propagation direction substantially parallel to the longitudinal direction x, a part of the light is posterior to the propagation direction in each zone having a high refractive index. Scattered.

  If the wavelength of light in the transmissive material is substantially equal to twice the spacing of the high index zones, some of the light reflected in the high index zones interferes constructively. As a result, most of the light is reflected by the grating portion and the transmittance of the line 103 of transmissive material for this light is reduced.

  Conversely, when the wavelength of light in the transmissive material is significantly different from twice the spacing of the high refractive index zones, the portion of the light reflected by the high refractive index zones interferes so as to weaken. For this reason, light is not reflected by the grating region but passes through the grating region.

  As successive wavelengths of light pass through the line 103 of transparent material, the portion of light having a wavelength substantially equal to twice the spacing of the high refractive index zones in the transparent material is reflected. The remaining light is substantially transmitted through the line 103 of transmissive material. For this reason, the spectrum of the reflected light includes a characteristic wavelength peak representing the interval between the high refractive index zones. The spectrum of transmitted light has a minimum at the characteristic wavelength.

  When stress is present in the semiconductor structure 100, the line 103 of permeable material is stretched or compressed. Thereby, the space | interval of a high refractive index zone increases / decreases. As a result, the characteristic wavelength of the line 103 increases or decreases. Thus, the characteristic wavelength is a characteristic representing the stress state within the semiconductor structure 100.

  Line 103 may extend over most of semiconductor structure 100. In some embodiments of the present invention, the semiconductor structure 100 comprises a wafer having a plurality of chips. The plurality of chips have an electric element having the above electric element. The line 103 can be formed at an interval between chips (scribe line) provided for cutting the wafer after the manufacturing process. This advantageously allows stress sensitive elements to be provided in the semiconductor structure with very little extra wafer area required. In another embodiment of the invention, the wafer has a test structure in which lines 103 are formed.

  The lattice region may constitute the majority of the line 103 of transmissive material. Thus, the average stress in the semiconductor structure 100 can be measured. In another embodiment of the invention, the lattice region constitutes only a part of the semiconductor structure 100. The length of the grating region can be less than 400 μm. In another embodiment of the present invention, the length of the grating region can be less than 100 μm or less than 200 μm. This is advantageous because it allows a specific measurement of stress in a narrow region of the semiconductor structure 100.

  In yet another embodiment of the present invention, the characteristic of the line 103 of transmissive material representing the stress state in the semiconductor structure 100 is the birefringence of light in the transmissive material. In such embodiments, the transmissive material can include glass, polymer, or any other transmissive material that exhibits stress-induced birefringence known to those skilled in the art.

  When stress is present in the semiconductor structure 100, the line 103 of permeable material is also stressed. This stress causes birefringence of the transmissive material. As is well known to those skilled in the art, in birefringence, the refractive index of the material is determined by the direction of polarization of light through the line 103 of transmissive material. For this reason, the polarization state of the light passing through the line 103 can change.

  FIG. 5 shows a semiconductor structure according to another embodiment of the present invention. The semiconductor structure 500 has a substrate on which a layer structure 507 is formed. The layer structure 507 includes a first material layer 502, a second material layer 504, and a third material layer 505. Similar to the layer structure 107 of the semiconductor structure 100 described with reference to FIG. 1, the layer structure 507 is an electrical element provided in the form of a conductive line 510 separated from the rest of the layer 505 by an insulating portion 506. Have In another embodiment, the conductive element may be provided in the form of a field effect transistor.

  In addition, the semiconductor structure 500 also has an elastic element 509. The elastic element 509 includes a beam 520 that crosses the trench 513 and is fixed to the side walls 511 and 512 of the trench 513. The side walls 511 and 512 are mounts, and a distance h is defined between the beam 520 and the bottom surface of the trench 513. The beam 520 includes a part of the layer 504 and a part of the layer 505.

  The beam 520 need not have two layers of material. In another embodiment of the present invention, the beam 520 may have only one layer of material or three or more layers of material.

  When compressive stress is present in the layer structure 507, the beam 520 receives a force acting from the side walls 511 and 512 toward the central portion of the beam 520, and the beam 520 can be bent. The behavior of beam 520 under the influence of force can be determined by elasticity theory known to those skilled in the art. When the force is small, the beam stays straight. When the force exceeds the critical strength, the beam bends. At this time, the central portion of the beam is lifted by the bending height d. The bend and the bend height d of the beam 520 represent the stress state in the semiconductor structure 500. From the bending height d, the stress in the semiconductor structure 500 can be calculated.

  The beam 520 of the semiconductor structure 500 according to the present invention need not be bent upward as shown in FIG. In another embodiment of the present invention, the beam 520 is bent downward so that the height of the central portion of the beam 520 from the bottom surface of the trench 513 is lower than the portions close to the side walls 511 and 512, and the bending height d The value of may be a negative value.

  When tensile strain is present in the semiconductor structure 500, the beam is subjected to a force acting toward the side walls 511, 512. Such a force tends to stretch the beam 520. As the beam 520 stretches, the stiffness of the beam 520 relative to the force acting on the beam increases. Thus, the stiffness of the beam 520 is a characteristic of the beam 520 that represents the stress state within the semiconductor structure 500. From the stiffness of the beam 520, the stress in the semiconductor structure 500 can be calculated using elasticity theory.

  FIG. 7 illustrates a semiconductor structure 700 according to another embodiment of the present invention. The semiconductor structure 700 includes a substrate 701, over which a layer structure 707 having a first material layer 502, a second material layer 504, and a third material layer 505 is formed. The layer structure 707 can include an electrical element having a conductive line 710 and an insulating portion 706 that separates the conductive line 710 from other portions of the layer 705. In another embodiment of the invention, the electrical element can comprise a field effect transistor.

  The semiconductor structure 700 has an elastic element 709. The elastic element has a cantilever beam 720 provided on the trench 713 and fixed to the side wall 711 of the trench 713. The side wall 711 is a mount and defines a space h ′ between the cantilever 720 and the bottom surface of the trench 713. The beam has a portion of layers 704 and 705. When stress is applied to one or both of the layers 704, 705, deflection of the cantilever 720, including the curvature of the cantilever 720, occurs. Due to the bending, the tip of the cantilever beam 720 is lifted by the bending height b. The bending height b takes a positive value or a negative value depending on whether the cantilever beam 720 is bent upward or downward.

  The relationship between the stress in the layers 704 and 705 and the bending height b can be derived by elasticity theory known to those skilled in the art. For this reason, the curvature of the cantilever beam 720 and the curvature height b are the characteristics of the elastic element representing the stress state in the semiconductor structure 700.

  The present invention is not limited to a semiconductor structure having one stress sensitive element. The semiconductor structure according to the present invention may have a plurality of stress sensitive elements. These stress sensitive elements are substantially the same and can be located in different parts of the semiconductor structure. For this reason, the stress of the different part of a semiconductor structure can be determined.

  In another embodiment of the invention, the semiconductor structure has different stress sensitive elements. For example, the semiconductor structure may have an array of beams similar to the beams 520 of the semiconductor structure 500 described above with reference to FIG. The beams in the array can vary in length or width. As is well known to those skilled in the art, the critical stress at which a beam bends depends on the width and length of the beam, and a long, narrow beam has a lower critical stress than a short, narrow beam. For this reason, if it is determined whether or not the beams are bent with respect to a plurality of beams having different dimensions, it is possible to obtain information on the strength of strain even when the bending height of the beams is not measured.

  In yet another embodiment of the invention, the semiconductor structure may have a plurality of different types of stress sensitive elements. For example, the plurality of stress sensitive elements can be a beam, a cantilever beam, and a line of transmissive material. Thus, the stress in the semiconductor structure can be measured by a plurality of different methods. This is advantageous because the stress can be measured more accurately.

  FIG. 2 shows a system 200 for measuring stress in a semiconductor structure according to one illustrative embodiment of the invention. The system 200 includes a semiconductor structure 100 as described above with reference to FIG. The system 200 further includes a light source 201 such as a laser. The light source 201 is adapted to emit a light beam 202. The first beam splitter 203 is adapted to split the light beam 202 into a first light beam portion 205 and a second light beam portion 204. The input coupler 210 is adapted to couple the first light beam portion 205 to the line 103 of transmissive material in the semiconductor structure 100. The input coupler 210 can include a first focusing optical element that can include a lens. The focus of the first focusing optical element can be set at the first end of the line 103 of transmissive material. The output coupler 211 is adapted to couple the first light beam 205 emanating from the line 103 of transmissive material. Similar to the input coupler 210, the output coupler 211 can include a second focusing optical element that can include a lens. The focal point of the second focusing optical element can be set at the second end of the line 103 of transmissive material.

  The first mirror 207 is adapted to reflect the first light beam portion 205 towards the second beam splitter 208. The second mirror 206 is adapted to reflect the second light beam portion 204 towards the second beam splitter 208.

  In the second beam splitter 208, the first light beam portion 205 is combined with the second light beam portion 204 to form an integrated light beam 216. The first light flux portion 205 and the second light flux portion 204 interfere with each other. For this reason, the first beam splitter 203, the first mirror 207, the second mirror 206, and the second beam splitter 208 form an interferometer as a whole.

  The photodetector 209 is adapted to measure the intensity of the integrated light beam 216. The intensity of the integrated light beam 216 is determined by the optical path length of light passing through the line 103 of the transmissive material. This is because the phase difference between the first light beam portion 205 and the second light beam portion 204 depends on the optical path length. Because it changes. Thus, the change in the optical path length of the light in the line 103 of transmissive material can be determined from the change in the intensity of the integrated light beam 216 measured by the photodetector 209. For this reason, the interferometer, the light source 201, and the photodetector 209 form a first analyzer adapted to determine the optical path length of the light in the line 103 of transmissive material.

  Furthermore, the system 200 can include a second analysis unit 214. The first wire 212 and the second wire 213 electrically connect the second analysis unit and the electric element of the semiconductor structure 100.

  In an embodiment of the invention in which the electrical element has a conductive line 110, the second analyzer 214 comprises a power source, an ammeter adapted to measure the amperage of the current flowing through the conductive line 110, and a power source. A voltmeter adapted to determine the supplied voltage. Thus, Ohm's law can be used to determine the resistance of conductive line 110, which contributes to the contact resistance between conductive line 110 and another structural element in semiconductor structure 100. May also be included.

  In the embodiment of the present invention in which the semiconductor structure 100 includes a field effect transistor, the second analysis unit 214 additionally performs electrical connection between the second power source, the gate electrode of the field effect transistor, and the second power source. And a third wire connected to the. The first wire and the second wire are each configured to electrically connect the power source and one of the source region or the drain region of the field effect transistor. The voltage supplied by the second power source can be used to make the channel region of the field effect transistor conductive. Ammeters, voltmeters and power supplies are used to determine the resistance of the channel region of the field effect transistor, from which the mobility of charge carriers in the channel region can be calculated.

  In another embodiment of the present invention, the second analysis unit 214 and the wires 212 and 213 may be omitted. In such an embodiment, the semiconductor structure 100 need not have an electrical element.

  In yet another embodiment of the present invention, the interferometer may include optical fibers instead of the first and second beam splitters 203, 208 and the first and second mirrors 206, 207. The first split optical fiber is connected to the light source 201 and is adapted to split the light beam 202 into a first light beam portion 205 and a second light beam portion 204. The first end 205 of the first split optical fiber having the first light beam portion 205 is formed by connecting the first end of the first split optical fiber to the semiconductor structure 110, etc. Connected to the first end. Thus, the first end of the first split optical fiber forms an input coupler adapted to couple the light emitted from the light source 201 to the line 103 of transmissive material. The first end of the second split optical fiber is connected to the second end of the line 103 of transmissive material, thus forming an output coupler adapted to couple light exiting from the line 103. ing. The second end of the first optical fiber and the second end of the second optical fiber are connected to each other. For this reason, the second split optical fiber is adapted to form the integrated light beam 216 by integrating the first light beam portion 205 and the second light beam portion 204. The second split optical fiber is connected to the photodetector 209.

  FIG. 4 illustrates a system 400 for measuring stress in a semiconductor structure according to another embodiment of the invention. The system 400 includes a semiconductor structure 100 as described above with reference to FIG. In addition, the system 400 includes a light source 401 and a photodetector 409. The first optical fiber 414 connects the light source 401 to the semiconductor structure 100 and is adapted to supply light emitted from the light source 401 to the line 103 of transmissive material in the semiconductor structure 100. The second optical fiber 416 connects the semiconductor structure 100 to the photodetector 409 and supplies the light transmitted through the line 103 of transmissive material to the photodetector 409. The light source 401, the light detector 409, and the first and second optical fibers 415, 416 form an analyzer that is adapted to determine the optical properties of the line 103 of transmissive material as a whole.

  In addition, the system 400 is similar to the second analyzer 214 of the system 200 described with reference to FIG. 2, and the second analyzer is adapted to determine the characteristics of the electrical elements of the semiconductor structure 100. 414. The second analysis unit 414 can be connected to an electric element by wires 412 and 413.

  The photodetector 409 can have a spectrometer. For this reason, the analyzer is adapted to determine the spectrum of the light transmitted through the line 103 of transparent material. A photodetector with a spectrometer is particularly advantageous when the line 103 of transmissive material of the semiconductor structure 100 has a grating region. In such an embodiment of the present invention, the light source 401 can be configured to emit light of multiple wavelengths. More particularly, the light source 401 can be adapted to emit light in a continuous band of wavelengths near the characteristic wavelength of the grating region when there is no distortion in the semiconductor structure 100.

  The spectrum of transmitted light includes the minimum value at the characteristic wavelength of the grating region, which represents the stress in the semiconductor structure 100. For this reason, the stress in the semiconductor structure 100 can be determined from the position of the minimum value in the spectrum.

  In another embodiment of the present invention, a branched optical fiber is used instead of the optical fibers 415 and 416. Similar to the optical fiber 415, the branch optical fiber is connected to a line 103 of transmissive material in the semiconductor structure 100. The first end of the branch optical fiber is connected to the light source 401. The second end of the branch optical fiber is connected to the photodetector 409. For this reason, the branch optical fiber guides the light emitted from the light source 401 to the line 103 of the transparent material and guides the light reflected by the line 103 to the photodetector 409. For this reason, the analyzer is adapted to determine the spectrum of light reflected by the line 103 of transparent material. The spectrum includes peaks at characteristic wavelengths in the lattice region of line 103. The stress in the semiconductor structure 100 can be calculated from the position of the peak in the spectrum.

  In another embodiment of the invention, the light source 401 is adapted to emit polarized light having a first polarization direction. In another embodiment, the light source is adapted to emit unpolarized light, and the first light source 401 and the first optical fiber 415 or the first optical fiber 415 and the semiconductor structure 100 are the first. A first polarization filter adapted to transmit light polarized in the polarization direction of the first polarization filter may be provided. For this reason, polarized light having a predetermined polarization direction is coupled to the line 103 of transmissive material.

  Photodetector 409 is adapted to detect the intensity of light that is transmitted through semiconductor structure 100 and has a second polarization direction. For this purpose, the photodetector can have an optical sensor adapted to detect the intensity of the light provided to the second polarization filter. In another embodiment, the second polarization filter may be provided between the semiconductor structure 100 and the second optical fiber 416. For this reason, the analyzer is adapted to detect the polarization characteristics of the light transmitted through the line 103 of transparent material.

  An analyzer adapted to detect polarization properties is particularly advantageous when the property representing the stress in the line 103 of the transparent material of the semiconductor structure 100 is birefringence of light in the transparent material. .

  In order to detect the birefringence of light in the line 103 of transparent material, the first polarization direction and the second polarization direction can be orthogonal to each other. If there is no birefringence in the transmissive medium, the second polarization filter substantially blocks the light transmitted through the line 103. However, when the transmissive material is birefringent, the polarization characteristics of the transmitted light change, and a part of the transmitted light passes through the second polarization filter. The intensity of the light passing through the second filter and measured by the photodetector represents the stress in the semiconductor structure 100.

  In yet another embodiment of the present invention, the system 400 has a first focusing element instead of the optical fibers 415 and 416 to couple the light emitted by the light source 401 to the line 103 of transmissive material. And an output coupler configured to couple light exiting from the line 103 of transmissive material. Each of the first focusing element and the second focusing element may have a lens.

  FIG. 8 illustrates a system 800 for measuring stress in a semiconductor structure according to yet another embodiment of the present invention. The system 800 includes a semiconductor structure 500 as described with reference to FIG. In addition, the system 800 includes a light source 801 adapted to emit a light beam 802. The beam splitter 803 is adapted to split the light beam 802 into a first light beam portion 805 and a second light beam portion 804.

  A first focusing element 810 that may have a lens is provided between the beam splitter 803 and the semiconductor structure 500. The first light beam portion 805 passes through the first focusing element and enters the semiconductor structure 500. A second focusing element 811 that may have a lens is provided between the beam splitter 803 and the reference plane 806. The reference plane 806 can be a plane. The second light beam portion 804 passes through the second focusing element and enters the reference surface 806.

  First light flux portion 805 is reflected from semiconductor structure 500. The first reflected light 812 reflected from the surface of the beam 520 passes through the first focusing element 812 and the beam splitter 803 and travels toward the photodetector 809. Similarly, the second light beam portion 804 is reflected from the reference surface 806. The second reflected light 813 reflected from the reference surface 806 is reflected by the beam splitter 803 and travels toward the photodetector 809. In the beam splitter 803, the first reflected light 812 and the second reflected light 813 interfere with each other, and an integrated light beam 816 is formed. For this reason, the beam splitter 803, the first focusing element 810, the second focusing element 811 and the reference plane 806 form an interferometer as a whole. The photodetector 809 is adapted to measure the intensity of the integrated light beam 816.

  The first focusing element 810 and the second focusing element 811 can be adapted such that the beam 520 and the reference plane 806 are imaged on the photodetector 809. Therefore, a superposition of the image of the beam 520 and the image of the reference plane 806 is formed at the position of the photodetector 809. The photodetector 809 can include a two-dimensional sensor configured to record the superposition of the image of the beam 520 and the image of the reference plane 806. In certain embodiments of the invention, the detector 809 may comprise a charge coupled device or a photographic film.

  The intensity of the integrated light beam 816 represents the phase difference between the first reflected light 812 and the second reflected light 813. The phase difference represents the height profile of the beam 520. When the beam 520 is bent, the height profile of the beam 520 has a curved shape, and the height of the central portion is higher than the height of the peripheral portion of the beam 520 near the side walls 511 and 512. The difference in height between the central portion and the peripheral portion is substantially equal to the bending height d, which is a characteristic of the beam 520 representing the stress in the semiconductor structure 500.

  Thus, the stress in the semiconductor structure 500 can be determined from an analysis of the intensity of the integrated beam 816 measured by the detector 809.

  In another embodiment of the present invention, the system 800 includes the semiconductor structure 700 described above with reference to FIG. The first beam portion 805 is incident on the semiconductor structure 700 and the first reflected light 812 is reflected from the surface of the cantilever 720. Thus, the height profile of the cantilever 720 and thus the curvature of the cantilever 720 can be determined from an analysis of the light intensity of the integrated beam 816 measured by the detector 809.

  FIG. 9 illustrates a system 900 for measuring stress in a semiconductor structure according to another embodiment of the invention. The system 900 includes a semiconductor structure 500 as described above with reference to FIG. The system further includes a light source 901 adapted to emit a light beam 902. The beam splitter 903 reflects a portion 905 of the light beam 902 toward the semiconductor structure 500. This portion 905 passes through a first focusing element 910 provided between the beam splitter 903 and the semiconductor structure 500. The first focusing element 910 can include a lens. Thereafter, the portion 905 enters the semiconductor structure 500 and is at least partially reflected by the semiconductor structure 500. In this embodiment of the invention, the beam 520 has some transparency so that a portion of the light incident on the beam 520 is transmitted through the beam 520.

  The first reflected light 912 is reflected from the surface of the beam 520 and passes through the focusing element 910 and the beam splitter 903. The second reflected light 913 is reflected from the bottom surface of the trench 513 and passes through the focusing element 910 and the beam splitter 903. The first reflected light 912 and the second reflected light 913 are incident on the photodetector 909.

  The focusing element can be adapted such that the beam 520 and the trench 513 are imaged on the detector 909. Thus, an image of the semiconductor structure 500 is formed on the detector 909. Similar to the photodetector 809 of the embodiment described with reference to FIG. 8, the photodetector 909 can include a two-dimensional sensor configured to record an image of the semiconductor structure 500.

  The first reflected light 912 and the second reflected light 913 interfere with each other. For this reason, the beam splitter 903 and the focusing element 910 form an interferometer as a whole. The intensity of the light recorded by the photodetector 809 represents the phase difference between the first reflected light 912 and the second reflected light 913, which is the beam 520 representing the stress state in the semiconductor structure 500. Represents a profile.

  Thus, the stress in the semiconductor structure 500 can be determined from an analysis of the light intensity measured by the photodetector 909.

  In another embodiment of the present invention, the system 900 includes the semiconductor structure 700 described above with reference to FIG.

  A portion 905 of the light beam 902 is reflected toward the semiconductor structure 700 and is incident on the semiconductor structure 700. The first reflected light 912 is reflected from the surface of the cantilever beam 720. The second reflected light 913 is reflected from the bottom surface of the trench 713. The first reflected light 912 and the second reflected light interfere with each other so that the light intensity recorded by the photodetector 809 represents the height profile of the cantilever 720. For this reason, the curve and the curve height b of the cantilever 720 can be determined from the recorded light intensity.

  In the system for measuring stress in a semiconductor substrate described above, the characteristics of the stress sensitive element representing the stress state in the semiconductor structure are determined in a non-contact manner by optical means. However, in other embodiments, the characteristics of the stress sensitive element may be determined by various contact methods.

  A system for measuring stress in a semiconductor structure may include an atomic force microscope. An atomic force microscope known to those skilled in the art has its tip disposed at the end of the cantilever. As the tip approaches the sample, the cantilever is deflected by the force between the sample and the tip, and this deflection can be detected by known means. The distance between the tip and the sample is adjusted using a feedback mechanism so that the force is substantially constant as the sample surface is scanned by the tip. The feedback mechanism may have a piezoelectric element that is adapted to adjust the distance between the tip and the sample. In this way, the height profile of the sample can be determined.

  The system may have a semiconductor structure 500 as described above with reference to FIG. The height profile of the beam 520 can be scanned by an atomic force microscope. From the height profile, the deflection and bending height d of the beam 520 can be determined. From the height profile and / or the bending height d, the stress in the semiconductor structure 500 can be calculated.

  In another embodiment of the present invention, the system includes a semiconductor structure 700 as described above with reference to FIG. The height profile of the cantilever 720 can be scanned with an atomic force microscope and the bending height b can be determined from the height profile. The stress in the semiconductor structure can be calculated from the height profile and / or the curved height b.

  In a system for measuring stress in a semiconductor structure having an atomic force microscope, the atomic force microscope may be adapted to apply a force to the elastic element. For this purpose, the piezoelectric element is activated and the distance between the elastic element and the tip is shortened to a distance shorter than the distance used for scanning the elastic element. As a result, the elastic element can be bent. The deflected elastic element exerts a force on the cantilever beam of the atomic force microscope. The strength of this force represents the stiffness of the elastic element.

  In one embodiment of the invention, the system comprises a semiconductor structure 500 as described above with reference to FIG. The atomic force microscope is adapted to apply a force to the beam 520 and, therefore, is adapted to determine the stiffness of the beam 520 representing the stress state in the semiconductor structure 500.

  In another embodiment of the present invention, the semiconductor structure 500 may have a film instead of the beam 520. In addition to the side walls 511 and 512, the film may be fixed to a third side wall provided on one side of the beam 520. Thus, the semiconductor structure 500 has a cavity between the film and the layer 502. Similar to beam 520, the membrane can have a portion of layers 504, 505. When compressive stress is present in the semiconductor structure 500, the film bends, that is, moves away from the substrate 501 and arches upward. When tensile stress is present in the semiconductor structure 500, the stiffness of the film increases. Thus, film bulge and film stiffness are film characteristics representing the stress state within the semiconductor structure 500.

  FIG. 10 shows a system 1000 for measuring stress in a semiconductor structure, according to yet another illustrative embodiment of the invention. System 1000 includes a semiconductor structure 1001. The semiconductor structure 1001 has a first material layer 1002 formed on a substrate 1001. A stress sensitive element 1003 is formed on the layer 1002. The stress sensitive element 1003 has an elastic element provided in the form of a lattice 1005 having a plurality of trenches 1006 to 1010. Lines 1016 to 1020 are provided between the trenches 1006 to 1010. The length of the grating 1005 is l. The interval between adjacent trenches is s. The depth of the trenches 1006 to 1010 may be smaller than the thickness of the lattice 1005. In another embodiment of the invention, the trenches 1006-1010 pass through the lattice 1005. Further, the stress sensitive element 1003 includes a mount 1004 configured to define a spacing h between the grating 1005 and the layer 1002.

  When the lattice 1005 has a component of the surface of the lattice 1005 and receives a stress orthogonal to the direction of the grooves 1006 to 1010 (indicated by an arrow 1050 in FIG. 10), the stress depends on whether the stress is a tensile stress or a compressive stress. The grid length l increases or decreases. When the length l changes, the interval s between the trenches 1006 to 1010 also changes. Therefore, the length l and the interval s are characteristics of the stress sensitive element 1003 that represents the stress state in the semiconductor structure 1100.

  System 1000 includes a diffractometer in addition to semiconductor structure 1100. The diffractometer 1200 includes a light source 1040 and a photodetector 1012. The light source 1040 is adapted to emit a light beam 1011 incident on the grating 1005. The direction of the light beam 1011 forms an angle α with respect to the direction orthogonal to the surface of the grating 1005. In each line of the grating 1005, a part of the light from the light beam 1011 is scattered.

  The detector 1012 is arranged so that light scattered in a direction that forms an angle β with the direction orthogonal to the surface of the grid 1005 reaches the detector 1012. The detector 1012 is adapted to measure the intensity of light scattered from the grid 1005 toward the detector 1012.

  The light parts scattered by the lines 1016 to 1020 interfere with each other. When the optical path difference between the light parts scattered from the adjacent lines is substantially equal to an integral multiple of the wavelength of the light beam 1011, the interference is intensified and the intensity of the light received by the detector 1012 increases. If they are not equal, the interference is weakened and the intensity of the light received by the detector 1012 is reduced. The optical path difference is determined by the angles α and β and the interval s between adjacent lines of the grid 1005.

  For a predetermined value of the angle α in the direction of the light beam 1011 and the direction orthogonal to the surface of the grating 1005, the intensity of the light measured by the detector 1012 has a maximum value at the predetermined value of the angle β and is between the lines 1016 to 1020. The interval s is represented. For this reason, the interval s can be determined by measuring the angle β at which the scattered light intensity is maximum. Thus, the diffractometer 1012 is adapted to determine the spacing s representing the stress state in the semiconductor structure 1100.

  In another embodiment of the present invention, the system 1000 can include a microscope. The length l of the grating 1005 and / or the spacing s between the trenches 1006 to 1010 can be measured from a microscopic image of the grating 1005. The microscope can include an optical microscope, an electron microscope (especially a scanning electron microscope), or an atomic force microscope that can optically inspect the characteristics of the stress sensitive element 1003.

  In addition to the stress sensitive element 1003, the semiconductor structure 1100 can include an electrical element. The electric element may have a conductive line similar to the conductive lines 110, 510, and 710 of the embodiment of the present invention described with reference to FIGS. In another embodiment of the present invention, the semiconductor structure 1100 may include an electrical element having a field effect transistor.

  In addition to the diffractometer 1200, the system 1000 can have an analyzer adapted to measure the properties of the electrical elements. If the electrical element has a conductive line, the analyzer can be adapted to measure the resistance of the conductive line. If the electrical element comprises a field effect transistor, the analyzer can be adapted to measure the mobility of charge carriers within the channel region of the field effect transistor.

  A method for adjusting the manufacturing process of a semiconductor structure and a method for examining the effect of stress on the electrical elements of the semiconductor structure according to an embodiment of the invention are described below.

  A first semiconductor structure is formed by a first manufacturing process. The first semiconductor structure may be a semiconductor structure 100 as described above with reference to FIG. In this manufacturing process, the substrate 100 is first prepared. Next, a layer 102 of a first material is deposited on the substrate 101. This can be done by film deposition techniques known to those skilled in the art such as physical vapor deposition, chemical vapor deposition and / or plasma enhanced chemical vapor deposition.

  A line 103 of transmissive material is formed in the first semiconductor structure 100. For this purpose, a trench is formed in the layer 102, which can be done by photolithography and etching techniques known to those skilled in the art. Next, a layer of transmissive material is deposited on the semiconductor structure 100. A polishing step is performed to planarize the semiconductor structure 100 and remove the portion of the layer of transmissive material that exits the trench. This polishing process may include chemical mechanical polishing.

  In some embodiments of the present invention, a lattice region is formed in the line 103 of transmissive material, as described below with reference to FIG. In the formation of the grating region, the laser beam 302 emitted by the laser 301 can be divided into a first light beam portion 304 and a second light beam portion 305. This can be done by the beam splitter 303. The laser beam 302 can include ultraviolet light. The first light flux portion 304 is reflected by the first mirror 306 toward the first semiconductor structure. The second light beam portion 305 is reflected by the second mirror 307 toward the first semiconductor structure 100. The first light flux portion 304 and the second light flux portion 305 interfere with each other in the semiconductor structure 100. The phase difference between the light of the first light beam portion 304 and the light of the second light beam portion 305 that has reached a specific zone of the line 103 of the transmissive material is determined by the position of the zone in the longitudinal direction x of the line 103. Therefore, along the line 103, there are a zone that interferes so that the first light beam portion and the second light beam portion are intensified, and a zone that interferes so that the first light beam portion and the second light beam portion are weakened. Appear alternately. Intensifying interference zones have high received light intensity. In such a zone, the refractive index of the transmissive material increases, which can be explained by the chemical bonds of the transmissive material being broken by energetic photons. For this reason, a zone with a high refractive index is formed. In the zone of destructive interference, the intensity of received light is low. In such a zone, the refractive index of the transmissive material is not substantially changed.

  In the manufacturing process, a second material layer 104 and a third material layer 105 shown in FIG. This can be performed by a known film forming technique.

  An electrical element may be formed in the first semiconductor structure 100. In one embodiment of the present invention, the electrical element has a conductive line 110, which can be formed by damascene technology as described below. Prior to depositing layer 105, insulating portion 106 is formed over layer 104. This can be done by photolithography techniques known to those skilled in the art. In another embodiment of the present invention, insulating portion 106 may be formed in layer 104. For this purpose, the portion of the layer 104 coming out of the insulating portion 106 is thinned, which can be done by photolithography and etching techniques known to those skilled in the art. The material lost from layer 104 can be proactively addressed by increasing the thickness of layer 104 deposited on semiconductor structure 100 in anticipation of this. After depositing the third material layer 105, a polishing process is performed to remove excess third material from the insulating portion 106 and planarize the surface of the semiconductor structure 100.

  In another embodiment of the present invention, the first semiconductor structure is a semiconductor structure 500 as described above with reference to FIG. FIG. 6a shows the semiconductor structure 500 in the first stage of the manufacturing process. In the manufacturing process, first a layer 502 is deposited on a substrate 501. In forming the stress sensitive element 509, a sacrificial layer 508 is formed on the layer 502. This can be done using known deposition and patterning techniques.

  FIG. 6b shows the semiconductor structure 500 in a later stage of the manufacturing process. In the manufacturing process, a layer 504 is further deposited on the semiconductor structure 500. Since the thickness of the portion of the layer 504 deposited on the sacrificial layer 508 and the thickness of the portion deposited on the layer 502 are substantially equal, the surface of the layer 504 is raised above the sacrificial layer 508. A polishing step, such as a chemical mechanical polishing process, can be performed to remove this ridge and make the layer 504 flat.

  An electrical element provided in the form of a conductive line 510 may be formed in the semiconductor structure 500. For this purpose, an insulating portion 506 is formed on the layer 504. Similar to the formation of the insulating portion 106 in the method described with reference to FIGS. 1-4, the insulating portion deposits a layer of insulator over the semiconductor structure 500 and patterns it, or in another embodiment. The layer 504 can be formed by thinning a portion other than the insulating portion 506.

  FIG. 6c shows the semiconductor structure 500 in a later stage of the manufacturing process. In the manufacturing process, a layer 505 of a third material is deposited over the semiconductor structure 500 and the layer 505 is planarized to make the layer 505 a flat surface and remove a portion of the layer 505 over the insulating portion 506. Is done.

  Thereafter, the formation of stress sensitive elements continues by forming trench portions 514, 516 near the pre-beam formation structure 515. For this purpose, layers 504, 505 and sacrificial layer 508 are patterned by removing portions of layers 504, 505 and sacrificial layer 508, which can be done by known photolithography and etching techniques. The bottom surfaces of the trench portions 514 and 516 are the surface of the layer 502. The pre-beam formation structure 515 has portions of the layers 504 and 505 on the remaining sacrificial layer 508.

  The remaining sacrificial layer 508 is removed. This can be done by exposing the semiconductor structure 500 to an etchant adapted to selectively remove the material of the sacrificial layer 508, but the first material layer, the second material layer, and the first material layer. The material of the third material layers 502, 504, 505 and the insulating portion 506 is hardly affected by the etching agent. When the remaining sacrificial layer 508 is removed, the trench portions 514 and 516 are connected to each other to form the trench 513, and the beam 520 (see FIG. 5) straddling the trench 513 is the layer 504 of the pre-beam formation structure 515. , 505.

  In this way, the semiconductor structure 500 shown in FIG. 5 is obtained. When stress is present in the semiconductor structure 500, a force is applied to the beam 520. This stress may be due to residual stresses in the layers 504 and 505 that are generated during the deposition of the layers 504 and 505 and result from a mismatch between the crystal structure of the second material and the crystal structure of the third material. The stress may also be caused by different coefficients of thermal expansion of the substrate and the layers 502, 504, 505 materials. If the layer is deposited at a high temperature, the layer material tends to contract differently with different shrinkage as the temperature decreases. For example, if the coefficient of thermal expansion of the substrate or layer 502 is greater than the layers 504, 505, the layers 504, 505 are compressed when the temperature drops after the layers 504, 505 are deposited. When the compressive stress present in the semiconductor structure 500 is small, the beam 520 remains substantially straight. However, when the compressive stress exceeds the critical stress, the force exceeds the critical strength and the beam 520 bends as detailed above. When tensile stress is present in the semiconductor structure 500, the stiffness of the beam 520 increases.

  In one embodiment of the invention in which the semiconductor structure 500 has a film instead of the beam 520, the film can be formed in the same manner as the beam 520 is formed. Layers 504 and 505 are deposited on a sacrificial layer similar to sacrificial layer 508. Layers 504 and 505 and the sacrificial layer are patterned to form a trench portion near the pre-film formation structure having a portion of layers 504 and 505 over a portion of the sacrificial layer. Thereafter, etching for removing a portion of the sacrificial layer is performed to complete the film.

  In another embodiment of the present invention, the first semiconductor structure is a semiconductor structure 700 as described above with reference to FIG. The manufacture of the first semiconductor structure 700 and the formation of the stress sensitive element 709 can be performed in the same manner as the manufacture of the first semiconductor structure 500 and the formation of the stress sensitive element 509. In the formation of the stress sensitive element 709, trench portions similar to the trench portions 514 and 516 are formed near the pre-cantilever beam formation structure similar to the pre-beam formation structure 515. Furthermore, a third trench portion is formed across the pre-cantilever beam formation structure. The rest of the sacrificial layer, similar to sacrificial layer 508, separates portions of layers 704 and 705 that form layer 702.

  Although the semiconductor structure 700 is exposed to an etchant adapted to selectively remove the sacrificial layer material, other portions of the material of the semiconductor structure 700 are hardly affected by the etchant. In this way, a cantilever beam 720 and a trench 713 are formed.

  In yet another embodiment of the invention, the first semiconductor structure is a semiconductor structure 1100 as described above with reference to FIG.

  FIG. 11a shows the semiconductor structure 1100 in the first stage of the manufacturing process. A layer 1002 is deposited on the substrate 1001. In forming the stress sensitive element 1005, the mount 1004 is formed on the layer 1002, and this can be performed by a known photolithography technique.

  FIG. 11b shows the semiconductor structure 1100 at a later stage in the manufacturing process. A sacrificial layer 1030 is deposited on the semiconductor structure 1100. Next, a chemical mechanical polishing process is performed to planarize the surface of the sacrificial layer 1030 and remove a portion of the sacrificial layer from the mount 1004. In this way, the upper surface of the mount 1004 is exposed.

  Yet another stage in the manufacturing process of the semiconductor structure 1100 is shown in FIG. A grating 1005 is formed on the sacrificial layer 1030 and the exposed top surface of the mount 1004. To this end, a layer of lattice material is deposited on the sacrificial layer 1030 and the exposed top surface of the mount 1004. Next, the layer of lattice material is patterned by known photolithography techniques. In this way, trenches 1006 to 1010 are formed. The trenches are provided at a known predetermined interval.

  Thereafter, the semiconductor structure 1100 is exposed to an etchant adapted to selectively remove the material of the sacrificial layer 1030, although the lattice material, mount 1004 material, and layer 1002 material are affected by the etchant. Hardly receive.

  In this way, the semiconductor structure 1100 shown in FIG. 10 is obtained. During the deposition of a layer of lattice material, stress can occur in the layer. This stress can result from, for example, a mismatch between the crystal structure of the lattice material and the crystal structure of the sacrificial layer 1030 material. The stress in the layer of lattice material may also be caused by different thermal expansion rates of the sacrificial layer 1030 and the layer of lattice material. If the layer of lattice material is deposited at a high temperature, the layer of lattice material and the sacrificial layer 1030 tend to contract differently with different shrinkage as the temperature decreases after the deposition process. However, since the lattice material layer and the sacrificial layer are fixed together, the shrinkage process of the layers is inhibited. For this reason, stress is generated in the two layers.

  When the sacrificial layer 1030 is removed, the suppression due to the lattice material layer being fixed to the sacrificial layer 1030 disappears and the lattice 1005 can be relaxed freely. When the lattice 1005 is stressed, the shape of the lattice 1005 changes due to this relaxation. More specifically, when the stress has a component in the direction perpendicular to the direction of the trenches 1006 to 1010 in the plane of the lattice 1005, the spacing s between the trenches 1006 to 1010 of the lattice 1005 patterns the layer of lattice material. This is different from the predetermined interval of the trenches 1006 to 1010 set at the time. The deviation between the predetermined spacing and the spacing s is a characteristic representing the stress state in the layer of lattice material of the semiconductor structure 1100.

  A characteristic of the stress sensitive element representing the stress state in the semiconductor structure is determined.

  In an embodiment of the invention in which the first semiconductor structure is the semiconductor structure 100 as described above with reference to FIG. 1, when determining the characteristics of the stress sensitive element, the characteristics of the line 103 of permeable material are It is determined. The characteristic of the line 103 of transmissive material may be the optical path length of light passing through the line 103 of transmissive material. The optical path length can be determined by a system 200 for measuring stress in a semiconductor structure incorporating the semiconductor structure 100 as described above with reference to FIG. The change in optical path length can be determined from measurement of the intensity of the integrated light beam 216.

  In another embodiment of the present invention, the characteristic of the line 103 of transmissive material may be the wavelength of light reflected by the line 103 of transmissive material.

  In determining the wavelength of the reflected light, the semiconductor structure 100 can be incorporated into a system 400 for measuring stress in a semiconductor structure having a spectrometer, as described above with reference to FIG. The wavelength of the reflected light can be determined by analyzing the spectrum of light transmitted through the semiconductor structure 100 and / or the spectrum of light reflected by the semiconductor structure 100.

  In yet another embodiment of the present invention, the characteristic of the line 103 of transmissive material may be the birefringence of light transmitted through the line 103. The detection of birefringence is based on a system 400 for measuring stress in a semiconductor structure having an analyzer adapted to detect the polarization characteristics of transmitted light, as described above with reference to FIG. This can be done by incorporating the semiconductor structure 100. The birefringence of light in the line 103 of transmissive material can be detected by measuring the intensity of light passing through the second polarization filter.

  In embodiments of the present invention where the first semiconductor structure is a semiconductor structure 500 as described above with reference to FIG. 5, the flexure of the elastic element can be determined when determining the characteristics of the stress sensitive element. This can be done by determining whether the beam 520 is bent. Furthermore, the bending height d can also be measured.

  In one embodiment of the present invention, the semiconductor structure 500 is incorporated into a system for measuring stress in the semiconductor structure described above with reference to FIG. 8 when determining the characteristics of the stress sensitive element 509. As detailed above, the deflection of the beam 520 can be detected by analyzing the height profile of the beam 520, which is referred to as the first reflected light 812 reflected from the surface of the beam 520. It can be determined from an analysis of the intensity of the integrated light beam 816 having an interference pattern between the second reflected light 813 that is a beam. Also, the bending height of the beam 520 can be determined from the height profile.

  In another embodiment of the present invention, the deflection of the beam 520 can be determined by incorporating the semiconductor structure 500 in a system for measuring stress in the semiconductor structure described above with reference to FIG. As detailed above, the height profile of the beam 520, and hence the presence or absence of the bend and the bend height d, is measured by the photodetector 909 and is reflected by the first reflected light reflected from the surface of the beam 520. It can be determined from the intensity of light having an interference pattern between 912 and the second reflected light reflected from the bottom surface of the trench 513.

  Similarly, in embodiments of the present invention where the first semiconductor structure is the semiconductor structure 700 described above with reference to FIG. 7, in determining the characteristics of the stress sensitive element, the deflection of the cantilever 720 may be determined. . The bend and bend height d of the cantilever beam 720, which is a characteristic of the stress sensitive element 709 representing the stress in the semiconductor structure 700, is reflected from the light reflected from the surface of the cantilever and from the bottom surface of the trench 713 or the reference beam. Can be determined by observing the interference pattern between the emitted light. The interference pattern measures the stress in the semiconductor structure 800 as described above with reference to FIG. 9, or the system 800 for measuring stress in the semiconductor structure as described above with reference to FIG. Can be determined by incorporating the semiconductor structure 700 into the system.

  In an embodiment of the invention in which the first semiconductor structure is the semiconductor structure 1100 as described above with reference to FIG. 11, in determining the characteristics of the stress sensitive element, the spacing s between the trenches 1006 to 1010 is determined. Alternatively, this can be done by analyzing the diffraction pattern of light diffracted from the stress sensitive element. This can be done by incorporating a semiconductor structure 1100 into a diffractometer 1200 as shown in FIG.

  In one embodiment of the invention, the angle α is fixed. By moving the detector 1012, the angle β is changed. The intensity of light scattered in the direction towards detector 1012 is measured as a function of angle β. Next, the interval s between the trenches 1006 to 1010 can be obtained from the value of the angle β at which the measured intensity becomes the maximum value, and this can be performed by calculation known to those skilled in the art.

  In another embodiment of the invention, the angle β is fixed and the angle α is changed by moving the light source 1040. The intensity of light scattered in the direction towards detector 1012 is measured as a function of angle α. Next, the interval s between the trenches 1006 to 1010 can be determined from the value of the angle α at which the measured intensity is the maximum value, and this can be performed by calculations known to those skilled in the art.

  In yet another embodiment of the invention, both angle α and angle β are fixed. The light source 1040 is adapted to emit light of a plurality of wavelengths. More particularly, the light source 1040 can be adapted to emit light having a continuous spectrum.

  The spectrum of light scattered by the grating 1005 is determined. For this purpose, the photodetector 1012 can comprise a spectrometer. As detailed above, the phase difference between the portions of light reflected from lines 1016-1020 depends on the wavelength of the scattered light. Therefore, the spectrum of the scattered light becomes the maximum value at the predetermined angle values α and β. The maximum wavelength represents the distance between the trenches 1006 to 1010. This maximum wavelength is determined from the spectrum of scattered light measured by the detector 1012, and the interval s is determined from the maximum wavelength by calculations known to those skilled in the art.

  In yet another embodiment of the invention, the light source 1040 can be adapted to emit multiple wavelengths. Further, by moving one or both of the light source 1040 and the photodetector 1012, one of the angles α and β is changed. The photodetector 1012 has a spectrometer. Therefore, a plurality of spectra obtained by changing the values of the angles α and β can be recorded. Multiple spectra can be used to determine the interval s from computer simulation techniques known to those skilled in the art. In this way, the spacing s can be determined more accurately, and other characteristics of the grating 1005 (eg, the depth of the trenches 1006-1010 and / or the refractive index of the grating 1005) can be determined, which is advantageous. It is.

  The stress between the lattice material layer and the sacrificial layer 1030 can then be calculated from the difference between the measured spacing s and the predetermined trench spacing set when patterning the layer of lattice material.

  The determination of the characteristics of the stress sensitive element representing the stress state in the semiconductor structure may be performed after the manufacturing process is completed. The determination of the characteristics of the stress sensitive element may be performed during operation of the electrical element in the semiconductor structure. For this reason, it is possible to monitor the generation or relaxation of stress induced by the operation of the electric element and caused by, for example, partial thermal expansion of the semiconductor structure due to heat generated by current.

  In another embodiment of the present invention, particularly if the first semiconductor structure is a semiconductor structure 100 as described above with reference to FIG. 1, the characteristics of the stress sensitive element are measured in-situ during the manufacturing process. can be monitored in situ) or in-line.

  To this end, the semiconductor structure 100 is incorporated into a system 200, 400 for measuring stress in a semiconductor structure, which system can be used for physical vapor deposition, chemical vapor deposition and / or plasma enhanced chemical vapor deposition. Can be provided in an apparatus adapted to perform the method or any other deposition process known to those skilled in the art. Thus, the occurrence of stress in the semiconductor structure 100 during deposition of at least one of the layers 104, 105 is observed continuously or at multiple times by determining the characteristics of the line 103 of transparent material. Can do. Further, the characteristics of the line 103 of permeable material representing the stress state in the semiconductor structure 100 may be determined after the deposition of the layer 104 and / or the deposition of the layer 105. Thus, it is possible to observe changes in stress in the semiconductor structure 100 at intervals of the manufacturing process where deposition is not performed, thereby reducing the stresses in the layers 104 and / or 105 that reduce the stress in the semiconductor structure 100. The relaxation process can be monitored.

  The determination of the characteristics of the stress sensitive element may be performed during processing steps other than material deposition. More particularly, the determination of the characteristics of the stress sensitive element may be performed during or after the thermal annealing process.

  In thermal annealing, the semiconductor structure is exposed to high temperatures for a predetermined time. During thermal annealing, stress may be generated due to different coefficients of thermal expansion of the plurality of materials of the semiconductor structure. However, thermal annealing may also promote stress relaxation in the semiconductor structure, which increased the mobility of atoms and / or molecules at high temperatures, resulting in active and unfavorable high stress states. This is because the particles can be reorganized into a more favorable state.

  Determining the characteristics of the stress sensitive element during the thermal annealing process includes a system 200, 400, 800, for measuring stress in a semiconductor structure with the addition of a heater adapted to raise the temperature of the semiconductor structure. This can be done by incorporating a semiconductor structure in 900, 1000 and determining the characteristics of the stress sensitive element during operation of the heater.

  Based on the determined characteristics of the stress sensitive element, the manufacturing process can be modified.

  A manufacturing process may be changed by changing one or more parameters of the manufacturing process. The parameter can include a temperature at which a manufacturing step is performed (eg, a temperature at which one or more of the layers in the semiconductor structure are formed). The parameter may include a pressure or composition of a reaction gas in the film forming process. The parameter may include the composition of the substrate and / or the composition of one of the deposited layers. The parameter may also include a dimension of a component of the semiconductor structure 100 (eg, one or more film thicknesses of the layers) or a lateral dimension of the structural element (eg, the width of a conductive line and / or the width of an insulating portion). .

  In some embodiments of the invention, the manufacturing process change may be to form additional layers of one or more materials. In another embodiment of the present invention, the manufacturing process change may be to omit the formation of layers. The second semiconductor structure can be formed by a modified manufacturing process.

  Modified manufacturing processes include the formation of electrical elements in the second semiconductor structure (eg, formation of conductive lines and / or field effect transistors similar to the conductive lines 110, 510, 710 of the first semiconductor structure). It may be included. Due to a change in the manufacturing process, the electrical element of the second semiconductor structure can be subjected to a different stress state than the electrical element of the first semiconductor structure.

  In some embodiments of the invention, a stress sensitive element is formed in the second semiconductor structure, including a line of transparent material similar to the line 103 of the semiconductor structure 100 and the beam 520 of the semiconductor structure 500. , A cantilever similar to the cantilever 720 of the semiconductor structure, or a lattice similar to the lattice 1005 of the semiconductor structure 1100 may be included. The formation of the stress sensitive element on the second semiconductor structure can be performed by substantially the same processing steps as the formation of the stress sensitive element on the first semiconductor structure.

  The characteristics of the stress sensitive element of the second semiconductor structure representing the stress state in the second semiconductor structure can be determined in the same manner as the characteristics of the stress sensitive element of the first semiconductor structure.

  The characteristics of the stress sensitive element of the second semiconductor structure may be compared with the characteristics of the stress sensitive element of the first semiconductor structure. For this reason, it is possible to obtain information on the influence of the change in the manufacturing process on the stress in the semiconductor structure.

  In some embodiments of the invention, a plurality of first semiconductor structures are formed. Each of the first semiconductor structures is formed by a manufacturing process that is different from the manufacturing process used to form the other semiconductor structures. The manufacturing process may differ in one or more of the parameters detailed above. Also, the manufacturing process may differ in the presence or absence of additional material layers.

  A stress sensitive element is formed in each of the first semiconductor structures. Each of the stress sensitive elements has a characteristic representing a stress state within an individual semiconductor structure. A characteristic of each stress sensitive element of the plurality of first semiconductor structures is determined. For this reason, the information regarding the stress in each of the first semiconductor structures can be obtained.

  The stress in each of the first semiconductor structures may be associated with one or more of the manufacturing process parameters used to form the individual first semiconductor structures. Thus, the dependence of the stress in the semiconductor structure on one or more parameters can be identified. In determining the dependence of the stress on one or more parameters, the mathematics includes the data including the one or more parameters and the stress in the first semiconductor structure formed by the manufacturing process having these parameters. Function fitting can be performed.

  A second manufacturing structure is formed by the modified manufacturing process, the manufacturing process change being a specified dependency between the stress, the first semiconductor structure, and one or more parameters of the manufacturing process. Based on

  A change in the manufacturing process can be performed by determining an improved value for one or more parameters based on the mathematical function obtained in the approximation. This can be done by an optimization technique.

  In some embodiments of the invention, the manufacturing process change is adapted to reduce stress in the second semiconductor structure. The value of one or more parameters is determined by minimizing the stress calculated by the mathematical function obtained in the approximation, which can be done by optimization algorithms known to those skilled in the art.

  In another embodiment of the invention, the manufacturing process change is adapted to bring the stress in the second semiconductor structure closer to a predetermined target stress value. The value of one or more parameters can be obtained by minimizing the square of the difference between the stress calculated by the mathematical function obtained in the approximation and the predetermined stress value. In another embodiment, the value of one or more parameters for which the approximate mathematical function takes a predetermined stress value may be determined. This can be done by solving algorithms known to those skilled in the art.

  The second semiconductor structure may have an integrated circuit having a plurality of electrical elements and may not have a stress sensitive element.

  For example, in some embodiments of the invention, electrical elements (eg, conductive lines or field effect transistors) are formed in each of the plurality of first semiconductor structures. The characteristics of the individual electrical elements can be determined. If the electrical element has a conductive line, the specific resistance of the line can be determined. If the electrical element has a field effect transistor, the mobility of charge carriers in the channel region of the individual field effect transistor can be determined.

  The characteristics of the electrical element of the first semiconductor structure can be associated with the characteristics of the stress sensitive element of the first semiconductor structure. For this reason, it is possible to specify the dependency of the characteristics of the electrical element on the stress in the semiconductor structure. Identifying the dependence between electrical element properties and stress in the semiconductor structure is advantageous, as it can be determined that the desired or undesirable characteristics of the electrical element are due to the effects of stress. .

  In yet another variation of the present invention, the formation of stress sensitive elements on the first semiconductor structure includes a plurality of periodic features similar to known overlay structures used to test the accuracy of photolithography alignment. Formation may be performed. Properties of a plurality of periodic features (eg, periodic feature spacing and / or periodic feature refractive index and / or periodic feature dimensions) are determined by diffraction methods. From the determined characteristics of the periodic features, the stress in the semiconductor structure can be calculated.

  The specific embodiments described above are merely examples, and the invention may be modified and implemented by different but equivalent alternatives, which will be apparent to those skilled in the art having the benefit of the teachings of the disclosure. For example, the above process steps may be performed in an order different from the order described. Further, the details of construction or design described herein are not limited except as by the appended claims. For this reason, it is obvious that the specific embodiments described above can be modified or changed, and all such modifications are intended to be included in the scope and spirit of the present invention. Accordingly, the subject matter claimed for protection herein is as set forth in the appended claims.

1 is a schematic view of a semiconductor structure according to an embodiment of the present invention. 1 is a schematic diagram of a system for measuring stress in a semiconductor structure, according to one embodiment of the invention. FIG. 1 is a schematic diagram of a laser apparatus for forming a stress sensitive element in a semiconductor structure according to an embodiment of the present invention. 1 is a schematic diagram of a system for measuring stress in a semiconductor structure, according to one embodiment of the invention. FIG. 1 is a schematic view of a semiconductor structure according to an embodiment of the present invention. FIG. 6 illustrates a manufacturing stage of a semiconductor structure according to an embodiment of the present invention. FIG. 6 illustrates a manufacturing stage of a semiconductor structure according to an embodiment of the present invention. FIG. 6 illustrates a manufacturing stage of a semiconductor structure according to an embodiment of the present invention. 1 is a schematic view of a semiconductor structure according to an embodiment of the present invention. FIG. 2 illustrates a system for measuring stress in a semiconductor structure according to an embodiment of the present invention. FIG. 2 illustrates a system for measuring stress in a semiconductor structure according to an embodiment of the present invention. FIG. 2 illustrates a system for measuring stress in a semiconductor structure according to an embodiment of the present invention. FIG. 6 illustrates a manufacturing stage of a semiconductor structure according to an embodiment of the present invention. FIG. 6 illustrates a manufacturing stage of a semiconductor structure according to an embodiment of the present invention. FIG. 6 illustrates a manufacturing stage of a semiconductor structure according to an embodiment of the present invention.

Claims (21)

A semiconductor structure,
A stress sensitive element, wherein the characteristic of the stress sensitive element represents a stress state in the semiconductor structure (100);
An electrical element (110),
The stress sensitive element and the electrical element (110) are a semiconductor structure having a portion of a common layer structure (107).   The semiconductor structure according to claim 1, wherein the stress sensitive element comprises a line of permeable material.   The semiconductor structure according to claim 1, wherein the stress-sensitive element includes elastic elements (509) and (709).   The semiconductor structure of claim 3, further comprising at least one mount (511), (512) configured to define a spacing between the elastic elements (509), (709) and a bottom surface.   The semiconductor structure according to claim 1, wherein the layer structure has at least two layers of different materials. A system for measuring stress in a semiconductor structure, the stress sensitive element formed in the semiconductor structure (100);
An electrical element (110) formed in the semiconductor structure, the stress sensitive element and the electrical element (110) having a part of a common layer structure (107),
A first analyzer adapted to determine characteristics of the stress sensitive element representing a stress state in the semiconductor structure (100);
A second analyzer adapted to determine a characteristic of the electrical element (110).   The system of claim 6, wherein the stress sensitive element comprises a line (103) of permeable material.   The system of claim 6, wherein the stress sensitive element comprises an elastic element (509), (709).   The system of claim 6, wherein the layer structure (107) comprises at least two layers of different materials.   The system of claim 8, further comprising at least one mount (511), (512) configured to define a spacing between the elastic elements (509), (709) and a bottom surface. A system for measuring stress in a semiconductor structure, the stress sensitive element formed in the semiconductor structure (100);
An analysis unit having a light source (201) and a photodetector (209), the analysis unit determining characteristics of the stress sensitive element representing a stress state in the semiconductor structure (100) Systems that are adapted to. The stress sensitive element has a line (103) of permeable material, and the analysis unit comprises:
An input coupler adapted to couple light emitted by the light source (201) to the line (103) of transmissive material;
12. A system according to claim 11, comprising an output coupler configured to couple light emanating from the line (103) of transmissive material. A method for adjusting a manufacturing process of a semiconductor structure, comprising:
Forming a first semiconductor structure (100) by the manufacturing process;
Forming a stress sensitive element in the first semiconductor structure (100);
Determining a characteristic of the stress sensitive element representing a stress state in the first semiconductor structure (100);
Modifying the manufacturing process based on the determined characteristics of the stress sensitive element;
Forming a second semiconductor structure by the modified manufacturing process;
Forming an electrical element (110) in the second semiconductor structure.   14. The method of claim 13, wherein forming the stress sensitive element comprises forming a line of permeable material (103) in the first semiconductor structure.   15. The method of claim 14, wherein determining the characteristic of the stress sensitive element comprises determining a wavelength of light reflected by the line (103) of transmissive material.   16. The method of claim 15, wherein determining the characteristic of the stress sensitive element comprises measuring a change in optical path length of the line (103) of transmissive material.   14. The method of claim 13, wherein forming the stress sensitive element comprises forming elastic elements (509), (709).   The method of claim 17, wherein determining the characteristic of the stress sensitive element comprises determining a deflection of the elastic elements (509), (709). A method for investigating the effects of stress on electrical elements of a semiconductor structure,
Forming a stress sensitive element in the semiconductor structure (100);
Forming an electrical element in the semiconductor structure (100);
Determining a characteristic of the stress sensitive element representing a stress state in the semiconductor structure (100);
Determining the characteristics of the electrical element;
Associating the characteristic of the electrical element with the characteristic of the stress sensitive element.   20. The method of claim 19, wherein forming the stress sensitive element comprises forming a line of permeable material (103) in the semiconductor structure.   20. The method of claim 19, wherein forming the stress sensitive element comprises forming elastic elements (509), (709).

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