CN117405590A - Semiconductor device structure with micro-nano structure for raman characterization - Google Patents
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- 238000001069 Raman spectroscopy Methods 0.000 title claims abstract description 78
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000012512 characterization method Methods 0.000 title claims abstract description 55
- 239000002086 nanomaterial Substances 0.000 title claims abstract description 40
- 238000012360 testing method Methods 0.000 claims abstract description 206
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- 230000003287 optical effect Effects 0.000 claims abstract description 37
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- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 239000010409 thin film Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 9
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical group O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910000484 niobium oxide Inorganic materials 0.000 claims description 6
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 claims description 6
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 229920000642 polymer Polymers 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000001902 propagating effect Effects 0.000 claims description 2
- 230000008859 change Effects 0.000 abstract description 9
- 238000012545 processing Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 6
- 230000035515 penetration Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000003841 Raman measurement Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/01—Arrangements or apparatus for facilitating the optical investigation
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/62—Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light
- G01N21/63—Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light optically excited
- G01N21/65—Raman scattering
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/01—Arrangements or apparatus for facilitating the optical investigation
- G01N2021/0106—General arrangement of respective parts
- G01N2021/0112—Apparatus in one mechanical, optical or electronic block
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Abstract
The invention provides a semiconductor device structure with a micro-nano structure for Raman characterization, comprising: a semiconductor device structure to be tested, comprising: a substrate and a part to be tested; the substrate comprises a first test light incidence area, a test area and a first test light emergence area; the part to be tested is formed in the test area; the first optical structure is formed in the first test light incidence area and the first test light emergence area, so that the component to be tested is embedded into the first optical structure; wherein the first optical structure is configured to cause the conduction path of the test light to form a "U" shaped path. The technical scheme provided by the invention solves the problems of how to realize the change of the direction of the test light on the micro-nano structure scale in the Raman test, more accurately represent the information in the part to be tested and simultaneously avoid noise caused by the background signal of the substrate arranged below the sample.
Description
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a semiconductor device structure having a micro-nano structure for raman characterization.
Background
Raman spectroscopy is a fast, non-destructive optical characterization technique that can provide important information about the material and lattice of a sample. The technology is playing an increasingly critical role as an important characterization link in the manufacturing process of CMOS integrated circuits. However, with the continued evolution of CMOS technology nodes, the size of micro-nano structures in integrated circuits is shrinking, which presents a significant challenge for optical-based characterization techniques such as raman spectroscopy.
Since CMOS devices are still based on silicon substrates, the penetration depth of raman incident light in the silicon substrate is relatively deep (e.g., commonly used incident light at 532nm, penetration depth is around 1 um; incident light at 405nm, penetration depth is around 100 nm). CMOS devices are usually manufactured by processing on the surface of a wafer, and the range in the longitudinal direction is not more than 100nm, and the range of a channel layer of the device, a dielectric layer having a great influence on the device performance, and the like is more in the range of 20 nm. Therefore, the area to be characterized has a too small duty ratio in the longitudinal direction within the transmission range of the incident light. The depth of penetration can be reduced to a great extent by adopting deep ultraviolet incident light (the penetration depth is about 10 nm), and the signal duty ratio of a characterization area in the longitudinal direction can be improved theoretically, but the deep ultraviolet incident light has the problems that light spots are not easy to shrink, the laser stability is poor, fluorescent signal interference possibly exists in the measuring process, and the like.
In addition, in common raman measurements, the incident light is incident normal to the sample surface, i.e., back-scattered mode (backscattering geometry). In this way, the direction of incidence of the light is fixed and not variable. However, for some structures with anisotropy, such as fins (Fin), the direction of the incident light parallel to the fins may enhance the response of phonon modes in a particular direction, which is advantageous for better characterization of information in the fins. However, the conventional raman measurement method does not meet the requirement, and in some advanced test devices, the direction of the incident light can be changed by rotating the sample stage, but the adjustment method based on mechanical rotation is rough, and it is difficult to realize the change of the direction on the micro-nano structure scale.
Thus, the development of an improved raman test system to better characterize the information in the fins is a technical focus to be solved by those skilled in the art.
Disclosure of Invention
The invention provides a semiconductor device structure with a micro-nano structure for Raman characterization, which aims to solve the problem of how to realize the change of the direction of test light on the micro-nano structure scale in Raman test, more accurately characterize information in a part to be tested and simultaneously avoid noise caused by background signals of a substrate arranged below a sample.
According to a first aspect of the present invention there is provided a semiconductor device structure having a micro-nano structure for raman characterization, comprising:
a semiconductor device structure to be tested; the semiconductor device structure to be tested comprises a substrate and a component to be tested; the substrate comprises a first test light incidence area, a test area and a first test light emergence area; the test light conduction area is positioned between the first test light incidence area and the first test light emergence area; the part to be tested is formed in the test area;
a first optical structure; the first optical structure is formed in the first test light incidence area and the first test light emergence area, so that the component to be tested is embedded in the first optical structure;
the first optical structure is used for conducting the test light incident to the first test light incident area to the component to be tested, and emitting the test light from the first test light emergent area through the component to be tested so as to obtain stress information of the component to be tested and used for the Raman characterization;
wherein the conductive path of the test light forms a "U" shaped path.
Optionally, the first optical structure is a grating structure; the grating structure comprises:
a waveguide substrate; the waveguide substrate is formed on the first test light incidence area and the first test light emergence area; the component to be tested is embedded into the waveguide substrate;
a coupling-in structure; the coupling-in structure is formed on the waveguide substrate in the first test light incident region;
a coupling-out structure; the coupling-out structure is formed on the waveguide substrate in the first laser exit region;
wherein the grating structure is for: and coupling the test light incident on the first test light incident area into the waveguide substrate through the coupling-in structure, conducting the test light into the component to be tested through the waveguide substrate, conducting the test light into the coupling-out structure through the waveguide substrate, and emitting the test light out of the first test light emitting area through the coupling-out structure, so that a Raman test device obtains stress information of the component to be tested for Raman characterization.
Optionally, a first thin film layer is further included between the waveguide substrate and the substrate, and the first thin film layer is used for refracting light leakage emitted from the first surface of the waveguide substrate back into the waveguide substrate, and propagating through total reflection in the waveguide substrate, and finally coupling out through the coupling-out structure; the first surface of the waveguide base characterizes a side of the waveguide base proximate to the substrate.
Optionally, the material of the first thin film layer is titanium oxide, niobium oxide, or a polymer doped with the titanium oxide or the niobium oxide.
Optionally, the material of the grating structure is silicon oxide.
Optionally, the structure of the semiconductor device to be tested is a gate-all-around device;
the component to be tested is as follows: a first process stage structure; the first process stage structure comprises: a sacrificial material layer and a channel material layer stacked; wherein the first process stage structure is embedded in the grating structure.
Optionally, the structure of the semiconductor device to be tested is a gate-all-around device;
the component to be tested is as follows: a second process stage structure; the second process stage structure comprises: a plurality of fins: each fin comprises a stacked sacrificial layer and a nanowire-shaped channel layer; wherein the second process stage structure is embedded in the grating structure.
Optionally, the structure of the semiconductor device to be tested is a gate-all-around device;
the component to be tested is as follows: a third process stage structure; the third stage structure comprises: a sacrificial structure layer and a channel structure layer stacked; the source region material layer and the drain region material layer are formed on two sides of the fin structure along the first direction; the first direction is perpendicular to the stacking direction of the sacrificial structure layer and the channel structure layer; wherein the third process stage structure is embedded in the grating structure.
Optionally, the structure of the semiconductor device to be tested is a gate-all-around device;
the component to be tested is as follows: a fourth process stage structure; the fourth stage structure comprises: channel structure layers stacked at intervals;
the source region material layer and the drain region material layer are formed on two sides of the fin structure along the first direction;
wherein the fourth process stage structure is embedded in the grating structure.
Optionally, the structure of the semiconductor device to be tested is a gate-all-around device;
the component to be tested is as follows: a fifth process stage structure; the fifth process stage structure comprises: channel structure layers stacked at intervals;
a gate dielectric layer and a gate metal layer; the gate dielectric layer wraps the channel structure layer, and the gate metal layer wraps the gate metal layer;
the source region material layer and the drain region material layer are formed on two sides of the fin structure along the first direction;
wherein the fifth process stage structure is embedded in the grating structure.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device structure having a micro-nano structure for raman characterization, comprising:
providing a substrate; the substrate comprises a first test light incidence area, a test area and a first test light emergence area;
forming a first optical member at the first test light incident region and the first test light exit region;
forming a part to be tested in the test area; the semiconductor device structure to be tested comprises the substrate and a component to be tested; the component to be tested is embedded into the first optical component;
the first optical structure is used for conducting the test light incident to the first test light incident area to the component to be tested, passing through the component to be tested and emitting the test light from the first test light emitting area so as to obtain stress information of the component to be tested for Raman characterization;
wherein the conductive path of the test light forms a "U" shaped path.
According to a third aspect of the present invention, there is provided a raman test system for a ring gate device comprising the semiconductor device structure having a micro-nano structure for raman characterization according to any one of the first aspect of the present invention, the raman test system for a ring gate device further comprising:
a raman test device; the Raman test device is used for emitting test light to the first test light incidence area, acquiring the test light passing through the component to be tested and exiting from the first test light emergence area, and acquiring stress information of the component to be tested in the ring grating device according to the acquired test light so as to perform Raman characterization.
According to the semiconductor device structure with the micro-nano structure for Raman characterization, the first optical structure is formed in the semiconductor device structure to be tested, so that the first optical structure conducts test light incident on the first test light incident area to the component to be tested, the test light is emitted from the first test light emergent area through the component to be tested, a light path is enabled to show a U-shaped characteristic, stress information of the component to be tested is obtained, and the stress information is used for Raman characterization; so as to realize accurate characterization of the micro-nano structure. Therefore, the technical scheme provided by the application realizes the change of the direction on the micro-nano structure scale, so that the test light is incident in the direction parallel to the part to be tested and passes through the part to be tested, and the phonon mode in the specific direction can be enhanced by utilizing the direction of the incident test light parallel to the part to be tested, thereby being beneficial to better representing the information in the part to be tested; on the basis, the vertical incidence mode of the test light is changed, so that the test light does not need to penetrate through the substrate, and noise caused by background signals of a substrate arranged below the sample is avoided. In addition, the micro-nano processing mode adopted by the grating structure is compatible with the CMOS technology; the test light parallel to the part to be tested means: the test light is conducted laterally in the part under test, rather than vertically through the part under test.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a raman test system for a gate-all-around device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the optical paths of test light in a first optical structure and a component to be tested in a Raman test system of a ring-gate device according to an embodiment of the present invention;
FIG. 3 is a schematic view of a device structure according to a first process stage structure according to an embodiment of the present invention;
FIG. 4 is a schematic view of a device structure according to a second process stage structure according to an embodiment of the present invention;
FIG. 5 is a schematic view of a device structure according to a third process stage structure according to an embodiment of the present invention;
FIG. 6 is a schematic view of a device structure according to a fourth process stage structure provided in accordance with an embodiment of the present invention;
FIG. 7 is a schematic view of a device structure according to a fifth process stage structure provided in accordance with an embodiment of the present invention;
FIG. 8 is a flow chart of a method for fabricating a semiconductor device structure having a micro-nano structure for Raman characterization according to an embodiment of the present invention;
reference numerals illustrate:
10-grating structure;
a 101-waveguide substrate;
102-an out-coupling structure;
103-a coupling-in structure;
20-a substrate;
30-a part to be tested;
301-a layer of sacrificial material;
302-channel material layer
303-a sacrificial layer;
304-a channel layer;
305-sacrificial structural layer;
306-a channel structure layer;
307-a source region material layer or a drain region material layer; 308-a gate dielectric layer;
309-gate metal layer;
40-raman test device.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In the raman spectroscopy characterization step of the CMOS integrated circuit fabrication process, the incident light is incident perpendicular to the sample surface, i.e., in a back-scattering mode (backscattering geometry). On the one hand, when the surface of a sample is vertically incident, the occupation ratio of a region to be characterized in the longitudinal direction is too small in the transmission range of incident light, and noise caused by a background signal of a substrate arranged below the sample cannot be avoided; on the other hand, when the surface of the sample is perpendicularly incident, the characterization effect of raman test information on the sample is not ideal, and the direction of the incident light of the Fin (Fin) parallel to the Fin can enhance the response of phonon modes in a specific direction, which is beneficial to better characterize the information in the Fin, but the conventional raman measurement mode does not meet the requirement, even in some advanced test equipment, the direction of the incident light can be changed by rotating the sample table, but the adjustment mode based on mechanical rotation is rough, and the change of the direction on the micro-nano structure scale is difficult to realize.
In view of this, the inventors of the present application have presented, towards raman characterization of micro-nano structures in advanced CMOS nodes: and in a micro-nano processing mode, manufacturing a grating in a certain area of the CMOS micro-nano structure to be characterized, and adjusting the incident direction and the incident direction of Raman incident light on a micro-nano scale by utilizing the structural characteristics of the grating, so as to change the conduction direction of the test light in the CMOS device and change the emergent direction of emergent light, and the Raman testing device obtains the emergent light, namely: the optical path is enabled to present a U-shaped characteristic so as to realize accurate characterization of the micro-nano structure; wherein, the micro-nano processing mode is the processing mode of the grating structure.
Therefore, the technical scheme provided by the application realizes the change of the direction on the micro-nano structure scale, and the phonon mode in the specific direction can be enhanced by utilizing the direction of the incident light parallel to the fins, so that the information in the fins can be better represented; on the basis, the vertical incidence mode of the test light is changed, so that the test light does not need to penetrate through the substrate, and noise caused by background signals of a substrate arranged below the sample is avoided. In addition, the micro-nano processing mode of the grating structure is compatible with the CMOS technology.
The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
Referring to fig. 1-8, according to an embodiment of the present invention, there is provided a semiconductor device structure having a micro-nano structure for raman characterization, comprising:
a semiconductor device structure to be tested; the structure of the semiconductor device to be tested comprises a substrate 20 and a component to be tested 30; the substrate 20 includes a first test light incident area, a test area, and a first test light emergent area thereon; the test light conduction area is positioned between the first test light incidence area and the first test light emergence area; the part 30 to be tested is formed in the test area;
a first optical structure; the first optical structure is formed in the first test light incident area and the first test light emitting area such that the part to be tested 30 is embedded in the first optical structure; the first optical structure is the micro-nano structure for Raman characterization;
the first optical structure is configured to conduct the test light incident on the first test light incident area to the component 30 to be tested, and emit the test light from the first test light emitting area through the component 30 to be tested, so as to obtain stress information of the component 30 to be tested, and be used for the raman characterization;
wherein the conduction path of the test light forms a "U" shaped path; please refer to fig. 2 for the light path diagram.
According to the semiconductor device structure with the micro-nano structure for Raman characterization, the first optical structure is formed in the semiconductor device structure to be tested, so that the first optical structure conducts test light incident on the first test light incident area to the component to be tested, the test light is emitted from the first test light emergent area through the component to be tested, a light path is enabled to show a U-shaped characteristic, stress information of the component to be tested is obtained, and the stress information is used for Raman characterization; so as to realize accurate characterization of the micro-nano structure.
Therefore, the technical scheme provided by the application realizes the change of the direction on the micro-nano structure scale, so that the test light is incident in the direction parallel to the part to be tested and passes through the part to be tested, and the phonon mode in the specific direction can be enhanced by utilizing the direction of the incident test light parallel to the part to be tested, thereby being beneficial to better representing the information in the part to be tested; on the basis, the vertical incidence mode of the test light is changed, so that the test light does not need to penetrate through the substrate, and noise caused by background signals of a substrate arranged below the sample is avoided. In addition, the micro-nano processing mode adopted by the grating structure is compatible with the CMOS technology; the test light parallel to the part to be tested means: the test light is conducted laterally in the part under test, rather than vertically through the part under test.
In one embodiment, the first optical structure is a grating structure 10; the grating structure 10 comprises:
a waveguide substrate 101; the waveguide substrate 101 is formed on the first test light incident region and the first test light emergent region; the component 30 to be tested is embedded in the waveguide substrate 101;
a coupling-in structure 103; the coupling-in structure 103 is formed on the waveguide substrate 101 in the first test light incident region;
a coupling-out structure 102; the coupling-out structure 102 is formed on the waveguide substrate 101 in the first laser exit region;
wherein the grating structure 10 is used for: the test light incident on the first test light incident area is coupled into the waveguide substrate 101 through the coupling-in structure 103, is conducted into the component to be tested 30 through the waveguide substrate 101, passes through the component to be tested 30, is conducted into the coupling-out structure 102 through the waveguide substrate 101, and is emitted from the first test light emitting area through the coupling-out structure 102, so that the raman test device 40 obtains stress information of the component to be tested 30 for the raman characterization.
Wherein the angle of incidence of the test light is greater than the critical angle such that the test light is totally reflected and conducted in the grating structure 10.
The test light consumed by the secondary diffraction in the grating structure 10 provided by the invention is far less than the influence of noise brought by the normal incidence substrate 20 on the Raman test result.
In one embodiment, a first thin film layer is further included between the waveguide substrate 101 and the substrate 20, and is configured to refract the light leakage exiting from the first surface of the waveguide substrate 101 back into the waveguide substrate 101, and propagate through total reflection in the waveguide substrate 101, and finally be coupled out through the coupling-out structure 102 and be captured by the raman test device 40; the first surface of the waveguide base 101 characterizes a side of the waveguide base 101 adjacent to the substrate 20.
Wherein, the first thin film layer has a high refractive index and a low refractive index, when the first thin film layer is disposed on the light leakage side of the waveguide substrate 101 (the waveguide substrate 101 and the substrate 20), total reflection of the test light in the waveguide substrate 101 can be achieved to collect and utilize energy of the light leakage side of the waveguide substrate 101, and light leakage phenomenon generated due to secondary diffraction in the waveguide substrate 101 can be reduced to further improve test accuracy. In one embodiment, the material of the first thin film layer is titanium oxide, niobium oxide, or a polymer doped with the titanium oxide or the niobium oxide. Of course, the material of the first thin film layer may be other materials, which is not limited to the present invention, and any implementation form of the material of the first thin film layer is within the scope of the present invention.
In one embodiment, the material of the grating structure 10 is silicon oxide. Of course, the material of the foregoing grating structure 10 may be other materials, and the present invention is not limited thereto, and any implementation of the material of the grating structure 10 is within the scope of the present invention.
In one embodiment, the semiconductor device structure to be tested is a gate-all-around device;
the part to be tested 30 is: a first process stage structure; the first process stage structure comprises: a sacrificial material layer 301 and a channel material layer 302 stacked; wherein the first process stage structure is embedded in the grating structure 10; the first process stage structure is shown in fig. 3.
In one embodiment, the semiconductor device structure to be tested is a gate-all-around device;
the part to be tested 30 is: a second process stage structure; the second process stage structure comprises: a plurality of fins: each fin includes a stacked sacrificial layer 303, and a nanowire-shaped channel layer 304; wherein the second process stage structure is embedded in the grating structure 10; the second process stage structure is shown in fig. 4.
In one embodiment, the semiconductor device structure to be tested is a gate-all-around device;
the part to be tested 30 is: a third process stage structure; the third stage structure comprises: a sacrificial structure layer 305 and a channel structure layer 306 stacked; a source region material layer 307 and a drain region material layer 307, wherein the source region material layer 307 and the drain region material layer 307 are formed on two sides of the fin structure along the first direction; the first direction is perpendicular to the lamination direction of the sacrificial structure layer 305 and the channel structure layer 306; wherein the third process stage structure is embedded in the grating structure 10; the third process stage structure is shown in fig. 5.
In one embodiment, the semiconductor device structure to be tested is a gate-all-around device;
the part to be tested 30 is: a fourth process stage structure; the fourth stage structure comprises: channel structure layers 306 stacked at intervals;
a source region material layer 307 and a drain region material layer 307, wherein the source region material layer 307 and the drain region material layer 307 are formed on two sides of the fin structure along the first direction;
wherein the fourth process stage structure is embedded in the grating structure 10; the fourth process stage structure is shown in fig. 6.
In one embodiment, the semiconductor device structure to be tested is a gate-all-around device;
the part to be tested 30 is: a fifth process stage structure; the fifth process stage structure comprises: channel structure layers 306 stacked at intervals;
gate dielectric layer 308 and gate metal layer 309; the gate dielectric layer 308 wraps the channel structure layer 306, and the gate metal layer 309 wraps the gate metal layer 309;
a source region material layer 307 and a drain region material layer 307, wherein the source region material layer 307 and the drain region material layer 307 are formed on two sides of the fin structure along the first direction;
wherein the fifth process stage structure is embedded in the grating structure 10; the fifth process stage structure is shown in fig. 7.
Next, according to an embodiment of the present invention, there is also provided a method for manufacturing a semiconductor device structure having a micro-nano structure for raman characterization, the method having a flow chart shown in fig. 8, the method including:
s11: providing a substrate 20; the substrate 20 includes a first test light incident area, a test area, and a first test light emergent area thereon;
s12: forming a first optical member at the first test light incident region and the first test light exit region; wherein, the optical component can be the grating structure 10, the manufacturing process of the grating structure 10 is a process which should be known by a person skilled in the art, the innovation point of the invention is that the grating structure 10 is compatible with the semiconductor process, and the combination structure can improve the accuracy of the Raman characterization;
s13: forming a part 30 to be tested in the test area; the semiconductor device structure to be tested comprises the substrate 20 and a component 30 to be tested; the part 30 to be tested is embedded in the first optical part;
the first optical structure is configured to conduct the test light incident on the first test light incident area into the component to be tested 30, pass through the component to be tested 30, and emit the test light from the first test light emitting area, so as to obtain stress information of the component to be tested 30, for raman characterization;
wherein the conductive path of the test light forms a "U" shaped path.
In the first embodiment, when the part to be tested 30 is in the first process stage structure, step S13: forming the part under test 30 in the test region includes:
forming a stacked sacrificial material layer 301 and channel material layer 302 on the substrate 20; wherein the first process stage structure is embedded in the grating structure 10.
Wherein the semiconductor device structure to be tested comprises the substrate 20 and a first process stage; the first process stage structure is shown in fig. 3.
In the second embodiment, when the part to be tested 30 is in the second process stage structure, step S13: forming the part under test 30 in the test region includes:
a number of fins are formed on the substrate 20: each fin includes a stacked sacrificial layer 303, and a nanowire-shaped channel layer 304; wherein the second process stage structure is embedded in the grating structure 10.
Wherein the semiconductor device structure to be tested comprises the substrate 20 and a second process stage; the second process stage structure is shown in fig. 4.
In the third embodiment, when the part to be tested 30 is in the third process stage structure, step S13: forming the part under test 30 in the test region includes:
a stacked sacrificial structure layer 305 and channel structure layer 306, source region material layer 307 and drain region material layer 307 are formed on the substrate 20, wherein the third process stage structure is embedded in the grating structure 10.
Wherein the semiconductor device structure to be tested comprises the substrate 20 and a third process stage; the third process stage structure is shown in fig. 5.
In the fourth embodiment, when the part to be tested 30 is in the fourth process stage structure, step S13: forming the part under test 30 in the test region includes:
forming channel structure layers 306 stacked at intervals on the substrate 20, a source region material layer 307 and a drain region material layer 307; wherein the fourth process stage structure is embedded in the grating structure 10.
Wherein the semiconductor device structure to be tested includes the substrate 20 and a fourth process stage; the fourth process stage structure is shown in fig. 6.
In the fifth embodiment, when the part to be tested 30 is in the fifth process stage structure, step S13: forming the part under test 30 in the test region includes:
forming the fifth process stage structure on the substrate 20 includes: a channel structure layer 306, a gate dielectric layer 308 and a gate metal layer 309 which are stacked at intervals; the gate dielectric layer 308 wraps the channel structure layer 306, and the gate metal layer 309 wraps the gate metal layer 309; a source region material layer 307 and a drain region material layer 307;
wherein the fifth process stage structure is embedded in the grating structure 10.
Wherein the semiconductor device structure to be tested comprises the substrate 20 and a fifth process stage; the fifth process stage structure is shown in fig. 7. Step S13: the process of the method of fabricating the grating structure 10 in each of the embodiments in which the test region forms the part 30 to be tested is compatible with the process of the method of fabricating the structure at different process stages, and is feasible.
In addition, according to an embodiment of the present invention, there is also provided a raman test system of a gate-all-around device, as shown in fig. 1, including the semiconductor device structure having a micro-nano structure for raman characterization according to any one of the foregoing embodiments of the present invention, the raman test system of a gate-all-around device further includes:
a raman test device 40; the raman test device 40 is configured to emit test light to the first test light incident area, obtain the test light passing through the part to be tested 30 and exiting from the first test light exiting area, and obtain stress information of the part to be tested 30 in the ring gate device according to the obtained test light, so as to perform raman characterization;
wherein the conduction path of the test light forms a "U" shaped path; the light path diagram is shown in fig. 2.
Taking the first process stage structure as an example, a process of performing raman test on the first process stage structure by using the raman test system of the gate-all-around device to obtain initial stress information is described in detail below: wherein the initial stress information characterizes stress information in the first process stage structure;
step S11: providing a substrate; the substrate comprises a first test light incidence area, a test area and a first test light emergence area;
step S12: forming a grating structure in the first test light incident area and the first test light emergent area;
step S13: forming a first process stage structure in the test region; at this time, the gate-all-around device includes a substrate and a first process stage structure; the first process stage structure is embedded into the grating structure;
the grating structure is used for transmitting the test light incident on the first test light incident area to the component to be tested, passing through the first process stage structure and emitting the test light from the first test light emitting area so as to obtain initial stress information of the first process stage structure for Raman characterization; wherein the conduction path of the test light forms a "U" shaped path.
Based on the determined stress information, the influence of the corresponding process links on the channel stress is analyzed.
In addition, different stress information determined after the same process link is implemented by adopting different process conditions can be obtained; and comparing the different stress information, and analyzing the influence of different process conditions on the stress of the corresponding position of the channel. The raman test process of the gate-all-around device in other four stages is the same, and the description of the process is omitted here; the first stress information of the second process stage structure, the second stress information of the third process stage, the third stress information of the fourth process stage and the fourth stress information of the fifth process stage are respectively obtained. Of course, stress information of other process stages may be obtained, which is not limited in this application. The aforementioned stress information may be any information that matches (or is understood to be capable of characterizing) the corresponding stress and/or stress variation. And finally, analyzing the influence of the corresponding process links on the channel stress based on the determined stress information. Different stress information determined after the same process link is implemented by adopting different process conditions can also be obtained; and comparing the different stress information, and analyzing the influence of different process conditions on the stress of the corresponding position of the channel.
To sum up: the Raman test scheme provided by the invention can realize better characterization of information in the fin under the constraint of the existing Raman architecture (vertical incidence of laser, and observation of laser drop point position and sample position by a microscope coaxial with the laser), and simultaneously avoid the technical effect of noise caused by background signals of a substrate arranged below the sample. In addition, the micro-nano processing mode of the grating structure is compatible with the CMOS technology.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (12)
1. A semiconductor device having a micro-nano structure for raman characterization, comprising:
a semiconductor device structure to be tested; the semiconductor device structure to be tested comprises a substrate and a component to be tested; the substrate comprises a first test light incidence area, a test area and a first test light emergence area; the test light conduction area is positioned between the first test light incidence area and the first test light emergence area; the part to be tested is formed in the test area;
a first optical structure; the first optical structure is formed in the first test light incidence area and the first test light emergence area, so that the component to be tested is embedded in the first optical structure;
the first optical structure is used for conducting the test light incident to the first test light incident area to the component to be tested, passing through the component to be tested, and emitting the test light from the first test light emitting area to obtain stress information of the component to be tested for the Raman characterization;
wherein the conduction path of the test light is a U-shaped path.
2. The semiconductor device with micro-nano structure for raman characterization according to claim 1, wherein the first optical structure is a grating structure; the grating structure comprises:
a waveguide substrate; the waveguide substrate is formed on the first test light incidence area and the first test light emergence area; the component to be tested is embedded into the waveguide substrate;
a coupling-in structure; the coupling-in structure is formed on the waveguide substrate in the first test light incident region;
a coupling-out structure; the coupling-out structure is formed on the waveguide substrate in the first laser exit region;
wherein the coupling-in structure and the coupling-out structure are configured to: the coupling-in structure is used for conducting the test light incident on the first test light incident area to the component to be tested and conducting the test light in the component to be tested, and the coupling-out grid structure is used for emitting the test light from the first test light emitting area to obtain stress information of the component to be tested for Raman characterization.
3. The semiconductor device with micro-nano structure for raman characterization according to claim 2, wherein a first thin film layer is further included between the waveguide substrate and the substrate, the first thin film layer is used for refracting the light leakage exiting from the first surface of the waveguide substrate back into the waveguide substrate, and propagating through total reflection in the waveguide substrate, and finally being coupled out through the coupling-out structure; the first surface of the waveguide base characterizes a side of the waveguide base proximate to the substrate.
4. A semiconductor device having a micro-nano structure for raman characterization according to claim 3, wherein the material of the first thin film layer is titanium oxide, niobium oxide, or a polymer doped with the titanium oxide or the niobium oxide.
5. The semiconductor device with micro-nano structure for raman characterization according to claim 4, wherein the material of the grating structure is silicon oxide.
6. The semiconductor device with micro-nano structure for raman characterization according to claim 5, wherein the semiconductor device structure to be tested is a ring gate device;
the component to be tested is as follows: a first process stage structure; the first process stage structure comprises: a sacrificial material layer and a channel material layer stacked;
wherein the first process stage structure is embedded in the grating structure.
7. The semiconductor device with micro-nano structure for raman characterization according to claim 5, wherein the semiconductor device structure to be tested is a ring gate device;
the component to be tested is as follows: a second process stage structure; the second stage structure comprises: a plurality of fins: each fin comprises a sacrificial layer and a nanowire-shaped channel layer;
wherein the second process stage structure is embedded in the grating structure.
8. The semiconductor device with micro-nano structure for raman characterization according to claim 5, wherein the semiconductor device structure to be tested is a ring gate device;
the component to be tested is as follows: a third process stage structure; the third stage structure comprises: a sacrificial structure layer and a channel structure layer stacked;
the source region material layer and the drain region material layer are formed on two sides of the fin structure along the first direction;
wherein the third process stage structure is embedded in the grating structure.
9. The semiconductor device with micro-nano structure for raman characterization according to claim 5, wherein the semiconductor device structure to be tested is a ring gate device;
the component to be tested is as follows: a fourth process stage structure; the fourth stage structure comprises: channel structure layers stacked at intervals;
the source region material layer and the drain region material layer are formed on two sides of the fin structure along the first direction;
wherein the fourth process stage structure is embedded in the grating structure.
10. The semiconductor device with micro-nano structure for raman characterization according to claim 5, wherein the semiconductor device structure to be tested is a ring gate device;
the component to be tested is as follows: a fifth process stage structure; the fifth process stage structure comprises: channel structure layers stacked at intervals;
a gate dielectric layer and a gate metal layer; the gate dielectric layer wraps the channel structure layer, and the gate metal layer wraps the gate metal layer;
the source region material layer and the drain region material layer are formed on two sides of the fin structure along the first direction;
wherein the fifth process stage structure is embedded in the grating structure.
11. A method of fabricating a semiconductor device having a micro-nano structure for raman characterization, comprising:
providing a substrate; the substrate comprises a first test light incidence area, a test area and a first test light emergence area;
forming a first optical component in the first test light incident region and the first test light emergent region;
forming a part to be tested in the test area; the semiconductor device structure to be tested comprises the substrate and a component to be tested;
the first optical structure is used for horizontally conducting a light beam incident on the first test light incident area into the component to be tested, passing through the component to be tested, and emitting test light from the first test light emergent area for Raman characterization so as to obtain stress information of the component to be tested.
12. A raman test system for a ring-gate device, comprising: the semiconductor device having a micro-nano structure for raman characterization of any one of claims 1-10, the raman test system of the ring gate device further comprising:
a raman test device; the Raman test device is used for emitting test light to the first test light incidence area, acquiring the test light passing through the component to be tested and exiting from the first test light emergence area, and acquiring stress information of the component to be tested in the ring grid device according to the acquired test light so as to perform Raman characterization.
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