KR20070028471A - Semiconductor structures comprising stress sensitive elements and methods of measuring stress in semiconductor structures - Google Patents

Abstract

The semiconductor structure includes a stress sensitive element. The nature of the stress sensitive element is indicative of the stresses in the semiconductor structure 100. Additionally, the semiconductor structure may include an electrical element 110. The stress sensitive element and the electrical element comprise portions of a common layer structure 107. Analyzers can determine the properties of the stress sensitive element and the electrical element 110 exhibiting stress in the semiconductor structure 100. The properties of the stress sensitive element can be determined and the fabrication process can be modified based on the determined properties of the stress sensitive element. The properties of the electrical element 110 may be related to the properties of the stress sensitive element to investigate the effect of stress on the electrical element.

Description

TECHNICAL FIELD OF THE INVENTION A semiconductor structure comprising a stress sensitive element and a method of measuring stress in the semiconductor structure.

The present invention relates to the manufacturing area of semiconductor devices, and more particularly to the stress measurement of semiconductor structures.

Integrated circuits include a large number of individual circuit components, such as transistors, capacitors, and resistors, for example. These components are internally connected through electrically conductive lines to form complex circuits such as memory devices, logic devices and microprocessors. Improving the performance of integrated circuits requires a reduction in feature size. In addition to increasing operating speed due to reduced time of signal propagation, reduced feature size increases the number of functional components in the circuit to expand functionality. Today, improved semiconductor structures can include features having a size of 0.1 μm or smaller.

As the size of structural components, such as circuit components and electrically conductive lines, decreases, the effects of stress become increasingly important. Electrically conductive lines are typically embedded in an intermediate dielectric. If stress occurs in the interlayer dielectric, the mechanical connection between the electrically conductive liars and the interlayer dielectric and / or structural components to which they are connected, such as other electrically conductive lines and circuit components, will be weakened. Can be. Conversely, this affects the stability of the integrated circuit and leads to an increase in contact resistance between the electrically conductive lines. In addition, increased contact resistance may adversely affect the functionality of the integrated circuit, resulting in rapid deterioration due to excessive heat formation. The stress also causes it to separate it from the structural components to which the electrically conductive lines are connected, which can result in the destruction of the integrated circuit.

The stress in the interlayer dielectric can be particularly disadvantageous if the interlayer dielectric contains a low-k material that is used to reduce delays in signal propagation due to parasitic capacitances. Because these materials have relatively weak bonds, the stress can also form cracks and / or separate electrical conductive lines from the interlayer dielectric.

Conversely, stress can be intentionally used for circuit components to improve performance. Tensile or compressive stress in the semiconductor material can modify the mobility of electrons and holes. Creating a tensile stress increases the mobility of the electrons, where it increases by about 20% depending on the magnitude of the tensile stress, and directly deforms into an increase corresponding to conductivity. Increasing the induced stress in the mobility of the charges can be used to improve the performance of the N-type field effect transistor by increasing the mobility of the charge carriers in the channel region. On the other hand, compressive stress in the channel region of the P-type field effect transistor increases the mobility of the holes, which can be used to improve the performance of the transistor.

In order to increase the tensile or compressive stress in the channel region of the transistor, it has been proposed to introduce a silicon / germanium layer or a silicon / carbon layer, for example in or below the channel region. In general, the stress in the channel region may be generated by depositing a strained spacer layer or etching the strained spacer layer to produce a spacer component having tensile or compressive stress in close proximity to the gate electrode.

Thus, stresses in integrated circuits can significantly affect circuit performance. Therefore, the measurement of stresses in semiconductor structures is important in the design of integrated circuits or structural components therein.

Depending on the state of the art, a method of measuring stress in a semiconductor structure will now be described. Typically, the curvature of the substrate is measured using a profiler (profilometer), which is a mechanism for scanning the surface of the substrate by a stylus. Subsequently, a layer of material is deposited on the substrate. If the deposition of the layer of material creates stress, the substrate is warped. Therefore, the curvature of the substrate is changed. After deposition of the layer, the curvature of the substrate is measured once again. The stress in the film can then be calculated from the curvatures measured before and after deposition of the layer by an equation derived by elastic theory.

One problem with conventional measurements of stress in semiconductor structures is that the thickness of the substrate is involved in the calculation of the stress. The thicker the substrate, the smaller the change in curvature due to the particular stress, and the less sensitive the measurement is. Conversely, thin substrates are easily deformed by gravity and, conversely, can affect accurate measurements.

Another problem with conventional measurements of stress in semiconductor structures is that the curvature of the substrate must be measured over a range of several centimeters, as a result of which heterogeneity and / or deposited layers of the substrate can lead to false results in the measurement.

In addition, another problem in the conventional measurement of stress in a semiconductor structure is that in order to measure the stress between the first material and the second material, a substrate comprising one of the materials must be provided. This can significantly increase the cost of the measurement process, especially if expensive and / or unwieldy materials have to be investigated.

In addition, another problem with conventional measurements of stress in a semiconductor structure is that while the semiconductor structure is being processed, the measurement cannot be performed in-situ.

In view of the above-mentioned problems, there is a need for a system and method for accurately measuring stress in semiconductor structures.

The following presents a brief summary of the invention in order to provide a basic understanding of certain aspects of the invention. This summary is not an exhaustive overview. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present the concepts in a simplified form as a prelude to the more detailed description that will be discussed later.

In accordance with an exemplary embodiment of the present invention, the semiconductor structure includes a stress sensitive element. The nature of the stress sensitive element is indicative of the stress conditions within the semiconductor structure. In addition, the semiconductor structure includes an electrical element. The stress sensitive element and the electrical element comprise portions of a common layer structure.

According to another exemplary embodiment of the present invention, a system for measuring stress in a semiconductor structure includes a stress sensitive element formed in the semiconductor structure and an electrical element formed in the semiconductor structure. The stress sensitive and electrical elements comprise portions of a common layer structure. The system includes a first analyzer for determining the characteristics of the stress sensitive element exhibiting stress conditions within the semiconductor structure and a second analyzer for determining the characteristics of the electrical element.

According to yet another exemplary embodiment of the present invention, a system for measuring stress in a semiconductor structure includes a stress sensitive element and an analyzer formed in the semiconductor structure. The analyzer includes a light source and a light detector. The analyzer determines the properties of the stress sensitive element, the properties representing stress conditions within the semiconductor structure.

According to yet another exemplary embodiment of the present invention, a method of adjusting a manufacturing process for a semiconductor structure includes forming a first semiconductor structure by the manufacturing process. In addition, the method includes forming a stress sensitive element in the first semiconductor structure. The properties of the stress sensitive element are determined. The property indicates stress conditions in the first semiconductor structure. The manufacturing process is modified based on the determined properties of the stress sensitive element. The second semiconductor structure is formed by a modified manufacturing process, and electrical elements are formed in the second semiconductor structure.

According to yet another exemplary embodiment of the present invention, a method for investigating the effect of stress on an electrical element in a semiconductor structure includes forming a stress sensitive element in the semiconductor structure and forming an electrical element in the semiconductor structure. . The properties of the stress sensitive element are determined. The property is indicative of the stress conditions in the semiconductor structure. The characteristics of the electrical element are determined. The properties of the electrical element are related to the properties of the stress sensitive element.

The invention may be understood with reference to the following description with reference to the accompanying drawings, wherein like reference numerals identify similar components, and:

1 shows a schematic view of a semiconductor structure, in accordance with an embodiment of the present invention;

2 shows a schematic sketch of a system for measuring stress in a semiconductor structure, in accordance with an embodiment of the present invention;

3 shows a schematic sketch of a laser device for forming a stress sensitive element in a semiconductor structure, in accordance with an embodiment of the present invention;

4 shows a schematic sketch of a system for measuring stress in a semiconductor structure, in accordance with an embodiment of the present invention;

5 shows a schematic view of a semiconductor structure, in accordance with an embodiment of the present invention;

6A-6C illustrate steps for fabricating a semiconductor structure, in accordance with one embodiment of the present invention;

7 shows a schematic view of a semiconductor structure, in accordance with an embodiment of the present invention;

8-10 show sketches of systems for measuring stress in a semiconductor structure, in accordance with one embodiment of the present invention; And

11A-11C illustrate steps for fabricating a semiconductor structure, in accordance with one embodiment of the present invention.

While the invention is to be taken in various modifications and in an alternative form, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the description of specific embodiments herein is not intended to limit the invention to the particular forms disclosed, and, conversely, the invention is equivalent to all modifications, equivalents, within the spirit and scope of the invention as defined in the appended claims. Water, and alternatives.

Exemplary embodiments of the invention are described below. In the interest of clarity, not all features of the embodiments have been described herein. Of course, in the deployment of any such practical embodiment, many run-specific decisions must be made to achieve the developer's specific goals, such as complying with system and business constraints, which vary from one implementation to another. Will be understood. Moreover, it is to be understood that such development efforts are complex and time consuming, and can nevertheless be undertaken conventionally for those skilled in the art having the benefit of this disclosure.

The invention will now be described with reference to the accompanying drawings. Various structures, systems, and devices have been shown schematically in the drawings for purposes of explanation only and so as to not obscure the present invention with details that are well known to those skilled in the art. Nevertheless, the attached drawings include describing or describing exemplary views of the invention. The words and phrases used herein should be understood and interpreted in a manner consistent with the meaning of the words and phrases used in the art. Any particular definition of a term or phrase is not intended to be implied by the term or phrase consistently used herein, that is, a definition different from the usual and customary meaning understood by those skilled in the art. If a term or phrase is intended to have a special meaning, ie, meaning that is different from what is understood by the skilled artisan, it will be clearly stated by way of definition that provides a direct and distinctly specific definition of the term or phrase.

The present invention allows the measurement of mechanical stress in a semiconductor structure to determine its influence on an electrical element that can be an electrically conductive line or field effect transistor and to adjust the manufacturing process for the semiconductor structure. The stress sensitive element may be performed during the wafer level fabrication process by process steps used in semiconductor fabrication. The measurement may be performed in place during the measurement of the semiconductor structure to monitor the strengthening and / or relaxation of the stress in the semiconductor structure and / or after completion of the semiconductor structure. The invention can be used to monitor the stress characteristics of a semiconductor structure, which semiconductor structure can be, for example, a wafer comprising one or more integrated circuits that are processed in situ or immediately during an industrial production process, and The present invention can be used to modify the production process for controlling the stresses in the fabricated semiconductor structure.

According to an exemplary embodiment, the semiconductor structure includes a stress sensitive element, the characteristics of which represent stress conditions within the semiconductor structure. In addition, the semiconductor structure may include electrical elements. The stress sensitive element and the electrical element may comprise portions of a common layer structure. By determining the properties of the stress sensitive element, the stress in the semiconductor structure affecting the electrical element can be measured. The characteristics of the electrical element can be determined and related to the characteristics of the stress sensitive element for investigating the stress effect on the performance of the electrical element.

In other embodiments of the present invention, the stress sensitive element is formed in the first semiconductor structure, and the properties of the stress sensitive element indicative of the stress condition in the first semiconductor structure are determined. Next, the fabrication process used to fabricate the semiconductor structure is modified taking into account the stress conditions in the first semiconductor structure that are estimated from the properties of the stress sensitive element. The second semiconductor structure is manufactured by a modified manufacturing process, and electrical elements are formed in the second semiconductor structure. Therefore, the electrical element in the second semiconductor structure can be exposed to well defined stress conditions.

The system for measuring stress in a semiconductor structure may include a stress sensitive element formed within the semiconductor structure, and an analyzer determines the characteristics of the stress sensitive element. In particular, the analyzer can be configured to determine characteristics by means of light. Additionally, a second analyzer may be provided that determines the characteristics of the electrical element formed within the semiconductor structure.

1 shows a schematic view of a semiconductor structure 100, in accordance with an exemplary embodiment of the present invention. The semiconductor structure 100 includes a substrate 101. The layer structure 107 is formed over the substrate 101. The layer structure 107 includes a first material layer 102, a second material layer 104, and a third material layer 105. The stress sensitive element is provided to form a line 103 of transparent material extending through the layer 102 in the semiconductor structure 100 in the longitudinal direction x. The layer 105 includes the electrical elements provided in the formation of the electrically conductive line 110. The electrically conductive line 110 is separated from other portions of the layer 105 by insulating portions 106.

The transparent material of the line 103 may comprise glass, polymer, ceramic material or any other material having a high transmittance to light. By this, the term light can be understood to encompass not only infrared and ultraviolet light but also visible light wavelength ranges. The ceramic material may include aluminum oxide (Al ₂ O ₃ ). The layer 102 may comprise a first dielectric material, which may include, for example, silicon dioxide. The layer 103 may include a second dielectric material that is a low-k (k) material, such as silicon oxycarbide (SiCOH). The third material may comprise a metal, for example copper. In another embodiment of the present invention, the first and second materials may comprise essentially the same dielectric material, for example silicon dioxide.

In further embodiments of the present invention, the semiconductor structure 100 may include electrical elements other than electrically conductive lines. In particular, the electrical element may comprise a field effect transistor.

In such embodiments, the layer 102 and the layer 105 may comprise silicon. The layer 104 may create compressive or tensile stress in the layer 105 and may include, for example, silicon and germanium alloys or silicon and carbon alloys. A channel region of the field effect transistor may be formed in the layer 105. The substrate 101 may include an insulator material such as silicon dioxide. Therefore, the field effect transistors are formed of silicon on an insulator configuration. In general, the substrate 101 may include a semiconductor material such as, for example, silicon.

The nature of the stress sensitive element 103 is indicative of the stress conditions within the semiconductor structure 100.

The property can be the length of the optical path of light passing through line 103 of transparent material. If there is stress in the semiconductor structure 100, the line 103 is deformed. The line 103 can be stretched in the longitudinal direction x depending on whether the layer structure 107 is subjected to tensile or compressive stress, so that the length of the line 103 increases, or lengthwise It can be compressed in the direction x, so that the length of the line 103 is reduced.

As the length of the line 103 increases or decreases, the length of the optical path of light through the line 103 of transparent material increases or decreases, respectively. Thus, the length of the optical path of light passing through the line 103 of transparent material becomes a characteristic of the line 103 representing a stress condition within the semiconductor structure 100.

In another embodiment of the present invention, the characteristic of the line 103 of the transparent material representing the stress condition in the semiconductor structure 100 is the wavelength of the light reflected on the line 103 of the transparent material.

For this purpose, the line 103 comprises a grating region, where the refractive index changes periodically in the longitudinal direction x. The grating region comprises a region where the refractive index of the transparent material is greater than the other portions of the line 103. The high refractive index zones have a predetermined spacing.

Because of the refractive index change, light is scattered due to the Bragg effect. If light having wavelengths passes through line 103 of transparent material in a direction of propagation essentially parallel to the longitudinal direction x, the portion of the light is scattered in a direction opposite to the direction of propagation in each of the regions of high refractive index.

If the wavelength of light in the transparent material is essentially the same as twice the spacing of the high index region, the portions of the light reflected in the high index region reinforce and interfere. This allows many fragments of the light to be reflected by the grating portion and lowers the transmission of the line 103 of transparent material.

Conversely, if the wavelength of the light in the transparent material is significantly different from the double spacing of the high refractive index regions, the portions of the light reflected in the high refractive index region cancel and interfere. Therefore, the light is not reflected in the grating region and is transmitted through the grating region.

If light with continuous wavelengths passes through line 103 of transparent material, a portion of the light with a wavelength in the transparent material that is essentially equal to twice the spacing of the high refractive index regions is reflected. The remainder of the light is transmitted essentially through the line 103 of transparent material. The reflected light spectrum therefore contains a peak at a characteristic wavelength that represents the spacing of the high index areas. The transmitted spectrum contains the minimum at the characteristic wavelength.

If stress is present in the semiconductor structure 100, the line 103 of transparent material is stretched or compressed. Thus, the spacings between the high refractive index regions are increased or decreased. This increases or decreases the characteristic wavelength of the line 103. Thus, the characteristic wavelength becomes a characteristic representing the stress condition in the semiconductor structure 100.

The line 103 can extend to a substantial portion of the semiconductor structure 100. In some embodiments of the present invention, the semiconductor structure 100 includes a wafer including a plurality of chips. The plurality of chips include electrical elements in addition to the electrical elements described above. The line 103 may be formed in spaces (scribe lines) between chips provided for cutting the wafer after the fabrication process. Advantageously, this makes it possible to prepare stress sensitive elements in the semiconductor structure essentially without requiring additional wafer area. In another embodiment of the present invention, the wafer includes a test structure in which the line 103 is formed.

The grating region may comprise a substantial portion of the line 103 of transparent material. Thus, the average stress of the semiconductor structure 100 can be measured. In another embodiment of the present invention, the grating region only includes a portion of the semiconductor structure 100. The lattice region may have a length of less than 400 μm. In another embodiment of the present invention, the lattice region may have a length of less than 200 μm or 100 μm. Advantageously, this allows for a specific measurement of stress within a narrow region of the semiconductor structure 100.

In another embodiment of the present invention, the line 103 characteristic of the transparent material indicative of the stress condition in the semiconductor structure 100 is in the birefringence of light in the transparent material. In such embodiments, the transparent material may include glass, polymers, or any other transparent material that exhibits birefringent stresses known to those skilled in the art.

If stress is present in the semiconductor structure 100, the line 103 of transparent material is also subjected to stress. The stress induces birefringence of the transparent material. In birefringence, the index of refraction of a material depends on the polarization direction of light passing through the line 103 of transparent material as is well known to those skilled in the art. Thus, the polarization state of the light passing through the line 103 can be changed.

5 illustrates a semiconductor structure, in accordance with another embodiment of the present invention. The semiconductor structure 500 includes a substrate 501 on which a layer structure 507 is formed. The layer 507 includes a first material layer 502, a second material layer 504, and a third material layer 505. Similar to the layer structure 107 in the semiconductor structure 100 described in connection with FIG. 1, the layer structure 502 is electrically separated from other portions of the layer 505 by insulating portions 506. Electrical elements provided in the form of conventional conductive lines 510. Alternatively, the electrically conductive component can be provided in a field effect transistor.

In addition, the semiconductor structure 500 includes an elastic element 509. The elastic element 509 includes a beam 520 spanning across the trench 513 and secured to the sidewalls 511, 512 of the trench 513. The side walls 511 and 512 are mounts that provide a space h between the beam 520 and the bottom surface of the trench 513. The beam 520 includes a portion of the layer 504 and a portion of the layer 505.

Beam 520 need not include two layers of material. In another embodiment of the present invention, the beam 520 includes only one material layer or three or more layers.

If there is compressive stress in the layer structure 507, the beam 520 is forced from the sidewalls 511, 512 toward the central portion of the beam 520 that induces the deflection of the beam 520. Apply. The behavior of the beam 520 under the influence of the force may be determined by elastic theory known to those skilled in the art. If the force is small, the beam remains straight. Once the force exceeds the critical intensity, the beam bends. Thus, the central portion of the beam rises to a buckling height d. The buckling of the beam 520 and the buckling height d represent stress conditions within the semiconductor structure 500. The stress in the semiconductor structure 500 can be calculated from the buckling height d.

The beam 520 in the semiconductor structure 500 according to the present invention does not need to be buckle upwards as shown in FIG. In other embodiments of the present invention, the beam 520 may be buckle downward, such that the central portions of the beam 520 are associated with the sidewalls 511 and 512 in response to a negative value of the buckleing height d. It has a smaller height above the bottom surface of the trench 513 than adjacent portions.

If there is a tensile strain in the semiconductor structure 500, the beam is subjected to a force acting toward the sidewalls 511, 512. These forces tend to stretch the beam 520. As the beam 520 is stretched, the stiffness of the beam 520 increases with respect to the forces applied to the beam. Thus, the stiffness of the beam 520 becomes a characteristic of the beam 520 representing the stress condition within the semiconductor structure 500. The stress in the semiconductor structure 500 may be calculated from the stiffness of the beam 520 through elastic theory.

7 illustrates a semiconductor structure 700 in accordance with another embodiment of the present invention. The semiconductor structure 700 includes a substrate 701 having a layer structure 707 including a first material layer 502, a second material layer 504, and a third material layer 505. The layer structure 707 may include an electrical element that may include an electrically conductive line 710 and insulating portions 706 that separate the electrically conductive line 710 from other portions of the layer 705. Can be. In other embodiments of the invention, the electrical element may comprise a field effect transistor.

The semiconductor structure 700 includes an elastic component 709. The elastic element includes a cantilever beam 720 provided over the trench 713 and is fixed to the sidewall 711 of the trench 713. The sidewall 711 is a mount providing a space h 'between the cantilever beam 720 and the trench bottom surface. The beam includes portions of the layers 704 and 705. If either or both of the layers 704 and 705 are stressed, the refraction of the cantilever beam 720 occurs, including the bending of the cantilever beam 720. Due to the bending, the tip of the cantilever beam 720 is raised to the bending height b. The bending height b may be positive or negative depending on the cantilever beam 720 being bent upwards or downwards.

The relationship between the stress in the layers 704 and 705 and the bending height b is derived by elastic theory to those skilled in the art. Thus, the bending and the bending height b of the cantilever beam 720 are characteristics of the elastic element representing the stress condition in the semiconductor structure 700.

The invention is not limited to semiconductor structures comprising a single stress sensitive element. The semiconductor structure according to the invention may comprise a plurality of stress sensitive elements. The stress sensitive elements are not essentially identical and are arranged in different parts of the semiconductor structure. Therefore, stresses in other parts of the semiconductor structure can be determined.

In another embodiment of the present invention, the semiconductor structure includes other stress sensitive elements. For example, the semiconductor structure includes an array of beams similar to the beam 520 in the semiconductor structure described above with respect to FIG. As is well known to the skilled person, the critical stress for buckling of the beam depends on the thickness and length of the beam, with long narrow beams having smaller critical stress than short and narrow beams. Therefore, even if the buckling heights of the beams are not measured, a determination as to whether each of the plurality of beams with different dimensions has been buckle allows obtaining information about the strength of the deformation.

In a further embodiment of the invention, the semiconductor structure comprises a plurality of different types of stress sensitive elements. For example, the plurality of stress sensitive elements include beams, cantilever beams and lines of transparent material. Therefore, the stress in the semiconductor structure can be measured in a number of different ways. Advantageously, this allows the stress to be measured more accurately.

2 illustrates a system for measuring stress in a semiconductor structure, in accordance with one exemplary embodiment of the present invention. The system 200 includes a semiconductor structure 100 as described above with respect to FIG. Additionally, the system 200 may include a source 201 of light, such as a laser, for example. The light source 201 emits a light beam 202. The first beam splitter 203 splits the light beam 202 into a first light beam portion 205 and a second light beam portion 204. Output coupler 210 couples the first light beam portion 205 with a line 103 of transparent material in the semiconductor structure 100. Output coupler 210 may include a first focusing optical component that may include lenses. The focal point of the first focusing optical component may be located at the first end of the transparent material line 103. The output coupler 211 is coupled with the first light beam 205 exiting the line 103 of transparent material. Similar to the input coupler 210, the output coupler 211 may include a second focusing optical component that may include lenses. The focal point of the second focusing optical component may be located at the second end of the line 103 of transparent material.

The first mirror 207 reflects the first light beam portion 205 towards the second beam splitter 208. The second mirror 206 reflects the second light beam portion towards the second beam splitter 208.

In the second beam splitter 208, the first light beam portion 205 is integrated with the second light beam portion to form an integrated light beam 216. The first light beam portion 205 and the second light beam portion 204 interfere with each other. Thus, the first beam splitter 203, the first mirror 207, the second mirror 206 and the second beam splitter 208 together form an interferometer.

The photo detector 209 measures the intensity of the integrated light beam 216. The intensity of the integrated light beam 216 changes the phase difference between the first light beam portion 205 and the second light beam portion 204 depending on the length of the optical path, so that the line 103 of transparent material It depends on the optical path of the light passing through it. Thus, the change in the length of the optical path of light in the transparent material line 103 can be determined from the intensity of the integrated light beam 216 measured by the light detector 209. The interferometer, ie the light source 201 and the light detector 209, thus forms a first analyzer that determines the length of the optical path of the light in the line 103 of transparent material.

Additionally, the system 200 may include a second analyzer 214. First wire 212 and second wire 213 provide electrical contact between the second analyzer and the electrical element in the semiconductor structure 100.

In another embodiment of the present invention, wherein the electrical element comprises an electrically conductive line 110, and the second analyzer 214 measures the amperage of the current flowing through the power source and the electrically conductive line 110. An ammeter and a voltmeter for determining the voltage provided by the power source. Thus, using Ohm's law, the resistance of the electrically conductive line 110 can be determined and also the resistance including the contribution of contact resistance between the electrically conductive line 110 and other structural components can be determined.

In one embodiment of the invention, the semiconductor structure 100 includes a field effect transistor, and the second analyzer 214 is in electrical contact between the second power source and the gate electrode of the field effect transistor and the second power source. It may further include a third wire to provide. The first and second wires may be configured to provide electrical contact between the second power source and the source / drain regions of the field effect transistor. The voltage provided by the second power source can be used to bring the channel region of the field effect transistor into an electrically conductive state. Ammeters, voltmeters, and power sources can be used to determine the electrical resistance of the channel region of the field effect transistor that can calculate charge carrier mobility in the channel region.

In another embodiment of the present invention, the second analyzer 214 and the wires 212 and 213 may be omitted. In this embodiment, the semiconductor structure 100 need not include electrical elements.

In a further embodiment of the present invention, the interferometer may include optical fibers instead of the first and second beam splitters 203 and 208 and the first and second mirrors 206 and 207. The first split optical fiber is connected with the light source 201 and splits the light beam 202 into a first light beam portion 205 and a second light beam portion 204. The first end of the first split optical fiber comprising the first light beam portion 205 is connected with the first end of the line 103 of transparent material. For example, by bonding the first end of the first split optical fiber to the semiconductor structure 110. The first end of the first split optical fiber thus forms an output coupler connecting the light emitted by the light source 201 to the transparent material line 103. The first end of the second split optical fiber is connected with the second end of the transparent material line 103, thereby forming an output coupler that couples the light exiting the line 103. Second ends of the first and second optical fibers are connected to each other. The second split optical fiber thus integrates the first light beam portion 205 and the second light beam portion 204 to form an integrated light beam 216.

4 illustrates a system 400 for measuring stress in a semiconductor structure in accordance with another embodiment of the present invention. The system 400 includes a semiconductor structure 100 as described above with respect to FIG. Additionally, the system 400 includes a light source 401 and a light detector 409. The first optical fiber 415 connects the light source 401 with the semiconductor structure 100, and provides light emitted by the light source 401 to the transparent material line 103 in the semiconductor structure 100. do. The second optical fiber 416 connects the semiconductor structure 100 with the photo detector 409 and provides the light detector 409 with light transmitted through the transparent material line 103. The light source 401, the light detector 409, and the first and second optical fibers 415, 416 together form an analyzer that determines the optical properties of the transparent material line 103.

Additionally, the system 400 includes a second analyzer 414 that determines the characteristics of electrical elements within the semiconductor structure 100 similar to the second analyzer 214 in the system 200 described above with respect to FIG. can do. The second analyzer 414 may be connected to the electrical element by wires 412 and 413.

The photo detector 409 may include a spectrometer. Thus, the analyzer determines the spectrum of light transmitted through line 103 of transparent material. Photo detectors comprising a spectrometer are particularly advantageous if the transparent material line 103 in the semiconductor structure 100 includes a grating region. In this embodiment of the invention, the light source 401 may be configured to emit light having a plurality of wavelengths. In particular, the light source 401 emits light having a continuous band wavelength near the characteristic wavelength of the grating region without deformation in the semiconductor structure 100.

The spectrum of transmitted light includes a minimum at the characteristic wavelength of the grating region, which represents the stress in the semiconductor structure 100. Thus, the stress in the semiconductor structure 100 can be determined from the minimum location of the spectrum.

In another embodiment of the present invention, the system 400 includes branched optical fibers instead of optical fibers 415 and 416. Similar to the optical fiber 415, the branched optical fiber is connected with the transparent material line 103 in the semiconductor structure 100. The first end of the branched fiber is connected to the light source 401. The second end of the branched fiber is connected to the photo detector 409. The branched fiber thus directs light from the light source 401 to the transparent material line 103 and guides the light reflected within the line 103 to the photo detector 409. The analyzer thus determines the spectrum of light reflected from the transparent material line 103. The spectrum includes peaks at characteristic wavelengths of the grating region in line 103. The stress of the semiconductor structure 100 can be calculated from the location of the peaks in the spectrum.

In another embodiment of the invention, the light source 401 emits polarized light having a first polarization direction. In general, the light source may emit unpolarized light, and a first polarization filter for transmitting polarized light in the first polarization direction may be disposed between the light source 401 and the first optical fiber 415. Alternatively, the semiconductor device may be provided between the first optical fiber 415 and the semiconductor structure 100. So the polarized light with the predicted polarization direction is coupled to the line 103 of transparent material.

The photo detector 409 senses the intensity of light transmitted through the semiconductor structure 100 and has a second polarization direction. For this purpose, the photo detector may include an optical sensor to sense the intensity of light provided to the second polarization filter. In general, the second polarizing filter may be provided between the semiconductor structure 100 and the second optical fiber 416. Thus, the analyzer senses polarization characteristics of light transmitted through the transparent material line 103.

An analyzer for sensing polarization properties is particularly advantageous if the property of the transparent material line 103 exhibiting stress in the semiconductor structure 100 includes birefringence of light in the transparent material.

In order to measure the birefringence of light in the transparent material line 103, the first and second polarization directions may be perpendicular to each other. When there is no birefringence in the transparent media, the second polarizing filter essentially blocks any light transmitted through line 103. However, if the transparent material is birefringent, the polarization characteristic of the transmitted light is changed and the fragment of transmitted light is transmitted through the second polarization filter. The intensity of light passing through the second filter measured by the photo detector is indicative of the stress in the semiconductor structure 100.

In a further embodiment of the invention, the system 400 includes a first focusing component that couples the light emitted by the light source 401 with the transparent material line 103 instead of the optical fibers 415, 416. And an output coupler that includes an input coupler and a second focusing component configured to couple light from line 103 of transparent material. The first and second focusing components may each comprise a lens.

8 illustrates a method of measuring stress in a semiconductor structure, in accordance with another embodiment of the present invention. The system 800 includes a semiconductor structure 500 as described above with respect to FIG. Additionally, the system 800 includes a light source 801 that emits a light beam 802. The beam splitter 803 splits the light beam 802 into a first light beam portion 805 and a second light beam portion 804.

A first focusing component 810, which may include a lens, is provided between the beam splitter 803 and the semiconductor structure 500. The first light beam portion 805 passes through a first focusing component and is imaged on the semiconductor structure 500. A second focusing component 811, which may include a lens, is provided between the beam splitter 803 and a reference surface 806. The reference surface 806 may be planar. The second light beam portion 804 passes through the second focusing component and is imaged on the reference surface 806.

The first light beam portion 805 is reflected from the semiconductor structure 500. The first reflected light 812 reflected from the surface of the beam 520 passes through the first focusing component 810 and the beam splitter 803 toward the photo detector 809. Similarly, the second light beam portion 804 is reflected from the reference surface 806. The second reflected light 813 reflected from the reference surface 806 is reflected toward the light detector 809 in the beam splitter 803. Within the beam splitter 803, the first reflected light 812 and the second reflected light 813 interfere with each other and form an integrated light beam 816. The beam splitter 803, the first focusing component 810, the second focusing component 811, and the reference surface 806 together form an interferometer. The photo detector 809 measures the intensity of the integrated light beam 816.

The first focusing component 810 and the second focusing component 811 may cause the beam 520 and the reference surface 806 to be imaged on the photo detector 809. Thus an overlap of the image of the beam 520 and the image of the reference plane 806 is formed at the location of the photo detector 809. Photodetector 809 may include a two-dimensional sensor configured to record an overlap of an image of beam 520 and reference plane 806. In a particular embodiment of the invention, the detector 809 may include a charge coupled device and a photographic film.

The intensity of the integrated light beam 816 represents the phase difference between the first reflected light 812 and the second reflected light 813. The phase difference represents the height profile of the beam 520. If the beam 520 is buckled, the height profile of the beam 520 is obtained in a curved shape with a central portion having a height greater than the height of the peripheral portion of the beam 520 proximate the sidewalls 511, 512. The difference in height between the central portion and the peripheral portions is essentially the same as the buckling height d, which is characteristic of the beam 520 representing the stress in the semiconductor structure 500.

Thus the stress in semiconductor structure 500 can be determined by analyzing the intensity of the integrated light beam 816 measured by the detector.

In another embodiment of the present invention, system 800 includes semiconductor structure 700 instead of semiconductor structure 500 as described above with respect to FIG. The first beam portion 805 impinges on the semiconductor structure 700, and the first reflected light 812 is reflected from the surface of the cantilever beam 720. Thus, the height profile of the cantilever beam 720 and the bending of the cantilever beam 720 can be determined by analyzing the light intensity of the integrated beam 816 measured by the detector.

9 illustrates a system 900 for measuring stress in a semiconductor structure in accordance with another embodiment of the present invention. The system 900 includes a semiconductor structure 500 as described above with respect to FIG. 5. Additionally, the system includes a light source 901 that emits a light beam 902. Beam splitter 903 reflects portion 905 of light beam 902 toward semiconductor sphere 500. The portion 905 passes through a first focusing component 910 provided between the beam splitter 903 and the semiconductor structure 500. The first focusing component 910 may comprise a lens. Subsequently, the portion 905 impinges on the semiconductor structure 500 and is at least partially reflected by the semiconductor structure. In this embodiment of the present invention, the beam 520 has some transparency, so that the portion of light impinging on the beam 520 is transmitted through the beam 520.

The first reflected light 912 is reflected from the surface of the beam 520 and passes through the focusing component 910 and the beam splitter 903. Second reflected light 913 is reflected from the bottom surface of trench 513 and passes through focusing component 910 and beam splitter 903. The first reflected light 912 and the second reflected light 913 impinge on the photo detector 909.

The focusing component may cause the beam 520 and the trench 513 to be imaged on the detector 909. Thus, an image of the semiconductor structure 500 is formed on the detector 909. Similar to the photo detector 809 in the embodiment described with respect to FIG. 8, the photo detector 909 may include a two-dimensional sensor configured to record an image of the semiconductor structure 500.

The first reflected light 912 and the second reflected light 913 interfere with each other. Thus, the beam splitter 903 and the focusing component 910 together form an interferometer. The intensity of the light recorded by the photo detector 809 represents a phase difference between the first reflected light 912 and the second reflected light 913, which subsequently causes stress conditions in the semiconductor structure 500. The profile of the beam 520 is shown.

Thus, the stress in semiconductor structure 500 can be determined by analyzing the intensity of light measured by photo detector 909.

In another embodiment of the present invention, system 900 includes semiconductor structure 700 instead of semiconductor structure 500 as described above with respect to FIG.

The portion 905 of the light beam 902 is reflected toward the semiconductor structure 700 and impinges on the semiconductor structure 700. The first reflected light 912 is reflected from the surface of the cantilever beam 720. The second reflected light 913 is reflected from the bottom surface of the trench 713. The first reflected light and the second reflected light interfere with each other, so that the intensity of the light recorded by the photo detector 809 represents the height profile of the cantilever beam 720. Thus, the bending and bending height d of the cantilever beam 720 can be determined from the recorded light intensity.

In the system for measuring the stress of the semiconductor substrate described above, the properties of the stress sensitive element representing the stress condition in the semiconductor structure are determined in the non-contact mode by optical means. However, in other embodiments the properties of the stress sensitive element can be determined by various contact methods.

A system for measuring stress in a semiconductor structure can include an atomic force microscope. Atomic Force Microscopy known to those skilled in the art includes a tip provided at the end of the cantilever. If the tip approaches the sample, the force between the sample and the tip induces the deflection of the cantilever, which can be detected by known means. The feedback mechanism is used to adjust the distance between the tip and the sample so that the force remains essentially constant as the sample surface is scanned into the tip. The feedback mechanism may include a piezoelectric element for adjusting the distance between the tip and the sample. So the height profile of the sample can be determined.

As described above in FIG. 5, the system may include a semiconductor structure 500. The height profile of the beam 520 can be scanned with an atomic force microscope. The deflection and buckling height d of the beam 520 can be determined from the height profile. The stress of the semiconductor structure 500 can be calculated from the height profile and / or the buckling height d.

In another embodiment of the present invention, the system includes a semiconductor structure 700 as described above with respect to FIG. The height profile of the cantilever beam 720 can be scanned by atomic force microscope, and the bending height d can be determined by the height profile. The stress in the semiconductor structure can be calculated from the height profile and / or the bending height d.

In a system for measuring stress in a semiconductor structure including an atomic microscope, an atomic force microscope can apply a force to an elastic element. For this purpose, the piezoelectric element is activated to reduce the distance between the elastic element and the tip, where the distance can be less than the distance used for scanning of the elastic element. This induces the refraction of the elastic element. The refracted elastic element exerts a force on the cantilever of the atomic force microscope. The magnitude of the force represents the rigidity of the elastic element.

In one embodiment of the present invention, the system includes a semiconductor structure 500 as described above with respect to FIG. An atomic force exerts a force on the beam 520, thereby determining the stiffness of the beam 520, which represents a stress condition within the semiconductor structure 500.

In another embodiment of the present invention, the semiconductor structure 500 may include a film instead of the beam 520. In addition to the side walls 511 and 512, the film may be secured to a third side wall provided in the beam 520. Thus, the semiconductor structure 500 may include a cavity between the film and the layer 502. Similar to the beam 520, the film may include portions of layers 504 and 405. If there is compressive stress in the semiconductor structure 500, the film is refracted, i.e., bent in an upward direction away from the substrate 501. If there is tensile stress in the semiconductor structure 500, the stiffness of the film increases. Thus the arching of the film and the stiffness of the film are the properties of the film indicative of the stress conditions within the semiconductor structure 500.

10 illustrates a system 1000 for measuring stress in a semiconductor structure, in accordance with another exemplary embodiment of the present invention. The system 1000 includes a semiconductor structure 1001. The semiconductor structure 1001 includes a first material layer 1002 formed on the substrate 1001. A stress sensitive element 1003 is formed on the layer 1002. The stress sensitive element 1003 includes an elastic element provided in the formation of a grating 1005 having a plurality of trenches 1006-1010. The grating 1005 has a length l. Adjacent trenches are spaced apart in space s. The trenches 1006-1010 may have a thickness smaller than the thickness of the grating 1005. In another embodiment of the present invention, the trenches 1006-1010 extend through the grating 1005. Additionally, stress sensitive element 1003 includes a mount 1004 configured to provide a space h between the grating 1005 and the layer 1002.

If the grating 1005 has a component in the plane of the grating 1005 and is subjected to a stress that is essentially perpendicular to the direction of the grooves 1006-1010 (indicated by the arrows in FIG. 10), the The length l of the grating increases or decreases depending on whether the stress is tensile or compressive. As the length l changes, the space s between the trenches 1006-1010 also changes. The length l and space s are thus characteristic of the stress sensitive element indicative of the stress condition in the semiconductor structure 1100.

In addition to the semiconductor structure 1100, the system 1000 includes a diffractometer. The diffractometer 1200 includes a light source 1040 and a light sensor 1012. The light source 1040 emits a light beam 1011 impinging on the grating 1005. The direction of the light beam 1011 has an angle α in the direction perpendicular to the surface of the grating 1005. In each of the lines of the grating 1005, the light portion of the light beam 1011 is scattered.

The detector 1012 is arranged such that light scattered in the direction having angle β in a direction perpendicular to the surface of the grid 1005 reaches the detector 1012. The detector 1012 measures the intensity of light scattered from the grid 1005 toward the detector 1012.

The light portions are dispersed in lines 1016-1020 that interfere with each other. If the difference in the optical path between the portions of the light scattered between adjacent lines is essentially the same as the integer product of the wavelength of the light in the light beam 1011, the interference is constructive interference and the detector 1012 The intensity of the light received by it increases. Otherwise, the interference cancels out and the intensity of the light received by the detector is reduced. The difference in the optical path depends on the space s between the angles α, β and the adjacent lines of the grid 1005.

For a case where the angle between the direction of the light beam 1011 and the direction perpendicular to the grating 1005 is a particular angle α, the intensity of light measured by the detector 1012 is determined between the lines 1016-1020. It has a maximum at the value of each β appearing in the space s. Thus, by measuring the angle β at which the intensity of the scattered light is maximum, the space s can be determined. The diffractometer 1012 thus determines the space s representing the stress condition within the semiconductor structure 1100.

In another embodiment of the invention, system 1000 may comprise a microscope. The length l of the grating 1005 and the space s between the trenches 1006-1010 may be measured from a fine image of the grid 1005. The microscope may comprise an optical microscope, an electron microscope, in particular a scanning electron microscope or an atomic microscope, for investigating the optical properties of the stress sensitive element 1003.

In addition to the stress sensitive element 1003, the semiconductor structure 1100 may include an electrical element. The electrical element may include electrical conductive lines similar to the battery conductive lines 110, 510, and 710 in the embodiment of the present invention described above with respect to FIGS. In another embodiment of the present invention, semiconductor structure 1100 may include an electrical element that includes a field effect transistor.

In addition to the diffractometer 1200, the system 1000 may include an analyzer for measuring the properties of electrical components. If the electrical element comprises an electrically conductive line, the analyzer can measure the electrical resistance of the electrically conductive line. If the electrical component comprises a field effect transistor, the analyzer can measure charge carrier mobility in the channel region of the field effect transistor.

In accordance with one embodiment of the present invention, methods for adjusting the manufacturing process for a semiconductor structure and for investigating the effect of stress on electrical elements within the semiconductor structure will be described below.

The first semiconductor structure is formed by the first manufacturing process. The first semiconductor structure may be the semiconductor structure 100 as described above with reference to FIG. 1. In the manufacturing process, the first substrate 100 is provided. In addition, the first material layer 102 is deposited on the substrate 101. This is accomplished by deposition techniques such as physical vapor deposition, chemical vapor deposition, and / or improved plasma chemical vapor deposition known to those skilled in the art.

Transparent material lines 103 are formed in the first semiconductor structure 100. For this purpose, trenches are formed in the layer 102, which can be performed by photolithography and etching techniques known to those skilled in the art. Thereafter, a transparent material layer is deposited on the semiconductor structure 100. A polishing process is performed to planarize the semiconductor structure 100 and to remove portions of the transparent material layer outside of the trenches. The polishing process may include chemical mechanical polishing.

In some embodiments of the present invention, the grating region is formed in the transparent material line 103 as described in FIG. Forming the grating region includes separating the laser beam 302 emitted by the laser 301 into a first light beam portion 304 and a second light beam portion 305. This can be done by the beam splitter 303. The laser beam 302 may include ultraviolet light. The first light beam portion 304 is reflected towards the first semiconductor structure by the first mirror 306. The second light beam portion 305 is reflected toward the first semiconductor structure 100 by a second mirror 307. In the semiconductor structure 100, the first and second light beam portions 304 and 305 interfere with each other. The difference in phase between the light in the first light beam portion 304 and the light in the second light beam portion 305 reaching a particular zone in the transparent material line 103 is determined by Depends on the location. Thus, along line 103, the areas where the first and second light beam portions reinforce and interfere with each other and the areas where the first and second light beam portions cancel and intersect alternately occur. Zones with constructive interference receive a strong intensity of light. In this zone, the refractive index of the transparent material increases, which explains the breakdown of chemical bonds in the transparent material by powerful photons. Thus regions with high refractive indexes are created. Zones of destructive interference only receive weak light intensity. In these zones, the refractive index of the transparent material is essentially unchanged.

The manufacturing process further includes depositing the second material layer 104 and the third material layer 105 shown in FIG. 1 over the layer 102. This can be done by known deposition techniques.

Electrical elements may be formed in the first semiconductor structure 100. In one embodiment of the invention, the electrical element may comprise an electrically conductive line 110, which may be formed by a damascene technique, as described below. Prior to the deposition of layer 105, insulating portions 106 are formed over the layer 104. This can be done by photolithography techniques known to those skilled in the art. For this purpose, the portions of the insulating portions 106 outer layer 104 are thinned, which can be performed by photolithography and etching techniques known to those skilled in the art. Loss of material in the layer 104 may be considered by correspondingly increasing the thickness of the layer 104 deposited on the semiconductor structure 100 in advance. After depositing the third material layer 105, a polishing process is performed to remove excess third material from the insulating portion 105 and to planarize the surface of the semiconductor structure 100.

In another embodiment of the present invention, the first semiconductor structure 500 may be a semiconductor structure 500 as described above with respect to FIG. 5. 6A shows the semiconductor structure 500 in a first step of the fabrication process. In the manufacturing process, the first layer 502 is deposited on the substrate 501. Forming stress sensitive element 509 includes forming sacrificial layer 508 on layer 502. This can be done using known deposition and patterning techniques.

6B shows semiconductor structure 500 at a later stage of the manufacturing process. The manufacturing process further includes depositing a layer 504 on the semiconductor structure 500. Since the thickness of the portion of the layer 504 deposited on the sacrificial layer 508 and the thickness of the portion of the layer 504 deposited on the layer 502 are essentially the same, the surface of the layer 504 Includes a bump over the sacrificial layer 508. A polishing process, which may be a chemical mechanical polishing process, may be performed to remove the bumps and obtain a planar layer of the layer 504.

Electrical elements provided in the formation of the electrically conductive lines 510 may be formed in the semiconductor structure 500. For this purpose, insulating portions 506 are formed on the layer 504. Similar to the formation of insulating portions 106 in the method described with reference to FIGS. 1-4, the insulating portions may be formed by depositing a layer of insulating material on the semiconductor structure 500 and patterning the insulating layer. Or, alternatively, may be performed by thinning a portion of the layer 504 different from the insulating portions 506.

6C shows semiconductor structure 500 at a later stage of the fabrication process. The fabrication process deposits a third layer of material 505 on the semiconductor structure 500, and obtains a planar surface of the layer 505 and removes the portion of the layer 505 over the insulating portion 506. Planarizing the layer 505.

Subsequently, formation of the stress sensitive element continues by forming trench portions 514, 516 proximate the beam precursor structure 515. For this purpose, the layers 504, 505 and sacrificial layer 508 are patterned by removing portions of the layers 504, 505 and sacrificial layer portions 508, which are known by known photolithography and etching techniques. Can be performed. The bottom surface of the trench portions 514, 516 includes the surface of the layer 502. The beam bulb structure 515 includes portions of the layers 504 and 505 over the remainder of the sacrificial layer 508.

The remainder of the sacrificial layer 508 is removed. This is done by exposing the semiconductor structure 500 to a corrosion solution that selectively removes the sacrificial layer 508 material, but the first, second and third materials of the layers 502, 504 and 505 and the insulating portion ( The material of 506 is not essentially affected by the caustic solution. As the remainder of the sacrificial layer 508 is removed, the trench portions 514, 516 are connected to each other to form the trench 513, and the beam 520 spanning across the trench 513. ) Is formed from portions of layers 504 and 505 within the beam bulb structure 515.

Thus, a semiconductor structure 500 as shown in FIG. 5 is obtained. If stress is present in the semiconductor structure 500, a force is applied to the beam 520. There may be stress This occurs because residual stresses in the layers 504, 505 can be generated in the deposition of the layers 504, 505 and from incompatibility of the crystal structure of the second material with the crystal structure of the third material. Stresses also vary the coefficient of thermal expansion of the materials in the substrate and layers 502, 504 and 505. If the layers are deposited at elevated temperatures, the material in the layers will tend to shrink differently as the temperature decreases. For example, if the substrate or layer 502 has a larger coefficient of thermal expansion than the layers 504, 505, the layers 504, 505 will compress when the temperature decreases after deposition of the layers 504, 505. If a small compressive stress is present in the semiconductor structure 500, the beam 520 remains essentially straight. However, if the compressive stress exceeds the critical stress, the force exceeds the critical magnitude and the beam 520 is buckle as described above. Tensile stresses in the semiconductor structure 500 will induce to increase the stiffness of the beam 520.

In one embodiment of the invention, semiconductor structure 500 includes a film instead of beam 520, which may be formed similar to the formation of beam 520. The layers 504 and 505 are deposited over the sacrificial layer similarly to the sacrificial layer 508. The layers 504 and 505 and the sacrificial layer are patterned to form trench portions proximate the membrane bulb structure including portions of layers 504 and 505 over the sacrificial layer portion. Subsequently, the film is completed by etching a portion of the sacrificial layer.

In other embodiments of the present invention, the first semiconductor structure may be a semiconductor structure 700 as described above with respect to FIG. Fabrication of the first semiconductor structure 700 and formation of the stress sensitive element 709 may be performed similarly to fabrication of the first semiconductor structure 500 and formation of the stress sensitive element 509. Formation of the stress sensitive element 709 includes forming trench portions similar to the trench portions 514 and 516 in close proximity to the cantilever beam bulb structure similar to the beam bulb structure 515. Additionally, a third trench portion is formed that intersects the cantilever beam bulb structure. The remainder of the sacrificial layer, similar to the sacrificial layer 508, separates portions of the layers 704 and 705 from the layer 702. The semiconductor structure 700 is exposed to the corrosive to selectively remove the sacrificial layer material, but the materials of the other portions of the semiconductor structure 700 are not essentially affected by the corrosive. Thus, the cantilever beam 720 and the trench 713 are formed.

In a further embodiment of the present invention, the first semiconductor structure may be a semiconductor structure 100 as described above with reference to FIG. 10.

11A shows a semiconductor structure 1100 in a first step of the manufacturing process. Layer 1002 is deposited on substrate 1001. Forming stress sensitive element 1005 includes forming mount 1004 on layer 1002, which can be performed by known photolithography techniques.

11B shows the semiconductor structure 1100 at a later stage of the fabrication process. The sacrificial layer 1030 is deposited on the semiconductor structure 1100. A chemical mechanical polishing process is then performed to planarize the surface of the sacrificial layer 1030 and to remove the sacrificial layer portion from the mount 1004. Thus, the top surface of the mount 1004 is exposed.

Meanwhile, another step in the manufacturing processes of the semiconductor structure 1100 is shown in FIG. 11C. A grating 1005 is formed on the exposed top surface of the sacrificial layer 1030 and the mount 1004. For this purpose, a layer of lattice material is deposited on the exposed top surface of the sacrificial layer 1030 and the mount 1004. The grating material layer is patterned by known photolithography techniques. Thus, the trenches 1006-1010 are formed. The trenches have a known and foreseen space.

Subsequently, the semiconductor structure 1100 is exposed to a corrosion solution that selectively removes the sacrificial layer 1030 material, but the lattice material and the mount 1004 materials and the layer 1002 are essentially formed by the corrosion solution. It is not affected.

Thus, the semiconductor structure 1100 shown in FIG. 10 is obtained. When depositing the layer of lattice material, stress may occur in the layer of lattice material. For example, the stress may make the crystal structure of the lattice material and the crystal structure of the sacrificial layer 1030 material incompatible. The stress in the lattice material layer can also vary the thermal expansion coefficients of the sacrificial layer 1030 and the lattice material layer. If the lattice material layer is deposited at an elevated temperature, the lattice material layer and the sacrificial layer 1030 will tend to shrink differently as the temperature decreases after the deposition process. However, since the lattice material layer and the sacrificial layer are fixed to each other, the shrinking processes of the layers constrain each other. Thus stress is formed in both layers.

As the sacrificial layer 1030 is removed, the restraint of the lattice material layer due to the layer fixed to the sacrificial layer 1030 is removed, and the lattice 1005 may be freely relaxed. If the grating 1005 is stressed, this relaxation will change the shape of the grating 1005. In particular, if the stress has a component on the plane of the grating 1005 and a component perpendicular to the direction of the trenches 1006-1010, the space between the trenches 1006-1010 in the grating 1005. (s) differs from the predicted space of the trenches 1006-1010 provided for the patterning of the lattice material layer. The deviation between the predicted space and the space s is characterized by a stress condition in the lattice material layer in the semiconductor structure 100.

The properties of the stress sensitive element representing the stress in the semiconductor structure are determined.

In one embodiment of the present invention, the first semiconductor structure may be the semiconductor structure 100 as described above with respect to FIG. 1, wherein determining the properties of the stress sensitive element determines the properties of the transparent material line 103. It includes. The characteristic of the transparent material line 103 can be the length of the optical path of light through the transparent material line 103. The length of the optical path can be determined by the system 200 for measuring stress in the semiconductor structure inserted into the semiconductor structure 100 as described above with respect to FIG. The change in the length of the optical path can be determined from the intensity measurement of the integrated light beam 216.

In another embodiment of the present invention, the characteristic of the transparent material line 103 may be the wavelength of light reflected from the transparent material line 103.

Determining the wavelength of the reflected light may include inserting the semiconductor structure 100 into a system 400 for measuring stress in the semiconductor structure including a spectrometer as described above with respect to FIG. 4. The wavelength of the reflected light may be determined by analyzing the spectrum of light transmitted through the semiconductor structure 100 and / or the spectrum of light reflected from the semiconductor structure 100.

In further embodiments of the invention, the characteristic of the transparent material line 103 may be birefringence of light transmitted through the line 103. Sensing the birefringence may be performed by inserting the semiconductor structure 100 into a system 400 for measuring stress in the semiconductor structure including an analyzer that senses polarization characteristics of the transmitted light as described above with respect to FIG. 4. have. The birefringence of light in the transparent material line 103 can be sensed by measuring the intensity of light passing through the second polarization filter.

According to an embodiment of the present invention, the first semiconductor structure may be the semiconductor structure 500 as described above in FIG. 5, and the characteristics of the stress sensitive element may include determining the refraction of the elastic element. This may be done by determining whether the beam 520 has been buckled. In addition, the buckling height d can be measured.

In accordance with one embodiment of the present invention, determining the characteristics of the stress sensitive element 509 includes inserting the semiconductor structure 500 into a system for measuring stress in the semiconductor structure as described above in FIG. As described above, the refraction of the beam 520 can be sensed by analyzing the height profile of the beam 520, which is referenced to the first reflected light 812 reflected from the surface of the beam 520. It can be determined from analysis of the intensity of the integrated light beam 816 including the interference pattern between the second reflected light 813 being the beam. The buckling height of the beam 520 can also be determined from the height profile.

In other embodiments of the present invention, the refraction of the beam 520 is determined by inserting the semiconductor structure 500 into a system for measuring stress in the semiconductor structure as described above with respect to FIG. As described above, the height profile of the beam 520 and also the presence of buckling and the buckling height d are defined by the first reflected light 912 and the trench (reflected from the surface of the beam 520). It can be determined from the intensity of light measured by the photo detector 909 including an interference pattern between the second reflected light reflected from the bottom surface of 513.

Similarly, in one embodiment of the present invention, the first semiconductor structure may be a semiconductor structure 700 as described above with respect to FIG. 7, and determining the characteristics of the stress sensitive element determines the deflection of the cantilever beam 720. To include. The bending and banding heights d of the cantilever beam 720, which are characteristics of the stress sensitive element 709, represent the interference pattern between the light reflected from the surface of the cantilever beam and the light reflected from the bottom surface of the trench 713 or the reference beam. Can be determined by observing. The interference pattern causes the semiconductor structure 700 to be placed in a system 800 for measuring stress in the semiconductor structure as described above with respect to FIG. 8 or in a system for measuring stress in the semiconductor structure as described above with respect to FIG. Can be determined by injection.

In one embodiment of the invention, the first semiconductor structure may be a semiconductor structure 1100, as described above with respect to FIG. 11, wherein determining the characteristics of the stress sensitive element is between trenches 1006-1010. Determining the space s, which can be done by analyzing the refraction pattern of light refracted from the stress sensitive element. This involves injecting the semiconductor structure 1100 into the diffractometer 1200 as shown in FIG.

In one embodiment of the invention, each α is fixed. The angle β is changed by moving the detector 1012. The intensity of light scattered in the direction toward the sensing paper 1012 is measured as a function of angle β. Thereafter, the space s between the trenches 1006-1010 is determined from the value of the angle β at which the measured intensity is maximum, which can be performed by calculations known to those skilled in the art. .

In another embodiment of the present invention, the angle β is fixed while angle α is changed by moving the light source 1040. The intensity of light scattered in the direction towards the detector 1012 is measured as a function of angle α. The space s between the trenches 1060-1010 is determined from the value of angle α at which the measured intensity is maximum, which can be performed by calculations known to those skilled in the art.

Meanwhile, in another embodiment of the present invention, both angle α and angle β are fixed. The light source 1040 emits light having a plurality of wavelengths. In particular, light source 1040 emits light having a continuous spectrum.

The spectrum of light scattered in the grating 1005 is determined. For this purpose, the photo detector 1012 may comprise a spectrometer. As described above in detail, the phase difference between the portions of light reflected from lines 1016-1020 depends on the wavelength of the scattered light. Therefore, the spectrum of light scattered at the particular angle α, β contains the maximum. The maximum wavelength represents the space s between the trenches 1006-1010. The wavelength of the maximum value is determined from the spectrum of scattered light measured by the detector 1012, and the space s is determined from the maximum wavelength by calculations known to those skilled in the art.

In a further embodiment of the invention, the light source 1040 may emit a plurality of wavelengths. Additionally, one of each α, β is changed by moving either or both of the light source 1040 and the light detector 1012. The photo detector 1012 includes a spectrometer. Thus a plurality of spectra obtained at different values of each α, β can be recorded. The space s can be determined from a plurality of spectra using computer simulation techniques known to those skilled in the art. Advantageously, this allows more accurate determination of the space s and further determination of other properties of the grating 1005. For example, the depth of trenches 1006-1010 and / or the refractive index of the grating 1005 can be determined.

The stress between the grating material layer and the sacrificial layer 1030 may be calculated from the difference between the measured space s in the pattern of the material layer and the predicted space of the grating trenches.

Determining the properties of stress sensitive elements that represent stress conditions in the semiconductor structure can be performed after the manufacturing process is complete. Determining the characteristics of the stress sensitive element can be performed during operation of the electrical element in the semiconductor structure. The generation or relaxation of stress is thus induced by the operation of the electrical element and its result, for example from the result of the thermal expansion of the parts of the semiconductor structure being monitored due to induced current formation.

In another embodiment of the present invention, the properties of the stress sensitive element may be monitored in situ or with immediate treatment during the manufacturing process, especially if the first semiconductor structure is the semiconductor structure 100 as described above in FIG.

For this purpose, the semiconductor structure 100 may be implanted with systems 200,400 for measuring stress in the semiconductor structure, which may be physical vapor deposition, chemical vapor deposition and / or improved plasma chemical vapor deposition or the art. Provided in the apparatus to perform any other deposition process known to those skilled in the art. Thus, while at least one of the layers 104, 105 is deposited, the formation of stresses in the semiconductor structure 100 can be observed by determining the properties of the transparent material line 103 at successive or multiple time points. Additionally, the properties of the transparent material line 103 representing stress conditions in the semiconductor structure 100 may be determined after deposition of layer 104 and / or after deposition of layer 105. Thus a change in stress in the semiconductor structure 100 can be observed in a section of the fabrication process where no deposition is performed, which may result in the layer 104 and / or layer 105 inducing stress reduction in the semiconductor structure 100. Monitor relaxation processes in the

Determining the properties of the stress sensitive element may also be performed during process steps other than depositing the material. In particular, determining the properties of the stress sensitive element can be performed during or after the thermal annealing process.

In thermal annealing, the semiconductor structure is exposed to elevated temperatures for a predicted time. During thermal annealing, stresses may be generated due to different coefficients of thermal expansion of the material in the semiconductor structure. However, since rising temperatures also increase the mobility of atoms and / or molecules, thermal annealing can promote relaxation of stress in the semiconductor structure, resulting in high stress arrangements of significantly disadvantageous particles that can be rearranged into a more advantageous arrangement. Can be.

The determination of the properties of the stress sensitive element during the thermal annealing process can be performed by injecting the semiconductor structure in the system for measuring the stress in the semiconductor structure 200, 400, 800, 900, 1000, and additionally a heater to increase the temperature of the semiconductor structure. ) And determining the properties of the stress sensitive element during operation of the heater.

The manufacturing process can be modified based on determining the properties of the stress sensitive element.

The manufacturing process can be modified by converting one or more parameters of the manufacturing process. The parameters can include the temperature at which the fabrication step is performed, for example, can be formed at one or more temperatures in the semiconductor structure. The parameter may also include the pressure or composition of the reactant gas in the deposition process. The parameter may include the configuration of the substrate and / or the configuration of one of the deposited layers. The parameter may include the dimensions of the components of the semiconductor structure 100, for example one or more thicknesses of layers or lateral dimensions of the structural components, the width of the electrically conductive lines and / or the insulating portion. It may include the width of.

In some embodiments of the invention, modification of the manufacturing process may include forming a layer of one or more additional materials. In another embodiment of the invention, modification of the manufacturing process may include omitting the formation of a layer. The first semiconductor structure can be formed by a modified manufacturing process.

The modified manufacturing process may include forming electrical elements in the second semiconductor structure, for example, forming electrical conductive lines similar to electrical conductive lines 110, 510, 710 in the first semiconductor structure and / or field effect transistor. It may include. Due to the modification of the manufacturing process, the electrical elements in the second semiconductor structure may be subject to stress conditions that are different from the electrical elements in the first semiconductor structure.

In some embodiments of the present invention, the stress sensitive element is formed in the second semiconductor structure, which is similar to the line of transparent material similar to the line 103 in the semiconductor structure 100, similar to the beam 520 in the semiconductor structure 500. Beams, cantilever beams similar to the cantilever beam 720 in the semiconductor structure, or gratings similar to the grating 1005 in the semiconductor structure 1100. Formation of the stress sensitive element in the second semiconductor structure may be performed by process steps such as formation of the stress sensitive element in the first semiconductor structure.

The characteristics of the stress sensitive element in the second semiconductor structure indicative of the stress condition in the second semiconductor structure may be determined similarly to determining the characteristics of the stress sensitive element in the first semiconductor structure.

The properties of the stress sensitive elements in the second semiconductor structure can be compared with the properties of the stress sensitive elements in the first semiconductor structure. Thus information can be obtained regarding the effect of manufacturing process modifications on the stress in the semiconductor structure.

In some embodiments of the present invention, a plurality of first semiconductor structures are formed. Each of the first semiconductor structures is formed by a manufacturing process different from the manufacturing processes used to form another semiconductor structure. The manufacturing processes may differ in one or more of the variables described above in detail. The manufacturing processes may also differ whether or not additional layers of material are formed.

In each of the first semiconductor structures, a stress sensitive element is formed. Each stress sensitive element has properties that represent stress conditions within each semiconductor structure. The properties of the stress sensitive elements in each of the plurality of first semiconductor structures are determined. Thus, information on the stress in each first semiconductor structure can be obtained.

The stress in each of the first semiconductor structures may be associated with one or more parameters of the fabrication process used to form each first semiconductor structure. Thus, the dependence of the stresses in the semiconductor structure on one or more parameters can be achieved. Achieving a dependency of stress on one or more parameters may include fitting a mathematical function to data including one or more parameters, wherein the stresses in the first semiconductor structure may affect these parameters. The branches are formed by the manufacturing process.

The second semiconductor structure may be formed by a modified manufacturing process, the modification of which is based on the stress and the established dependency between the first semiconductor structure and one or more parameters of the manufacturing process.

Modifications of the manufacturing process include determining improved values of one or more parameters based on a fitted mathematical function. This can be done by optimization methods.

In some embodiments of the present invention, modification of the manufacturing process reduces the stress in the second semiconductor structure. The values of one or more parameters can be determined by minimizing the stress calculated by a suitable mathematical function, which can be performed by optimization algorithms known to those skilled in the art.

In another embodiment of the present invention, modification of the manufacturing process causes the stress in the second semiconductor structure to be close to the predicted target stress value. The values of one or more parameters can be obtained by minimizing the square of the difference between the stress calculated by the appropriate mathematical function and the predicted stress value. In general, one or more values from which a suitable mathematical function estimates the predicted stress value can be determined. This can be done by solving algorithms known to the skilled person.

The second semiconductor structure may comprise an integrated circuit comprising a plurality of electrical elements, and need not include stress sensitive elements.

In another embodiment of the present invention, electrical elements, ie, electrically conductive lines or field effect transistors, are formed in each of the plurality of first semiconductor structures. The characteristics of each electrical element can be determined. If the electrical element comprises an electrically conductive line, the resistance of the line can be determined. If the electrical elements comprise field effect transistors, the mobility of the charge carriers in the channel region of each field effect transistor can be determined.

The properties of the electrical element in the first semiconductor structures may be related to the properties of the stress sensitive element in the first semiconductor structures. Thus, the dependence of the electrical element properties on the stress in the semiconductor structure is achieved. Advantageously, achieving a dependency between the properties of the electrical element and the stresses in the semiconductor structure allows the desirable or undesirable properties of the electrical element to contribute to the effect of the stress.

In a further modification of the invention, the formation of the stress sensitive element in the first semiconductor structure may comprise forming a plurality of periodic features similar to known overlay structures used to test the precision of alignment in photolithography. Can be. The characteristics of the plurality of periodic features, for example the refractive index of the periodic features and / or the periodic features and / or the dimensions of the periodic features, are determined by the diffractometer. The stress in the semiconductor structure can be calculated from the properties of the determined periodic features.

The specific embodiments disclosed above are merely exemplary, and thus the invention may be modified and practiced in other equivalent manners as apparent to those skilled in the art having the benefit of education herein. For example, the disclosed process steps may be performed in a different order. Furthermore, it is not intended to be limited to the details of construction or design shown herein, nor is it intended to be anything other than as described in the claims below. It is therefore evident that the specific embodiments described above may be altered or modified, and all such changes are considered within the spirit and scope of the invention. The protection herein is therefore as disclosed in the claims below.

Claims (21)

The stress sensitive element and the properties of the stress sensitive element represent stress conditions in the semiconductor structure 100; And An electrical element (110), Wherein the stress sensitive element and the electrical element (110) comprise portions of a common layer structure. The semiconductor structure of claim 1, wherein the stress sensitive element comprises a transparent material line (103). The method of claim 1. Wherein the stress sensitive element comprises an elastic element (509,709). 4. The semiconductor structure of claim 3, further comprising at least one mount (511,512) configured to provide a space between the resilient element (509,709) and the bottom surface. 2. The semiconductor structure of claim 1, wherein the layer structure (107) comprises at least two different material layers. A stress sensitive element formed in the semiconductor structure (100); An electrical element (110) formed in the semiconductor structure, wherein the stress sensitive element and the electrical element comprise portions of a common layer structure (107); A first analyzer for determining a characteristic of said stress sensitive element, said characteristic representing a stress condition in said semiconductor structure (100); And And a second analyzer for determining the characteristics of the electrical element (110). 7. The system of claim 6, wherein the stress sensitive element comprises a transparent material line (103). 7. The system of claim 6, wherein the stress sensitive element comprises an elastic element (509, 709). 7. The system of claim 6, wherein the layer structure comprises at least two different materials. 9. The system of claim 8, further comprising at least one mount (511,512) configured to provide a space between the elastic element (509,709) and the bottom surface. A stress sensitive element formed in the semiconductor structure; And An analyzer comprising a light source 201 and a light detector 209, wherein the analyzer determines a characteristic of the stress sensitive element, the characteristic representing a stress condition within the semiconductor structure 100. System for measuring stresses in the body. 12. The method of claim 11 wherein the stress sensitive element comprises a transparent material line (103); And Wherein the analyzer comprises an input coupler for coupling the light emitted by the light source 201 with the transparent material line 103 and an output coupler configured to couple the light exiting the transparent material line 103. A system for measuring stress in a semiconductor, characterized in that Forming a first semiconductor structure (100) by a manufacturing process; Forming a stress sensitive element in the first semiconductor structure (100); Determining a property of the stress sensitive element, the property representing a stress condition in the first semiconductor structure (100); Modifying the manufacturing process based on the determined characteristic of the stress sensitive element; Forming a second semiconductor structure by the modified manufacturing process; And Forming an electrical element within said second semiconductor structure. The method of claim 13, wherein forming the stress sensitive element comprises forming a line of transparent material in the first semiconductor structure. 15. The method of claim 14, wherein determining said property of said stress sensitive element comprises determining a wavelength of light reflected from said transparent material line (103). Way. 16. The process of claim 15, wherein determining said property of said stress sensitive element comprises measuring a change in the length of an optical path in said transparent material line (103). How to. 14. The method of claim 13 wherein forming the stress sensitive element comprises forming an elastic element (509, 709). 18. The method of claim 17, wherein determining the property of the stress sensitive element comprises determining the refraction of the elastic element (509, 709). Forming a stress sensitive element in the semiconductor structure (100); Forming an electrical element in the semiconductor structure (100); Determining a property of the stress sensitive element, the property representing a stress condition in the semiconductor structure (100); Determining a characteristic of the electrical element; And Associating the property of the electrical element with the property of the stress sensitive element. 20. The method of claim 19, wherein determining the stress sensitive element comprises forming a transparent material line (103) in the semiconductor structure. 20. The method of claim 19, wherein forming the stress sensitive element comprises forming an elastic element (509, 709).

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