JP2008301685A - Drive unit of power converter circuit, and power conversion system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a partial discharge occurs during the rotation control of a motor generator. <P>SOLUTION: Operation signals gup, gun, gvp, gvn, gwp, gwn which operate a switching element of an inverter are calculated based on the magnitude relation between command voltages vuc, vvc, vwc and a carrier to a three-phase motor generator. When the command voltage vuc changes from a state larger to a state smaller than the command voltage vvc in a positive region of the command voltages vuc, vvc, a polarity inversion of UV interphase voltage is decided based on a logic inversion of the operation signal gvp on a negative-going edge of the operation signal gup. The surge noise is suppressed by elongating a switching time when the polarity is inverted. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a drive device and a power conversion system for driving a voltage-controlled switching element of a power conversion circuit connected to a multiphase rotating electrical machine.

As this type of driving device, for example, as shown in Patent Document 1 below, when starting an inverter connected to a three-phase motor, it is also proposed to reduce the voltage applied to the gate of the switching element. ing. Thereby, the rise of the current flowing between the input / output terminals of the switching element when the inverter is started can be mitigated.
JP 2001-268926 A

  Incidentally, in recent years, with the demand for higher performance of electric motors, the voltage applied to the electric motors also tends to increase. Under such circumstances, in a motor, so-called partial discharge in which charge transfer occurs via an insulating film between the windings is likely to occur. In particular, it has been found that partial discharge tends to occur when the polarity of the interphase voltage applied to the electric motor is reversed.

  As a measure for suppressing or avoiding this partial discharge, it is conceivable to increase the insulating property by increasing the thickness of the insulating film. However, in this case, the space factor of the electric motor is lowered, and as a result, the electric motor may be increased in size.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a driving device for a power conversion circuit and a power conversion system capable of suitably suppressing partial discharge.

  Hereinafter, means for solving the above-described problems and the operation and effects thereof will be described.

  According to the first aspect of the present invention, in the power conversion circuit connected to the multiphase rotating electrical machine, in the drive device for driving the voltage-controlled switching element, the polarity of the interphase voltage applied to the multiphase rotating electrical machine is reversed. And a changing means for changing an operation mode of the switching element when it is determined that the polarity is reversed.

  In the above invention, by providing the determination means, it is possible to grasp the inversion timing of the polarity of the applied interphase voltage, which is the timing at which partial discharge is particularly likely to occur. For this reason, by changing the operation mode of the switching element at this time, for example, application of voltage to the conduction control terminal can be changed so as to suppress surge noise, and thus partial discharge can be suitably suppressed.

  The invention according to claim 2 is characterized in that, in the invention according to claim 1, the changing means includes an extending means for extending a switching time of the switching state of the switching element when it is determined that the polarity is reversed. And

  The surge noise is reduced as the switching time of the switching state is extended. That is, when the switching element is switched from the on state to the off state, the change in voltage between the input and output terminals of the switching element is reduced as the switching time is extended, and surge noise due to the change in the voltage is suppressed. Further, when the power conversion circuit includes a rectifying means in parallel with the switching element, when the switching element is switched from the off state to the on state, the longer the switching time, the greater the switching time between the input and output terminals of the switching element. Changes in the flowing current are alleviated, and surge noise generated between the phases is reduced.

  According to a third aspect of the present invention, in the first or second aspect of the present invention, the determination means includes a means for obtaining an operation signal of the switching element, and for any two phases of the multiphase rotating electrical machine. Based on the operation signal, it is determined whether or not the polarity of the interphase voltage between the two phases is reversed.

  In the said invention, the presence or absence of polarity inversion can be judged appropriately based on the operation signal. In particular, when the power conversion circuit constitutes a high voltage system and the operation signal is generated in the low voltage system, it is possible to determine whether the polarity is reversed or not in the high voltage system. When outputting to the changing means, it is not necessary to use means for insulating the high pressure system from the low pressure system.

  According to a fourth aspect of the present invention, in the third aspect of the present invention, the operation signal is generated based on a magnitude relationship between a command voltage for the multi-phase rotating electrical machine and a carrier. For any two phases, the logical value of the operation signal of the other phase at the time of either switching from the on-state to the off-state or switching from the off-state to the on-state of the switching element of one of the phases The presence or absence of the polarity inversion is determined based on the change.

  When the operation signal is generated based on the magnitude of the command voltage and the carrier, the period during which the corresponding switching element is turned on or off is determined according to the magnitude relationship of the command voltage. In particular, whether the period during which the switching element of any phase is in the on state (off state) is included in the period of the on state (off state) of the switching element in another phase or whether this period is included depends on the command voltage It is uniquely determined according to the size relationship. Therefore, the timing at which the logic value of the operation signal of the switching element of the other phase is inverted when the switching element of one switching element is turned off or turned on can coincide with the timing at which the inversion of the inclusion relationship occurs. In other words, it can coincide with the timing at which polarity inversion occurs. In the above invention, by paying attention to this point, the presence or absence of polarity inversion can be suitably determined.

  The relationship between the one phase and the other phase in the determining means when changing the operation mode of the switching element of each phase is the same as that in the determining means when changing the operation mode of any one phase switching element. It is desirable that the relationship is obtained by cyclically replacing the relationship on the basis of the relationship.

  Further, it is preferable that the changing means changes the operation state of the switching element of the one phase when it is determined that the polarity is reversed.

  According to a fifth aspect of the present invention, in the invention according to the third or fourth aspect, the operation signal is generated based on a magnitude relationship between a command voltage for the multi-phase rotating electrical machine and a carrier. , With respect to the arbitrary two phases, the logical value of the operation signal of the other phase in accordance with either switching from the on-state to the off-state or switching from the off-state to the on-state of one of the phases And a pulse generating means for generating a one-shot pulse signal indicating that the polarity is inverted based on a change in the value stored by the storing means.

  When the operation signal is generated based on the magnitude of the command voltage and the carrier, the period during which the corresponding switching element is turned on or off is determined according to the magnitude relationship of the command voltage. In particular, whether the period during which the switching element of any phase is in the on state (off state) is included in the period of the on state (off state) of the switching element in another phase or whether this period is included depends on the command voltage It is uniquely determined according to the size relationship. Therefore, the timing at which the logical value of the operation signal of the switching element of the other phase is reversed when the switching element of one phase is switched to the OFF state or the ON state is coincident with the timing at which the inversion of the inclusion relationship is generated. obtain. In other words, it can coincide with the timing at which polarity inversion occurs. In the above invention, paying attention to this point, it is possible to suitably determine the presence or absence of polarity reversal by providing the storage means and the pulse generation means.

  The relationship between the one phase and the other phase in the determining means when changing the operation mode of the switching element of each phase is the same as that in the determining means when changing the operation mode of any one phase switching element. It is desirable that the relationship is obtained by cyclically replacing the relationship on the basis of the relationship.

  Further, it is preferable that the changing means changes the operation state of the switching element of the one phase when it is determined that the polarity is reversed.

  The invention according to claim 6 is the invention according to claim 4 or 5, wherein after the polarity of the interphase voltage applied to the multiphase rotating electrical machine is inverted, the interphase voltage becomes zero and becomes the polarity after the inversion again. It further comprises post-inversion judgment means for judging timing, and the change means continues to change the operation mode of the switching element when it is judged that the timing is the polarity after the inversion again. .

  Even after the polarity is reversed, partial discharge is likely to occur near the timing of the reversal because the charge distribution between the phases of the multiphase rotating electrical machine can be approximated at the time of polarity reversal. In this regard, in the above invention, surge noise can be further suppressed by changing the operation mode of the switching element at the timing when the polarity is reversed again after polarity reversal, and thus partial discharge is even more suitable. Can be suppressed.

  The invention according to claim 7 is the invention according to claim 6, wherein the carrier gradually increases at the rising edge and gradually decreases at the falling edge, and the post-inversion judging means is the switching element of the other phase. The determination is performed based on a change in the logical value of the operation signal of the one phase when switching to a different side from the above.

  When using the carrier, when the inversion phenomenon of the inclusion relationship accompanying polarity inversion occurs, the ON state (OFF state) period of the switching element of one phase is the ON state (OFF state) of the switching element of the other phase. ) Of the phase is completely included in such a manner that both ends thereof do not coincide with each other, or the period of one phase is completely included in the period of the other phase. For this reason, the timing of the polarity after inversion again after the switching timing to one state for the switching element of one phase is the switching timing to the side different from any of the switching elements of the other phase. Become. In the above-mentioned invention, paying attention to this point, it is possible to appropriately determine the timing for shifting again to the polarity after inversion.

  The invention according to claim 8 is the invention according to claim 6 or 7, wherein the carrier gradually increases at the rising edge and gradually decreases at the falling edge. Storage means for storing the logical value of the operation signal of the one phase in accordance with switching to a different side of the switching element, and after the inversion again based on a change in the value stored by the storage means And a pulse generation means for generating a one-shot pulse signal to the effect that the polarity is

  When using the carrier, when the inversion phenomenon of the inclusion relationship accompanying polarity inversion occurs, the ON state (OFF state) period of the switching element of one phase is the ON state (OFF state) of the switching element of the other phase. ) Of the phase is completely included in such a manner that both ends thereof do not coincide with each other, or the period of one phase is completely included in the period of the other phase. For this reason, the timing at which the polarity after reversal after the switching timing to one state for the switching element of one phase is the switching timing to the side different from any of the switching elements of the other phase is Become. In the above invention, paying attention to this point, the storage means and the pulse generation means are provided, so that it is possible to appropriately determine the timing for shifting again to the polarity after inversion.

  The invention according to claim 9 is the invention according to any one of claims 1 to 8, wherein the changing means variably sets a path for applying a voltage to the conduction control terminal of the switching element and a resistance value of the path. It is characterized by comprising with a means to do.

  When the resistance value of the path for applying a voltage to the conduction control terminal of the switching element is changed, the charge rate of charge to the conduction control terminal and the charge discharge rate from the conduction control terminal change. In particular, the switching time for switching can be extended by increasing the resistance value of the path.

  The invention according to claim 10 is the invention according to any one of claims 1 to 8, wherein the changing means changes a voltage applied to a conduction control terminal of the switching element so as to switch a switching state of the switching element. It is characterized by comprising means for temporarily changing the applied voltage to the opposite side to the changing direction in the course of the process.

  In the above invention, the applied voltage is temporarily changed to the opposite side to the changing direction in the course of changing the voltage applied to the conduction control terminal. When this process is performed when the switching element is switched to the OFF state, a change in voltage between the input / output terminals of the switching element at the time of switching can be reduced. Further, when this process is performed when the switching element is switched to the ON state, a change in current flowing between the input / output terminals of the switching element at the time of switching can be reduced. For this reason, the surge noise at the time of switching can be suppressed suitably.

  A power conversion system comprising: the power conversion circuit drive device according to any one of claims 1 to 10; and the power conversion circuit.

(First embodiment)
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a first embodiment in which a power conversion circuit driving device and a power conversion system according to the present invention are applied to a motor generator power conversion circuit driving device and a power conversion system mounted on a hybrid vehicle. This will be described with reference to FIG.

  FIG. 1 shows the overall configuration of a motor generator control system according to this embodiment.

  As illustrated, an inverter 12 is connected to three phases (U phase, V phase, and W phase) of a motor generator 10 as a three-phase electric motor / generator. The inverter 12 is a three-phase inverter, and appropriately applies the voltage of the high voltage battery 14 to the three phases of the motor generator 10. Specifically, the inverter 12 is a parallel connection body of the switching elements SW1, SW2, the switching elements SW3, SW4, and the switching elements SW5, SW6 so that each of the three phases and the positive electrode side or the negative electrode side of the high voltage battery 14 are electrically connected. It is configured with. A connection point for connecting switching element SW <b> 1 and switching element SW <b> 2 in series is connected to the U phase of motor generator 10. Further, a connection point for connecting switching element SW3 and switching element SW4 in series is connected to the V phase of motor generator 10. Furthermore, a connection point for connecting switching element SW5 and switching element SW6 in series is connected to the W phase of motor generator 10. Incidentally, these switching elements SW1 to SW6 are constituted by insulated gate bipolar transistors (IGBT) in this embodiment. The inverter 12 includes flywheel diodes D1 to D6 connected in antiparallel to the switching elements SW1 to SW6.

  A capacitor 16 is connected in parallel between the parallel connection body of the switching elements SW1 and SW2, the switching elements SW3 and SW4, and the switching elements SW5 and SW6 and the high voltage battery 14. Furthermore, a drive circuit DS for applying a drive voltage to the gate is connected to the conduction control terminals (gates) of the switching elements SW1 to SW6.

  The switching elements SW1 to SW6 are operated via the interface 18 by a microcomputer (microcomputer 20) using the low voltage battery 22 as a power source. Here, the interface 18 is configured to include an insulating element such as a photocoupler, and insulates the low-voltage system including the microcomputer 20 from the high-voltage system including the inverter 12 and the like, It is possible to send and receive signals with both of them. Further, the microcomputer 20 controls the motor generator 10 and performs various controls according to a request from the user and the state of the motor generator 10. That is, the microcomputer 20 generates the operation signals gup, gun, gvp, gvn, gwp, and gwn of the switching elements SW1 to SW6 by PWM control using the command voltage and the carrier, and supplies this to the drive circuit DS through the interface 18. Output. Thereby, switching elements SW1 to SW6 of inverter 12 are operated, and the rotational state of motor generator 10 and the like are controlled.

  FIG. 2 shows a processing mode of PWM control according to the present embodiment. Specifically, FIG. 2A shows the transition of the command voltage, FIG. 2B shows the transition of the operation signal gup of the switching element SW1 of the U-phase upper arm, and FIG. The transition of the operation signal gun of the switching element SW2 of the side arm is shown. FIG. 2D shows the transition of the operation signal gvp of the switching element SW3 of the V-phase upper arm, and FIG. 2E shows the transition of the operation signal gvn of the switching element SW4 of the V-phase lower arm. . FIG. 2 (f) shows the transition of the operation signal gwp of the switching element SW5 of the W-phase upper arm, and FIG. 2 (g) shows the transition of the operation signal gwn of the switching element SW6 of the W-phase lower arm. FIG. 2 (h) shows the transition of the U-phase voltage relative to the V phase, FIG. 2 (i) shows the transition of the V-phase voltage relative to the W phase, and FIG. 2 (j) shows the W phase relative to the U phase. The transition of the interphase voltage is shown.

  As shown in FIG. 2A, in this embodiment, a triangular wave that gradually increases at the rising edge and gradually decreases at the falling edge is used as the carrier. Further, sine waves are used as the command voltages vuc, vvc, vwc. The upper arm operation signals gup, gvp, and gwp are set to logic “H” when the command voltages vuc, vvc, and vwc are larger than the carrier. The lower arm operation signals gun, gvn, and gwn are logically inverted signals of the upper arm operation signals gup, gvp, and gwp (more precisely, the dead time is generated by shaping the waveform) ). By generating the operation signal in this way, the voltage applied to the motor generator 10 can suitably follow the command voltages vuc, vvc, vwc.

  By the way, in the motor generator 10, the location where the distance of arbitrary two-phase windings mutually approaches (closes) arises. And when a big difference arises in the voltage applied to these two phases, there exists a possibility that partial discharge may arise between these two phases. In particular, when the polarity of the interphase voltage applied between any two phases is reversed, partial discharge tends to occur. FIG. 3 shows experimental results showing that partial discharge is likely to occur during polarity reversal.

  FIG. 3A and FIG. 3B show whether or not partial discharge occurs when a voltage is applied between two adjacent wires via an insulator. In particular, FIG. 3 (a) shows a case where the voltage applied between these two electric wires changes from a negative voltage to a positive voltage through zero, and FIG. 3 (b) shows the case between the two electric wires. The case where the applied voltage is changed from a positive voltage to a positive voltage through zero is shown. As shown in the figure, partial discharge is more likely to occur when the polarity of the voltage applied between the two wires is reversed. This is because, by applying a voltage to each of the two wires, opposite charges are generated around them, and when the polarity is reversed thereafter, the charges generated around the wires before the inversion and the polarity reversal. This is considered to be caused by an increase in the potential difference between two adjacent lines due to the electric charge generated in the electric wire.

  If partial discharge continues, the reliability of the motor generator 10 is reduced. Here, even if the withstand voltage in the motor generator 10 is set according to the voltage of the high voltage battery 14, partial discharge may be unavoidable. This is because the interphase voltage can be larger than the voltage of the high voltage battery 14 due to the occurrence of surge noise when switching the switching states of the switching elements SW1 to SW6. That is, when the switching elements SW1 to SW6 are switched from the on-state to the off-state, the voltage between the collector and the emitter suddenly rises and surge noise occurs. Further, when the switching elements SW1 to SW6 are switched from the OFF state to the ON state, the collector current increases rapidly, so that the current flowing through the diodes D1 to D6 of the arm on the opposite side of the corresponding phase rapidly increases. Surge noise occurs due to the decrease.

  For this reason, in order to suppress the occurrence of partial discharge, it is effective to suppress the superposition of surge noise between phases. Here, in order to suppress the surge noise, it is effective to reduce the charge charge rate to the gate and the charge discharge rate from the gate when switching the switching states of the switching elements SW1 to SW6. As a result, when the state of the switching elements SW1 to SW6 switches from the on state to the off state, the rate of increase of the voltage between the collector and the emitter is reduced, and surge noise is suppressed. Further, when the switching elements SW1 to SW6 are switched from the off state to the on state, the increasing speed of the collector current is reduced, and thus surge noise is suppressed. However, when the switching time is extended by reducing the charge rate or the discharge rate, the switching loss increases. As described above, the surge noise reduction processing and the switching loss reduction are in a trade-off relationship.

  Therefore, in this embodiment, it is determined whether or not the polarity of the interphase voltage applied to the motor generator 10 is reversed, and the charge rate and the discharge rate are reduced only in the vicinity of the timing when the polarity is determined to be reversed. Hereinafter, a method for determining polarity inversion will be described in detail.

  In FIG. 4A, in the positive region (region larger than the amplitude center), the magnitude relationship is reversed when the U-phase command voltage vuc and the V-phase command voltage vvc are larger than the carrier. The transition of the operation signals gup, gvp and the UV interphase voltage is shown. As shown in the figure, when the U-phase command voltage vuc is higher than the V-phase command voltage vvc, the period in which the operation signal gup is logic “H” is the period in which the operation signal gvp is logic “H”. Are completely included. On the other hand, when the U-phase command voltage vuc is lower than the V-phase command voltage vvc, the period during which the operation signal gup is logic “H” is the same as the period during which the operation signal gvp is logic “H”. Included. For this reason, the timing at which the polarity reversal occurs when the command voltage vuc changes from the state where the command voltage vuc is higher to the state where the command voltage vvc is higher coincides with the falling edge of the U-phase operation signal gup. Specifically, it coincides with the timing at which the logical value of the V-phase operation signal gvp is inverted at the falling edge of the U-phase operation signal gup. Thereby, the presence or absence of polarity inversion can be determined appropriately.

  Further, after the polarity inversion, the timing of the polarity after the inversion again coincides with the rising edge of the V-phase operation signal gvp. Specifically, it coincides with the timing at which the logical value of the U-phase operation signal gup changes at the rising edge of the V-phase operation signal gvp.

  Thus, the polarity reversal timing when the command voltage is positive and greater than the carrier is the logic of the operation signal that becomes larger at the falling edge where the applied voltage (command voltage) becomes smaller after reversal. This is the timing at which the value changes. Further, the timing at which the polarity is reversed again after the reversal is the timing at which the logical value of the smaller operation signal changes at the rising edge that is larger.

  Here, when operating the switching elements SW1, SW3, and SW5 of the upper arm, it is only necessary to determine the presence or absence of polarity reversal only in the region where the command voltage is positive. This is because no current flows through the switching elements SW1, SW3, SW5 of the upper arm in the region where the command voltage is negative. On the other hand, in the operation signals gun, gvn, and gwn of the lower arm, it is only necessary to determine the presence / absence of polarity reversal only in the negative command voltage region.

  However, since the lower arm operation signals gun, gvn, and gwn are logically inverted signals of the upper arm operation signals gup, gvp, and gwp, in the above, the larger applied voltage is the smaller one and the smaller one is the smaller one. Should be read as larger. That is, the polarity inversion timing is the timing at which the logical value of the smaller operation signal changes at the falling edge where the applied voltage (command voltage) increases after inversion. In addition, after the inversion, the timing at which the polarity is reversed again is the timing at which the logical value of the larger operation signal changes at the smaller rising edge.

  From the above, when the magnitude relationship of the command voltage is reversed when the command voltage is larger than the carrier, the polarity inversion timing referred to for both the upper arm and the lower arm is the difference between the applied voltage (command voltage) and the amplitude center after the inversion. At the falling edge where the absolute value of the difference becomes smaller, the timing at which the logical value of the operation signal whose absolute value becomes larger changes. In addition, after the inversion, the timing at which the polarity is inverted again is the timing at which the logical value of the operation signal with the smaller absolute value changes at the rising edge with the larger absolute value.

  However, as can be seen from the example shown in FIG. 4B, when the magnitude relationship of the command voltage is reversed in an area smaller than the carrier, the polarity inversion timing and the timing at which the polarity is inverted again after the inversion are obtained. The combination with the edge timing is reversed. In FIG. 4B, in the positive region (region larger than the amplitude center), the magnitude relationship is reversed when the U-phase command voltage vuc and the V-phase command voltage vvc are smaller than the carrier. The transition of the operation signals gup, gvp and the UV interphase voltage is illustrated.

  In the PWM control, normally, the update cycle of the command voltages vuc, vvc, vwc and the carrier cycle coincide with each other, and the update timing is a carrier peak (maximum value) or valley (minimum value). For this reason, in such a case, the reversal of the magnitude relationship of the command voltage occurs only in one of the regions larger or smaller than the carrier, and does not occur in the other. Incidentally, FIG. 4A shows an example in which the command voltage is updated at the carrier valley, and FIG. 4B shows an example in which the command voltage is updated at the carrier peak.

  FIG. 5 shows an internal configuration of the drive circuit DS that applies a voltage to the gates of the switching elements SW1 to SW6 while inverting the polarity by the above method. The drive circuits DS have the same structure, but the drive circuit DS of the U-phase upper arm is illustrated in the drawing. Hereinafter, the switching elements SW1 to SW6 are collectively referred to as a switching element SW.

  The drive circuit DS includes a voltage level converter 30. The voltage level converter 30 converts the voltage level of the signal received from the input terminal T1 into an appropriate voltage level for applying to the gate of the switching element SW. The output signal of the voltage level converter 30 is taken into the buffer 32. The buffer 32 includes, for example, an emitter follower. The output of the buffer 32 is applied to the gate of the switching element SW (for example, the switching element SW1) via the resistor 34 and the output terminal T4. A switching element 36 and a resistor 38 are connected in parallel to the resistor 34. Thereby, when the switching element 36 is turned on, the resistance value between the gates of the buffer 32 and the switching element SW is reduced as compared with the case where the switching element 36 is turned off.

  In the flip-flop 40, the absolute value of the difference between the phase command voltage corresponding to the input terminal T1 and the amplitude center is larger than the absolute value of the difference between the phase command voltage corresponding to the input terminal T2 and the amplitude center. This is to detect the polarity reversal timing when the command voltage is shifted from a small to a small state in a state where the command voltage is larger than the carrier. In addition, the flip-flop 40 has the polarity after the inversion again immediately after the polarity inversion at the time of the transition in a state where the command voltage of the phase corresponding to the input terminal T1 and the command voltage of the phase corresponding to the input terminal T2 are smaller than the carrier. The timing which becomes is detected. The flip-flop 40 captures a signal obtained by logically inverting the signal captured from the input terminal T1 by the inverter 42 to the clock terminal. Then, in synchronization with the rising edge of the signal taken in through the clock terminal, the signal inputted from the input terminal T2 is taken into the D input terminal. As a result, the signal output from the Q output terminal is updated with the signal newly taken into the D input terminal.

  A one-shot circuit 44 is connected to the Q output terminal of the flip-flop 40. The one-shot circuit 44 outputs a logic “H” pulse signal triggered by a rising edge of an input signal, that is, a signal output from the Q output terminal of the flip-flop 40. This pulse signal becomes logic “H” only for about one switching time.

  On the other hand, in the flip-flop 46, the absolute value of the difference between the phase command voltage corresponding to the input terminal T3 and the amplitude center is larger than the absolute value of the difference between the phase command voltage corresponding to the input terminal T1 and the amplitude center. From the large state to the small state, the timing at which the polarity after the reversal is detected again immediately after the reversal of polarity when the command voltage is shifted to a state larger than the carrier is detected. In addition, the flip-flop 46 has a polarity after the reversal immediately after the polarity reversal at the time of the transition in a state where the command voltage of the phase corresponding to the input terminal T3 and the command voltage of the phase corresponding to the input terminal T1 are smaller than the carrier. The timing which becomes is detected. The flip-flop 46 takes in the signal input to the input terminal T1 to the clock terminal. Then, the signal input from the input terminal T3 is input to the D input terminal in synchronization with the rising edge of the signal acquired via the clock terminal. Then, an inverted signal of the captured signal is output from the inverted output terminal.

  A one-shot circuit 48 is connected to the inverting output terminal of the flip-flop 46. The one-shot circuit 48 outputs a logic “H” pulse signal triggered by the rising edge of the input signal, that is, the signal output from the inverting output terminal of the flip-flop 46. This pulse signal becomes logic “H” only for about one switching time.

  The outputs of the one-shot circuits 44 and 48 are taken into the OR circuit 49. The OR circuit 49 outputs a logical sum signal of these outputs to the switching element 36. As a result, the switching element 36 is turned off only during the period when the pulse signal is output by the one-shot circuits 44 and 48. In other words, when the signal fetched from the input terminal T2 is logically inverted at the falling edge of the signal fetched from the input terminal T1, and when the signal fetched from the input terminal T3 is logically inverted at the rising edge of the signal fetched from the input terminal T1. It turns off only when reversing. Thereby, only when the polarity of the interphase voltage is inverted and when the polarity is inverted again immediately after the inversion, the charge rate to the gate and the discharge rate from the gate can be reduced. Incidentally, FIG. 2 shows the detection mode of the polarity reversal of the UV interphase voltage.

  The U-phase, V-phase, and W-phase operation signals gup, gvp, and gwp input to the input terminals T1 to T3 of the V-phase and W-phase drive circuit DS of the upper arm are input to the U-phase drive circuit DS. Using the pattern as a reference, this can be obtained by cyclic replacement in the order of V phase and W phase. Further, the U-phase, V-phase, and W-phase operation signals gn, gvn, and gwn input to the input terminals T1 to T3 of the V-phase and W-phase drive circuit DS of the lower arm are supplied to the U-phase drive circuit DS. Using the input pattern as a reference, it can be obtained by cyclically replacing this in the order of V phase and W phase.

  FIG. 6 illustrates an operation mode of the switching element SW1 at the time of polarity reversal by the above circuit. Specifically, FIG. 6A shows the transition of the U-phase operation signal gup, FIG. 6B shows the transition of the output signal of the flip-flop 40, and FIG. 6C shows the one-shot circuit 44. FIG. 6D shows the transition of the collector current of the switching element SW1, and FIG. 6E shows the transition of the voltage between the collector and the emitter of the switching element SW1.

  As shown in the figure, a pulse signal is output from the one-shot circuit 44 when the output of the flip-flop 40 is inverted to logic “H” in synchronization with the falling edge of the operation signal gup of the switching element SW1. Thereby, since the switching element 36 is turned off, the discharge rate of the gate is lowered, and the decrease rate of the collector current and the increase rate of the voltage between the collector and the emitter are alleviated. As a result, surge noise accompanying a rise in voltage between the collector and the emitter is reduced. In FIGS. 6D and 6E, a broken line indicates an example in which the gate discharge rate is not reduced.

  According to the embodiment described in detail above, the following effects can be obtained.

  (1) When it is determined that the polarity is reversed, the switching time of the switching elements SW1 to SW6 is extended. Thereby, the surge noise at the time of a polarity reversal can be suppressed suitably, and a partial discharge can be suppressed suitably by extension.

  (2) Based on the operation signals gup, gun, gvp, gvn, gwp, gwn output to the motor generator 10 side (high voltage system side) via the interface 18, it was determined whether or not the polarity of the interphase voltage was reversed. Thereby, when it is determined that polarity reversal occurs, a command signal for switching the switching element 36 to the OFF state can be generated in the high voltage system without being output from the microcomputer 20. Therefore, the switching state of the switching element 36 can be switched without increasing the number of insulating means that insulate the low voltage system including the microcomputer 20 from the high voltage system including the inverter 12.

  (3) The flip-flop 40 that stores the logical value of the signal fetched from the input terminal T2 in synchronization with the falling edge of the signal fetched from the input terminal T1, and the rise of the signal output from the Q output terminal of the flip-flop 40 And a one-shot circuit 44 that generates a pulse signal in synchronization with the edge. In addition, in synchronization with the rising edge of the signal fetched from the input terminal T1, the flip-flop 46 that stores the signal fetched from the input terminal T3, and in synchronization with the rising edge of the signal output from the inverting output terminal of the flip-flop 46. And a one-shot circuit 48 for outputting a pulse signal. Thus, the flip-flops 40 and 46 can suitably determine the presence / absence of polarity reversal and reversal after polarity reversal, and appropriately set the period during which the switching element 36 is turned on by the pulse signal. it can.

  (4) After the polarity of the interphase voltage is inverted, the timing when the phase voltage becomes zero and the polarity after the inversion is determined again is determined, and the switching element SW1 is also determined when it is determined that the timing becomes the polarity after the inversion again. ~ SW6 switching time was extended. Thereby, surge noise can be suppressed more suitably, and by extension, partial discharge can be suppressed more suitably.

  (5) By configuring the path for applying a voltage to the gates of the switching elements SW1 to SW6 including the resistors 34 and 38 and the switching element 36, the resistance value of the path is variably set. According to such a configuration, the switching time of the switching state can be extended by increasing the resistance value of the path.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  FIG. 7 shows a circuit configuration of the drive circuit DS according to the present embodiment. In FIG. 7, the same members as those in FIG.

  The one-shot circuit 44a generates a pulse signal in synchronization with the rising edge of the signal output from the Q output terminal of the flip-flop 40. However, the one-shot circuit 44a generates a pulse signal when shifting to the mirror period after the discharge of the gate of the switching element SW is started in synchronization with the falling edge of the signal input from the input terminal T1. , Has a function of causing a delay with respect to the falling timing. The pulse signal output from the one-shot circuit 44a is taken into the voltage level converter 50. The voltage level converter 50 converts the voltage level to the same voltage level as that by the voltage level converter 30 according to the logic level of the output signal of the one-shot circuit 44a. The buffer 52 for capturing the output signal of the voltage level converter 50 has the same configuration as the buffer 32. The output terminal of the buffer 52 is connected to the anode side of the diode 54, and the cathode side of the diode 54 is connected between the buffer 32 and the resistor 34.

  On the other hand, the one-shot circuit 48 a generates a pulse signal having a logic “L” in synchronization with the rising edge of the signal output from the inverting output terminal of the flip-flop 46. The one-shot circuit 48a rises in synchronization with the rising edge of the signal input from the input terminal T1 so as to generate a pulse signal when shifting to the mirror period after the gate of the switching element SW is started to be charged. It has a function of causing a delay with respect to the timing. The pulse signal output from the one-shot circuit 48 a is taken into the voltage level converter 56. The voltage level converter 56 converts the voltage level to the same voltage level as that of the voltage level converter 30 according to the logic level of the output signal of the one-shot circuit 48a. The output of the voltage level converter 56 is connected to the cathode side of the diode 60 via the buffer 58, and the anode side of the diode 60 is connected between the buffer 32 and the resistor 34.

  FIG. 8 shows processing in the vicinity of the U-phase polarity reversal by the above circuit. Specifically, FIG. 8A shows the transition of the U-phase operation signal gup, FIG. 8B shows the transition of the signal at the Q output terminal of the flip-flop 40, and FIG. 8C shows the flip-flop. FIG. 8D shows the transition of the pulse signal output from the one-shot circuit 44a, and FIG. 8E shows the transition of the pulse signal output from the one-shot circuit 48a. Indicates. Further, FIG. 8 (f) shows the transition of the gate voltage of the switching element SW1, FIG. 8 (g) shows the transition of the collector current of the switching element SW1, and FIG. 8 (h) shows the collector of the switching element SW1. And the transition of the voltage between the emitters.

  As shown in the figure, the output signal of the Q output terminal of the flip-flop 40 is inverted to logic “H” in synchronization with the falling edge of the operation signal gup, and the voltage applied to the gate of the switching element SW1 by the buffer 32 is The logic is set to “L”, and the gate voltage decreases. Then, after a predetermined time has elapsed from the falling timing and the transition to the mirror period in which the change in the gate voltage temporarily stagnates, a pulse signal of logic “H” is output from the one-shot circuit 44a. As a result, the voltage of the gate of the switching element SW1 rises to about a value obtained by subtracting the voltage drop due to the diode 54 from the output voltage of the buffer 52. Then, when the output of the one-shot circuit 44a is inverted again to the logic “L”, the gate voltage decreases to a value before the output of the pulse signal, and then the gate voltage is a value corresponding to the logic “L” at the end of the mirror period. Drop to. As a result, as indicated by a solid line in FIG. 8H, surge noise accompanying a rise in the voltage between the collector and the emitter does not perform a temporary gate voltage rise process by the pulse signal (FIG. 8). (Represented by broken lines in (h)).

  In addition, the output signal of the inverting output terminal of the flip-flop 46 is inverted to logic “H” in synchronization with the rising edge of the operation signal gup, and the voltage applied to the gate of the switching element SW1 by the buffer 32 becomes logic “H”. And the gate voltage rises. Then, after a predetermined time has elapsed from the rising timing and the transition to the mirror period in which the change in the gate voltage temporarily stagnates, a pulse signal of logic “L” is output from the one-shot circuit 48a. As a result, the gate voltage of the switching element SW1 decreases to a value that is about the amount of voltage drop of the diode 60. When the output of the one-shot circuit 48a is inverted again to the logic “H”, the gate voltage rises to the value before the output of the pulse signal, and then the gate voltage is a value corresponding to the logic “H” at the end of the mirror period. Rise up to. As a result, as indicated by a solid line in FIG. 8G, the collector current does not perform a temporary gate voltage reduction process using the pulse signal (indicated by a broken line in FIG. 8G). Compared to reduction. For this reason, the surge noise resulting from the sudden change of collector current can be reduced suitably.

  According to the embodiment described above in detail, the following effects can be obtained in addition to the effects (2) to (5) of the first embodiment.

  (6) In order to switch the switching state of the switching elements SW to SW6, the voltage to be applied was temporarily changed in the direction opposite to the change direction in the course of changing the voltage to be applied to the gate. Thereby, the influence of the surge noise at the time of switching can be suppressed suitably.

(Third embodiment)
Hereinafter, the third embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  In the first embodiment, the drive circuit DS is configured on the assumption that the phase relationship between the command voltages vuc, vvc, and vwc is uniquely determined. However, when the rotation of the motor generator 10 is reversed due to the reverse of the vehicle or the like, the phase relationship between the command voltages vuc, vvc, and vwc changes. Specifically, in the case of positive rotation, as shown in FIG. 2, the command voltage vuc shifts from a state larger than the command voltage vvc to a smaller state in the positive region, and the command voltage in the negative region. The transition from a state where vuc is smaller than the command voltage vvc to a larger state is reversed in reverse rotation. That is, in the case of reverse rotation, the command voltage vuc shifts from a state smaller than the command voltage vvc to a larger state in the positive region, and the command voltage vuc is smaller from a state larger than the command voltage vvc in the negative region. Transition to the state.

  Therefore, the relationship between the U phase and the V phase at the time of forward rotation is equal to the relationship between the U phase and the W phase at the time of reverse rotation, and the relationship between the V phase and the W phase at the time of forward rotation is the same as the V phase at the time of reverse rotation. The relationship between the W phase and the U phase during forward rotation is equal to the relationship between the W phase and the V phase during reverse rotation. Therefore, when determining the polarity inversion of the interphase voltage during reverse rotation, it is necessary to change the signal input to the flip-flops 40 and 46 of the drive circuit DS.

  FIG. 9 shows a circuit configuration of the drive circuit DS according to the present embodiment. In FIG. 7, the same members as those in FIG.

  As shown in the figure, in the present embodiment, a selection unit 70 that switches how signals that are input from the input terminal T2 and the input terminal T3 are allocated to the D input terminal of the flip-flop 40 and the D input terminal of the flip-flop 46, respectively. I have. This selection part is operated by the switching signal taken in from the input terminal T5. That is, when the motor generator 10 is rotating forward, a signal taken from the input terminal T2 is assigned to the D input terminal of the flip-flop 40, and a signal taken from the input terminal T3 is assigned to the D input terminal of the flip-flop 46. On the other hand, during reverse rotation of motor generator 10, a signal taken in from input terminal T 2 is assigned to the D input terminal of flip-flop 46, and a signal taken in from input terminal T 3 is assigned to the D input terminal of flip-flop 40. Thereby, regardless of the rotation direction of motor generator 10, it is possible to suitably determine the polarity inversion of the interphase voltage.

  The switching signal fetched from the input terminal T5 is a signal common to all the drive circuits DS. This signal may be output from the microcomputer 20.

  According to this embodiment described in detail above, the following effects can be obtained in addition to the effects (1) to (6) of the first embodiment.

  (7) The signal input to the flip-flops 40 and 46 of the drive circuit DS was changed when determining the polarity reversal of the interphase voltage during reverse rotation. Thereby, regardless of the rotation direction of motor generator 10, it is possible to suitably determine the polarity inversion of the interphase voltage.

(Fourth embodiment)
Hereinafter, the fourth embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  FIG. 10 shows the overall configuration of the motor generator control system according to the present embodiment.

  In the present embodiment, a booster circuit 80 that boosts the voltage of the high-voltage battery 14 is provided. Therefore, the voltage applied to the interphase voltage of motor generator 10 is higher than the value applied by high voltage battery 14 and corresponds to the value boosted by booster circuit 80. For this reason, the insulation between the windings of the motor generator 10 is also of a level that can cope with the case where the booster circuit 80 is operating.

  However, in this case, when the booster circuit 80 is not used, the possibility of partial discharge in the motor generator 10 is reduced. For this reason, if the switching time is extended at the time of polarity reversal up to this point, only switching loss increases. Therefore, in the present embodiment, when the boosting operation by the booster circuit 80 is not performed, the switching state switching time extension process based on the polarity inversion is not performed.

  That is, when an operation command for the booster circuit 80 is issued from the microcomputer 20, this command is input not only to the booster circuit 80 but also to each drive circuit DS. When each drive circuit DS determines that a boosting operation is being performed based on this input signal (step S10: YES in the flowchart in the figure), the polarity determination is performed (step S12), but the boosting operation is being performed. If it is determined that it is not (step S10: NO), the polarity is not determined (step S14).

  According to this embodiment described in detail above, the following effects can be obtained in addition to the effects (1) to (6) of the first embodiment.

  (8) When the booster circuit 80 is stopped, the switching switching time extension process at the time of polarity inversion is prohibited, so that the switching loss can be reduced as much as possible while suppressing the partial discharge.

(Other embodiments)
Each of the above embodiments may be modified as follows.

  The previous second and fourth embodiments may be changed according to the changes from the first embodiment in the third embodiment.

  -You may change previous 2nd Embodiment by the change from 1st Embodiment in the said 4th Embodiment.

  In the third embodiment, during reverse rotation, a signal applied to the clock terminal of the flip-flop 40 is taken as a signal taken from the input terminal T1, and a signal applied to the clock terminal of the flip-flop 46 is taken from the input terminal T1. It may be a logic inversion signal of the signal to be transmitted.

  If the switching time is extended only at the time of polarity reversal, for example, the command voltage is updated only at the valley of the carrier and the flip-flop 46 is omitted, the command voltage is updated only at the peak of the carrier, and the flip-flop 40, etc. May be omitted.

  The carrier is not limited to a triangular wave but may be a sawtooth wave, for example. In this case, in the first embodiment, when using a sawtooth wave that rises to the right (a waveform that gradually increases and then returns to the initial value), a rising edge is used, and a sawtooth wave that descends to the right (step) When using a falling edge, the polarity inversion timing can be detected. This is because the edge generated by the timing at which the carrier crosses while gradually increasing or decreasing, of the timing at which the command voltage and the carrier intersect immediately after the reversal of the command voltage magnitude relationship, is the polarity inversion timing. When the sawtooth carrier is used, the polarity inversion timing can be reliably determined by providing only one of the flip-flops 40 and 46 in the drive circuit DS. In this case, the pulse width of the one-shot circuit may be extended if a measure against partial discharge is desired even at the timing of reversal after polarity reversal.

  In the above embodiment, the presence / absence of polarity inversion is determined based on the operation signals gup, gun, gvp, gvn, gwp, and gwn output from the microcomputer 20 constituting the vehicle-mounted low-voltage system to the high-voltage system. . For example, the presence or absence of polarity reversal may be determined when the operation signals gup, gun, gvp, gvn, gwp, gwn are generated in the microcomputer 20.

  In the case where it is determined that the polarity is reversed, the means for extending the switching time of the switching state of the switching element is not limited to those exemplified in the above embodiments. For example, the voltage finally applied to the conduction control terminal of the switching element (for example, the output of the voltage level converter 30 in FIG. 5) may be variable. Further, not limited to the expansion means, what is essential is that the operation mode of the switching element can be changed to suppress the partial discharge, such as the operation mode of the switching element that can be changed so as to suppress the surge noise.

  In addition, the drive device of the power conversion circuit is not limited to that mounted on the in-vehicle hybrid vehicle, and may be mounted on an electric vehicle, for example.

The figure which shows the whole structure of the control system of the motor generator concerning 1st Embodiment. The time chart which shows the PWM control aspect concerning the embodiment. The figure which shows the experimental result which shows that a partial discharge tends to produce at the time of polarity reversal. The time chart which shows the judgment method of the polarity reversal of the phase voltage in the said embodiment. The circuit diagram which shows the circuit structure of the drive circuit concerning the embodiment. The time chart which shows the process of the said drive circuit. The circuit diagram which shows the circuit structure of the drive circuit concerning 2nd Embodiment. The time chart which shows the process of the said drive circuit. The circuit diagram which shows the circuit structure of the drive circuit concerning 3rd Embodiment. The figure which shows the whole structure of the control system of the motor generator concerning 4th Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Motor generator, 12 ... Inverter, 20 ... Microcomputer, DS ... Drive circuit.

Claims (11)

For a power conversion circuit connected to a multi-phase rotating electrical machine, in a drive device that drives the voltage-controlled switching element,
Determining means for determining whether or not the polarity of the interphase voltage applied to the multiphase rotating electrical machine is reversed;
When the polarity is determined to be reversed, the driving device for the power conversion circuit, comprising: changing means for changing an operation mode of the switching element.   2. The driving device of the power conversion circuit according to claim 1, wherein the changing unit includes an extending unit that extends a switching time of a switching state of the switching element when it is determined that the polarity is reversed.   The determination means includes means for obtaining an operation signal for the switching element, and whether or not the polarity of the interphase voltage between the two phases is reversed based on the operation signal for any two phases of the multiphase rotating electrical machine. The drive device for a power conversion circuit according to claim 1 or 2, characterized in that The operation signal is generated based on the magnitude relationship between the command voltage and the carrier for the multiphase rotating electrical machine,
The determination means is configured to switch the other phase when switching the switching element of one of the two phases from the on-state to the off-state and the off-state to the on-state. 4. The driving device for a power conversion circuit according to claim 3, wherein the presence / absence of the polarity inversion is determined based on a change in a logical value of an operation signal. The operation signal is generated based on the magnitude relationship between the command voltage and the carrier for the multiphase rotating electrical machine,
The determination means is configured to operate the other phase with respect to any of the two phases by switching the switching element of one of the phases from the on state to the off state and switching from the off state to the on state. 4. A storage means for storing a logical value of the signal, and a pulse generation means for generating a one-shot pulse signal indicating that the polarity is inverted based on a change in the value stored by the storage means. Or the drive device of the power converter circuit of 4. After the polarity of the interphase voltage applied to the multi-phase rotating electrical machine is reversed, further comprising a post-inversion judging means for judging the timing when the interphase voltage becomes zero and becomes the polarity after the inversion again,
6. The driving of the power conversion circuit according to claim 4, wherein the change unit continues to change the operation mode of the switching element when it is determined that the timing at which the polarity after the reversal is reached again. apparatus. The carrier gradually increases at the rising edge and gradually decreases at the falling edge,
The post-inversion determining means performs the determination based on a change in the logical value of the operation signal of the one phase when the switching element of the other phase is switched to a different side from the one. The power conversion circuit drive device according to claim 6. The carrier gradually increases at the rising edge and gradually decreases at the falling edge,
The post-inversion judging means stores a logical value of the operation signal of the one phase when the switching element of the other phase is switched to a different side from the one, and the storage means stores the logical value. 8. A drive device for a power conversion circuit according to claim 6, further comprising: pulse generation means for generating a one-shot pulse signal indicating that the polarity after the inversion is changed again based on a change in the value to be inverted. .   The said changing means is provided with the path | route which applies a voltage to the conduction | electrical_connection control terminal of the said switching element, and the means to variably set the resistance value of this path | route, It is comprised, The one of the Claims 1-8 characterized by the above-mentioned. The drive device of the power converter circuit as described in 2.   In the course of changing the voltage applied to the conduction control terminal of the switching element in order to switch the switching state of the switching element, the changing means temporarily changes the applied voltage to the opposite side of the change direction. The drive device for a power conversion circuit according to claim 1, further comprising means for changing. A drive device for a power conversion circuit according to any one of claims 1 to 10,
A power conversion system comprising the power conversion circuit.

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