JP2008301094A - Digital signal transmission device, method, and system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct disorder of a waveform period at the time of transmission of a serial digital signal at a fixed clock rate by using a low-cost and flexible device capable of being integrated and to easily correct the disorder even in the case of a wide transmission rate width. <P>SOLUTION: A digital signal transmission device includes: a clock generation means 6 which generates a clock having a rate higher than a clock rate of a serial digital signal; a storage means 1 into which the input serial digital signal is written and from which the written serial digital signal is read out with the clock generated by the clock generation means 6 as a read clock; and a period control means 5 which controls a read address of the storage means 1 to increase/reduce the waveform period of the serial digital signal read out from the storage means 1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an apparatus, method and system for transmitting a serial digital signal having a fixed clock rate over a long distance.

  In a television broadcasting station, serial digital signals with a fixed clock rate such as AES / EBU digital audio signals, SDI format digital video signals, and LTC time codes are transmitted between various broadcasting devices such as switchers, mixers, and VTRs. ing.

  When such a serial digital signal having a fixed clock rate is transmitted via a long-distance cable, the period of the signal waveform may be disturbed during transmission. For example, an AES / EBU digital audio signal includes preambles X, Y, and Z that do not follow the rules of biface mark encoding for the purpose of identifying subframes. FIG. However, at the time of transmission, in these preambles, a waveform section for three clock cycles (referred to as a 3T section) and a waveform section for two clock cycles (referred to as a 2T section) are transmitted. The period may be extended, or the period of the waveform corresponding to one clock period (referred to as a 1T period) may be contracted.

Conventionally, the following methods (1) to (3) have been used to correct the disturbance of the waveform period during the transmission of the serial digital signal.
(1) The device on the output side of the serial digital signal pre-emphasizes the output signal.
(2) The device on the output side of the serial digital signal controls the inclination of the output signal (there is a similar method using a multi-value output driver as the output driver of the serial digital signal).
(3) The device on the input side of the serial digital signal applies the input signal to the cable equalizer.

  However, a dedicated device for performing pre-emphasis and tilt control of an output signal and a cable equalizer are relatively expensive and difficult to integrate flexibly.

  In the case of an AES / EBU digital audio signal, the clock rate differs depending on the audio sampling rate (for example, the clock rate is 6.144 MHz when the sampling rate is 48 kHz, but the clock rate is 96 kHz when the sampling rate is 96 kHz). Therefore, it is difficult to design a cable equalizer.

  On the other hand, a technique for generating a correction signal for a serial digital signal to be transmitted and outputting a serial digital signal obtained by adding the correction signal has also been proposed (see, for example, Patent Document 1). However, this technique also requires a dedicated device for generating a correction signal, which also increases the cost and makes integration difficult.

JP 2006-352374 A

  In view of the above-mentioned points, the present invention corrects a disturbance in the waveform period during transmission of a serial digital signal at a fixed clock rate using a device that can be integrated at low cost and has a wide transmission rate. It is also an object to make corrections easily.

In order to solve the above problems, a digital signal transmission device according to the present invention is a digital signal transmission device that transmits a serial digital signal having a fixed clock rate.
Clock generating means for generating a clock faster than the clock rate of the serial digital signal;
Storage means for writing the input serial digital signal, and reading the written serial digital signal using the clock generated by the clock generation means as a read clock;
Period control means for controlling increase / decrease of the waveform period of the serial digital signal read from the storage means by controlling the read address of the storage means.

The digital signal transmission method according to the present invention is a digital signal transmission method for transmitting a serial digital signal having a fixed clock rate.
A first step of generating a clock faster than a clock rate of the serial digital signal;
A second step of writing the input serial digital signal to a storage unit, and reading the serial digital signal written to the storage unit as a read clock from the clock generated in the first step;
And a third step of increasing / decreasing the waveform period of the serial digital signal read from the storage means by controlling the read address of the storage means.

  In this digital signal transmission apparatus and digital signal transmission method, a clock having a speed higher than the clock rate of the serial digital signal to be transmitted is generated. Then, the input serial digital signal is written in the storage means, and the serial digital signal is read from the storage means by using the high-speed clock as a read clock, and the read address of the storage means is controlled to control the read serial digital signal. Increase / decrease the waveform period.

  Since the waveform period of the serial digital signal can be controlled to increase or decrease in this way, the disturbance of the waveform period during the transmission of the serial digital signal is corrected by increasing or decreasing the waveform period in the direction opposite to the disturbance (cancellation). To be able to).

  As a device that generates a high-speed clock used as a read clock, for example, a general-purpose PLD (Programmable Logic Device) or a PLL (Phase-Locked Loop) mounted on an FPGA (Field Programmable Gate Array) may be used. Therefore, compared with the case where the waveform period disturbance is corrected using a dedicated device for pre-emphasis and inclination control of the output signal, or the case where the waveform period disturbance is corrected using a cable equalizer, the cost is low. Yes, flexible integration is possible.

  Even when the transmission rate width is wide, by setting the waveform cycle increase / decrease control amount in accordance with the transmission rate, the disturbance of the waveform cycle can be easily corrected.

Next, a digital signal transmission system according to the present invention is a digital signal transmission system comprising a first device and a second device each having an input unit and an output unit for serial digital signals at a fixed clock rate.
The first device is:
Measuring means for measuring disturbance of the waveform period of the serial digital signal input to the input unit;
Clock generating means for generating a clock faster than the clock rate of the serial digital signal;
Storage means for writing the serial digital signal input to the input unit, and reading the written serial digital signal using a clock generated by the clock generation means as a read clock;
By controlling the read address of the storage means, cycle control means for increasing / decreasing the waveform period of the serial digital signal read from the storage means;
Setting means for setting a control amount of the cycle control means based on a measurement result of the measurement means;
Information transmission means for transmitting information indicating the control amount set by the setting means to the second device, the serial digital signal read from the storage means is output from the output unit,
The second device is:
Information acquisition means for acquiring information indicating the control amount transmitted from the information transmission means of the first device;
Clock generating means for generating a clock faster than the clock rate of the serial digital signal;
Storage means for writing the serial digital signal input to the input unit, and reading the written serial digital signal using a clock generated by the clock generation means as a read clock;
By controlling the read address of the storage means, cycle control means for increasing / decreasing the waveform period of the serial digital signal read from the storage means;
Setting means for setting the control amount of the cycle control means to the control amount indicated by the information acquired by the information acquisition means, and the serial digital signal read from the storage means is output from the output unit. It is characterized by that.

  In this digital signal transmission system, the first device measures the disturbance of the waveform period of the serial digital signal input to the input unit. In addition, a clock that is faster than the clock rate of the serial digital signal is generated, the input serial digital signal is written to the storage means, the serial digital signal is read from the storage means using the high-speed clock as a read clock, and the waveform cycle By controlling the read address by a control amount set based on the measurement result of the disturbance, the waveform period of the serial digital signal to be read is increased or decreased. Then, the serial digital signal read from the storage unit is output from the output unit, and information indicating the control amount of the set read address is transmitted to the second device.

  The second device acquires information indicating the control amount transmitted from the first device. Also, a clock that is faster than the clock rate of the serial digital signal is generated, the input serial digital signal is written to the storage means, the serial digital signal is read from the storage means using the high-speed clock as a read clock, and acquired. By controlling the read address by the control amount indicated by the information, the waveform cycle of the serial digital signal to be read is increased or decreased. And the serial digital signal read from the memory | storage means is output from an output part.

  As described above, the first device outputs the serial digital signal whose waveform cycle is increased or decreased based on the measurement result of the disturbance of the waveform cycle of the input serial digital signal, and the second device is also the first device. A serial digital signal whose waveform cycle is increased or decreased by the same amount is output.

  Accordingly, if the output unit of the first device and the input unit of the second device and the output unit of the second device and the input unit of the first device are connected with a cable of equal length, Since the disturbance of the waveform period of the serial digital signal input to the second device and the disturbance of the waveform period of the serial digital signal input to the first device are equal, the serial digital signal is transmitted between the first device and the second device. In a normal cable connection mode for transmitting the signal (a loopback connection in which the connection between the first device and the second device is disconnected and the output unit and the input unit of the first device are connected with a cable) Without doing so, it is possible to measure the waveform period disturbance during transmission of the serial digital signal between the first device and the second device and correct the disturbance.

  As a device that generates a high-speed clock used as a read clock, for example, a general-purpose PLD or a PLL mounted on an FPGA may be used, so that low-cost and flexible integration is possible.

  Even when the transmission rate width is wide, by setting the waveform cycle increase / decrease control amount in accordance with the transmission rate, the disturbance of the waveform cycle can be easily corrected.

  According to the digital signal transmission apparatus and the digital signal transmission method according to the present invention, it is possible to correct the disturbance of the waveform period at the time of transmission of a serial digital signal having a fixed clock rate by using a device that can be integrated at low cost and flexibly. Moreover, it is possible to easily correct even when the transmission rate width is wide.

  According to the digital signal transmission system of the present invention, it is possible to integrate the waveform period disturbance at the time of transmission of a serial digital signal having a fixed clock rate between the first device and the second device at a low cost and in a flexible manner. It can be corrected using a device, and it can be easily corrected even when the transmission rate width is wide. Furthermore, a normal cable connection form for transmitting a serial digital signal between the first device and the second device is maintained ( There is an effect that correction can be performed without disconnecting the connection between the first device and the second device and performing a loopback connection in which the output unit and the input unit of the first device are connected by a cable.

  Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 2 is a block diagram showing a configuration example of a digital signal transmission apparatus to which the present invention is applied. This digital signal transmission device 10 is for correcting disturbances in the waveform period of the preamble of the AES / EBU digital audio signal, and is a dual port RAM 1 and a write address for generating a write address and a read address for the dual port RAM 1, respectively. A generator 2, a read address generator 3, a preamble detection circuit 4 for detecting a preamble of an AES / EBU digital audio signal, a cycle control circuit 5, and a PLL (Phase-Locked Loop) 6 are included.

  In the dual port RAM 1, the input AES / EBU digital audio signal is a transmission clock of the AES / EBU digital audio signal (for example, 6.144 MHz clock when the sampling rate of the AES / EBU digital audio signal is 48 kHz). Is written as a write clock.

  The write address generator 2 always supplies the current write address information to the preamble detection circuit 4. The preamble detection circuit 4 supplies information indicating the write address supplied from the write address generator 2 at the timing when the preamble is detected (that is, information indicating the write address of the preamble) to the cycle control circuit 5.

  The PLL 6 generates a clock faster than the transmission clock of the AES / EBU digital audio signal (as an example, a clock of 995.328 MHz≈1 GHz which is 162 times the transmission clock 6.144 MHz).

  The dual port RAM 1 is used as a FIFO memory, and the written AES / EBU digital audio signal is read using the clock generated by the PLL 6 as a read clock. That is, assuming that the transmission clock is 6.144 MHz, the time length of the waveform for one transmission clock cycle of the AES / EBU digital audio signal is 1 / 6144000≈163 ns (nanoseconds), so that the waveform is written at the address where the waveform is written. On the other hand, the waveform is read by repeatedly reading for 163 nanoseconds using the clock generated by the PLL 6 as a read clock.

  The cycle control circuit 5 controls the increase / decrease of the waveform cycle of the preamble by controlling the read address of the dual port RAM 1 when reading the preamble based on the information of the preamble write address supplied from the preamble detection circuit 4. Is supplied to the read address generator 3.

  When transmitting an AES / EBU digital audio signal via a long-distance cable, in a preamble that does not follow the biface mark encoding rules, a waveform period (3T period) for two clock periods or two clock periods The period of the waveform section (2T section) may be extended, or the period of the waveform section (1T section) for one clock period may be contracted.

  FIG. 3 is a diagram illustrating an actual measurement example of the disturbance of the waveform periods of the preambles X and Y when an AES / EBU digital audio signal is transmitted via a long-distance cable. Assuming that the transmission clock is 6.144 MHz, when there is no disturbance in the waveform period, the total time length of the preambles X and Y is 1.302 μs (microseconds) as shown in FIG. The periods of the 2T section and the 1T section are 489 ns, 326 ns, and 163 ns, respectively.

  On the other hand, after transmitting an AES / EBU digital audio signal via a cable having a length of 300 meters, in preamble X, as shown in FIG. Both the period of the 3T section of the eye became 502 ns (expanded by 13 ns), the period of the 1T section of the 7th bit became 145 ns (shrinked by 18 ns), and the period of the 1T section of the 8th bit became 155 ns (8 ns) Contracted). In the preamble Y, the period of the 1st to 3rd bits of the 3T section becomes 499 ns (expands 10 ns), the period of the 4th to 5th bits of the 2T section becomes 326 ns (no change), and the 6th bit of 1T The period of the section became 145 ns (shrinked by 18 ns), and the period of the 2T section of the 7th to 8th bits became 334 ns (expanded by 8 ns). There was no change in the overall time length of the preambles X and Y.

  When disturbance of the waveform period as shown in FIG. 3B occurs in the preamble during the transmission of the AES / EBU digital audio signal, the digital signal transmission apparatus 10 shown in FIG. 2 is disturbed in the direction opposite to the disturbance of the waveform period. By setting the increase / decrease control amount of the preamble waveform period in the period control circuit 5 so as to increase / decrease the waveform period by the amount corresponding to the magnitude, the disturbance of the preamble waveform period during transmission is corrected (cancelled). It becomes possible.

  FIG. 4 shows preambles X and Y in which the waveform period is increased or decreased by the period control circuit 5 by an amount corresponding to the magnitude of the disturbance in the direction opposite to the disturbance of the waveform period of FIG. 3B. For the preamble X, the address of the dual port RAM 1 in which the 3T section of the 1st to 3rd bits and the 3T section of the 4th to 6th bits are written is 2.85 times one cycle of the transmission clock 6.144 MHz. Reads repeatedly for a period of time, and reads the addresses of the dual-port RAM 1 in which the 1T section of the 7th bit is written for a time that is 1.2 times the period of the transmission clock 6.144 MHz. By repeatedly reading the address of the dual port RAM 1 in which the 1T section of the 8th bit is written for a time 1.1 times as long as one cycle of the transmission clock 6.144 MHz, the 1st to 3rd bits are read. The period of the 3T section and the 3T section of the 4th to 6th bits are both reduced by 2.85 / 3 times (indicated as 2.85T), and 7 bits. The period of the 1T section of the third bit is increased by 1.2 times (denoted as 1.2T), and the period of the 1T section of the eighth bit is increased by 1.1 times (denoted as 1.1T) is doing). The shaded portions of the rising and falling sides of the waveforms of these periods 2.85T, 2.85T, 1.2T, and 1.1T are the original periods 3T, 3T, 1T, and 1T (FIG. 1). Shows the time lag.

  For the preamble Y, the address of the dual port RAM 1 in which the 1st to 3rd bit 3T sections are written is repeatedly read for a time 2.9 times one cycle of the transmission clock 6.144 MHz. The address of the dual port RAM 1 in which the 2T section of the fifth bit is written is repeatedly read for a period (2T) of two cycles of the transmission clock 6.144 MHz, and the 1T section of the sixth bit is written The address of the dual port RAM 1 in which the 7T bit 2T interval is written is repeatedly read out for a time 1.2 times as long as one cycle of the transmission clock 6.144 MHz. The address should be read repeatedly for a time that is 1.9 times the period of the transmission clock 6.144 MHz. Therefore, the period of the 3T section of the 1st to 3rd bits is reduced to 2.9 / 3 times (denoted as 2.9T), and the period of the 2T section of the 4th to 5th bits is kept as 2T. The period of the 1T section of the bit is increased by 1.2 times (denoted as 1.2T), and the period of the 2T section of the 7th to 8th bits is decreased by 1.9 / 2 times (1 .9T). The shaded portions of the rising and falling sides of the waveforms of these periods 2.9T, 2T, 1.2T, and 1.9T are the same as the original periods 3T, 2T, 1T, and 2T (FIG. 1). It shows a time lag.

  3 and FIG. 4 show only the preambles X and Y, but the preamble Z can be corrected in the same way for the disturbance of the waveform period during transmission.

  As described above, the digital signal transmission apparatus 10 shown in FIG. 2 increases or decreases the waveform period of the preamble in the direction opposite to the disturbance of the preamble waveform period when transmitting the AES / EBU digital audio signal. Can be corrected.

  For example, a PLL 6 that generates a high-speed clock used as a read clock may be one mounted on a general-purpose PLD (Programmable Logic Device) or FPGA (Field Programmable Gate Array). Therefore, compared with the case where the waveform period disturbance is corrected using a dedicated device for pre-emphasis and inclination control of the output signal, or the case where the waveform period disturbance is corrected using a cable equalizer, the cost is low. Yes, flexible integration is possible.

  The clock rate of the AES / EBU digital audio signal differs depending on the audio sampling rate (for example, the clock rate is 6.144 MHz when the sampling rate is 48 kHz, but the clock rate is 12.288 MHz when the sampling rate is 96 kHz). Therefore, even when the transmission rate width is wide, it is easy to set the waveform cycle increase / decrease control amount in the cycle control circuit 5 according to the transmission rate. Periodic disturbance can be corrected.

  Next, an example in which the digital signal transmission device 10 shown in FIG. 2 is mounted on an audio device will be described. FIG. 5 is a diagram showing an AES / EBU digital audio routing switcher equipped with the digital signal transmission apparatus 10.

  The AES / EBU digital audio routing switcher 20 basically has a plurality of channel input units (such as input drivers) DICH1 to DICHn, a plurality of channel output units (such as output drivers) DOCH1 to DOCHn, and an input for each channel. The broadcasting device includes a switching unit 21 that switches which output unit outputs an AES / EBU digital audio signal input to each unit, and a CPU 22 that controls the inside. Here, each output unit DOCH1 to DOCHn The digital signal transmission devices 10 shown in FIG. 2 (denoted as digital signal transmission devices 10-1 to 10-n for distinction from each other) are provided in the preceding stage.

  For example, an AES / EBU digital audio signal input to the input unit DICH1 is output from the output unit DOCH1 via the switching unit 21 and the digital signal transmission apparatus 10-1, and as illustrated in FIG. Assume that the data is transmitted to the VTR 40 via a cable having a length of 100 meters or more. In this case, in order to correct the disturbance of the preamble waveform period of the AES / EBU digital audio signal transmitted to the VTR 40 (disturbance as illustrated in FIG. 3B), first, as shown in FIG. The cable 30 is disconnected, and a loopback connection is performed so that the output unit DOCH1 and the input unit other than the input unit DICH1 (input unit DICH2 in FIG. 5B) are connected by the cable 30.

  Then, the CPU 22 is caused to execute a control amount setting process as shown in FIG. In this process, first, the time between the edges of the waveform of the AES / EBU digital audio signal re-input to the AES / EBU digital audio routing switcher 20 by the loopback connection (the time between the rising edge and the subsequent falling edge, And the time between the falling edge and the subsequent rising edge) are measured by an internal counter, thereby detecting the 3T section of the preamble from the AES / EBU digital audio signal and disturbing the waveform period of the 3T section ( (Disturbance as exemplified in FIG. 3B) is measured (step S1).

  When a waveform having a period of 3T or more is detected, the period of the subsequent 5-bit waveform is measured by measuring the time between edges in the same manner, so that preambles X, Y, and Z (for X and Y) 1), and the disturbance of the waveform period in each section (3T section, 2T section, or 1T section) for 5 bits is measured (step S2).

  Subsequently, the waveform period of each section of the preamble is increased or decreased by an amount corresponding to the magnitude of the disturbance in a direction opposite to the direction of disturbance of the waveform period of each section of the preamble measured in steps S1 and S2. (Increase or decrease as illustrated in FIG. 4) The digital signal transmission device 10 at the front stage of the output unit that outputs the AES / EBU digital audio signal (here, the digital signal transmission device 10-1 at the front stage of the output unit DOCH1) The control amount of the cycle control circuit 5 (FIG. 2) in () is calculated (step S3).

  Then, the control amount of the cycle control circuit 5 for the preamble is set by supplying information indicating the calculated control amount to the cycle control circuit 5 in the digital signal transmission apparatus 10 (step S4).

  Subsequently, it is determined whether or not the control amount has been set for all the preambles X, Y, and Z by the processing up to step S4 (step S5). If no, the process returns to step S1, and if yes, the process ends.

  After setting the control amount of the cycle control circuit 5 in the digital signal transmission apparatus 10-1 for the preambles X, Y, and Z in this way, if the cable 30 is connected to the VTR 40 again as shown in FIG. Disturbance of the waveform period of the preamble of the AES / EBU digital audio signal transmitted to the VTR 40 via the digital signal is corrected by the digital signal transmission device 10-1.

  Next, a digital signal transmission system using the digital signal transmission apparatus 10 shown in FIG. 2 will be described. FIG. 7 is a diagram illustrating an example of a digital signal transmission system using the digital signal transmission apparatus 10.

  This digital signal transmission system includes an AES / EBU digital audio routing switcher 50 and a VTR 60. Similar to the AES / EBU digital audio routing switcher 20 shown in FIG. 5, the AES / EBU digital audio routing switcher 50 includes input units DICH1 to DICHn, output units DOCH1 to DOCHn, a switching unit 51, a CPU 52, and a digital signal transmission device 10-. 1 to 10-n and a LAN interface 53.

  In FIG. 7, only the audio input unit DI, the audio output unit DO, the CPU 61 that controls the inside, and the LAN interface 62 are shown as the components related to the present invention for the VTR 60. The digital signal transmission device 10 shown in FIG. 2 is provided in the previous stage of the audio output unit DO.

  The AES / EBU digital audio signal input to the input unit DICH1 of the AES / EBU digital audio routing switcher 50 is output from the output unit DOCH1 and transmitted to the VTR 60 via the cable 70 (for example, a cable having a length of 100 meters or more). And input to the audio input unit DI.

  In the VTR 60, the AES / EBU digital audio signal is sent to a recording processing unit (not shown) and is directly output from the audio output unit DO via the digital signal transmission device 10, and has the same length and characteristics (thickness) as the cable 70. The AES / EBU digital audio routing switcher 50 is input to the input unit DICH2 via the cable 71 of the manufacturer.

  The cable connection form between the AES / EBU digital audio routing switcher and the VTR as shown in FIG. 7 is for transmitting an AES / EBU digital audio signal between the AES / EBU digital audio routing switcher and the VTR in the television broadcasting station. This is what is usually done.

  The LAN interface 53 of the AES / EBU digital audio routing switcher 50 and the LAN interface 62 of the VTR 60 are connected to the control LAN 80.

  In this digital signal transmission system, the waveform period of the preamble of the AES / EBU digital audio signal transmitted to the VTR 60 is disturbed without disconnecting the cable 70 and 71 between the AES / EBU digital audio routing switcher 50 and the VTR 60 ( (Disturbance as illustrated in FIG. 3B) is corrected. FIG. 8 is a flowchart showing a control amount setting process to be executed by the CPU 52 in the AES / EBU digital audio routing switcher 50 for this purpose. Steps having the same contents as those shown in FIG. Description is omitted.

  In this process, after step S4, information indicating the control amount calculated in step S3 is transmitted from the LAN interface 53 to the VTR 60 via the LAN 80 (step S10). Then, the process proceeds to step S5.

  The CPU 61 in the VTR 60 acquires the control amount information sent from the AES / EBU digital audio routing switcher 50 by the processing of FIG. 8 from the LAN interface 62, and the period control circuit 5 in the digital signal transmission apparatus 10 (FIG. The control amount of 2) is set to the control amount indicated by the information.

  As described above, in this digital signal transmission system, the AES / EBU digital audio routing switcher 50 increases or decreases the waveform period of the preamble based on the measurement result of the disturbance of the waveform period of the AES / EBU digital audio signal input from the VTR 60. The AES / EBU digital audio signal is output to the VTR 60, and the VTR 60 also converts the serial digital signal whose preamble waveform period is increased / decreased by the same amount as the AES / EBU digital audio routing switcher 50 into the AES / EBU digital audio routing switcher 50. Output for.

  A cable 70 for transmitting an AES / EBU digital audio signal from the AES / EBU digital audio routing switcher 50 to the VTR 60 (connecting the output unit DOCH1 of the AES / EBU digital audio routing switcher 50 and the input unit DI of the VTR 60); A cable 71 that transmits an AES / EBU digital audio signal from the VTR 60 to the AES / EBU digital audio routing switcher 50 (connects the output unit D0 of the VTR 60 and the input unit DICH2 of the AES / EBU digital audio routing switcher 50) to each other. The length and characteristics are equal.

  As a result, the disturbance of the waveform period of the AES / EBU digital audio signal input to the VTR 60 and the disturbance of the waveform period of the AES / EBU digital audio signal input from the VTR 60 to the audio routing switcher 50 become equal. A normal cable connection configuration for transmitting AES / EBU digital audio signals between the VTRs 60 is maintained (the connection between the audio routing switcher 50 and the VTR 60 is disconnected, and the output unit and the input unit of the audio routing switcher 50 are connected by a cable. (Without making such a loopback connection), it is possible to correct the disturbance of the waveform period during transmission of the AES / EBU digital audio signal between the audio routing switcher 50 and the VTR 60. That.

  In the embodiment described above, in the AES / EBU digital audio routing switcher shown in FIG. 5 and the digital signal transmission system shown in FIG. 7, the cycle control circuit in the digital signal transmission apparatus 10 is processed by the CPU. 5 (FIG. 2) is automatically set. However, as another example, the user may be able to set this control amount using the operation panel of the AES / EBU digital audio routing switcher (not shown in FIGS. 5 and 7).

  FIG. 9 is a flowchart showing an example of a change in the processing of the CPU 52 of FIG. 8 for enabling the user's setting operation. Steps having the same contents as the processing shown in FIG. Therefore, duplicate explanation is omitted.

  In this process, after step S3, it is determined whether or not the control amount has been calculated for all the preambles X, Y, and Z by the process up to step S3 (step S20). If no, return to step S1.

  If the answer is yes in step S20, a control amount setting screen for the user to set the control amount is displayed on the display unit of the operation panel (step S21).

  FIG. 10 is a diagram showing a display example of the control amount setting screen in step S21. On the upper side of the display unit 91 of the operation panel 90, the measurement result of the disturbance of the waveform period in steps S1 and S2 of FIG. 9 (for example, the same as the disturbance of the preamble X shown in FIG. 3B) is a numerical value. It is displayed. A setting field for the user to set the control amount is displayed at the bottom of the screen of the display unit 91.

  In this setting column, an increase / decrease amount of the waveform period due to the control amount calculated in step S3 in FIG. 9 (as an example, the same increase / decrease amount for the preamble X shown in FIG. 4) is used as the recommended control amount in the waveform. A check box 91a for selecting this recommended control amount is also displayed.

  Furthermore, the setting field displays an input field 91b for the user to enter and set an arbitrary control amount numerically, and a confirm button 91c for confirming the setting contents in the check box 91a or the input field 91b. Has been.

  FIG. 10 shows a screen for setting only the preamble X. However, a control amount setting screen for setting all the preambles X, Y, and Z on one screen may be displayed. You may display the control amount setting screen which performs the setting about each preamble X, Y, Z on a separate screen. Further, in the example of FIG. 10, the measurement result of the waveform period disturbance is displayed as a numerical value and the recommended control amount is displayed as a waveform. However, the measurement result of the waveform period disturbance is displayed as a waveform, or the recommended control is displayed. The quantity may be displayed numerically.

  The user can set a control amount on this control amount setting screen by operating a punching device (trackpad or the like) 92a or numeric keypad 92b of the operation unit 92 of the operation panel 90.

  As shown in FIG. 10, following step S21, the process waits until the setting contents on the control amount setting screen for all the preambles X, Y, and Z are determined (step S22).

  When the setting contents are confirmed, information indicating the control amount for the preambles X, Y, and Z set on the control amount setting screen is transmitted to the digital signal transmission device 10 (in FIG. 7, the digital signal transmission device 10-1 preceding the output unit DOCH1). ) Is sent to the cycle control circuit 5 to set the control amount of the cycle control circuit 5 in the digital signal transmission device 10 (step S23).

  Subsequently, information indicating the control amount for the preambles X, Y, and Z set on the control amount setting screen is transmitted from the LAN interface 53 to the VTR 60 via the LAN 80 (step S24). Then, the process ends.

  In the embodiment described above, in the digital signal transmission system shown in FIG. 7, the CPU 52 in the AES / EBU digital audio routing switcher 50 stores information indicating the control amount calculated in step S3 in FIG. The data is transmitted to the VTR 60 via the LAN 80 (step S10 in FIG. 8). However, as another example, information indicating this control amount is stored in the user data area of the AES / EBU digital audio signal and transmitted, and the CPU 61 in the VTR 60 receives the user of the AES / EBU digital audio signal input to the VTR 60. This information may be acquired from the data area.

  In the embodiment described above, in the example of FIGS. 5 and 7, the digital signal transmission apparatus 10 shown in FIG. 2 is mounted on an AES / EBU digital audio routing switcher or VTR. However, the present invention is not limited to this, and the digital signal transmission apparatus 10 shown in FIG. 2 may be mounted on an audio device (for example, an audio mixer) other than the AES / EBU digital audio routing switcher and the VTR.

  In the embodiment described above, the present invention is applied in order to eliminate the disturbance of the waveform period of the AES / EBU digital audio signal. However, the present invention is not limited to this, and the present invention can also eliminate disturbances in the waveform period of serial digital signals (SDI format digital video signals, LTC time codes, etc.) other than AES / EBU digital audio signals. May apply.

It is a figure which shows the waveform of the preambles X and Y of an AES / EBU digital audio signal. It is a block diagram which shows the structural example of the digital signal transmission apparatus to which this invention is applied. It is a figure which shows the actual measurement example of the disturbance of the waveform period of preamble X, Y at the time of long-distance transmission of an AES / EBU digital audio signal. It is a figure which shows the waveform of preamble X, Y which carried out increase / decrease control of the waveform period by the period control circuit. It is a figure which shows the AES / EBU digital audio routing switcher carrying the digital signal transmission apparatus of FIG. It is a flowchart which shows the control amount setting process which CPU of FIG. 5 performs. It is a figure which illustrates the digital signal transmission system using the digital signal transmission apparatus of FIG. It is a flowchart which shows the control amount setting process which CPU in the AES / EBU digital audio routing switcher of FIG. 7 performs. It is a flowchart which shows the example of a change of the control amount setting process which CPU in the AES / EBU digital audio routing switcher of FIG. 7 performs. It is a figure which shows the example of a display of the control amount setting screen by the process of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Dual port RAM, 2 Write address generator, 3 Read address generator, 4 Preamble detection circuit, 5 Period control circuit, 6 PLL, 10 Digital signal transmission apparatus, 20 AES / EBU digital audio routing switcher, 22 CPU, 30 Cable, 50 AES / EBU digital audio routing switcher, 52 CPU, 60 VTR, 61 CPU, 70, 71 cable, 80 LAN

Claims (11)

In a digital signal transmission device that transmits a serial digital signal at a fixed clock rate,
Clock generating means for generating a clock faster than the clock rate of the serial digital signal;
Storage means for writing the input serial digital signal, and reading the written serial digital signal using the clock generated by the clock generation means as a read clock;
A digital signal transmission apparatus comprising: cycle control means for increasing / decreasing the waveform period of the serial digital signal read from the storage means by controlling a read address of the storage means. The digital signal transmission device according to claim 1,
Measuring means for measuring disturbance of the waveform period of the input serial digital signal;
A digital signal transmission apparatus further comprising setting means for setting a control amount of the period control means based on a measurement result of the measurement means. The digital signal transmission device according to claim 2,
The digital signal transmission apparatus characterized in that the measuring means measures the time between the edges of the waveform of the input serial digital signal, thereby measuring the disturbance of the waveform period of the serial digital signal. The digital signal transmission device according to claim 2,
The digital signal transmission apparatus characterized in that the setting means sets the control amount of the period control means so as to increase or decrease the waveform period in a direction opposite to the direction of disturbance of the waveform period measured by the measurement means. . The digital signal transmission device according to claim 2,
The digital signal transmission apparatus, wherein the setting means includes display means for displaying a measurement result of the measurement means, and operation means for performing an operation for setting a control amount of the cycle control means. The digital signal transmission device according to claim 2,
The serial digital signal is an AES / EBU digital audio signal;
The measuring means measures the disturbance of the waveform period of the preamble of the AES / EBU digital audio signal,
The digital signal transmission apparatus, wherein the setting means sets a control amount of the period control means for a preamble of an AES / EBU digital audio signal. The digital signal transmission device according to claim 1,
The digital signal transmission apparatus, wherein the clock generation means is a PLL (Phase-Locked Loop) mounted on a PLD (Programmable Logic Device) or FPGA (Field Programmable Gate Array). In a digital signal transmission method for transmitting a serial digital signal having a fixed clock rate,
A first step of generating a clock faster than a clock rate of the serial digital signal;
A second step of writing the input serial digital signal to a storage unit, and reading the serial digital signal written to the storage unit as a read clock from the clock generated in the first step;
And a third step of increasing / decreasing the waveform period of the serial digital signal read from the storage means by controlling a read address of the storage means. The digital signal transmission method according to claim 8.
A fourth step of measuring disturbance of the waveform period of the input serial digital signal;
And a fifth step of setting a control amount in the third step based on a measurement result of the fourth step. In a digital signal transmission system comprising a first device and a second device each having an input unit and an output unit for serial digital signals at a fixed clock rate
The first device is:
Measuring means for measuring disturbance of the waveform period of the serial digital signal input to the input unit;
Clock generating means for generating a clock faster than the clock rate of the serial digital signal;
Storage means for writing the serial digital signal input to the input unit, and reading the written serial digital signal using a clock generated by the clock generation means as a read clock;
By controlling the read address of the storage means, cycle control means for increasing / decreasing the waveform period of the serial digital signal read from the storage means;
Setting means for setting a control amount of the cycle control means based on a measurement result of the measurement means;
Information transmission means for transmitting information indicating the control amount set by the setting means to the second device, the serial digital signal read from the storage means is output from the output unit,
The second device is:
Information acquisition means for acquiring information indicating the control amount transmitted from the information transmission means of the first device;
Clock generating means for generating a clock faster than the clock rate of the serial digital signal;
Storage means for writing the serial digital signal input to the input unit, and reading the written serial digital signal using a clock generated by the clock generation means as a read clock;
By controlling the read address of the storage means, cycle control means for increasing / decreasing the waveform period of the serial digital signal read from the storage means;
Setting means for setting the control amount of the cycle control means to the control amount indicated by the information acquired by the information acquisition means, and the serial digital signal read from the storage means is output from the output unit. A digital signal transmission system. The digital signal transmission device according to claim 10, wherein
Between the output unit of the first device and the input unit of the second device, and between the output unit of the second device and the input unit of the first device are of equal length. A digital signal transmission system characterized by being connected by a cable.

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