JP2008282868A - Method for manufacturing semiconductor laser element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor laser element which can divide the multilayer semiconductor structure easily and can enhance emission efficiency. <P>SOLUTION: In the method for manufacturing a semiconductor laser element, a plating electrode layer 5 formed such that the peripheral portion serves as eaves 7 is used as a mask when an underlying electrode layer 4 is etched. Consequently, the underlying electrode layer 4 is not etched at the eaves 7 of the plating electrode layer 5 but left as it is. Thereafter, cleavage is performed along a division line D set at a position overlapping the eaves 7 when viewed from the laminating direction so that the underlying electrode layer 4 extends with a substantially equal thickness up to the opposite end faces 1a and 1a of the semiconductor laser element 1 thus enhancing emission efficiency of the semiconductor laser element 1. When cleavage is performed along a division line D from the other side of a semiconductor substrate 2, the multilayer semiconductor structure 3 can be divided without making the cleavage interface reach the plating electrode layer 5. Consequently, the multilayer semiconductor structure 3 can be divided easily. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor laser device.

  As a conventional semiconductor laser element, there is one in which a multilayer semiconductor structure including a semiconductor mesa portion is formed on one side of a substrate, and a metal electrode layer such as Ti, Pt, or Au is formed on the surface of the multilayer semiconductor structure. In such a semiconductor laser element, the electrode pattern of the metal electrode layer is formed on the surface of the multilayer semiconductor structure by dry etching using, for example, Au plating as a mask. On the other hand, when the multilayer semiconductor structure is divided for each chip by cleavage, for example, there is no Au plating in the vicinity of the dividing line so that it can be easily divided.

However, when there is no Au plating in the vicinity of the dividing line, the metal electrode layer of the portion is removed by etching. For this reason, there is a problem that the amount of injected current is insufficient near the end face (cleavage face) of the semiconductor element after cleavage, and the light emission efficiency of the semiconductor laser element is lowered. Thus, for example, in the method of manufacturing a semiconductor element described in Patent Document 1, when the metal electrode layer is removed by etching, the vicinity of the dividing line is covered with an Au layer, and the surface of the multilayer semiconductor structure corresponding to the portion is Ti. The layer and the Pt layer are left.
Japanese Patent Laid-Open No. 4-291979

  However, in the semiconductor element manufacturing method according to Patent Document 1 described above, the Au layer coated in the vicinity of the dividing line is etched in parallel with the etching of the Pt layer. Therefore, the Au layer exists only in the portion corresponding to the Au plating, and does not exist in the vicinity of the cleavage plane. Therefore, in the vicinity of the cleavage plane, the thickness of the metal electrode layer covering the multilayer semiconductor structure cannot be ensured, and the amount of injected current is still insufficient, so it is difficult to improve the light emission efficiency of the semiconductor laser device. there were.

  The present invention has been made to solve the above-described problems, and provides a method for manufacturing a semiconductor laser device that can easily divide a multilayer semiconductor structure and can improve luminous efficiency. Objective.

  In order to solve the above problems, a semiconductor laser manufacturing method according to the present invention includes a step of forming a multilayer semiconductor structure including a semiconductor mesa portion on one side of a semiconductor substrate, and a semiconductor mesa portion on the surface of the multilayer semiconductor structure. Corresponding to a step of forming a dielectric layer having a striped first opening to be exposed, a step of forming a base electrode layer on the surface of the dielectric layer and inside the first opening, and the first opening A resist layer having a second opening and having an inclined inner wall of the second opening is formed on the surface of the base electrode layer so that the opening area of the second opening gradually decreases toward the base electrode layer. A step of forming, a step of forming a plating electrode layer on the surface of the base electrode layer so that a peripheral portion thereof is a ridge using the resist layer as a mask, and a step of etching the base electrode layer using the plating electrode layer as a mask Process and multilayer semiconductor And a step of setting a dividing line at a position overlapping with the ridge when viewed from the stacking direction of the structure, and cleaving from the other surface side of the semiconductor substrate along the dividing line to divide the multilayer semiconductor structure. It is said.

  In this method of manufacturing a semiconductor laser device, when the base electrode layer is etched, a plating electrode layer formed so that the peripheral edge is a ridge is used as a mask. Therefore, the base electrode layer remains without being etched at the ridge portion of the plating electrode layer. Then, by cleaving along the dividing line set at a position overlapping with the ridges when viewed from the stacking direction of the multilayer semiconductor structure, the thickness of the base electrode layer covering the multilayer semiconductor structure is made substantially equal to the cleavage interface. It becomes possible to do. Thereby, a sufficient amount of current injected into the multilayer semiconductor structure can be ensured, and the light emission efficiency of the semiconductor laser device can be improved. Further, by cleaving from the other surface side of the semiconductor substrate along the dividing line, the multilayer semiconductor structure can be divided without extending the cleavage interface to the plating electrode layer. Therefore, the multilayer semiconductor structure can be easily divided.

  The width of the ridge is preferably 10 μm or more. In consideration of cleavage accuracy, if the width of the ridge is 10 μm or more, the cleavage can be easily performed along a dividing line set at a position overlapping with the ridge when viewed from the stacking direction of the multilayer semiconductor structure.

  The width of the ridge is preferably 20 μm or less. When the width of the ridge exceeds 20 μm, the internal stress of the plating electrode layer acts excessively on the multilayer semiconductor structure, which may be a factor of reducing reliability. Therefore, the reliability of an element is ensured by making the width | variety of a ridge or less into the said width | variety.

  In addition, the base electrode layer and the plating electrode layer have a pad electrode portion protruding in the direction of the dividing line, and the multilayer semiconductor structure has a pad electrode portion between the adjacent multilayer semiconductor structure with the dividing line interposed therebetween. It is preferable to arrange on the semiconductor substrate so that the protruding directions are opposite to each other. Such an arrangement can ensure the yield of the chip.

  According to the semiconductor laser device manufacturing method of the present invention, the element portion can be easily separated and the light emission efficiency of the semiconductor laser device can be improved.

  Hereinafter, preferred embodiments of a method for manufacturing a semiconductor laser device according to the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing an example of a semiconductor laser device manufactured by using the method for manufacturing a semiconductor laser device according to one embodiment of the present invention. 1A is a plan view of the semiconductor laser, FIG. 1B is a cross-sectional view taken along line AA in FIG. 1A, and FIG. 1C is a cross-sectional view taken along line BB in FIG. FIG.

  A semiconductor laser element 1 shown in FIGS. 1A to 1C is an element that outputs light generated by intersubband transition of a quantum well structure, and is used as a light source for optical communication or a light source for spectroscopic analysis. It is what is used. The semiconductor laser device 1 includes a semiconductor substrate 2, a multilayer semiconductor structure 3 formed on one surface side of the semiconductor substrate 2, a base electrode layer 4 formed on the surface of the multilayer semiconductor structure 3, and a surface of the base electrode layer 4. The formed plating electrode layer 5 and the back surface electrode layer 6 are provided.

The semiconductor substrate 2 is, for example, an n-type InP substrate doped with Sn. The impurity concentration of the semiconductor substrate 2 is about 3e ⁺¹⁸ cm ^−3, and the thickness of the semiconductor substrate 2 is about 100 μm.

  The multilayer semiconductor structure 3 includes a semiconductor mesa unit 10 and a buried layer 11. The semiconductor mesa unit 10 is formed in a raised shape with a height of about 4 μm with respect to the semiconductor substrate 2, and in order from the semiconductor substrate 2 side, the buffer layer 20, the lower light confinement layer 21, the active layer 22, the upper light confinement layer 23, A clad layer 24, an intermediate layer 25, and a contact layer 26 are stacked.

The buffer layer 20 is, for example, an n-type InP layer doped with Si. The impurity concentration of the buffer layer 20 is about 8e ⁺¹⁷ cm ^−3, and the thickness of the buffer layer 20 is about 0.5 μm. The lower optical confinement layer 21 is, for example, an undoped InGaAsP layer. The active layer 22 is, for example, an InGaAsP layer. The upper optical confinement layer 23 is, for example, an undoped InGaAsP layer.

The clad layer 24 is, for example, a p-type InP layer doped with Zn. The impurity concentration of the cladding layer 24 is about 1e ⁺¹⁸ cm ^−3, and the thickness of the cladding layer 24 is about 2.0 μm. The intermediate layer 25 is, for example, a p-type InGaAsP layer doped with Zn.

The impurity concentration of the intermediate layer 25 is about 5e ^{+ 18} cm ^−3, and the thickness of the intermediate layer 25 is about 0.1 μm. The contact layer 26 is, for example, a p-type InGaAs layer doped with Zn. The impurity concentration of the contact layer 26 is about 1e ^{+ 19} cm ^−3, and the thickness of the contact layer 26 is about 0.2 μm.

  The buried layer 11 is an InP layer doped with Fe, for example. The buried layer 11 is formed on both sides of the semiconductor mesa unit 10, and the multilayer semiconductor structure 3 is a planar type by embedding the semiconductor mesa unit 10 with the buried layer 11.

An insulating layer 30 made of, for example, SiO ₂ is formed on the surface of the multilayer semiconductor structure 3. The insulating layer 30 is formed with a thickness of about 0.4 μm, for example, and has a stripe-shaped opening 30 a that exposes the semiconductor mesa unit 10. The width of the opening 30a is, for example, about 3 μm.

  The base electrode layer 4 is configured by laminating a Ti layer 41, a Pt layer 42, and an Au layer 43 in order from the multilayer semiconductor structure 3 side. The base electrode layer 4 has a stripe shape with a width of about 3 μm, and closes the opening 30 a of the insulating layer 30 so as to close both end faces 1 a, corresponding to the longitudinal direction of the semiconductor mesa 10 in the semiconductor laser element 1. It extends with almost equal thickness up to 1a.

  The Ti layer 41 is formed, for example, to a thickness of about 500 mm so as to close the opening 30a, and is also formed inside the opening 30a so as to contact the surface of the multilayer semiconductor structure 3 exposed to the opening 30a. ing. The Pt layer 42 is formed with a thickness of about 500 mm, for example. The Au layer 43 is formed with a thickness of about 2000 mm, for example.

  The plating electrode layer 5 is, for example, Au plating and has a thickness of about 10 μm. The plating electrode layer 5 has a stripe shape with a width of about 3 μm, and both end portions 5 a and 5 a in the longitudinal direction of the plating electrode layer 5 protrude from the both end surfaces 1 a and 1 a of the semiconductor laser element 1 by about several μm. It is in a state.

  An inclined surface 5b of about 45 ° is formed on the peripheral edge of the plating electrode layer 5 on the base electrode layer 4 side so that the cross-sectional area of the plating electrode layer 5 gradually decreases toward the base electrode layer 4 side. Yes. With such a configuration, a ridge 7 is formed by the plating electrode layer 5 on the surface of the base electrode layer 4, and a gap S is formed between the surface of the base electrode layer 4 and the ridge 7 by the plating electrode layer 5. Is present. When viewed from the stacking direction, the width of the ridges 7 formed at both ends in the longitudinal direction of the plating electrode layer 5 is, for example, about 10 μm.

  Further, as shown in FIG. 1A, the base electrode layer 4 and the plating electrode layer 5 protrude in the direction perpendicular to the opening 30 a on the surface of the insulating layer 30, thereby constituting the pad electrode portion 8. By using the pad electrode portion 8 as a current injection portion, the influence of heat on the semiconductor mesa portion 10 can be reduced.

  The back electrode layer 6 is formed on the other surface side of the semiconductor substrate 2. The back electrode layer 6 has an AuGeNi layer with a thickness of about 200 mm, an Au layer with a thickness of about 200 mm, a Ti layer with a thickness of about 500 mm, a Pt layer with a thickness of about 500 mm, and a thickness of about 8000 mm in order from the semiconductor substrate 2 side. The Au layer is laminated.

  Then, the manufacturing method of the semiconductor laser element 1 mentioned above is demonstrated, referring FIGS. In each figure, (a) is a plan view, (b) is an AA section view in (a), and (c) is a BB section view in (a). For convenience of explanation, the manufacturing process will be described by focusing on one element, but actually, a plurality of elements are arranged in a matrix on the wafer (see FIG. 8).

  First, as shown in FIGS. 2A to 2C, a semiconductor substrate 2 made of n-type InP doped with Sn is prepared. Then, the buffer layer 20, the lower light confinement layer 21, the active layer 22, the upper light confinement layer 23, the clad layer 24, the intermediate layer 25, and the contact layer 26 are sequentially stacked on one surface side of the semiconductor substrate 2 by MOCVD, for example. To do.

Next, an insulating layer made of, for example, SiN is stacked on the entire surface of the contact layer 26. An insulating layer of SiN is formed in a stripe shape having a width of about 1.5 μm by photolithography. Then, the semiconductor mesa portion 10 having a height of about 4 μm is formed by performing dry etching using a gas such as SiCl ₄ using the striped insulating layer as a mask.

  After the semiconductor mesa portion 10 is formed, the modified layer formed during dry etching is removed by predetermined wet etching. After removing the modified layer, the buried layers 11 are stacked on both sides of the semiconductor mesa unit 10 by, for example, MOCVD. Then, the multilayer semiconductor structure 3 is formed on one surface side of the semiconductor substrate 2 by removing the insulating layer of SiN by wet etching.

Next, an insulating layer 30 made of, for example, SiO _{2 is} stacked on the entire surface of the multilayer semiconductor structure 3 by about 4000 mm. In addition, a resist layer is formed on the surface of the insulating layer 30. Then, a stripe-shaped opening (first opening) 30 a having a width of about 3 μm is formed in the insulating layer 30 by photolithography using this resist layer as a mask, and the semiconductor mesa 10 is exposed. After the semiconductor mesa unit 10 is exposed, as shown in FIGS. 3A to 3C, a Ti layer 41, a Pt layer 42, and an Au layer 43 are sequentially deposited so as to cover the opening 30a. Thereafter, heat treatment is performed at a temperature of about 400 ° C. for about 3 minutes.

  Next, as shown in FIGS. 4A to 4C, a resist layer 51 having a thickness of about 15 μm is formed on the entire surface of the Au layer 43 by, for example, photolithography. Then, heat treatment is performed at a temperature of about 90 ° C. for about 1 minute, and exposure is performed for about 30 seconds using an i-line contact aligner. After the exposure, development is performed using a predetermined photoresist developer, and heat treatment is performed at a temperature of about 90 ° C. for about 1 minute.

  As a result, in the resist layer 51, at the position corresponding to the opening 30a of the insulating layer 30, the opening in which the inner wall 52 is inclined by about 45 ° so that the opening area gradually decreases toward the base electrode layer 4 side. A portion (second opening) 51a is formed. Further, an opening 51b corresponding to the pad electrode portion 8 is also formed at a substantially central portion of the opening 51a.

  After forming the resist layer 51, as shown in FIGS. 5 (a) to 5 (c), the wafer is immersed in a non-cyan weak alkaline bright gold plating solution containing sodium gold sulfite, and a predetermined electric field is applied. Call. Then, the plating electrode layer 5 having a thickness of about 10 μm is formed on the surface of the base electrode layer 4 using the resist layer 51 as a mask.

  At this time, since the inner wall 52 of the opening 51a of the resist layer 51 has the above-described inclination, the plating electrode layer 5 is also inclined at a portion corresponding to the inner wall 52 of the resist layer 51. As a result, an inclined surface 5b of about 45 ° is formed at the peripheral edge of the plating electrode layer 5 on the base electrode layer 4 side so that the cross-sectional area of the plating electrode layer 5 gradually decreases toward the base electrode layer 4 side. It is formed.

  After the plating electrode layer 5 is formed, as shown in FIGS. 6A to 6C, when the resist layer 51 is removed using an organic solvent or the like, the surface of the base electrode layer 4 has a plating electrode layer. 5 is formed, and a gap S is formed between the surface of the base electrode layer 4 and the ridge 7 formed by the plating electrode layer 5. When viewed from the stacking direction, the width of the ridges 7 formed at both ends in the longitudinal direction of the plating electrode layer 5 is, for example, about 10 μm.

Next, as shown in FIGS. 7A to 7C, the Au layer 43 and the Pt layer 42 are dry-etched with Ar gas, for example, using the plating electrode layer 5 as a mask. Further, the Ti layer 41 is dry-etched with CF ₄ gas. This dry etching of the base electrode layer 4 is performed under conditions of, for example, a pressure of 1.0 Pa, a gas flow rate of 30 sccm, and an RF power of 100 W. The etching rates of the Au layer 43, the Pt layer 42, and the Ti layer 41 are, for example, 150 / min, 100 / min, and 100 / min, respectively.

  Next, the semiconductor substrate 2 is attached to a quartz substrate, and the other surface side of the semiconductor substrate 2 is polished to a thickness of about 100 μm. Further, the back electrode layer 6 is formed on the other surface side of the semiconductor substrate 2 and heat treatment is performed at a temperature of about 350 ° C. for about 1 minute. Then, as shown in FIG. 8, a dividing line D is set at a position overlapping the flange 7 of the plating electrode layer 5 when viewed from the stacking direction. For example, a scribe mark is formed on the extended line of the dividing line D at the wafer end by a scriber. Each E is formed.

  After forming the scribe flaw E, as shown in FIG. 9, the wafer is placed on the cleaving device 60 so that the back electrode layer 6 is on the upper surface side. A recess 60a extending along the dividing line D is provided on the upper surface side of the cleavage device 60, and a camera for checking the scribe scratch E is installed on the bottom surface of the recess 60a. A cleavage blade 61 is set above the cleavage device 60.

  Then, by pressing the cleavage blade 61 against the wafer in a state where the positions of the scribe flaw E and the cleavage blade 61 are aligned on the recess 60a by the camera, the other side of the semiconductor substrate 2 along the dividing line D Cleavage from Thereafter, similar cleavage is performed in the direction orthogonal to the dividing line D, whereby the multilayer semiconductor structure 3 is divided for each chip, and the semiconductor laser device 1 shown in FIG. 1 is completed.

  As described above, in this method of manufacturing a semiconductor laser element, when the base electrode layer 4 is etched, the plating electrode layer 5 formed so that the peripheral edge thereof becomes the ridge 7 is used as a mask. Therefore, the base electrode layer 4 remains without being etched in the portion of the ridge 7 of the plating electrode layer 5. Thereafter, cleavage is performed along a dividing line D set at a position overlapping with the flange 7 when viewed from the stacking direction, so as to reach both end faces 1a and 1a corresponding to the longitudinal direction of the semiconductor mesa 10 in the semiconductor laser element 1. Thus, the base electrode layer 4 can be extended with substantially the same thickness.

  Thereby, a sufficient amount of current injected into the multilayer semiconductor structure 3 can be secured, and the light emission efficiency of the semiconductor laser device 1 can be improved. Further, by cleaving from the other surface side of the semiconductor substrate 2 along the dividing line D, when the cleavage interface reaches the surface of the base electrode layer 4 from the other surface side of the semiconductor substrate 2, the multilayer semiconductor structure 3 can be divided. Thus, since it is not necessary to extend the interface to the plating electrode layer 5, the multilayer semiconductor structure 3 can be easily divided.

  Further, in the manufacturing method of the semiconductor laser element 1, the width of the flange 7 is not less than 10 μm and not more than 20 μm. For example, since the cleavage accuracy by the scriber is about ± 5.0 μm, if the width of the ridge 7 is 10 μm or more, the cleavage is easily performed along the dividing line D set at a position overlapping the ridge 7 when viewed from the stacking direction. be able to. On the other hand, when the width of the ridge 7 exceeds 20 μm, the internal stress of the plating electrode layer 5 acts excessively on the multilayer semiconductor structure 3 and may be a factor of reducing the reliability of the semiconductor laser device 1. Therefore, the reliability of the semiconductor laser device 1 is ensured by setting the width of the flange 7 to 20 μm or less.

  Further, in this method of manufacturing a semiconductor laser device, the base electrode layer 4 and the plating electrode layer 5 have the pad electrode portion 8 protruding in the direction of the dividing line D, and the multilayer semiconductor structure 3 has the dividing line D formed thereon. The pad electrodes 8 are arranged on the semiconductor substrate 2 so that the protruding directions of the pad electrode portions 8 are opposite to each other between the multilayer semiconductor structures 3 adjacent to each other (see FIG. 8). Such an arrangement can ensure the yield of the chip.

It is a figure which shows an example of the semiconductor laser element manufactured using the manufacturing method of the semiconductor laser element which concerns on one Embodiment of this invention. FIG. 6 is a diagram showing a manufacturing process of the semiconductor laser element shown in FIG. 1. FIG. 3 is a diagram showing a step subsequent to FIG. 2. FIG. 4 is a diagram showing a step subsequent to FIG. 3. FIG. 5 is a diagram showing a step subsequent to FIG. 4. FIG. 6 is a diagram showing a step subsequent to FIG. 5. FIG. 7 is a diagram showing a step subsequent to FIG. 6. FIG. 8 is a diagram showing a step subsequent to FIG. 7. FIG. 9 is a diagram showing a step subsequent to that in FIG. 8.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor laser element, 2 ... Semiconductor substrate, 3 ... Multi-layered semiconductor structure, 4 ... Base electrode layer, 5 ... Plated electrode layer, 7 ... 庇, 8 ... Electrode pad part, 11 ... Semiconductor mesa part, 30 ... Insulating layer ( Dielectric layer), 30a ... opening (first opening), 51 ... resist layer, 51a ... opening (second opening), 52 ... inner wall, D ... dividing line.

Claims (4)

Forming a multilayer semiconductor structure including a semiconductor mesa portion on one surface side of the semiconductor substrate;
Forming a dielectric layer having a stripe-shaped first opening exposing the semiconductor mesa portion on the surface of the multilayer semiconductor structure;
Forming a base electrode layer on the surface of the dielectric layer and inside the first opening;
A second opening corresponding to the first opening, and the inner wall of the second opening is inclined so that the opening area of the second opening gradually decreases toward the base electrode layer side. Forming a resist layer on the surface of the base electrode layer;
Using the resist layer as a mask, and forming a plating electrode layer on the surface of the base electrode layer so that a peripheral edge thereof is a ridge;
Etching the base electrode layer using the plating electrode layer as a mask;
Setting a dividing line at a position overlapping with the ridges when viewed from the stacking direction of the multilayer semiconductor structure, cleaving from the other surface side of the semiconductor substrate along the dividing line, and dividing the multilayer semiconductor structure; A method for manufacturing a semiconductor laser device, comprising:   2. The method of manufacturing a semiconductor laser device according to claim 1, wherein the width of the flange is 10 [mu] m or more.   3. The method of manufacturing a semiconductor laser device according to claim 1, wherein the width of the flange is 20 [mu] m or less.   The base electrode layer and the plating electrode layer have a pad electrode portion protruding in the direction of the dividing line, and the multilayer semiconductor structure is between the multilayer semiconductor structures adjacent to each other across the dividing line. 4. The method of manufacturing a semiconductor laser device according to claim 1, wherein the pad electrode portions are arranged on the semiconductor substrate so that protruding directions thereof are opposite to each other.

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