JP4489691B2 - Semiconductor optical device manufacturing method - Google Patents

Semiconductor optical device manufacturing method Download PDF

Info

Publication number
JP4489691B2
JP4489691B2 JP2005336925A JP2005336925A JP4489691B2 JP 4489691 B2 JP4489691 B2 JP 4489691B2 JP 2005336925 A JP2005336925 A JP 2005336925A JP 2005336925 A JP2005336925 A JP 2005336925A JP 4489691 B2 JP4489691 B2 JP 4489691B2
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor optical
straight line
line portion
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2005336925A
Other languages
Japanese (ja)
Other versions
JP2007142317A (en
Inventor
貴司 中山
康宏 金谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anritsu Corp
Original Assignee
Anritsu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anritsu Corp filed Critical Anritsu Corp
Priority to JP2005336925A priority Critical patent/JP4489691B2/en
Publication of JP2007142317A publication Critical patent/JP2007142317A/en
Application granted granted Critical
Publication of JP4489691B2 publication Critical patent/JP4489691B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Description

本発明は、半導体光素子の製造方法に係り、特に、斜め端面構造を有する高信頼性の埋め込み型半導体光素子の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor optical device, and more particularly to a method for manufacturing a highly reliable embedded semiconductor optical device having an oblique end face structure.

外部共振器型半導体レーザ（ＥＣＬＤ）、スーパールミネッセントダイオード（ＳＬＤ）、半導体光増幅器(ＳＯＡ）等の半導体光素子にあっては、半導体光素子の両端面のうち少なくとも一方の端面の反射率を低反射率にする必要がある。   In a semiconductor optical device such as an external cavity semiconductor laser (ECLD), a super luminescent diode (SLD), a semiconductor optical amplifier (SOA), etc., the reflectance of at least one of the two end surfaces of the semiconductor optical device Must have a low reflectivity.

端面の反射率を光導波路の構造によって低反射率化した半導体光素子としては、例えば、低反射率側の光導波路端面を窓構造とした半導体光素子が公知である。   As a semiconductor optical device in which the reflectance of the end face is lowered by the structure of the optical waveguide, for example, a semiconductor optical device having a window structure on the end face of the optical waveguide on the low reflectance side is known.

また、光導波路の低反射面側開口を斜め端面構造として光導波路端面の反射率を低減した半導体光素子およびその製造方法が既に提案されている（例えば、特許文献１参照）。   Further, there has already been proposed a semiconductor optical device in which the low reflection surface side opening of the optical waveguide has an oblique end surface structure to reduce the reflectance of the optical waveguide end surface and a method for manufacturing the same (for example, refer to Patent Document 1).

図６（ａ）は特許文献１に開示された半導体光素子製造方法で製造した劈開前の半導体ウエハ４の上面図、図６（ｂ）は劈開により分離した１つの半導体光素子４２の上面図である。   6A is a top view of the semiconductor wafer 4 before cleaving manufactured by the semiconductor optical device manufacturing method disclosed in Patent Document 1, and FIG. 6B is a top view of one semiconductor optical device 42 separated by cleavage. It is.

特許文献１の半導体製造方法によれば、図６（ａ）に示すように、複数の斜め端面構造を有する複数の半導体光素子（４１、４２、４３等）が半導体ウエハ４上にモノリシックに形成される。そして、１つの半導体光素子、例えば半導体光素子４２の光導波路４２ｇは、図中の一点鎖線で示された劈開予定面を挟んで隣接する半導体光素子４１および半導体光素子４３の領域に所定の長さだけ延伸するように形成されている。   According to the semiconductor manufacturing method of Patent Document 1, a plurality of semiconductor optical elements (41, 42, 43, etc.) having a plurality of oblique end surface structures are formed monolithically on the semiconductor wafer 4 as shown in FIG. Is done. An optical waveguide 42g of one semiconductor optical element, for example, the semiconductor optical element 42, has a predetermined area in the regions of the semiconductor optical element 41 and the semiconductor optical element 43 that are adjacent to each other with the planned cleavage plane indicated by a dashed line in the figure. It is formed to extend by the length.

半導体光素子４２の光導波路４２ｇを隣接する半導体光素子４１および半導体光素子４３にまで延伸することによって、劈開予定面から実際の劈開面が例えば±１０マイクロメートル程度ずれた場合でも、実際の劈開面に光導波路４２ｇの端面を確実に開口させることができることとなる。
特開昭６２−２６９３７９号公報（第６頁第１２行目〜第７頁第２行目、第１図） By extending the optical waveguide 42g of the semiconductor optical device 42 to the adjacent semiconductor optical device 41 and the semiconductor optical device 43, even when the actual cleavage plane is deviated from the planned cleavage surface by, for example, about ± 10 micrometers, the actual cleavage is performed. Thus, the end surface of the optical waveguide 42g can be reliably opened on the surface.
JP-A-62-269379 (page 6, line 12 to page 7, line 2, FIG. 1)

しかしながら、上記の半導体製造方法によれば、図６（ｂ）に破線の丸で囲んで示すように、劈開によって生成された１つの半導体光素子４２に、劈開前に隣接していた半導体光素子４１の光導波路４１ｇの延伸部分および半導体光素子４３の光導波路４３ｇの延伸部分が残存することとなる。   However, according to the semiconductor manufacturing method described above, the semiconductor optical element adjacent to the one semiconductor optical element 42 generated by cleavage as shown in FIG. Thus, the extended portion of the 41 optical waveguide 41 g and the extended portion of the optical waveguide 43 g of the semiconductor optical device 43 remain.

残存部分の光導波路端面は、光導波路を形成する際のエッチングによって上述した窓構造の光導波路の端面と同一の構造となるので、光導波路端面近傍を流れる電流のために半導体光素子としての信頼性が低下することを回避できないという課題があった。   The remaining end face of the optical waveguide has the same structure as the end face of the optical waveguide having the window structure described above by etching when the optical waveguide is formed. There was a problem that it was not possible to avoid a decrease in performance.

本発明は、従来の問題を解決するためになされたものであって、斜め端面構造を有する高信頼性の埋め込み型半導体光素子の製造方法を提供することを目的とする。   The present invention has been made to solve the conventional problems, and an object of the present invention is to provide a method for manufacturing a highly reliable embedded semiconductor optical device having an oblique end surface structure.

本発明に係る半導体光素子の製造方法は、半導体基板上にクラッド層および活性層を含む複数の半導体層を堆積した活性層エピタキシャルウエハを製造する活性層エピタキシャルウエハ製造段階と、前記活性層エピタキシャルウエハに複数のストライプ状のエッチングマスクを形成するエッチングマスク形成段階と、前記エッチングマスク形成後の前記活性層エピタキシャルウエハの前記複数の半導体層を少なくとも前記活性層まで厚さ方向にエッチングにより除去してストライプ状の光導波路を形成する光導波路形成段階と、前記光導波路を埋め込み層により埋め込む埋め込み段階と、前記エッチングマスクを除去した後に、埋め込みクラッド層を含む複数の半導体層を堆積し、さらに上部電極および下部電極を形成して半導体ウエハを製造する半導体ウエハ製造段階と、前記半導体ウエハを、前記光導波路を横断する劈開予定面に沿って劈開し、かつ前記劈開予定面に垂直な方向に分離して、複数の半導体光素子を分離する半導体光素子分離段階とを含む半導体光素子の製造方法において、前記エッチングマスク形成段階が、１つの半導体光素子となる領域の一方の劈開予定面を垂直に貫通する第１の直線部と、他方の劈開予定面を前記第１の直線部と予め定められた角度を成して貫通する第２の直線部と、前記第１の直線部と前記第２の直線部とを接続する第１の曲線部とを含み、当該１つの半導体光素子となる領域および当該１つの半導体光素子となる領域に光の導波方向で隣接する半導体光素子となる領域の少なくとも３つの劈開予定面を通過する連続線状のエッチングマスクを形成する段階であることを特徴とする。   A method of manufacturing a semiconductor optical device according to the present invention includes an active layer epitaxial wafer manufacturing step of manufacturing an active layer epitaxial wafer in which a plurality of semiconductor layers including a cladding layer and an active layer are deposited on a semiconductor substrate, and the active layer epitaxial wafer An etching mask forming step of forming a plurality of stripe-shaped etching masks on the substrate; and removing the plurality of semiconductor layers of the active layer epitaxial wafer after the etching mask formation by etching in the thickness direction to at least the active layer. An optical waveguide forming step of forming an optical waveguide, an embedding step of embedding the optical waveguide with an embedding layer, a plurality of semiconductor layers including an embedded cladding layer are deposited after removing the etching mask, and an upper electrode and A lower electrode is formed to produce a semiconductor wafer A semiconductor wafer manufacturing stage, and a semiconductor that separates a plurality of semiconductor optical elements by cleaving the semiconductor wafer along a planned cleavage plane that crosses the optical waveguide and in a direction perpendicular to the planned cleavage plane In the method of manufacturing a semiconductor optical device including an optical device isolation step, the etching mask formation step includes a first straight line portion that vertically penetrates one cleavage planned surface of a region to be one semiconductor optical device, and the other A first straight line that connects the first straight line part and the second straight line part, the second straight line part that penetrates the first cleavage line at a predetermined angle with the first straight line part. A region that becomes the one semiconductor optical device and a region that becomes the semiconductor optical device adjacent to the region that becomes the one semiconductor optical device in the light guiding direction. Linear etching Characterized in that it is a step of forming a disk.

この製造方法により、劈開前に隣接していた半導体光素子の埋め込み層によって埋め込まれた光導波路の一部が残存しないので、半導体光素子の信頼性を高めることができることとなる。   According to this manufacturing method, since a part of the optical waveguide buried by the buried layer of the semiconductor optical element adjacent before the cleavage does not remain, the reliability of the semiconductor optical element can be improved.

本発明に係る半導体光素子の製造方法は、半導体基板上にクラッド層および活性層を含む複数の半導体層を堆積した活性層エピタキシャルウエハを製造する活性層エピタキシャルウエハ製造段階と、前記活性層エピタキシャルウエハに複数のストライプ状のエッチングマスクを形成するエッチングマスク形成段階と、前記エッチングマスク形成後の前記活性層エピタキシャルウエハの前記複数の半導体層を少なくとも前記活性層まで厚さ方向にエッチングにより除去してストライプ状の光導波路を形成する光導波路形成段階と、前記光導波路を埋め込み層により埋め込む埋め込み段階と、前記エッチングマスクを除去した後に、埋め込みクラッド層を含む複数の半導体層を堆積し、さらに上部電極および下部電極を形成して半導体ウエハを製造する半導体ウエハ製造段階と、前記半導体ウエハを、前記光導波路を横断する劈開予定面に沿って劈開し、かつ前記劈開予定面に垂直な方向に分離して、複数の半導体光素子を分離する半導体光素子分離段階とを含む半導体光素子の製造方法において、前記エッチングマスク形成段階が、１つの半導体光素子となる領域の劈開予定面に垂直な第１の直線部と、前記第１の直線部と予め定められた角度を成して当該劈開予定面のそれぞれを貫通する第２の直線部および第３の直線部と、前記第１の直線部と前記第２の直線部とを接続する第１の曲線部と、前記第１の直線部と前記第３の直線部とを接続する第２の曲線部とを含み、当該１つの半導体光素子となる領域および当該１つの半導体光素子となる領域に光の導波方向で隣接する半導体光素子となる領域の少なくとも３つの劈開予定面を通過する連続線状のエッチングマスクを形成する段階であることを特徴とする。   A method of manufacturing a semiconductor optical device according to the present invention includes an active layer epitaxial wafer manufacturing step of manufacturing an active layer epitaxial wafer in which a plurality of semiconductor layers including a cladding layer and an active layer are deposited on a semiconductor substrate, and the active layer epitaxial wafer An etching mask forming step of forming a plurality of stripe-shaped etching masks on the substrate; and removing the plurality of semiconductor layers of the active layer epitaxial wafer after the etching mask formation by etching in the thickness direction to at least the active layer. An optical waveguide forming step of forming an optical waveguide, an embedding step of embedding the optical waveguide with an embedding layer, a plurality of semiconductor layers including an embedded cladding layer are deposited after removing the etching mask, and an upper electrode and A lower electrode is formed to produce a semiconductor wafer A semiconductor wafer manufacturing stage, and a semiconductor that separates a plurality of semiconductor optical elements by cleaving the semiconductor wafer along a planned cleavage plane that crosses the optical waveguide and in a direction perpendicular to the planned cleavage plane In the method of manufacturing a semiconductor optical device including an optical device isolation step, the etching mask formation step includes a first straight portion perpendicular to a cleavage plane of a region to be a semiconductor optical device, and the first straight portion. And a second straight line part and a third straight line part penetrating each of the planned cleavage planes at a predetermined angle, and a first line part connecting the first straight line part and the second straight line part. 1 curve portion, and a second curve portion connecting the first straight line portion and the third straight line portion, and a region to be the one semiconductor optical element and the one semiconductor optical device Semiconductor adjacent to the region in the light guiding direction Characterized in that it is a step of forming a continuous line shaped etching mask to pass through at least three cleavage scheduled surface area as the element.

この製造方法により、劈開前に隣接していた半導体光素子の埋め込み層によって埋め込まれた光導波路の一部が残存しないので、半導体光素子の信頼性を高めることができることとなる。
本発明に係る半導体光素子の製造方法は、前記エッチングマスク形成段階が、前記連続線状のエッチングマスクを形成するための連続線状のフォトマスクパターンが形成されているとともに、前記連続線状のフォトマスクパターンの前記第１の直線部と平行であり、かつ前記少なくとも３つの劈開予定面を垂直に貫通する直線状のフォトマスクパターンが形成されているフォトマスクを用いて前記エッチングマスクを形成することを特徴とする。
この製造方法により、エッチングマスクを形成するためのフォトリソグラフィにおいて、ウエハの結晶面に対する平行合わせを容易にすることができることとなる。 According to this manufacturing method, since a part of the optical waveguide buried by the buried layer of the semiconductor optical element adjacent before the cleavage does not remain, the reliability of the semiconductor optical element can be improved.
In the method of manufacturing a semiconductor optical device according to the present invention, the etching mask forming step includes a continuous line-shaped photomask pattern for forming the continuous line-shaped etching mask, and the continuous line-shaped photomask pattern is formed. The etching mask is formed using a photomask in which a linear photomask pattern that is parallel to the first linear portion of the photomask pattern and perpendicularly penetrates the at least three planned cleavage planes is formed. It is characterized by that.
With this manufacturing method, parallel alignment with the crystal plane of the wafer can be facilitated in photolithography for forming an etching mask.

本発明は、１つの半導体光素子となる領域の劈開予定面を貫通する直線部を有するエッチングマスクを連続線状に形成することにより、劈開前に隣接していた半導体光素子の埋め込み層によって埋め込まれた光導波路が残存しないので半導体光素子の信頼性を高めることができるという効果を有する半導体光素子の製造方法を提供することができるものである。   According to the present invention, an etching mask having a linear portion that penetrates a planned cleavage plane of a region to be a semiconductor optical device is formed in a continuous line shape, thereby being embedded by a buried layer of a semiconductor optical device adjacent before the cleavage. Thus, there can be provided a method for manufacturing a semiconductor optical device having an effect that the reliability of the semiconductor optical device can be improved because the optical waveguide thus formed does not remain.

以下、本発明の実施の形態の半導体光素子の製造方法について、図面を用いて説明する。   Hereinafter, a method for manufacturing a semiconductor optical device according to an embodiment of the present invention will be described with reference to the drawings.

図１（ａ）は本発明に係る半導体光素子の製造方法によって製造される、一方の劈開予定面１ｓに開口する光導波路２の端面２ｅが斜め端面である半導体光素子１の上面図であって、光導波路２の端面２ｅから予め定められた長さＬの第２の直線部２ａが劈開予定面１ｓの法線に対して予め定められた角度θを成す。   FIG. 1A is a top view of a semiconductor optical device 1 manufactured by the method for manufacturing a semiconductor optical device according to the present invention, in which an end surface 2e of an optical waveguide 2 opening on one planned cleavage surface 1s is an oblique end surface. Thus, the second straight portion 2a having a predetermined length L from the end surface 2e of the optical waveguide 2 forms a predetermined angle θ with respect to the normal line of the planned cleavage surface 1s.

即ち、光導波路２は、劈開予定面１ｓの法線に対して予め定められた角度θを成す１つの端面２ｅを起点とする予め定められた長さＬの第２の直線部２ａと、劈開予定面１ｓに垂直な方向に延伸する第１の直線部２ｃと、第２の直線部２ａおよび第１の直線部２ｃに接続する第１の曲線部２ｂとから構成されている。   That is, the optical waveguide 2 includes a second straight portion 2a having a predetermined length L starting from one end surface 2e that forms a predetermined angle θ with respect to the normal line of the planned cleavage surface 1s, and a cleavage plane. The first straight line portion 2c extends in a direction perpendicular to the planned surface 1s, and the second straight line portion 2a and the first curved line portion 2b connected to the first straight line portion 2c.

図１（ｂ）は両方の劈開予定面１ｓおよび１ｓ’に開口する光導波路２の端面２ｅおよび２ｅ’が斜め端面である半導体光素子１の上面図である。   FIG. 1B is a top view of the semiconductor optical device 1 in which the end faces 2e and 2e 'of the optical waveguide 2 opening on both the planned cleavage faces 1s and 1s' are oblique end faces.

即ち、光導波路２は、２つの端面２ｅおよび２ｅ’を起点とし、劈開予定面１ｓおよび１ｓ’に対して予め定められた角度θおよびθ’を成す予め定められた長さＬおよびＬ’の直線である第２の直線部２ａおよび第３の直線部２ａ’と、劈開予定面１ｓおよび１ｓ’に垂直な方向に延伸する第１の直線部２ｃと、第１の直線部２ｃと第２、第３の直線部２ａおよび２ａ’にそれぞれ接続する第１、第２の曲線部２ｂおよび２ｂ’とを含む。   That is, the optical waveguide 2 has two predetermined end faces 2e and 2e ′, and predetermined lengths L and L ′ that form predetermined angles θ and θ ′ with respect to the cleavage planes 1s and 1s ′. The second straight line portion 2a and the third straight line portion 2a ′ which are straight lines, the first straight line portion 2c extending in the direction perpendicular to the planned cleavage surfaces 1s and 1s ′, the first straight line portion 2c and the second straight line portion 2c And first and second curved portions 2b and 2b 'connected to the third straight portions 2a and 2a', respectively.

本発明に係る半導体光素子の製造方法は、図２に示すように、（Ｉ）半導体基板上にクラッド層および活性層を含む複数の半導体層を堆積した活性層エピタキシャルウエハを製造する活性層エピタキシャルウエハ製造段階と、（II）活性層エピタキシャルウエハに複数のストライプ状のエッチングマスクを形成するエッチングマスク形成段階と、（III）活性層エピタキシャルウエハをエッチングして光導波路を形成する光導波路形成段階と、（ＩＶ）光導波路を埋め込み層により埋め込む埋め込み段階と、（Ｖ）エッチングマスクを除去した後に、埋め込みクラッド層を含む複数の半導体層を堆積し、さらに上部電極および下部電極を形成して半導体ウエハを製造する半導体ウエハ製造段階と、（ＶＩ）半導体ウエハを、光導波路を横断する劈開予定面に沿って劈開し、前記劈開予定面に垂直な方向に分離して、複数の半導体光素子を分離する半導体光素子分離段階とを含む。   As shown in FIG. 2, the method for producing a semiconductor optical device according to the present invention comprises: (I) an active layer epitaxial for producing an active layer epitaxial wafer in which a plurality of semiconductor layers including a cladding layer and an active layer are deposited on a semiconductor substrate. A wafer manufacturing stage, (II) an etching mask forming stage for forming a plurality of striped etching masks on the active layer epitaxial wafer, and (III) an optical waveguide forming stage for etching the active layer epitaxial wafer to form an optical waveguide. (IV) a step of filling the optical waveguide with a buried layer; and (V) removing the etching mask, depositing a plurality of semiconductor layers including a buried cladding layer, and forming upper and lower electrodes to form a semiconductor wafer And (VI) the semiconductor wafer crossing the optical waveguide Cleaved along the open scheduled surfaces, separated in a direction perpendicular to the cleave scheduled surface, and a semiconductor optical device isolation step of separating the plurality of semiconductor optical device.

即ち、活性層エピタキシャルウエハ製造段階（Ｉ）においては、有機金属気相成長（ＭＯＶＰＥ）法を用いて半導体基板３０上にｎ−ＩｎＰからなる第１のクラッド層３１、光導波路を形成するＩｎＧａＡｓＰ多重量子井戸からなる活性層３２、ｐ−ＩｎＰからなる第２のクラッド層３３を順次積層して活性層エピタキシャルウエハ３を製造する。   That is, in the active layer epitaxial wafer manufacturing stage (I), the first clad layer 31 made of n-InP and the optical waveguide are formed on the semiconductor substrate 30 by using the metal organic chemical vapor deposition (MOVPE) method. An active layer epitaxial wafer 3 is manufactured by sequentially stacking an active layer 32 made of a quantum well and a second cladding layer 33 made of p-InP.

エッチングマスク形成段階（II）においては、例えば、プラズマＣＶＤ法を用いてＳｉＮｘ膜を堆積し、フォトリソグラフィ技術とエッチング技術を用いて、複数のストライプ状のエッチングマスク３４を形成する。   In the etching mask formation stage (II), for example, a SiNx film is deposited using a plasma CVD method, and a plurality of stripe-shaped etching masks 34 are formed using a photolithography technique and an etching technique.

図３は本発明に係る半導体光素子の製造方法で使用する光導波路パターン、即ち、エッチングマスク３４のパターンを示す上面図であって、図３（ａ）は一方の劈開予定面に開口する光導波路の端面が斜め端面である半導体光素子用の光導波路パターンであり、図３（ｂ）は両方の劈開予定面に開口する光導波路の端面が共に斜め端面である半導体光素子用の光導波路パターンである。   FIG. 3 is a top view showing an optical waveguide pattern used in the method for manufacturing a semiconductor optical device according to the present invention, that is, a pattern of the etching mask 34. FIG. FIG. 3B shows an optical waveguide pattern for a semiconductor optical device in which both end surfaces of the optical waveguide opening to both cleavage planned surfaces are diagonal end surfaces. It is a pattern.

即ち、図３（ａ）に示す本発明に係る半導体光素子の製造方法で使用する光導波路パターンは、図１（ａ）に示した光導波路が少なくとも３つの劈開予定面を貫通して切れ目なしに繋がる形状を有しており、劈開予定面を中心とする予め定められた範囲を通過する部分の形状が、劈開予定面に対して予め定められた角度θを成す直線、または、劈開予定面に対して垂直に交わる直線となっている。   That is, in the optical waveguide pattern used in the method for manufacturing a semiconductor optical device according to the present invention shown in FIG. 3A, the optical waveguide shown in FIG. The shape of the part passing through a predetermined range centered on the planned cleavage plane is a straight line that forms a predetermined angle θ with respect to the planned cleavage plane, or the planned cleavage plane It is a straight line that intersects perpendicularly.

また、図３（ｂ）に示す本発明に係る半導体光素子の製造方法で使用する光導波路パターンは、図１（ｂ）に示した光導波路が少なくとも３つの劈開予定面を貫通して切れ目なしに繋がる形状を有しており、劈開予定面を中心とする予め定められた範囲を通過する部分の形状が、劈開予定面に対して予め定められた角度θまたはθ’を成す直線となっている。   Also, the optical waveguide pattern used in the method of manufacturing a semiconductor optical device according to the present invention shown in FIG. 3B has no breaks as the optical waveguide shown in FIG. 1B penetrates at least three planned cleavage planes. The shape of the portion that passes through a predetermined range centering on the planned cleavage plane is a straight line that forms a predetermined angle θ or θ ′ with respect to the planned cleavage plane. Yes.

３以上の半導体光素子に跨る光導波路を切り出す光導波路パターンにあっては、すべての半導体光素子の光導波路の形状を同一とするために、劈開予定面を通過する光導波路の直線が劈開予定面と成す角度θとθ’を同じ角度とすることが望ましい。   In an optical waveguide pattern that cuts out an optical waveguide that spans three or more semiconductor optical elements, the straight line of the optical waveguide that passes through the planned cleavage plane is planned to be cleaved in order to make the shape of the optical waveguides of all the semiconductor optical elements the same. It is desirable that the angles θ and θ ′ formed with the surface be the same angle.

前述したようにエッチングマスクのパターンは切れ目なしに繋がる形状をしているため、半導体基板の劈開予定面方向の結晶面に対して垂直を成す直線部分が、従来のエッチングマスクのパターンと比較して短くなってしまう。そのため、フォトリソグラフィにおいて、ウエハの結晶面（オリフラもしくはウエハの劈開面）に対して平行合わせをする際、図４に示すようにフォトマスク５０のフォトマスクパターン５０ａのみでは平行合わせをすることが困難になってしまう。そのため、フォトリソグラフィにおいて用いるフォトマスク５０に劈開予定面に垂直な平行合わせ用直線５０ｂを設ける。ウエハの結晶面（オリフラもしくはウエハの劈開面）をその平行合わせ用直線５０ｂに合わせてフォトリソグラフィを行う。   As described above, since the pattern of the etching mask has a shape that is continuously connected, the straight line portion perpendicular to the crystal plane in the direction of the cleavage plane of the semiconductor substrate is compared with the pattern of the conventional etching mask. It will be shorter. Therefore, in photolithography, when performing parallel alignment with the crystal plane of the wafer (orientation flat or cleaved surface of the wafer), it is difficult to perform parallel alignment only with the photomask pattern 50a of the photomask 50 as shown in FIG. Become. Therefore, a parallel alignment straight line 50b perpendicular to the planned cleavage plane is provided in the photomask 50 used in photolithography. Photolithography is performed with the crystal plane of the wafer (the orientation flat or the cleavage plane of the wafer) aligned with the parallel alignment straight line 50b.

光導波路形成段階（III）においては、上記により設計されたエッチングマスク３４と、塩酸、過酸化水素水および水の混合液からなるエッチング液を用いて、第１のクラッド層３１、活性層３２、第２のクラッド層３３をエッチングして、メサストライプ（光導波路パターン）を形成する。   In the optical waveguide formation stage (III), the first cladding layer 31, the active layer 32, the etching mask 34 designed as described above, and an etching solution composed of a mixture of hydrochloric acid, hydrogen peroxide solution, and water are used. The second cladding layer 33 is etched to form a mesa stripe (optical waveguide pattern).

埋め込み段階（ＩＶ）においては、光導波路形成を段階（III）で除去された部分にＭＯＶＰＥ法でｐ−ＩｎＰからなる下部埋め込み層３５およびｎ−ＩｎＰからなる上部埋め込み層３６を堆積して埋め込む。   In the embedding step (IV), the lower buried layer 35 made of p-InP and the upper buried layer 36 made of n-InP are deposited and buried in the portion where the optical waveguide is removed in step (III) by the MOVPE method.

半導体ウエハ製造段階（Ｖ）においては、まず、エッチングマスク３４を除去する。次に、ｐ−ＩｎＰからなる埋め込みクラッド層３７を形成し、その上部にｐ−ＩｎＧａＡｓからなるコンタクト層３８を形成する。次に、半導体基板３０の底面に第１の電極３９を形成し、コンタクト層３８上に第２の電極４０を形成する。   In the semiconductor wafer manufacturing stage (V), first, the etching mask 34 is removed. Next, a buried cladding layer 37 made of p-InP is formed, and a contact layer 38 made of p-InGaAs is formed thereon. Next, the first electrode 39 is formed on the bottom surface of the semiconductor substrate 30, and the second electrode 40 is formed on the contact layer 38.

半導体光素子分離段階（ＶＩ）では、半導体ウエハを図２（ＶＩ）の模式的な光導波路パターン上面図に示した予め定められた劈開予定面Ａ１Ａ１’、Ａ２Ａ２’等で劈開し、複数の半導体光素子が横方向に連なった半導体ウエハに分離する。 In the semiconductor optical element separation step (VI), the semiconductor wafer is formed on the predetermined cleavage planes A 1 A 1 ′, A 2 A 2 ′, etc. shown in the schematic optical waveguide pattern top view of FIG. Cleavage and separation into a semiconductor wafer in which a plurality of semiconductor optical elements are arranged in a horizontal direction.

最後に、複数の半導体光素子が横方向に連なった半導体ウエハを劈開予定面Ａ１Ａ１’、Ａ２Ａ２’等に垂直なＢ１Ｂ１’、Ｂ２Ｂ２’等の方向に分離して、個々の半導体光素子に分離する。なお、具体的な分離方法としては、劈開、ダイシング等がある。 Finally, a semiconductor wafer in which a plurality of semiconductor optical elements are arranged in a horizontal direction is oriented in the direction of B 1 B 1 ′, B 2 B 2 ′, etc. perpendicular to the planned cleavage planes A 1 A 1 ′, A 2 A 2 ′, etc. Separated into individual semiconductor optical elements. Specific separation methods include cleavage, dicing and the like.

なお、前述してきた本発明に係る半導体光素子の製造方法によって製造される斜め端面を有する半導体光素子には第１、第２の曲線部２ｂ、２ｂ’および第２、第３の直線部２ａ、２ａ’が存在し、それらの部分は劈開予定面に平行な結晶面の法線に対して角度を持っているため、光導波路形成段階においてその部分のエッチングにばらつきが生じる可能性がある。このため、半導体光素子の特性検査において、このようなエッチングのばらつきが生じた場合には特性が変化してしまうことがある。従って、半導体光素子に分離する前の半導体ウエハ（特に活性層の特性）の良し悪しを判断することができない。   In the semiconductor optical device having the oblique end face manufactured by the method for manufacturing a semiconductor optical device according to the present invention described above, the first and second curved portions 2b, 2b 'and the second and third straight portions 2a are used. 2a 'exist, and these portions have an angle with respect to the normal line of the crystal plane parallel to the cleavage plane, so that there is a possibility that the etching of the portion may vary in the optical waveguide formation stage. For this reason, in the characteristic inspection of the semiconductor optical device, when such variation in etching occurs, the characteristic may change. Therefore, the quality of the semiconductor wafer (particularly the characteristics of the active layer) before being separated into semiconductor optical elements cannot be judged.

そのため、エッチングのばらつきに影響を受けずに半導体ウエハ自体の良し悪しを評価するために、１つの第１の直線部が２つの劈開予定面に垂直に開口するようなパターン（ファブリペロー型レーザダイオードとなる部分）を、図５に示すようにエッチングマスクパターン上の一部に挿入する。半導体光素子分離段階において半導体光素子を分離する際に、ファブリペロー型レーザダイオードも分離し、これを半導体ウエハ評価用素子１０として利用する。   Therefore, in order to evaluate the quality of the semiconductor wafer itself without being affected by variations in etching, a pattern (Fabry-Perot type laser diode) in which one first straight line portion opens perpendicularly to two planned cleavage planes. Is inserted into a part of the etching mask pattern as shown in FIG. When separating the semiconductor optical element in the semiconductor optical element separation stage, the Fabry-Perot laser diode is also separated and used as the semiconductor wafer evaluation element 10.

それらの半導体ウエハ評価用素子１０の特性を測定することにより、光導波路形成段階において、第１、第２の曲線部２ｂ、２ｂ’および第２、第３の直線部２ａ、２ａ’のエッチングのばらつきの影響を受けずに、半導体ウエハ（特に活性層の特性）の良し悪しを把握することができる。   By measuring the characteristics of these semiconductor wafer evaluation elements 10, the first and second curved portions 2b and 2b 'and the second and third straight portions 2a and 2a' are etched in the optical waveguide formation stage. The quality of the semiconductor wafer (especially the characteristics of the active layer) can be ascertained without being affected by variations.

半導体ウエハ評価用素子１０の光の導波方向の長さは適宜設計可能であるが、できれば半導体光素子１と同程度の長さとすることが望ましい。そのためには、半導体ウエハ評価用素子１０となる領域の第１の直線部の長さを半導体光素子１の光の導波方向の長さ分だけ延長してやればよい。半導体ウエハ評価用素子１０の光の導波方向の長さを半導体光素子１のそれと同程度にすることで、異なる長さの素子が同時にプロセスされることによって生じうる不便を防ぎ、かつ利得や内部損失などの特性比較が行いやすくなるという利点が得られる。   The length of the light guide direction of the semiconductor wafer evaluation element 10 can be designed as appropriate. However, it is desirable that the length be approximately the same as that of the semiconductor optical element 1 if possible. For this purpose, the length of the first linear portion of the region to be the semiconductor wafer evaluation element 10 may be extended by the length of the optical waveguide direction of the semiconductor optical element 1. By making the length of the light guide direction of the semiconductor wafer evaluation element 10 to be approximately the same as that of the semiconductor optical element 1, inconveniences that may occur when elements of different lengths are processed simultaneously, and gain and There is an advantage that it is easy to compare characteristics such as internal loss.

なお、以上はＩｎＰ系の半導体光素子について説明してきたが、もちろんＧａＡｓ系の半導体光素子に対しても本発明の製造方法を適用できる。   Although the above has described the InP-based semiconductor optical device, the manufacturing method of the present invention can also be applied to a GaAs-based semiconductor optical device.

即ち、本発明に係る半導体光素子の製造方法によれば、半導体光素子内に隣接する半導体光素子の光導波路が残存しないため、半導体光素子の信頼性を向上することが可能となる。   That is, according to the method of manufacturing a semiconductor optical device according to the present invention, since the optical waveguide of the adjacent semiconductor optical device does not remain in the semiconductor optical device, the reliability of the semiconductor optical device can be improved.

以上のように、本発明に係る半導体光素子の製造方法は、劈開前に隣接していた半導体光素子の埋め込み層によって埋め込まれた光導波路が残存しないので半導体光素子の信頼性を高めることができるという効果を有し、光通信等において有効である。   As described above, the method for manufacturing a semiconductor optical device according to the present invention can improve the reliability of the semiconductor optical device because the optical waveguide embedded by the embedded layer of the semiconductor optical device adjacent before the cleavage does not remain. This is effective in optical communication and the like.

本発明に係る半導体光素子の製造方法によって製造される半導体光素子の上面図The top view of the semiconductor optical element manufactured by the manufacturing method of the semiconductor optical element concerning this invention 本発明に係る半導体光素子の製造方法の製造段階を示す断面図および上面図Sectional drawing and top view which show the manufacturing stage of the manufacturing method of the semiconductor optical element concerning this invention 本発明に係る半導体光素子の製造方法で使用する窒化シリコンパターンの上面図The top view of the silicon nitride pattern used with the manufacturing method of the semiconductor optical element concerning this invention 本発明に係る半導体光素子の製造方法の製造段階を示す上面図The top view which shows the manufacturing stage of the manufacturing method of the semiconductor optical element concerning this invention 本発明に係る半導体光素子の製造方法で使用する窒化シリコンパターンの上面図The top view of the silicon nitride pattern used with the manufacturing method of the semiconductor optical element concerning this invention 従来の斜め端面光導波路を備える半導体光素子ウエハおよび半導体光素子の上面図Semiconductor optical device wafer having a conventional oblique end face optical waveguide and a top view of the semiconductor optical device

符号の説明Explanation of symbols

１ 半導体光素子
１ｓ、１ｓ’ 劈開予定面
２ 光導波路
２ａ 第２の直線部
２ａ’ 第３の直線部
２ｂ 第１の曲線部
２ｂ’ 第２の曲線部
２ｃ 第１の直線部
２ｅ、２ｅ’ 端面
３ 活性層エピタキシャルウエハ
４ 半導体ウエハ
１０ 半導体ウエハ評価用素子
３０ 半導体基板
３１ 第１のクラッド層
３２ 活性層
３３ 第２のクラッド層
３４ エッチングマスク
３５ 下部埋め込み層
３６ 上部埋め込み層
３７ 埋め込みクラッド層
３８ コンタクト層
３９ 第１の電極
４０ 第２の電極
４１、４２、４３ 半導体光素子
４１ｇ、４２ｇ、４３ｇ 光導波路
５０ フォトマスク
５０ａ フォトマスクパターン
５０ｂ 平行合わせ用直線 DESCRIPTION OF SYMBOLS 1 Semiconductor optical element 1s, 1s 'Planned cleavage surface 2 Optical waveguide 2a 2nd linear part 2a' 3rd linear part 2b 1st curve part 2b '2nd curve part 2c 1st linear part 2e, 2e' End face 3 Active layer epitaxial wafer 4 Semiconductor wafer 10 Semiconductor wafer evaluation element 30 Semiconductor substrate 31 First cladding layer 32 Active layer 33 Second cladding layer 34 Etching mask 35 Lower embedded layer 36 Upper embedded layer 37 Embedded cladding layer 38 Contact Layer 39 First electrode 40 Second electrode 41, 42, 43 Semiconductor optical device 41g, 42g, 43g Optical waveguide 50 Photomask 50a Photomask pattern 50b Straight line for parallel alignment

Claims (3)

半導体基板上にクラッド層および活性層を含む複数の半導体層を堆積した活性層エピタキシャルウエハを製造する活性層エピタキシャルウエハ製造段階と、
前記活性層エピタキシャルウエハに複数のストライプ状のエッチングマスクを形成するエッチングマスク形成段階と、
前記エッチングマスク形成後の前記活性層エピタキシャルウエハの前記複数の半導体層を少なくとも前記活性層まで厚さ方向にエッチングにより除去してストライプ状の光導波路を形成する光導波路形成段階と、
前記光導波路を埋め込み層により埋め込む埋め込み段階と、
前記エッチングマスクを除去した後に、埋め込みクラッド層を含む複数の半導体層を堆積し、さらに上部電極および下部電極を形成して半導体ウエハを製造する半導体ウエハ製造段階と、
前記半導体ウエハを、前記光導波路を横断する劈開予定面に沿って劈開し、かつ前記劈開予定面に垂直な方向に分離して、複数の半導体光素子を分離する半導体光素子分離段階とを含む半導体光素子の製造方法において、
前記エッチングマスク形成段階が、１つの半導体光素子となる領域の一方の劈開予定面を垂直に貫通する第１の直線部と、他方の劈開予定面を前記第１の直線部と予め定められた角度を成して貫通する第２の直線部と、前記第１の直線部と前記第２の直線部とを接続する第１の曲線部とを含み、当該１つの半導体光素子となる領域および当該１つの半導体光素子となる領域に光の導波方向で隣接する半導体光素子となる領域の少なくとも３つの劈開予定面を通過する連続線状のエッチングマスクを形成する段階である半導体光素子の製造方法。 An active layer epitaxial wafer manufacturing stage for manufacturing an active layer epitaxial wafer in which a plurality of semiconductor layers including a cladding layer and an active layer are deposited on a semiconductor substrate;
An etching mask forming step of forming a plurality of stripe-shaped etching masks on the active layer epitaxial wafer;
An optical waveguide forming step of forming a striped optical waveguide by removing the plurality of semiconductor layers of the active layer epitaxial wafer after the etching mask formation to at least the active layer by etching in a thickness direction;
An embedding step of embedding the optical waveguide with an embedding layer;
After removing the etching mask, depositing a plurality of semiconductor layers including a buried cladding layer, and further forming a semiconductor wafer by forming an upper electrode and a lower electrode; and
A semiconductor optical element separation step for separating the semiconductor optical element by separating the semiconductor wafer along a planned cleavage plane crossing the optical waveguide and in a direction perpendicular to the planned cleavage plane. In the method for manufacturing a semiconductor optical device,
In the etching mask forming step, a first straight line portion that vertically penetrates one of the planned cleavage planes of a region to be a semiconductor optical element and the other planned cleavage plane are predetermined as the first straight line portion. A second straight line portion penetrating at an angle; a first curved line portion connecting the first straight line portion and the second straight line portion; a region to be the one semiconductor optical element; The semiconductor optical device is a step of forming a continuous linear etching mask that passes through at least three cleavage planes of a region to be a semiconductor optical device adjacent to the region to be the one semiconductor optical device in the light guiding direction. Production method. 半導体基板上にクラッド層および活性層を含む複数の半導体層を堆積した活性層エピタキシャルウエハを製造する活性層エピタキシャルウエハ製造段階と、
前記活性層エピタキシャルウエハに複数のストライプ状のエッチングマスクを形成するエッチングマスク形成段階と、
前記エッチングマスク形成後の前記活性層エピタキシャルウエハの前記複数の半導体層を少なくとも前記活性層まで厚さ方向にエッチングにより除去してストライプ状の光導波路を形成する光導波路形成段階と、
前記光導波路を埋め込み層により埋め込む埋め込み段階と、
前記エッチングマスクを除去した後に、埋め込みクラッド層を含む複数の半導体層を堆積し、さらに上部電極および下部電極を形成して半導体ウエハを製造する半導体ウエハ製造段階と、
前記半導体ウエハを、前記光導波路を横断する劈開予定面に沿って劈開し、かつ前記劈開予定面に垂直な方向に分離して、複数の半導体光素子を分離する半導体光素子分離段階とを含む半導体光素子の製造方法において、
前記エッチングマスク形成段階が、１つの半導体光素子となる領域の劈開予定面に垂直な第１の直線部と、前記第１の直線部と予め定められた角度を成して当該劈開予定面のそれぞれを貫通する第２の直線部および第３の直線部と、前記第１の直線部と前記第２の直線部とを接続する第１の曲線部と、前記第１の直線部と前記第３の直線部とを接続する第２の曲線部とを含み、当該１つの半導体光素子となる領域および当該１つの半導体光素子となる領域に光の導波方向で隣接する半導体光素子となる領域の少なくとも３つの劈開予定面を通過する連続線状のエッチングマスクを形成する段階である半導体光素子の製造方法。 An active layer epitaxial wafer manufacturing stage for manufacturing an active layer epitaxial wafer in which a plurality of semiconductor layers including a cladding layer and an active layer are deposited on a semiconductor substrate;
An etching mask forming step of forming a plurality of stripe-shaped etching masks on the active layer epitaxial wafer;
An optical waveguide forming step of forming a striped optical waveguide by removing the plurality of semiconductor layers of the active layer epitaxial wafer after the etching mask formation to at least the active layer by etching in a thickness direction;
An embedding step of embedding the optical waveguide with an embedding layer;
After removing the etching mask, depositing a plurality of semiconductor layers including a buried cladding layer, and further forming a semiconductor wafer by forming an upper electrode and a lower electrode; and
A semiconductor optical element separation step for separating the semiconductor optical element by separating the semiconductor wafer along a planned cleavage plane crossing the optical waveguide and in a direction perpendicular to the planned cleavage plane. In the method for manufacturing a semiconductor optical device,
The etching mask forming step includes forming a first straight line portion perpendicular to a planned cleavage plane of a region to be one semiconductor optical element, and a predetermined angle with the first straight line portion. A second straight line portion and a third straight line portion penetrating each other; a first curved line portion connecting the first straight line portion and the second straight line portion; the first straight line portion and the first straight line portion; A semiconductor optical element that is adjacent to the region to be the one semiconductor optical element and the region to be the one semiconductor optical element in the light guiding direction. A method of manufacturing a semiconductor optical device, the method comprising forming a continuous linear etching mask that passes through at least three cleavage planes of a region. 前記エッチングマスク形成段階は、The etching mask forming step includes
前記連続線状のエッチングマスクを形成するための連続線状のフォトマスクパターンが形成されているとともに、前記連続線状のフォトマスクパターンの前記第１の直線部と平行であり、かつ前記少なくとも３つの劈開予定面を垂直に貫通する直線状のフォトマスクパターンが形成されているフォトマスクを用いて前記エッチングマスクを形成することを特徴とする請求項１または請求項２に記載の半導体光素子の製造方法。A continuous line photomask pattern for forming the continuous line etching mask is formed, parallel to the first straight line portion of the continuous line photomask pattern, and at least 3 3. The semiconductor optical device according to claim 1, wherein the etching mask is formed using a photomask in which a linear photomask pattern that vertically penetrates two planned cleavage planes is formed. Production method.
JP2005336925A 2005-11-22 2005-11-22 Semiconductor optical device manufacturing method Active JP4489691B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005336925A JP4489691B2 (en) 2005-11-22 2005-11-22 Semiconductor optical device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005336925A JP4489691B2 (en) 2005-11-22 2005-11-22 Semiconductor optical device manufacturing method

Publications (2)

Publication Number Publication Date
JP2007142317A JP2007142317A (en) 2007-06-07
JP4489691B2 true JP4489691B2 (en) 2010-06-23

Family

ID=38204790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005336925A Active JP4489691B2 (en) 2005-11-22 2005-11-22 Semiconductor optical device manufacturing method

Country Status (1)

Country Link
JP (1) JP4489691B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5958916B2 (en) * 2011-05-02 2016-08-02 パナソニックＩｐマネジメント株式会社 Super luminescent diode

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62269381A (en) * 1986-05-19 1987-11-21 Canon Inc Manufacture of semiconductor laser device
JPH08211342A (en) * 1995-02-03 1996-08-20 Hitachi Ltd Semiconductor optical function element
JPH08255947A (en) * 1995-03-17 1996-10-01 Mitsubishi Electric Corp Semiconductor laser and fabrication thereof
JPH10300959A (en) * 1997-05-01 1998-11-13 Nippon Telegr & Teleph Corp <Ntt> Semiconductor optical waveguide functional element
JP2004221321A (en) * 2003-01-15 2004-08-05 Mitsubishi Electric Corp Wavelength variation semiconductor light equipment
JP2004266095A (en) * 2003-02-28 2004-09-24 Anritsu Corp Semiconductor optical amplifier

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62269381A (en) * 1986-05-19 1987-11-21 Canon Inc Manufacture of semiconductor laser device
JPH08211342A (en) * 1995-02-03 1996-08-20 Hitachi Ltd Semiconductor optical function element
JPH08255947A (en) * 1995-03-17 1996-10-01 Mitsubishi Electric Corp Semiconductor laser and fabrication thereof
JPH10300959A (en) * 1997-05-01 1998-11-13 Nippon Telegr & Teleph Corp <Ntt> Semiconductor optical waveguide functional element
JP2004221321A (en) * 2003-01-15 2004-08-05 Mitsubishi Electric Corp Wavelength variation semiconductor light equipment
JP2004266095A (en) * 2003-02-28 2004-09-24 Anritsu Corp Semiconductor optical amplifier

Also Published As

Publication number Publication date
JP2007142317A (en) 2007-06-07

Similar Documents

Publication Publication Date Title
JP4817255B2 (en) Optical semiconductor device and manufacturing method thereof
US8563342B2 (en) Method of making semiconductor optical integrated device by alternately arranging spacers with integrated device arrays
US9229168B2 (en) Semiconductor optical waveguide device and method for manufacturing the same
US6335559B1 (en) Semiconductor device cleave initiation
JP4651312B2 (en) Manufacturing method of semiconductor device
JP5617178B2 (en) Manufacturing method of optical waveguide
KR100380215B1 (en) Method of manufacturing semiconductor device
JP4489691B2 (en) Semiconductor optical device manufacturing method
US8889445B2 (en) Method for manufacturing semiconductor optical device and semiconductor optical device
JP4664742B2 (en) Semiconductor optical device and manufacturing method thereof
JP4151043B2 (en) Manufacturing method of optical semiconductor device
JP4959644B2 (en) Semiconductor laser device, semiconductor wafer, and manufacturing method of semiconductor laser device
US11056341B2 (en) Optical semiconductor element and method of manufacturing the same
JP5047665B2 (en) Semiconductor light emitting device and manufacturing method thereof
US11870212B2 (en) Semiconductor laser device and method for manufacturing the same
JP4769778B2 (en) Optical semiconductor device and manufacturing method thereof
JP2008311547A (en) Semiconductor laser element, and manufacturing method
JP4910870B2 (en) Manufacturing method of semiconductor laser device
JP2009117616A (en) Method for manufacturing semiconductor optical element
JP4606104B2 (en) Integrated semiconductor laser device
WO2020181497A1 (en) Double-cavity dfb laser chip, optical emission component, optical module, and optical network device
JP2008227287A (en) Method of fabricating semiconductor optical device
JP5264764B2 (en) Etched facet ridge laser with etch stop
JP2011035432A (en) Semiconductor element, semiconductor device and its manufacturing method
JPH06152062A (en) Manufacture of semiconductor laser

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090915

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090929

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091110

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100330

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100331

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130409

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4489691

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130409

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140409

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250