JP5043495B2 - Semiconductor light emitting device - Google Patents

Description

  The present invention relates to a semiconductor light emitting device including a semiconductor layer including a photoactive layer, and a method for manufacturing such a semiconductor light emitting device.

  A semiconductor light emitting element is an element that generates light in a photoactive layer and outputs the light. Among them, a semiconductor light emitting device having a ridge portion on a semiconductor layer including a photoactive layer is selected at a lower portion of the ridge portion in the photoactive layer, with the upper surface of the ridge portion being electrically connected to the electrode. A light emitting part is generated. In addition, a plurality of ridge portions may be arranged in parallel on the semiconductor layer with a groove portion interposed therebetween (see Patent Document 1). Such a semiconductor light emitting element including a plurality of ridges arranged in parallel is used in, for example, a laser printer.

Compared with a buried structure in which a photoactive region has a waveguide structure and is embedded in a semiconductor layer, a ridge-type semiconductor light emitting device is easy to manufacture and can be reduced in cost. The emission width is about several μm, and the horizontal spread angle of the emitted light is as small as about 10 degrees. Also, compared to the case where bump connection is made to the submount with junction down, when the submount is assembled with junction up and wire connection is made, stress during connection is avoided, and the emitted light is Polarization characteristics are stable.
JP-A-11-135893

  In a semiconductor light emitting device that includes a plurality of ridge portions arranged in parallel and is assembled in a junction-up manner, an electrode pad portion for wire connection is provided on the semiconductor layer corresponding to each ridge portion. The electrode pad is usually provided outside the peripheral region of the semiconductor chip, that is, the plurality of ridge portions arranged in parallel. When the first ridge portion and the second ridge portion are referred to in order from the electrode pad portion among the plurality of ridge portions, the electrical wiring between the electrode pad portion corresponding to the second ridge portion and the second ridge portion is as follows. Thus, the first ridge portion and the element isolation groove existing between the two are provided.

  However, the undesired portion is electrically connected to the electric wiring layer to be connected to the second ridge portion because the insulating layer is peeled off at the undesired portion during the manufacturing process or a film formation failure occurs. May end up. In this case, in the photoactive layer, a light emitting portion is generated at the same time not only under the second ridge portion but also under the undesired portion. And the beam quality of the light output from the semiconductor light emitting device is deteriorated.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor light emitting device capable of suppressing light emission under an undesired portion. Moreover, it aims at providing the method which can manufacture such a semiconductor light-emitting device.

A semiconductor light emitting device according to the present invention is provided in parallel with a semiconductor layer formed on a substrate and including a photoactive layer, an electrode pad portion provided on the semiconductor layer, and a groove portion on the semiconductor layer. And a plurality of ridge portions including a first ridge portion and a second ridge portion in order from the electrode pad portion. The semiconductor light emitting device according to the present invention includes (1) a first insulating layer formed on each side of a plurality of ridges from the side wall surface of each ridge to the bottom of the groove, and (2) a second ridge. A second insulating layer formed from the bottom of the groove on the electrode pad side to the electrode pad, and (3) a metal formed from the bottom of the groove opposite to the electrode pad on the second ridge to the electrode pad. And the layers are formed in order. Furthermore, the semiconductor light emitting device according to the present invention is characterized in that metallic layer is electrically connected to the upper surface of the second ridge portion. Further, it is preferable that an element isolation groove reaching the substrate is formed on the bottom surface of the groove portion, and the first insulating layer and the second insulating layer are formed on the inner wall surface and the bottom surface of the element isolation groove.

A method of manufacturing a semiconductor light emitting device according to the present invention includes: a semiconductor layer formed on a substrate and including a photoactive layer; an electrode pad portion provided on the semiconductor layer; and a semiconductor layer on the semiconductor layer in order from the electrode pad portion. A method of manufacturing a semiconductor light emitting device including a plurality of ridge portions including a first ridge portion and a second ridge portion and arranged in parallel with each other with a groove interposed therebetween, wherein (1) formation of a first insulating layer and Applying resist over the entire surface, selectively removing the resist on the upper surface of each of the plurality of ridges by exposure and development using a self-alignment method, and performing dry etching using the remaining resist layer as a mask , a first insulating layer forming step of forming a first insulating layer on both sides of each ridge to the bottom surface of the groove from the side wall surface of each ridge portion (2) an etching rate of the material of the first insulating layer Performed on the entire surface of the formation and application of resist in the second insulating layer made of a material with a high Ri, by performing dry etching using as a mask the remaining resist layer by exposure and development using a mask having a predetermined pattern, the second ridge a second insulating layer forming step of forming a second insulating layer from the bottom by the electrode pad portion or the groove portion of the electrode pad side parts, (3) the bottom surface of the groove opposite to the electrode pad portion side of the second ridge portion A metal layer forming step of forming a metal layer electrically connected to the upper surface of the second ridge portion from the electrode pad portion to the electrode pad portion. In addition, after forming the element isolation groove reaching the substrate at the bottom surface of the groove part, the first insulating layer forming step, the second insulating layer forming step, and the metal layer forming step are sequentially performed. In the first insulating layer forming step, the element isolation groove is formed Preferably, the first insulating layer is also formed on the inner wall surface and the bottom surface of the first insulating layer, and the second insulating layer is also formed on the inner wall surface and the bottom surface of the element isolation groove in the second insulating layer forming step.

  The present invention relates to a metal layer to be electrically connected to the second ridge portion when the first ridge portion and the second ridge portion are formed in order from the electrode pad portion, and the first insulation below the metal layer. The present invention relates to the structure of the layer and the second insulating layer.

  In the first insulating layer forming step, the first insulating layer can be removed at least on the upper surface of each ridge portion by exposing and developing the resist by the self-alignment method. At this time, the first insulating layer is formed even in an undesired portion. May be removed. However, in the subsequent second insulating layer forming step, the second insulating layer can be formed in a predetermined region by using a mask having a predetermined pattern instead of the self-alignment method and exposing and developing the resist. The desired portion is covered with the second insulating layer.

  The second insulating layer is made of a material having an etching rate larger than that of the material of the first insulating layer. By doing so, it is possible to avoid the removal of the first insulating layer by selectively removing the predetermined portion of the second insulating layer in the dry etching performed using the resist layer as a mask. . Therefore, the metal layer formed on the second insulating layer is prevented from being electrically connected to the semiconductor layer at the groove.

  According to the present invention, it is possible to suppress the emission of light below an undesired portion.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

FIG. 1 is a perspective view of a semiconductor light emitting device 1 according to this embodiment. FIG. 2 is a plan view of the semiconductor light emitting device 1 according to the present embodiment. The semiconductor light-emitting device 1 shown in FIG. 1 is assembled in a junction-up on the sub-mount 2, a metal layer ₇₃ 1-73 ₄ on the electrode pads 41 and 42 and the wire ₃ 1 to 3 ₄ It is connected. Each of the metal layers 73 _{1 to} 73 ₄ is electrically connected to the p-type cap layer in a wide range that continues along the extending direction of the corresponding ridge portions 31 to 34.

The semiconductor light emitting device 1 includes four ridge portions 31 to 34 provided in parallel on a semiconductor layer formed on a substrate and including a photoactive layer, and a peripheral region of the semiconductor chip on the ridge portion 31 side. The electrode pad portion 41 is provided, and the electrode pad portion 42 is provided in the peripheral region of the semiconductor chip on the ridge portion 34 side. Metal layer 73 ₁ is electrically connected to the semiconductor layer at the ridge portion 31, it is wire 3 ₁ electrically connected to the electrode pad portion 41. Metal layer 73 ₂ is electrically connected to the semiconductor layer at the ridge portion 32, it is wire 3 ₂ electrically connected to the electrode pad portion 41. Metal layer 73 ₃ is electrically connected to the semiconductor layer at the ridge portion 33, it is wire 3 ₃ electrically connected to the electrode pad portion 42. The metal layer 73 ₄ is electrically connected to the semiconductor layer at the ridge portion 34, it is wire 3 ₄ electrically connected to the electrode pad portion 42.

  The semiconductor light emitting device 1 includes a groove 51 provided between the electrode pad 41 and the ridge 31, a groove 52 provided between the ridge 31 and the ridge 32, and the ridge 32 and ridge. A groove 53 provided between the ridge 33, a groove 54 provided between the ridge 33 and the ridge 34, a groove 55 provided between the ridge 34 and the electrode pad 42, Is provided. Further, the semiconductor light emitting element 1 is provided in the element isolation layer 61 provided in the groove 51, the element isolation layer 62 provided in the groove 52, the element isolation layer 63 provided in the groove 53, and the groove 54. An element isolation layer 64 and an element isolation layer 65 provided in the groove 55 are provided. The electrode pad portions 41 and 42 have the same height as the adjacent groove portions 51 and 55 in the present embodiment, but may be higher than the groove portions 51 and 55.

  The semiconductor light emitting device 1 has a symmetrical structure with a central device isolation layer 63 as the center. Therefore, hereinafter, the cross-sectional structure and the manufacturing method will be mainly described between the central element isolation layer 63 and the electrode pad portion 41.

  FIG. 3 is a cross-sectional view of the semiconductor light emitting device 1 according to this embodiment. FIG. 2A shows a cross section along the line AA in FIG. FIG. 2B shows a cross section along the line BB in FIG.

  As shown in FIGS. 3A and 3B, the semiconductor light emitting device 1 includes an n-type cladding layer 12, a photoactive layer 13, and a p-type cladding layer 14 on one main surface of the n-type substrate 10. A semiconductor layer 11 is formed in this order, and p-type cap layers 21 and 22 are formed on the semiconductor layer 11. A metal layer 15 is formed on the other main surface of n-type substrate 10.

  Each of the cap layers 21 and 22 is provided so as to extend in a direction in which two opposing end surfaces of the substrate 10 are connected to each other, and the upper surface is substantially flat and the heights are substantially equal to each other. Each of the cap layers 21 and 22 extends in a direction perpendicular to the two opposite end surfaces of the substrate 10. Among them, the cap layer 21 is an element constituting the ridge portion 31. The cap layer 22 is an element constituting the ridge portion 32. The ridge portions 31 to 34 may have an inverted mesa shape or a forward mesa shape.

  A groove portion 51 is provided between the electrode pad portion 41 and the ridge portion 31. Further, a groove portion 52 is provided between the ridge portion 31 and the ridge portion 32. Each of the grooves 51 to 55 has a substantially flat bottom surface and a substantially equal depth. In addition, element isolation grooves 61 to 65 reaching the substrate 10 are formed on the bottom surfaces of the groove portions 51 to 55. These element isolation grooves 61 to 65 extend in parallel with the extending direction of each ridge portion.

  For example, the composition of the n-type substrate 10 is GaAs. The n-type cladding layer 12 has a composition of AlGaAs and a thickness of 1.0 μm. The photoactive layer 13 has a composition of AlGaAs and a thickness of 0.1 μm. The p-type cladding layer 14 is composed of AlGaAs and has a thickness of 1.0 μm. The p-type cap layers 21 and 22 have a composition of GaAs and a thickness of 1.0 μm. The width of the upper surface of each of the ridge portions 31 to 34 is 10 μm, and the width of the lower portion is 8 μm. Moreover, the width | variety of each bottom face of the groove parts 51-55 is 20 micrometers.

In the configuration of the semiconductor light emitting device 1 including the ridge portions 31 to 34 and the electrode pad portions 41 and 42, a first insulating layer 71, a second insulating layer 72, and a metal layer 73 are further formed in this order. Yes. However, the p-type cap layer 21 and electrically connected to the metal layer 73 _first part of the cross section (cross section taken along the line B-B in FIG. 2) in the ridge section 31, the p-type cap layer at the ridge portion 32 in the electrically connected to the metal layer 73 _second part of the cross section (cross section taken along the line a-a in FIG. 2) to 22, configuration is different.

  As shown in FIG. 3A, in the cross section along the line AA in FIG. 2, the first insulating layer 71 is formed on the both sides of the four ridge portions 31 to 34 from the side wall surface of each ridge portion. It is formed up to the bottom of the groove. The first insulating layer 71 may be formed on the upper surfaces of the electrode pad portions 41 and 42, may be formed on the entire bottom surfaces of the groove portions 51 to 55, and the element isolation groove 61. The inner wall surface and the bottom surface of each of -65 may also be formed. The first insulating layer 71 is not formed on the upper surfaces of the ridge portions 31 to 34.

  The second insulating layer 72 is formed from the bottom surface of the groove portion 52 on the electrode pad portion 41 side of the ridge portion 32 to the electrode pad portion 41, and from the bottom surface of the groove portion 54 on the electrode pad portion 42 side of the ridge portion 33 to the electrode. The pad part 42 is formed. The second insulating layer 72 is also formed on the inner wall surface and the bottom surface of each of the element isolation grooves 61 to 65. The second insulating layer 72 is not formed on the upper surface and the side wall surfaces on both sides of each of the ridge portions 32 and 33 and a part of the bottom surface of the groove portion continuing from the side wall surface.

Metal layer 73 ₂ is formed from the bottom surface of the groove portion 53 of the electrode pad portion 41 side and the opposite side of the ridge portion 32 to the electrode pad portions 41, also, the electrode pad portion 42 side of the ridge portion 33 of the opposite groove The electrode pad portion 42 is formed from the bottom surface of 53. Metal layer 73 ₂ has been also formed on the inner wall surface and the bottom surface of each element isolation trench 61,62,64,65, it is not formed in the inner wall surface and the bottom surface of the isolation trench 63.

Metal layer 73 ₂ is electrically connected to the upper surface of the p-type cap layer 22 of the ridge portion 32. However, the metal layer 73 _2, the p-type cap layer 21 of the ridge 31 not electrically connected, also not be electrically connected to the semiconductor layer of the electrode pad portion 41.

The etching rate of the material of the second insulating layer 72 is higher than the etching rate of the material of the first insulating layer 71. For example, the first insulating layer 71 is amorphous Si, and the second insulating layer 72 is SiN or SiO ₂ . Alternatively, the first insulating layer 71 is SiO ₂ and the second insulating layer 72 is SiN.

  As shown in FIG. 3B, each of the first insulating layers 71 is formed in the same range as that shown in FIG. 3A in the cross section along the line BB in FIG. ing. The second insulating layer 72 is formed from the bottom surface of the groove portion 51 to the electrode pad portion 41, is formed from the bottom surface of the groove portion 52 to the bottom surface of the groove portion 54, and is formed from the bottom surface of the groove portion 55 to the electrode pad portion 42. The second insulating layer 72 is also formed on the inner wall surface and the bottom surface of each of the element isolation grooves 61 to 65. The second insulating layer 72 is not formed on the upper surface and both side wall surfaces of the ridge portions 31 and 34 and a part of the bottom surface of the groove portion extending from the side wall surface.

Metal layer 73 ₁ is formed from the bottom surface of the groove portion 52 to the electrode pad portion 41. Metal layer 73 ₁ is also formed on the inner wall surface and the bottom surface of the isolation groove 61. Metal layer 73 ₁ is electrically connected to the upper surface of the p-type cap layer 21 of the ridge 31. However, the metal layer 73 _1, the p-type cap layer 22 of the ridge portion 32 not electrically connected, also not be electrically connected to the semiconductor layer of the electrode pad portion 41.

  The metal layer 73 is preferably composed of a plurality of metal films. In particular, the metal layer 73 is a plurality of metal films, and the lowermost layer is preferably a Ti film. The metal layer 73 is preferably made of a multi-layered metal film of Ti / Al / Au, Ti / Au or Cr / Au. If the lowermost layer is a Ti film, the adhesion between the first insulating layer 71 or the second insulating layer 72 and the metal layer 73 is good. For example, the thickness of the first insulating layer 71 is 1000 mm, the thickness of the second insulating layer 72 is 1000 mm, and the thickness of the metal layer 73 is 3500 mm.

In the semiconductor light emitting element 1, the metal layer ₇₃ 1-73 ₄ is a p-type electrode, the metal layer 15 is n-type electrode. When a voltage is applied between the metal layer 73 ₁ and the metal layer 15, metal layer 73 ₁ is photoactive layer 13 located below the ridge portion 31 which is electrically connected to the p-type cap layer 21 A light emitting portion is generated in the region. Similarly, when a voltage is applied between the metal layer 73 ₂ and the metal layer 15, the light emitting portion is generated in the area of the photoactive layer 13 located below the ridge portion 32. When a voltage is applied between the metal layer 73 ₃ and the metal layer 15, the light emitting portion is generated in the area of the photoactive layer 13 located below the ridge portion 33. Further, when a voltage is applied between the metal layer 73 ₄ and the metal layer 15, the light emitting portion is generated in the area of the photoactive layer 13 located below the ridge portion 34.

In each of these light emitting portions, light is generated by recombination of electrons and holes by voltage application. Further, in this semiconductor light emitting device 1, a Fabry-Perot resonator is constituted by two end faces perpendicular to the extending direction of each of the ridge portions 31 to 34, and laser oscillation is generated by this resonator. In addition, since a voltage can be independently applied to each of the metal layers 73 _{1 to} 73 _{4 with} respect to the common metal layer 15, the light emission is independently performed in the region of the photoactive layer 13 below each of the ridge portions 31 to 34. Parts can occur.

Further, in the semiconductor light emitting device 1, in the cross-sectional structure shown in FIG. 3A, the first insulating layer 71 may be peeled off during manufacture near the corner between the upper surface of the ridge 31 and the side wall surface. even or cause poor film formation, because it is still the second insulating layer 72 is formed, it is avoided that the metal layer 73 ₂ is electrically connected to the p-type cap layer of the undesired portion. Therefore, when a voltage is applied between the metal layer 73 ₂ and the metal layer 15 in the region of the photoactive layer 13 at the lower part of the undesired portion is prevented from unintended emission portion is produced. Thereby, the beam quality of the light output from the semiconductor light emitting device 1 is improved.

  Next, an example of a method for manufacturing the semiconductor light emitting device 1 according to this embodiment will be described. 4 to 7 are process diagrams illustrating the method for manufacturing a semiconductor light emitting device according to this embodiment. In the following, a method for manufacturing a cross-sectional structure along the line AA in FIG. 2 (that is, the structure shown in FIG. 3A) will be mainly described. When manufacturing a cross-sectional structure along the line B-B in FIG. 2 (that is, the structure shown in FIG. 3B), the range in which each layer is formed may be different. The manufacturing method is the same between the central element isolation layer 63 and the electrode pad portion 41 and between the element isolation layer 63 and the electrode pad portion 42.

  First, an n-type cladding layer 12, a photoactive layer 13, and a p-type cladding layer 14 are sequentially formed on one main surface of the n-type substrate 10 by epitaxial growth to form a semiconductor layer 11, and further, a semiconductor layer A p-type cap layer 20 is formed on the substrate 11 (FIG. 4A). These layers are formed on the entire main surface of one of the n-type substrates 10.

  Then, a resist is applied on the entire surface of the p-type cap layer 20, and a resist layer 81 is formed in a predetermined region on the p-type cap layer 20 by exposure and development using a mask having a predetermined pattern (FIG. 4 ( b)). Etching is performed using the resist layer 81 as a mask (FIG. 4C), and then the resist layer 81 is removed (FIG. 4D). Thereby, a p-type cap layer constituting each ridge portion and a groove portion between two adjacent ridge portions are formed. A p-type cap layer constituting each electrode pad portion and a groove portion between the ridge portion and the electrode pad portion may be formed.

  At this time, the p-type cap layer constituting each ridge portion may have an inverted mesa shape or a forward mesa shape. In addition, after etching, a part of the cap layer 20 may remain in each groove portion, or the entire cap layer 20 may be removed and the upper surface of the p-type cladding layer 14 may be exposed. A part of the p-type cladding layer 14 may be removed.

  Subsequently, a resist is applied to the entire surface, and a resist layer 82 is formed in a predetermined region by exposure and development using a mask having a predetermined pattern (FIG. 4E). Etching is performed using the resist layer 82 as a mask (FIG. 4F), and then the resist layer 82 is removed (FIG. 5A). Thereby, element isolation grooves 61 to 65 reaching the substrate 10 are formed on the bottom surfaces of the groove parts 51 to 55.

  After the formation of the element isolation trench, a first insulating layer 71 is formed on the entire surface by a CVD method (FIG. 5B). Further, a resist is applied on the entire surface, and exposure and development using a mask with a predetermined pattern are performed. A resist layer 83 is formed in a predetermined region (FIG. 5C). At this time, the resist layer 83 remains on the upper surface and both side wall surfaces of each ridge portion, and the bottom surface of the groove portion following the side wall surface. The remaining resist layer 83 is used as a mask to perform dry etching. Thus, the first insulating layer 71 is formed on the upper surface and both side wall surfaces of each ridge portion, and the bottom surface of the groove portion following the side wall surface (FIG. 5D). Thereafter, the resist layer 83 is removed (FIG. 5E).

  Subsequently, a resist 84 is applied on the entire surface (FIG. 5F). At this time, the resist layer 84 is relatively thin on the upper surface of each ridge portion and relatively thick on the upper surface of each electrode pad portion and the bottom surface of each groove portion. Therefore, the resist 84 on the upper surface of each ridge portion is selectively removed by exposure and development by a self-alignment method without using a mask. On the other hand, the resist 84 remains on the side wall surfaces on both sides of each ridge portion, the top and side surfaces of each electrode pad portion, and the bottom surface of each groove portion (including the inner wall surface and bottom surface of each element isolation groove) (FIG. 6 ( a)). By adopting this self-alignment method, it is easy to manufacture even a narrow ridge portion.

  The remaining resist 84 is used as a mask to perform dry etching. Thereby, the first insulating layer 71 is removed on the upper surface of each ridge portion. On the other hand, the first insulating layer 71 remains on the side wall surfaces on both sides of each ridge portion and the bottom surface of the groove portion following the side wall surface (FIG. 6B). Thereafter, the resist 84 is removed (FIG. 6C). The first insulating layer 71 is formed in a predetermined region by the steps so far (first insulating layer forming step).

  In this way, after the first insulating layer 71 is formed in a predetermined region, the second insulating layer 72 is formed on the entire surface by the CVD method (FIG. 6D), and a resist is further applied on the entire surface. A resist layer 85 is formed by exposure and development using a mask (FIG. 6E). At this time, the resist layer 85 is formed on the upper surface of each electrode pad portion, the upper surfaces and both side wall surfaces of the ridge portions 31 and 34, and the bottom surface of each groove portion (including the inner wall surface and the bottom surface of the element isolation groove). The resist layer 85 is not formed on the upper surface and both side wall surfaces of the ridge portions 32 and 33 and a partial region of the bottom surface of the groove portion following the side wall surface.

  The remaining resist layer 85 is used as a mask for dry etching. Thereby, the second insulating layer 72 is removed in the upper surface and both side wall surfaces of the ridge portions 32 and 33 and in a partial region of the bottom surface of the groove portion following the side wall surface. The remaining second insulating layer 72 is formed on the upper surface of each electrode pad portion, the upper surface and both side wall surfaces of the ridge portions 31 and 34, and the bottom surface of each groove portion (including the inner wall surface and the bottom surface of the element isolation groove). (FIG. 6 (f)). Thereafter, the resist layer 85 is removed (FIG. 7A). The second insulating layer 72 is formed in a predetermined region by the steps so far (second insulating layer forming step).

  After the second insulating layer 72 is thus formed in a predetermined region, a resist is applied to the entire surface, and a resist layer 86 is formed by exposure and development using a mask having a predetermined pattern (FIG. 7B). ). At this time, the resist layer 86 is formed in a region in the vicinity of the element isolation layer 63 among the region on the chip end side of each electrode pad portion, the inner wall surface and the bottom surface of the central element isolation layer 63, and the bottom surface of the groove portion 53. Yes. A metal layer 73 is formed thereon by vapor deposition (FIG. 7C). Then, the resist layer 86 and the portion of the metal layer 73 thereon are removed by lift-off (FIG. 7D). As a result, the metal layer 73 remains from each electrode pad portion to the vicinity of the element isolation layer 63. The metal layer 73 is formed in a predetermined region by the steps so far (metal layer forming step).

  And the metal layer 15 is formed in the other main surface of the n-type board | substrate 10, and the semiconductor light-emitting device 1 which has the structure shown by FIGS. 1-3 is manufactured (FIG.7 (e)).

  The semiconductor light emitting device 1 manufactured as described above has a ridge structure, and is manufactured through exposure and development by a self-alignment method, so that the light emission width can be about several μm.

By the way, in the semiconductor light emitting device manufacturing method according to the present embodiment described above, near the corner between the upper surface and the side wall surface of each ridge portion, and between the inner wall surface of each device isolation groove and the bottom surface of the groove. In the vicinity of the corner, the first insulating layer 71 may be peeled off or a film formation defect may occur during the manufacturing process. In particular, the resist 84 on the upper surface of each ridge portion is selectively removed by exposure and development using a self-alignment method (FIG. 6A), and then the first insulating layer 71 on the upper surface of each ridge portion is selectively removed. At the time of removal (FIG. 6B), the resist 84 and the first insulating layer 71 are removed in the upper portion of the side wall surface of each ridge portion and in the vicinity of the corner portion of each element isolation groove, so that the p-type cap layer is formed. May be exposed. If, when the immediately metal layer 73 ₂ is formed in this state, the metal layer 73 ₂ to be electrically connected only to the p-type cap layer 22 constituting the ridge portion 32, the other ridge Also in the upper part of the side wall surface of each part and in the vicinity of the corners of each element isolation trench, the p-type cap layer is electrically connected.

Therefore, in order to cope with such a problem, the second insulating layer 72 is further provided in the present embodiment. When the second insulating layer 72 is formed, the resist is exposed and developed using a mask having a predetermined pattern instead of the self-alignment method, so that the upper portion of the side wall surface of each ridge portion and each element isolation are formed. The second insulating layer 72 does not peel off at the upper part of the inner wall surface of the groove. Therefore, the metal layer 73 ₂ formed on the second insulating layer 72 is electrically connected only to the p-type cap layer 22 constituting the ridge portion 32, the p-type cap in other undesired portion There is no electrical connection to the layers, and light emission under undesired portions is avoided.

  Further, in the semiconductor light emitting device manufacturing method according to the present embodiment described above, when the second insulating layer 72 is formed (FIGS. 6D to 6F), the first insulating layer 71 and When the etching rates of the materials of the second insulating layers 72 are approximately the same, a predetermined portion of the second insulating material is used during dry etching performed using the resist layer 85 as a mask (FIG. 6F). Not only the layer 72 is removed, but also the first insulating layer 71 thereunder is removed. If a metal layer is further formed in this state, the metal layer is electrically connected to the semiconductor layer at the groove.

  Therefore, in order to cope with such a problem, in the present embodiment, the second insulating layer 72 is made of a material having an etching rate larger than that of the material of the first insulating layer 71. By doing in this way, it can be avoided that the first insulating layer 71 is removed during dry etching (FIG. 6F) performed using the resist layer 85 as a mask. Therefore, the metal layer 73 formed on the second insulating layer 72 is not electrically connected to the semiconductor layer in each groove portion.

The present invention is not limited to the above embodiment, and various modifications can be made. For example, the pattern of the metal layer 73 in the semiconductor light emitting device may be such that a plan view is shown in FIG. Compared with the pattern of the metal layer 73 shown in FIG. 2, in the semiconductor light emitting device shown in FIG. 8, each of the metal layers 73 _{1 to} 73 ₄ extends along the extending direction of the corresponding ridge portions 31 to 34. Each of the divided ranges is electrically connected to the p-type cap layer. Metal layer 73 _2, from above the ridge portion 32, passes between the two divided metal layer 73 ₁ on the ridge portion 31 is formed to the electrode pad portion 41, The metal layer 73 _3, from above the ridge portion 33, passes between the two divided metal layer 73 ₄ on the ridge portion 34 is formed to the electrode pad portion 42. In this case, the cross-sectional structure of the portion where the metal layer 73 ₂ is formed is as shown in FIG. 3 (a), also, the cross-sectional structure of a portion where the metal layer 73 ₁ is formed in FIG. 3 (b) As shown in

1 is a perspective view of a semiconductor light emitting device 1 according to an embodiment. 1 is a plan view of a semiconductor light emitting element 1 according to an embodiment. It is sectional drawing of the semiconductor light-emitting device 1 which concerns on this embodiment. It is a 1st process drawing explaining the semiconductor light-emitting device manufacturing method concerning this embodiment. It is a 2nd process drawing explaining the semiconductor light-emitting device manufacturing method concerning this embodiment. It is a 3rd process drawing explaining the semiconductor light-emitting device manufacturing method concerning this embodiment. It is a 4th process drawing explaining the semiconductor light-emitting device manufacturing method concerning this embodiment. It is a top view of the semiconductor light emitting element of a modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor light emitting element, 2 ... Submount, 3 ... Wire, 10 ... N-type substrate, 11 ... Semiconductor layer, 12 ... N-type clad layer, 13 ... Photoactive layer, 14 ... P-type clad layer, 15 ... Metal layer 20-26 ... p-type cap layer, 31-34 ... ridge portion, 41, 42 ... electrode pad portion, 51-55 ... groove portion, 61-65 ... element isolation groove, 71 ... first insulating layer, 72 ... second Insulating layer, 73... Metal layer.

Claims (4)

A semiconductor layer formed on a substrate and including a photoactive layer, an electrode pad portion provided on the semiconductor layer, and provided in parallel with each other across a groove on the semiconductor layer and close to the electrode pad portion A plurality of ridge portions including a first ridge portion and a second ridge portion in order,
A first insulating layer formed on both sides of each of the plurality of ridges from the side wall surface of each ridge to the bottom of the groove;
A second insulating layer formed from the bottom surface of the groove portion on the electrode pad portion side of the second ridge portion to the electrode pad portion;
A metal layer formed from the bottom surface of the groove portion on the side opposite to the electrode pad portion side of the second ridge portion to the electrode pad portion;
Are formed in order ,
Before Symbol metal layer is electrically connected to the upper surface of the second ridge portion,
A semiconductor light emitting element characterized by the above. An element isolation groove reaching the substrate at the bottom of the groove is formed,
A first insulating layer and a second insulating layer are formed on an inner wall surface and a bottom surface of the element isolation groove;
The semiconductor light emitting element according to claim 1. A semiconductor layer formed on a substrate and including a photoactive layer, an electrode pad portion provided on the semiconductor layer, and a first ridge portion and a second ridge portion on the semiconductor layer in order from the electrode pad portion. A plurality of ridge portions provided in parallel with each other across a groove portion, and a method of manufacturing a semiconductor light emitting device comprising:
The first insulating layer is formed and the resist is applied on the entire surface, and the resist on the upper surface of each of the plurality of ridges is selectively removed by exposure and development using a self-alignment method, and the remaining resist layer is used as a mask to dry the resist. A first insulating layer forming step of forming a first insulating layer on both sides of each of the plurality of ridge portions from the side wall surface of each ridge portion to the bottom surface of the groove portion by performing etching ;
The second insulating layer made of a material larger than the etching rate of the material of the first insulating layer and the application of the resist are performed on the entire surface, and the resist layer remaining by exposure and development using a mask of a predetermined pattern is used as a mask. by performing the dry etching, a second insulating layer forming step of forming a second insulating layer until the electrode pad portion from the bottom of the groove of the electrode pad portion of the second ridge portion,
A metal layer forming step of forming a metal layer electrically connected to the upper surface of the second ridge portion from the bottom surface of the groove portion on the opposite side of the second ridge portion to the electrode pad portion; ,
A method for manufacturing a semiconductor light emitting device, wherein the steps are sequentially performed. After forming an element isolation groove reaching the substrate at the bottom of the groove, the first insulating layer forming step, the second insulating layer forming step, and the metal layer forming step are sequentially performed.
In the first insulating layer forming step, the first insulating layer is also formed on the inner wall surface and the bottom surface of the element isolation groove,
In the second insulating layer forming step, the second insulating layer is also formed on the inner wall surface and the bottom surface of the element isolation groove.
The method of manufacturing a semiconductor light emitting element according to claim 3.

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